A method of semiconductor device manufacturing

Abstract

The application discloses a semiconductor device manufacturing method, relates to the technical field of semiconductor manufacturing, and aims to solve the problem of corrosion of a press welding point caused by residual fluorine ions in the press welding point. The semiconductor device manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and an aluminum conductive structure formed on the substrate; forming a passivation layer covering the aluminum conductive structure and the substrate; performing at least a patterning treatment on the passivation layer by using a fluorine-containing reaction gas to obtain a plurality of press welding points; performing in-situ post-treatment on the plurality of press welding points in a same processing chamber to remove fluorine ions remaining on the plurality of press welding points; and forming a plurality of conductive connection structures on the plurality of press welding points.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing semiconductor devices. Background Technology

[0002] In semiconductor manufacturing, the passivation layer needs to be etched to expose the underlying conductive metal layer, forming solder joints for connecting conductive structures. When etched using a fluorine-containing gas, fluorine ions remain in the solder joint area after the aluminum conductive layer forms the solder joints. These solder joints are then corroded by moisture and fluorine ions in the air after the semiconductor device is removed from the processing chamber. This leads to poor bonding between the solder joints and the conductive structures, affecting subsequent packaging and measurement. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device manufacturing method to solve the problem of solder joint corrosion caused by residual fluoride ions in the solder joint.

[0004] This invention provides a method for manufacturing a semiconductor device, comprising:

[0005] A substrate is provided, the substrate including a substrate and an aluminum conductive structure formed on the substrate.

[0006] A passivation layer is formed covering the aluminum conductive structure and the substrate.

[0007] The passivation layer is patterned using a fluorine-containing reactive gas to obtain multiple bonding points.

[0008] In the same processing chamber, multiple weld points are subjected to in-situ post-treatment to remove residual fluoride ions from the weld points.

[0009] Multiple conductive connection structures are formed on multiple pressure bonding points.

[0010] Compared with existing technologies, the semiconductor device manufacturing method provided by this invention removes residual fluoride ions from the solder joints after etching the passivation layer to form solder joints using an in-situ post-processing method. Once the fluoride ions in the solder joints are removed, there is no reaction between airborne water molecules and fluoride ions after the solder joints leave the processing chamber; therefore, airborne water molecules will not corrode the solder joints. Thus, by suppressing corrosion in the solder joint area in this invention, defects in subsequent packaging and testing processes can be reduced, and the yield from passivation layer etching to packaging can be improved. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figures 1-7 This is a process diagram of a semiconductor device fabrication method provided in an embodiment of the present invention.

[0013] Figure label:

[0014] 1-Substrate / first dielectric layer, 2-Aluminum conductive structure, 21-Aluminum metal layer, 22-Tantalum nitride layer, 3-Second dielectric layer, 4-Third dielectric layer, 5-Bond joint, 6-Conductive connection structure. Detailed Implementation

[0015] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0016] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0017] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0018] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] In semiconductor manufacturing, the passivation layer needs to be etched to expose the underlying conductive metal layer, forming solder joints for connecting the conductive structures. The passivation layer is typically silicon oxide or silicon nitride, or a combination of both. Silicon nitride has a stable structure and is generally etched using dry etching, with the etching reaction gas being a mixture of sulfur hexafluoride and oxygen. While silicon oxide can also be etched using wet etching, with the reaction solution composed of hydrofluoric acid, dry etching is generally used when opening the passivation layer because the underlying material is predominantly metal. The etching reaction gas is a mixture of oxygen and fluorine compounds. When the passivation layer is etched with a fluorine-containing gas, fluoride ions remain in the solder joint area after the aluminum conductive layer forms the solder joints. These solder joints are corroded by moisture and fluoride ions in the air after the semiconductor device is removed from the processing chamber. This leads to poor connection between the solder joints and the conductive structures, affecting subsequent packaging and measurement.

[0021] Figures 1-7 The following is a process diagram illustrating the semiconductor device fabrication method provided in an embodiment of the present invention. The embodiment of the present invention provides a semiconductor device manufacturing method, comprising:

[0022] like Figure 1 As shown, a substrate is provided, comprising a substrate 1 and an aluminum conductive structure 2 formed on the substrate. The substrate 1 can be a commonly used substrate such as a bulk silicon substrate or a silicon-on-insulator substrate. The substrate may also have a first dielectric layer 1, on which the aluminum conductive structure 2 is formed. The first dielectric layer 1 can be deposited on the surface of the substrate using any existing deposition process such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The first dielectric layer 1 can be silicon oxide, silicon nitride, or a composite layer of silicon oxide and silicon nitride.

[0023] like Figure 1 and Figure 2As shown, the aluminum conductive structure 2 may include an aluminum metal layer 21, or the aluminum conductive structure 2 may include an aluminum metal layer 21 and a titanium nitride layer 22 formed on the aluminum metal layer 21. First, an aluminum metal layer 21, or an aluminum metal layer 21 and a titanium nitride layer 22, is deposited on the first dielectric layer 1. Then, photoresist is coated on it, and the photoresist is exposed and developed to form the pattern corresponding to the aluminum conductive structure 2. The photolithography of the aluminum conductive structure 3 can be formed using positive photolithography. The aluminum metal layer 21 and the titanium nitride layer 22 (if present) are etched under the mask of the photoresist to obtain the aluminum conductive structure 2. The titanium nitride layer 22 is patterned under the mask of the photoresist layer. The reaction gas for etching the titanium nitride can be chlorine or boron chloride. A portion of the aluminum metal layer 21 is patterned under the mask of the photoresist layer. The reaction gas for etching the aluminum can be chlorine or boron chloride. The aluminum metal layer 21 can be formed on the first dielectric layer 1 by physical vapor deposition, and the titanium nitride layer 22 can be formed by physical vapor deposition or chemical vapor deposition.

[0024] After the aluminum conductive structure 2 is fabricated, the photoresist on the aluminum conductive structure 2 is removed, and the surface of the entire device is cleaned. Solution No. 1 (an aqueous solution of ammonia and hydrogen peroxide) and solution No. 3 (an aqueous solution of sulfuric acid and hydrogen peroxide) can be used to clean the surface of the device.

[0025] A passivation layer is formed covering the aluminum conductive structure 2 and the substrate. For example... Figure 3 and Figure 4As shown, the passivation layer may include a second dielectric layer 3 covering the aluminum conductive structure 2 and the first dielectric layer 1, and a third dielectric layer 4 formed on the second dielectric layer 3. The second dielectric layer 3 and the first dielectric layer 1 are made of the same material, silicon oxide. When the first dielectric layer 1 and the second dielectric layer 3 are made of the same material, the connectivity between them is optimal, preventing gaps from forming between the layers due to temperature or pressure, and thus preventing migration of the aluminum conductive structure 2. The third dielectric layer 4 is silicon nitride. The second dielectric layer 3 can be deposited on the aluminum conductive structure 2 and the first dielectric layer 1 using any existing deposition process, such as Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE). The third dielectric layer 4, being silicon nitride, is formed on the second dielectric layer 3 using Plasma Enhanced Chemical Vapor Deposition (PECVD). Silicon nitride has better overall properties than silicon oxide, but its adhesion to substrates or metal structures is relatively poor, while silicon oxide has better adhesion and compatibility. However, silicon nitride has stronger corrosion resistance and wear resistance, making it more suitable as the outer layer of a passivation layer and providing better protection for the internal components of devices.

[0026] The passivation layer described above can enhance the sealing performance of the device, shielding it from the influence of external impurities and moisture. The passivation layer can also serve as an insulating layer for conductive structures such as surface layers or redistribution layers.

[0027] The passivation layer is patterned using a fluorine-containing reactive gas to obtain multiple bonding points 5.

[0028] The passivation layer is patterned to obtain multiple openings. For example... Figure 5 As shown, for example, photoresist is coated on the third dielectric layer 4, and the photoresist is exposed and developed to form a pattern corresponding to the opening. The opening is formed using negative photolithography. Under the mask of the photoresist, the second dielectric layer 3 and the third dielectric layer 4 are etched to obtain the aforementioned multiple openings. When the second dielectric layer 3 of the passivation layer is silicon oxide and the third dielectric layer 4 is silicon nitride, during the dry etching patterning process of the passivation layer, the reaction gas for etching the second dielectric layer 3 is a mixture of oxygen and fluorocarbons, for example, monofluoromethane or trifluoromethane; the reaction gas for etching the third dielectric layer 4 can be a mixture of sulfur hexafluoride and oxygen. Therefore, fluoride ions will remain on the bonding pad 5.

[0029] Under the masking of the passivation layer, a portion of the aluminum conductive structure 2 is patterned to obtain multiple corresponding bonding points 5. For example... Figure 6As shown, when patterning the aluminum conductive structure 2, a photoresist layer is retained on the passivation layer, and etching is performed under the masking of the photoresist layer and the passivation layer.

[0030] When the aluminum conductive structure 2 includes an aluminum metal layer 21 and a titanium nitride layer 22 formed on the aluminum metal layer 21, the patterning process of a portion of the aluminum conductive layer under the masking of the passivation layer includes:

[0031] The titanium nitride layer 22 is patterned under the masking of the photoresist layer and passivation layer. The reaction gas for etching the titanium nitride can be chlorine or boron chloride.

[0032] A portion of the aluminum metal layer 21 is patterned under the masking of a photoresist layer and a passivation layer. The reaction gas used to etch the aluminum can be chlorine or boron chloride.

[0033] The etching of titanium nitride and aluminum using chloride-based plasma gas does not etch the passivation layer but does have an etching effect on some types of photoresist. This can be addressed by selecting a suitable photoresist or increasing its thickness. This allows the photoresist to be retained and protects the passivation layer during subsequent dry etching to remove fluoride ions. Alternatively, the photoresist on the passivation layer can be protected by forming a hard mask on the passivation layer.

[0034] In the same processing chamber, multiple weld points 5 are subjected to in-situ post-processing to remove fluoride ions remaining on the weld points 5.

[0035] Specifically, the above-mentioned in-situ post-processing involves introducing dry etching gas in-situ into the same chamber. The etching gas reacts with fluoride ions to remove fluoride ions remaining on the multiple bonding pads 5.

[0036] The aforementioned dry etching gas is at least one of CHF3, CH3F, C4F8, and C5F8. This reactive gas can ionize carbon and hydrogen ions, which can react with residual fluoride ions in the solder joint 5. The ionized carbon and hydrogen ions then bond with fluoride ions to form CF and HF radicals. Since the fluorine-based dry etching gas can etch the passivation layer, and given the limited amount of residual fluoride ions in the solder joint 5, preserving the photoresist layer on the passivation layer protects it from etching. Because the aforementioned dry etching gas contains carbon ions, fluoride ions will form CF radicals with the carbon ions, making it difficult to ionize fluoride radicals. Therefore, the in-situ introduced dry etching gas does not exhibit the fluoride ion residue problem seen with sulfur hexafluoride.

[0037] In the process of removing residual fluoride ions from the solder joint 5, the etching conditions for the dry etching gas are a source power of 500W-2000W and a bias power of 0W-200W. A high source power increases gas ionization, providing more hydrogen and carbon ions to react with the residual fluoride ions at the solder joint 5. A low bias power reduces the velocity of the ionized plasma, minimizing physical etching and allowing only chemical etching to remove fluoride ions, thus avoiding plasma damage.

[0038] Multiple conductive connection structures 6 are formed on multiple bonding pads 5. The conductive connection structure 6 can be a microbump or under-bump metal.

[0039] like Figure 7 As shown, when the above conductive connection structure 6 is a microbump or under-bump metal, its specific implementation can be as follows:

[0040] The photoresist layer on the passivation layer is removed, and a barrier layer and a copper seed layer are sequentially formed at the opening and the passivation layer. The barrier layer and the copper seed layer cover the surface of the passivation layer and the sidewalls and bottom wall of the opening. The material of the barrier layer can be at least one of tantalum, titanium, tantalum nitride, and titanium nitride.

[0041] A photoresist layer covering the copper seed layer is formed, the photoresist layer is patterned, and the corresponding etching image of the conductive connection structure 6 is formed.

[0042] Subsequently, a conductive connection structure of 6 layers is formed, which can be formed by electroplating.

[0043] The photoresist layer, copper seed layer, and barrier layer are removed to form the conductive connection structure 6. The removal of the copper seed layer and barrier layer can be achieved using wet etching.

[0044] Compared with existing technologies, the semiconductor device manufacturing method provided by this invention removes residual fluoride ions from the solder joints 5 by etching the passivation layer to form the solder joints 5 and then performing in-situ post-processing. Once the fluoride ions in the solder joints 5 are removed, there is no water molecules in the air reacting with the fluoride ions after the solder joints leave the processing chamber, thus preventing corrosion. By suppressing corrosion in the solder joint area, defects in subsequent packaging and testing processes can be reduced, improving the yield from passivation layer etching to packaging.

[0045] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0046] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a substrate and an aluminum conductive structure formed on the substrate; The substrate has a first dielectric layer, and the aluminum conductive structure is formed on the first dielectric layer; A passivation layer is formed covering the aluminum conductive structure and the substrate; the passivation layer includes a second dielectric layer covering the aluminum conductive structure and the first dielectric layer, and a third dielectric layer formed on the second dielectric layer; the first dielectric layer and the second dielectric layer are both silicon oxide, and the third dielectric layer is silicon nitride; The passivation layer is patterned using a fluorine-containing reactive gas to obtain multiple bonding points. Within the same processing chamber, in-situ post-processing is performed on the multiple bond joints to remove residual fluoride ions. This includes introducing a dry etching gas into the processing chamber, where the etching gas reacts with the fluoride ions to remove them. The dry etching gas ionizes to produce carbon and hydrogen ions, which then bond with fluoride ions to form free radicals of CF and HF. The etching conditions for the dry etching gas are: source power of 500W-2000W and bias power of 0W-200W. Multiple conductive connection structures are formed on the multiple bonding points; the conductive connection structure is a microbump or under-bump metal. The passivation layer is patterned using a fluorine-containing reactive gas to obtain multiple bonding pads, including: The passivation layer is patterned. Under the masking of the passivation layer, a portion of the aluminum conductive structure is patterned to obtain the corresponding plurality of bonding pads; wherein, during the patterning of the aluminum conductive structure, a photoresist layer is retained on the passivation layer, and etching is performed under the masking of the photoresist layer and the passivation layer.

2. The semiconductor device manufacturing method according to claim 1, characterized in that, The aluminum conductive structure includes an aluminum metal layer, or the aluminum conductive structure includes an aluminum metal layer and a titanium nitride layer formed on the aluminum metal layer.

3. The semiconductor device manufacturing method according to claim 1, characterized in that, When the aluminum conductive structure includes an aluminum metal layer and a titanium nitride layer formed on the aluminum metal layer, the patterning process of a portion of the aluminum conductive layer under the masking of the passivation layer includes: The titanium nitride layer is patterned under the masking of the passivation layer; The aluminum metal layer is patterned under the cover of the passivation layer.

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