Three-dimensional memory structure and manufacturing method thereof, memory device and system, electronic device

Abstract

The present disclosure relates to a three-dimensional memory structure, a manufacturing method thereof, a memory device, a memory system, and an electronic apparatus. The manufacturing method of the three-dimensional memory structure includes: forming a pre-step structure including alternately stacked insulating layers and sacrificial layers on a first side of a substrate; forming a sacrificial portion on each step of the pre-step structure, wherein the sacrificial portion is disposed adjacent to an uppermost sacrificial layer of each step, and has an etching selectivity with the sacrificial layer; forming a conductive via hole from a second side opposite to the first side of the substrate, wherein the conductive via hole sequentially penetrates the substrate and the pre-step structure from the second side of the substrate, and extends to the sacrificial portion; forming a plurality of expansion spaces by etching a portion of the sacrificial layer through the conductive via hole; spacing the conductive via hole from the sacrificial layer by filling an insulating material in the plurality of expansion spaces; and forming a conductive channel by filling a conductive material in the conductive via hole.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a three-dimensional storage structure and its manufacturing method, storage device, storage system, and electronic device. Background Technology

[0002] To increase the capacity of 3D storage structures, manufacturers aim to increase the number of layers in the stacked structure while keeping the 3D storage structure's lateral dimensions from becoming too large.

[0003] As the number of layers in a stacked structure increases, the number of conductive channels that need to be brought out also increases. The lateral process windows, such as the distance between conductive channels and the distance between conductive channels and the dummy channel structure, are significantly compressed. This greatly increases the difficulty of etching and deposition processes. There is a risk that the conductive channels and the dummy channel structure will merge and connect. Furthermore, there is a risk that the conductive channels will penetrate the stacked structure, and the stacked structure is more prone to bending during gate replacement. Summary of the Invention

[0004] The embodiments disclosed herein can at least solve one or more of the technical problems in the prior art described above, or can be used to solve some other technical problems in the prior art.

[0005] Embodiments of this disclosure provide a method for manufacturing a three-dimensional memory structure, the method comprising: forming a prefabricated stepped structure comprising alternating stacked insulating layers and sacrificial layers on a first side of a substrate; forming a sacrificial portion on each step of the prefabricated stepped structure, wherein the sacrificial portion is disposed adjacent to the uppermost sacrificial layer of each step, and the sacrificial portion and the sacrificial layer have etch selectivity; forming a conductive channel hole from a second side of the substrate opposite to the first side, wherein the conductive channel hole extends from the second side of the substrate sequentially through the substrate and the prefabricated stepped structure and extends to the sacrificial portion; etching a portion of the sacrificial layer through the conductive channel hole to form a plurality of expansion spaces; spacing the conductive channel from the sacrificial layer by filling the plurality of expansion spaces with insulating material; and filling the conductive channel hole with conductive material to form a conductive channel.

[0006] In some embodiments, adjacent expansion spaces are separated by the insulating layer in the extending direction of the conductive channel hole.

[0007] In some embodiments, the method further includes: replacing the sacrificial layer with a gate layer; and replacing the sacrificial portion with a conductive portion.

[0008] In some embodiments, a plurality of insulating portions are formed by the step of filling insulating material, the plurality of insulating portions including a first insulating portion located at the top of each of the steps, the material of the insulating portion being the same as the material of the sacrificial portion; wherein the step of replacing the sacrificial portion with a conductive portion includes: replacing the sacrificial portion and the first insulating portion with the conductive portion.

[0009] In some embodiments, the method further includes: forming a gate wire slot through the prefabricated stepped structure; wherein the step of replacing the sacrificial layer with the gate layer includes: replacing the sacrificial layer with the gate layer through the gate wire slot; wherein the step of replacing the sacrificial portion with the conductive portion includes: replacing the sacrificial portion with the conductive portion through the gate wire slot.

[0010] In some embodiments, the method further includes forming an insulating filler on the prefabricated stepped structure and the sacrificial portion.

[0011] In some embodiments, forming a prefabricated stepped structure comprising alternating stacked insulating and sacrificial layers on a first side of a substrate includes: forming a prefabricated stacked structure comprising alternating stacked insulating and sacrificial layers on the substrate, wherein a step region and a storage region are defined in a direction parallel to the substrate; and forming the portion of the prefabricated stacked structure located in the step region as the prefabricated stepped structure.

[0012] In some embodiments, the method further includes: forming a channel structure through the storage region, wherein the channel structure includes, in a radial direction from the inside to the outside, a channel layer, a tunneling layer, a charge trapping layer, a barrier layer, and a first high-dielectric layer.

[0013] In some embodiments, the step of replacing the sacrificial layer with the gate layer includes: removing the sacrificial layer to form a sacrificial space; forming a second high-dielectric layer and the gate layer in the sacrificial space, wherein the gate layer is separated from the insulating layer and from the channel structure by the second high-dielectric layer.

[0014] In some embodiments, the step of replacing the sacrificial portion and the first insulating portion with the conductive portion includes: removing the sacrificial portion and the first insulating portion; removing a portion of the second high-dielectric layer at the top of each step that is exposed; and filling the space formed after removing the sacrificial portion, the first insulating portion and the portion of the second high-dielectric layer that is exposed with conductive material to form the conductive portion.

[0015] Secondly, embodiments of this disclosure provide a three-dimensional memory structure, comprising: a semiconductor layer; a stacked structure including a gate layer and an insulating layer alternately stacked in a direction away from the semiconductor layer, wherein, in a direction parallel to the semiconductor layer, the stacked structure includes a memory region and a step region having multiple steps; a conductive portion located on the side of the step away from the semiconductor layer and electrically connected to a portion of the gate layer located at the step; a conductive channel penetrating the semiconductor layer and the step region, wherein the conductive channel is electrically connected to the conductive portion; and an insulating portion located between the gate layer and the conductive channel.

[0016] In some embodiments, adjacent insulating portions are spaced apart by the insulating layer in the direction of extension of the conductive channel.

[0017] In some embodiments, the three-dimensional storage structure further includes a channel structure extending through the stacked structure, comprising, in a radial direction from the inside out, a channel layer, a tunneling layer, a charge trapping layer, a barrier layer, and a first high-dielectric layer.

[0018] In some embodiments, the conductive portion includes: a first conductive portion located on the step; and a second conductive portion located between the gate layer and the conductive channel, wherein the first conductive portion is in contact with the second conductive portion and its maximum dimension in the direction parallel to the semiconductor layer is greater than the maximum dimension of the second conductive portion in the direction parallel to the semiconductor layer.

[0019] In some embodiments, the three-dimensional memory structure further includes: a channel structure extending through the stacked structure, comprising, in a radial direction from the inside out, a channel layer, a tunneling layer, a charge trapping layer, and a barrier layer; and a second high-dielectric layer located between the gate layer and the insulating layer, and between the gate layer and the channel structure.

[0020] In some embodiments, the three-dimensional storage structure further includes a grid line slot partition structure that extends through the stacked structure along the alternating stacking direction.

[0021] A third aspect of this disclosure provides a storage device, comprising: the aforementioned three-dimensional storage structure and peripheral circuitry electrically connected to the three-dimensional storage structure.

[0022] A third aspect of this disclosure provides a storage system comprising: the aforementioned storage device and a storage controller coupled to the storage device, the storage controller being configured to control the three-dimensional storage device to store data.

[0023] A fourth aspect of this disclosure provides an electronic device including the aforementioned storage system.

[0024] The method for manufacturing a three-dimensional storage structure provided by embodiments of this disclosure involves forming conductive channels from the side of a substrate facing away from a prefabricated stepped structure. These conductive channels and the surrounding insulating portion can be used to support the prefabricated stepped structure. Thus, after removing the sacrificial layer in the prefabricated stacked structure, the insulating layer can be supported, reducing the probability of collapse.

[0025] In this embodiment, the insulating portion can be disposed between two adjacent insulating layers, directly supporting the insulating layers for better protection, and ensuring electrical isolation between the gate layer and the conductive channel. Furthermore, since both the insulating portion and the conductive channel are formed through conductive channel vias, it helps avoid problems such as insufficient overlay accuracy and etching penetration caused by multiple via fabrication.

[0026] In three-dimensional memory structures, it is unnecessary to set up virtual channel structures between multiple conductive channels. This manufacturing method can be used to fabricate three-dimensional memory structures with a large number of stacked layers. While maintaining the same lateral dimensions, the density of conductive channels can be increased to increase the number of conductive channels, thus accommodating stacked structures with many layers. At the same time, it ensures that the stacked structure is well supported. Attached Figure Description

[0027] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to embodiments of the present disclosure; Figures 2 to 10 This is a process diagram based on an embodiment of the present disclosure; Figures 11 to 19 These are process diagrams based on some embodiments of this disclosure; Figure 20A and Figure 20B This is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of the present disclosure; Figure 21 This is a schematic structural diagram of a storage device according to an embodiment of the present disclosure; Figure 22 This is a schematic structural diagram of a storage system according to embodiments of the present disclosure; and Figure 23 This is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0028] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this disclosure, the first conductive portion discussed below may also be referred to as the second conductive portion, and vice versa.

[0030] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the number of layers in the stacked structure, the diameter of the conductive channels, etc., are not to scale in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0031] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0032] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] Figure 1 This is a method for manufacturing a three-dimensional storage structure according to embodiments of the present disclosure. (See reference...) Figure 1 The method 1000 provided in this disclosure includes the following steps.

[0035] Step S101: A prefabricated stepped structure comprising alternating stacked insulating and sacrificial layers is formed on a first side of the substrate. In a plane parallel to the substrate, the steps of the prefabricated stepped structure can be arranged both along a first direction and a second direction, which allows multiple sacrificial layers to be staggered between adjacent steps.

[0036] In step S102, a sacrificial portion is formed on each step of the prefabricated stepped structure. The sacrificial portion corresponds one-to-one with each step. The sacrificial portion is disposed adjacent to the uppermost sacrificial layer of each step. There is etching selectivity between the sacrificial portion and the sacrificial layer. Exemplarily, in a plane parallel to the substrate, there is a gap between the sacrificial portion and the adjacent step.

[0037] Step S103: A conductive channel hole is formed on the second side of the substrate, penetrating the substrate and the prefabricated step structure and extending to the sacrificial portion, wherein the second side of the substrate is the side opposite to the first side of the substrate.

[0038] Step S104: Forming multiple expansion spaces. The sacrificial layer can be exposed by the sidewalls of the conductive channel aperture, through which a portion of the sacrificial layer can be etched, thereby forming the expansion spaces. Exemplarily, adjacent expansion spaces are separated by an insulating layer in the extending direction of the conductive channel aperture.

[0039] Step S105: Fill the multiple expansion spaces with insulating material. Specifically, insulating portions can be formed in the expansion spaces by filling them with insulating material. An insulating portion can be formed in each expansion space, and multiple insulating portions can be formed in multiple expansion spaces. The material of the insulating portion can be the same as the material of the sacrificial portion.

[0040] Step S106: A conductive channel is formed in the conductive channel hole. Exemplarily, the conductive channel extends from a second side of the substrate to the sacrificial portion. An insulating portion may space the conductive channel hole from the sacrificial layer, or in other words, space the conductive channel hole from the remainder of the sacrificial layer. Subsequently, the conductive channel and the sacrificial layer are also spaced apart by an insulating portion.

[0041] For example, method 1000 further includes step S107, replacing the sacrificial layer with a gate layer. After the sacrificial layer is replaced with a gate layer, the prefabricated stepped structure can be transformed into a stepped structure.

[0042] In step S108, the sacrificial part is replaced with a conductive part. The conductive part is electrically connected to the conductive channel and to the gate layer in which it is located.

[0043] For example, no virtual channel structure is formed between multiple conductive channels.

[0044] For example, after step S102 and before step S103, the method 1000 may further include the step of forming an insulating filler on the prefabricated step structure and the sacrificial portion.

[0045] The following is in conjunction with the appendix Figures 2 to 19 The implementation methods provided in this disclosure are described in detail.

[0046] like Figure 2 As shown, the prefabricated stacked structure 2 includes a prefabricated step structure 21 located in the step region SS and a prefabricated storage structure 22 located in the storage region GB. The step region SS and the storage region GB are arranged along the x-direction. Since the prefabricated step structure 21 and the prefabricated storage structure 22 are an integral structure, in some cases, the prefabricated storage structure 22 can be regarded as the highest step of the prefabricated step structure 21, and the prefabricated stacked structure 2 can be regarded as a prefabricated step structure.

[0047] Specifically, form Figure 2 The steps of the structure shown may include: alternately stacking an insulating layer 201 and a sacrificial layer 202 on a substrate 1; then forming a channel structure 24 penetrating the prefabricated stacked structure 2 in the storage region GB, wherein the channel structure 24 can extend into the substrate 1; and obtaining a prefabricated step structure 21 in the step region SS by etching the prefabricated stacked structure 2; subsequently, a sacrificial portion 203 may be formed on each step of the prefabricated step structure 21; and an insulating filler 23 may be formed by filling with a material such as tetraethyl orthosilicate. For example, as... Figure 2As shown, the prefabricated step structure 21 may include multiple steps 21'. The height of each step gradually increases in the direction away from the substrate 1. Each step 21' may include at least one level, and each level may include a sacrificial layer 202 and an insulating layer 201 from top to bottom. The accompanying drawings only exemplarily illustrate the case where each step 21' includes three levels. Furthermore, it should be noted that the number of steps 21' can be adjusted as needed, depending on the number of sacrificial layers 202 and insulating layers 201 in the prefabricated stacked structure 2 and the number of levels contained in each step 21'. It should be understood that the terms "upper," "above," etc., used in this application refer to the direction away from the substrate. For example, the side of the prefabricated step structure 21 away from the substrate 1 is the upper side of the prefabricated step structure 21, and the side of the step 21' away from the substrate 1 is the upper side of the step 21'.

[0048] The material of substrate 1 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0049] The formation process of the prefabricated stacked structure 2 may include thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the insulating layer 201 may include, for example, silicon oxide, and the material of the sacrificial layer 202 may include, for example, silicon nitride. The sacrificial portion 203 is adjacent to the uppermost sacrificial layer 202 of the step 21' in which it is located. There is a gap between the sacrificial portion 203 and the higher-level step. The material of the sacrificial portion 203 may include silicon carbide-doped silicon nitride. There is etching selectivity between the material of the sacrificial portion 203 and the material of the sacrificial layer 202. Exemplarily, there is also etching selectivity between the material of the sacrificial portion 203 and the material of the insulating layer 201 or the insulating filler 23.

[0050] Insulating filler 23 is formed on the prefabricated stepped structure 21 and the sacrificial portion 203, and fills the gap between the prefabricated stepped structure 21 and the sacrificial portion 203. Exemplarily, insulating filler 23 also covers the channel structure 24.

[0051] like Figure 3As shown, in an exemplary embodiment, the channel structure 24 may include, in a radial direction (i.e., the X direction) from the inside out, a channel layer 242, a tunneling layer 243, a charge trapping layer 244, a barrier layer 245, and a first high-dielectric layer 246, which are arranged sequentially from the inside out. Exemplarily, an insulating core layer 241 may also be provided inside the channel layer 242.

[0052] After the insulating filler 23 is formed, a conductive channel hole 204 can be formed on the opposite side of the substrate 1 where the prefabricated stacked structure 2 is provided, or on the side of the substrate 1 opposite to the prefabricated stepped structure 21, extending through the substrate 1 and the prefabricated stepped structure 21 to the sacrificial portion 203. Exemplarily, before forming the conductive channel hole 204, the substrate 1 can be mechanically and chemically polished to thin the substrate 1. This makes it easier to form the conductive channel hole 204, resulting in... Figure 4 The structure shown.

[0053] In this embodiment, the sacrificial layer 202 can be etched through the conductive via 204 to form a plurality of expansion spaces 205. Because there is etching selectivity between the material of the sacrificial portion 203 and the material of the sacrificial layer 202, the sacrificial portion 203 is less affected when the sacrificial layer 202 is etched. Figure 5 As shown, adjacent expansion spaces 205 are separated by an insulating layer 201 in the extending direction of the conductive channel hole 204. The projection of the expansion space 205 onto the substrate 1 can be approximately annular. It can be assumed that the inner circle of this annularity coincides with the conductive channel hole 204, or that the inner circle of the annular expansion space 205 coincides with the inner wall of the insulating layer 201 at the conductive channel hole 204. It can be assumed that the outer circle of the annular expansion space 205 is larger than the conductive channel hole 204, or in other words, in a projection plane parallel to the substrate 1, the outer circle of the annular expansion space 205 extends into the insulating layer 201.

[0054] In other embodiments, the thickness of the sacrificial portion 203 may be set to be greater than the circumferential width of the expansion space 205, i.e., the etching depth of the sacrificial layer 202 along the direction parallel to the substrate. For example, this ensures that the sacrificial portion 203 is not etched through when the sacrificial layer 202 is etched. For instance, if the etching selectivity ratio of the material of the sacrificial layer 202 to the material of the sacrificial portion 203 is, for example, 10 times, then the thickness of the sacrificial portion 203 must be at least 0.1 times greater than the etching depth of the sacrificial layer 202.

[0055] For example, insulating material can be filled into multiple expansion spaces 205 to form multiple insulating portions 206. The main purpose of providing insulating portions 206 is to space the conductive channel holes 204 from the sacrificial layer 202, while also providing support for the prefabricated laminated structure 2. Figure 5 and Figure 6As shown, the insulating portion 206 is located between the conductive channel hole 204 and the sacrificial layer 202, and between two adjacent insulating layers 201. Exemplarily, the insulating portion 206 may not completely fill the expansion space 205, or it may partially protrude into the conductive channel hole 204.

[0056] For example, the plurality of insulating portions 206 include a first insulating portion 206a. The first insulating portion 206a may be formed by filling the expansion space 205 at the uppermost part of each step 21' with insulating material. For example, the first insulating portion 206a may be formed at the sacrificial layer 202 at the bottom of the conductive channel hole 204. When the material of the insulating portion 206 is the same as the material of the sacrificial portion 203, the first insulating portion 206a and the sacrificial portion 203 can be considered to be integrally formed. When the material of the first insulating portion 206a is different from the material of the sacrificial portion 203, the sacrificial portion 203 needs to be exposed to the conductive channel hole 204.

[0057] In summary, the method 1000 provided in this disclosure can form an insulating portion 206 at the exposed portion of the sacrificial layer 202, thereby forming a conductive channel 207 within the conductive channel hole 204. For example... Figure 7 As shown, the conductive channel 207 penetrates the substrate 1 and the prefabricated stacked structure 2, extends to the sacrificial portion 203, and is separated from the multiple sacrificial layers 202 it passes through by multiple insulating portions 206.

[0058] Exemplarily, a gate line slot (not shown) penetrating the prefabricated stepped structure 21 can be formed. For example, a gate line slot penetrating the prefabricated stepped structure 21 can be formed on the side of the substrate 1 where the prefabricated stepped structure 21 is provided, i.e., on the side of the substrate 1 opposite to the prefabricated stacked structure 2. Of course, in another embodiment, after forming the insulating filler 23, a stop layer (not shown) can be formed on the insulating filler 23. Then, a gate line slot penetrating the substrate 1, the prefabricated stepped structure 21, and the insulating filler 23, and stopping at the stop layer, can be formed on the opposite side of the substrate 1 where the prefabricated stepped structure 21 is provided, i.e., on the side of the substrate 1 away from the prefabricated stacked structure 2. The material of the stop layer may include polysilicon. It should be understood that the stop layer may be an etch stop layer for the gate line slot. The gate line slot extends along the x-direction and cuts the prefabricated stacked structure 2 into at least two pieces. In a direction perpendicular to the xz plane, both the prefabricated stacked structure 2 and the sacrificial portion 203 are exposed by the gate line slot.

[0059] Since the sacrificial layer 202, the sacrificial portion 203, and the insulating layer 201 can have etching selectivity among themselves, the sacrificial layer 202 or the sacrificial portion 203 can be selectively etched in different ways. For example, by replacing the sacrificial layer 202 with the gate layer 208 through a gate line slot, the following can be obtained: Figure 8The structure shown is as follows. After the step of replacing the gate layer 208, the prefabricated stacked structure 2 can be considered to be transformed into a stacked structure 20. Similarly, the prefabricated step structure 21 is transformed into a step structure 21', and the prefabricated memory structure 22 is transformed into a memory structure 220.

[0060] For example, the materials of the gate layer 208 and the conductive channel 207 may include conductive materials such as tungsten, and the gate layer 208 and the conductive channel 207 are separated by a plurality of insulating portions 206. During the replacement process, the plurality of insulating portions 206 and the conductive channel 207 support the stacked structure 20 to prevent the stacked structure 20 from collapsing and bending, so as to ensure that the formed gate layer 208 has a good morphology.

[0061] In this embodiment, since there is etching selectivity between the materials of the sacrificial layer 202 and the sacrificial portion 203, the sacrificial portion 203 is not replaced when the sacrificial layer 202 is replaced. After the gate layer 208 is formed, the sacrificial portion 203 can be replaced with the conductive portion 210 through the gate line slot trench. Figure 10 Specifically, the sacrificial portion 203 can be removed. In this embodiment, the material of the sacrificial portion 203 can be the same as the material of the insulating portion 206, therefore the first insulating portion 206a connected to the sacrificial portion 203 is also removed. Figure 9 As shown, a replacement space 209 is obtained after removing the sacrificial portion 203 and the first insulating portion 206a. The insulating portions other than the first insulating portion 206a are not etched due to the spacing of the insulating layer 201.

[0062] Conductive portions 210 can be formed in replacement space 209. For example... Figure 10 As shown, the conductive portion 210 electrically connects the conductive channel 207 to the gate layer 208 at its end. Multiple conductive channels 207 are electrically connected to multiple gate layers 208 in a one-to-one correspondence. The conductive portion 210 also ensures good conductivity between the conductive channel 207 and the gate layer 208, thereby enabling the manufactured three-dimensional memory structure to have good performance.

[0063] This disclosure also provides some methods for manufacturing three-dimensional storage structures, such as Figure 11 and Figure 12 As shown, when forming the channel structure 24 according to this method, a barrier layer 245, a charge trapping layer 244, a tunneling layer 243, and a channel layer 242 can be formed sequentially from the outside to the inside in a plane parallel to the substrate 1. In other words, the channel structure 24 may include the following components arranged sequentially from the inside to the outside along the radial direction (i.e., the X direction) of the channel structure: channel layer 242, tunneling layer 243, charge trapping layer 244, and barrier layer 245. Exemplarily, an insulating core layer 241 may also be provided inside the channel layer 242. In this embodiment, the steps of the aforementioned embodiments can be used to form the... Figure 11 The structure shown. Specifically, as... Figure 11 As shown, a prefabricated stacked structure 2 comprising alternating stacked insulating layers 201 and sacrificial layers 202 is disposed on substrate 1. The prefabricated stacked structure 2 can be divided into a prefabricated step structure 21 located in the step region SS and a prefabricated storage structure 22 located in the storage region GB. Sacrificial portions 203 may be disposed on the steps of the prefabricated step structure 21.

[0064] like Figure 13 As shown, a conductive channel hole 204 can still be formed through the substrate 1 and the prefabricated stepped structure 21 after the substrate 1 is thinned. The conductive channel hole 204 exposes the sacrificial portion 203.

[0065] For example, the sacrificial layer 202 can be etched through the conductive channel hole 204 to form the expansion space 205, such as Figure 14 As shown. An insulating portion 206 can then be formed in the expansion space 205, as... Figure 15 As shown. The plurality of insulating portions 206 include a first insulating portion 206a integrally connected to the sacrificial portion 203. After the plurality of insulating portions 206 are formed, a conductive channel 207 is formed in the conductive channel hole 204.

[0066] In an exemplary embodiment, the sacrificial layer 202 is replaced with the gate layer 208. Specifically, this replacement step includes: removing the sacrificial layer 202 to form a sacrificial space; forming a second high-dielectric layer 211 in the sacrificial space; and forming the gate layer 208 in the sacrificial space. Understandably, the prefabricated stacked structure 2 is transformed into a stacked structure 20, which also means that the prefabricated step structure 21 is transformed into a step structure 21', and the prefabricated memory structure 22 is transformed into a memory structure 220. Figure 17 As shown, the gate layer 208 and the insulating layer 201, as well as the gate layer 208 and the channel structure 24, are separated by a second high-dielectric layer 211. This embodiment improves the dielectric strength between the gate layer 208 and the surrounding structures by providing a second high-dielectric layer 211 surrounding the gate layer 208. This embodiment does not exclude the possibility of providing a first high-dielectric layer in the channel structure 24. For example, the sacrificial portion 203 and the first insulating portion 206a are replaced with a conductive portion 210. (See reference...) Figure 18 The sacrificial portion 203 and the first insulating portion 206a can be removed. After removing the sacrificial portion 203 and the first insulating portion 206a, a portion of the uppermost second high-dielectric layer 211 of each step 21' is exposed. Based on this, the exposed portion of the uppermost second high-dielectric layer 211 of each step 21' can be removed to obtain the replacement space 209. Figure 18 Conductive material can be filled into the space formed after the removal of the sacrificial portion 203, the first insulating portion 206a, and a portion of the second high-dielectric layer 211, to form the conductive portion 210. Figure 19Specifically, when the material of the sacrificial portion 203 and the material of the first insulating portion 206a are the same, both can be removed to form a replacement space 209, and a conductive portion 210 is formed in the replacement space 209. For example, when the sacrificial portion 203 is removed to form the replacement space 209, the second high-dielectric layer 211 at the edge of the sacrificial portion 203 is also etched, thereby exposing the gate layer 208 to the replacement space 209.

[0067] like Figure 19 As shown, the conductive part 210 electrically connects the conductive channel 207 to the gate layer 208 at the stepped surface to which the conductive channel 207 is connected.

[0068] According to the method for manufacturing a three-dimensional storage structure provided in this disclosure, subsequent processes such as back-end processes can be carried out, and the manufactured three-dimensional storage structure can be a 3D NAND type three-dimensional storage structure.

[0069] like Figure 20A and Figure 20B As shown, this disclosure also provides a three-dimensional storage structure. Figure 20A or Figure 20B The arrangement of the three-dimensional storage structure shown is merely illustrative and can be modified as needed during actual processing and use. This three-dimensional storage structure includes: a stacked structure 20, a conductive portion 210, an insulating portion 206, and a conductive channel 207.

[0070] Exemplarily, the three-dimensional storage structure also includes a semiconductor layer 1'. The stacked structure 20 includes a stepped structure 21' and a storage structure 220 arranged side by side in the x-direction parallel to the semiconductor layer 1', with the steps of the stepped structure 21' facing away from the semiconductor layer 1'.

[0071] The conductive channel 207 penetrates the semiconductor layer 1' and the step structure 21'. The conductive portion 230 may be located at the step surface of the step structure 21'. Specifically, the conductive portion 230 is electrically connected to the gate layer 208 furthest from the semiconductor layer 1' in the step, thereby electrically connecting the conductive channel 207 at the connected step surface to the gate layer 208.

[0072] The three-dimensional storage structure provided in this disclosure can have a large number of stacked layers. There is no need to set virtual channel structure between multiple adjacent conductive channels. Instead, the conductive channels and multiple insulating parts support the stacked structure, which can greatly alleviate the problem of insufficient process window between conductive channels.

[0073] Exemplarily, the stacked structure 20 includes alternately stacked gate layers 208 and insulating layers 201. The three-dimensional memory structure includes insulating portions 206 located between the gate layers 208 and the conductive channel 207. Exemplarily, in the extending direction of the conductive channel 207, any two adjacent insulating portions 206 are spaced apart by the insulating layer 201. Exemplarily, a high-dielectric layer may be disposed between the channel structure 24 and the gate layer 208.

[0074] For example, the channel structure 24 may include, from the inside to the outside, a channel layer 242, a tunneling layer 243, a charge trapping layer 244, a barrier layer 245, and a first high-dielectric layer 246, arranged sequentially from the inside to the outside along the radial direction (i.e., the X direction) of the channel structure. Alternatively, in another embodiment, the channel structure 24 may include, from the inside to the outside, a channel layer 242, a tunneling layer 243, a charge trapping layer 244, and a barrier layer 245, arranged sequentially from the inside to the outside along the radial direction (i.e., the X direction) of the channel structure. For example, an insulating core layer 241 may also be provided inside the channel layer 242.

[0075] For example, such as Figure 20B As shown, the conductive portion 230 may include a first conductive portion 230A and a second conductive portion 230B. The first conductive portion 230A may be located on the side of the stepped structure 21' furthest from the semiconductor layer 1'. The second conductive portion 230B may be adjacent to the first conductive portion 230A and may be located between the gate layer 208 and the conductive channel 207. Exemplarily, the maximum dimension H1 of the first conductive portion 230A in the direction parallel to the semiconductor layer 1' (e.g., the X direction) may be greater than the maximum dimension H2 of the second conductive portion 230B in the direction parallel to the semiconductor layer 1'.

[0076] Exemplarily, the three-dimensional memory structure of this disclosure further includes at least two gate line gap partition structures (not shown). The gate line gap partition structures extend through the stacked structure 20, and specifically, they may be fabricated by a back-side process. The conductive portion 210 extends to at least one gate line gap partition structure in a direction parallel to the semiconductor layer 1' (e.g., perpendicular to the x-direction).

[0077] Embodiments of this disclosure also provide a storage device. For example... Figure 21 As shown, the storage device 3 includes at least one three-dimensional memory 31 and peripheral circuitry 32. The three-dimensional memory 31 may include the aforementioned three-dimensional storage structure. The peripheral circuitry 32 is used to control the three-dimensional memory 31 and is specifically electrically connected to the three-dimensional storage structure.

[0078] Peripheral circuitry 32 and at least one three-dimensional memory 31 can be integrated into the memory card. The memory card may include PC cards (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), Universal Flash Memory (UFS), etc. The memory card may also include a connector 33 that couples the memory card to a host (not shown).

[0079] In another example, peripheral circuitry 32 and at least one three-dimensional memory 31 may be integrated into a solid-state drive (SSD). The SSD may also include a connector 33 that couples the SSD to a host (not shown). In some embodiments, the storage capacity and / or operating speed of the SSD is higher than that of the memory card.

[0080] Embodiments of this disclosure also provide a storage system. For example... Figure 22 As shown, the storage system 4 may include a storage device 3 and a storage controller 41 coupled to the storage device 3. The storage device 3 may be the same as the storage device described in any of the embodiments above, and will not be described again in this application.

[0081] The storage controller 41 is coupled to the three-dimensional memory 31 in the storage device 3 via channel CH to control the three-dimensional memory 31 to store data. The three-dimensional memory 31 receives commands CMD and addresses ADDR from the storage controller 41 via channel CH and accesses the region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 31 can perform internal operations corresponding to commands on the region selected by the address.

[0082] In some implementations, the storage system 4 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card or Memory Stick, etc.

[0083] Figure 23 This is a schematic structural diagram of the electronic device 5 provided in the embodiments of this disclosure.

[0084] like Figure 23As shown, at least one embodiment of this application also provides an electronic device 5. The electronic device 5 includes a storage system 4. The storage system 4 may be the same as the storage system described in any of the embodiments above, and will not be repeated here. The electronic device 5 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage functionality. Therefore, other modules of the electronic device 5, such as a controller, can be determined according to the specific device type of the electronic device 5. Other modules can be coupled to the storage system 4 via channels, etc., and interact with the storage system 4.

[0085] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this disclosure.

Claims

1. A method for manufacturing a three-dimensional storage structure, characterized in that, include: A prefabricated stepped structure comprising alternating stacked insulating and sacrificial layers is formed on the first side of the substrate; A sacrificial portion is formed on each step of the prefabricated stepped structure, wherein the sacrificial portion is disposed adjacent to the uppermost sacrificial layer of each step, and there is etching selectivity between the sacrificial portion and the sacrificial layer; A conductive channel hole is formed on the second side of the substrate, wherein the conductive channel hole extends from the second side of the substrate through the substrate and the prefabricated stepped structure in sequence, and extends to the sacrificial portion; the second side of the substrate is the side opposite to the first side of the substrate; Multiple expansion spaces are formed by etching a portion of the sacrificial layer through the conductive channel holes; The conductive channel holes are spaced apart from the sacrificial layer by filling the plurality of expansion spaces with insulating material, wherein the step of filling the insulating material forms a plurality of insulating portions, the plurality of insulating portions including a first insulating portion located at the top of each of the steps; A conductive channel is formed by filling the conductive channel hole with a conductive material. Replace the sacrificial layer with a gate layer; and The sacrificial portion and the first insulating portion are replaced with conductive portions.

2. The method according to claim 1, wherein, In the extending direction of the conductive channel hole, adjacent expansion spaces are separated by the insulating layer.

3. The method according to claim 1, wherein, The insulating part is made of the same material as the sacrificial part.

4. The method according to claim 1, wherein, The method further includes: Forming grid line slots that penetrate the prefabricated stepped structure; The step of replacing the sacrificial layer with the gate layer includes: replacing the sacrificial layer with the gate layer through the gate line slot. The step of replacing the sacrificial portion with the conductive portion includes: replacing the sacrificial portion with the conductive portion through the gate wire slot.

5. The method according to claim 1, wherein, The method further includes: An insulating filler is formed on the prefabricated stepped structure and the sacrificial portion.

6. The method according to claim 3, wherein, Forming a prefabricated stepped structure comprising alternating stacked insulating and sacrificial layers on the first side of the substrate includes: A prefabricated stacked structure comprising alternating stacked insulating and sacrificial layers is formed on the substrate, wherein the prefabricated stacked structure is divided into stepped regions and storage regions in a direction parallel to the substrate. The portion of the prefabricated laminated structure located in the stepped area is formed as the prefabricated stepped structure.

7. The method according to claim 6, wherein, The method further includes: A channel structure is formed in the storage area that penetrates the prefabricated stacked structure, wherein the channel structure includes, in order from the inside to the outside along the radial direction of the channel structure: a channel layer, a tunneling layer, a charge trapping layer, a barrier layer, and a first high dielectric layer.

8. The method according to claim 7, wherein, The step of replacing the sacrificial layer with the gate layer includes: The sacrificial layer is removed to form a sacrificial space; A second high-dielectric layer and the gate layer are formed in the sacrificial space, wherein the gate layer is separated from the insulating layer and from the channel structure by the second high-dielectric layer.

9. The method according to claim 8, wherein, The step of replacing the sacrificial portion and the first insulating portion with the conductive portion includes: Remove the sacrificial portion and the first insulating portion; Remove the exposed portion of the second high-dielectric layer at the top of each step; and The conductive portion is formed by filling the space created after removing the sacrificial portion, the first insulating portion, and a portion of the second high-dielectric layer that has been exposed with conductive material.

10. A three-dimensional storage structure, characterized in that, include: Semiconductor layer; A stacked structure comprising gate layers and insulating layers alternately stacked in a direction away from the semiconductor layer, wherein, in a direction parallel to the semiconductor layer, the stacked structure includes a memory region and a step region having multiple steps; A conductive portion is located on the side of the step away from the semiconductor layer, and one of the conductive portions is electrically connected to a portion of a target gate layer located at the step; A conductive channel extends through the semiconductor layer and the step region, wherein one conductive channel is electrically connected to a corresponding conductive portion, and the conductive channel comprises a conductive material; and An insulating portion is located between the gate layer and the conductive channel that are not electrically connected to the corresponding conductive portion. The conductive part includes: A first conductive portion is located on the step; and The second conductive portion is located between the target gate layer and the corresponding conductive channel, wherein the first conductive portion is in contact with the second conductive portion, and the second conductive portion is in direct contact with the conductive material in the conductive channel.

11. The three-dimensional storage structure according to claim 10, wherein, In the extending direction of the conductive channel, two adjacent insulating portions are spaced apart by the insulating layer.

12. The three-dimensional storage structure according to claim 10, wherein, The three-dimensional storage structure also includes: The channel structure, penetrating the stacked structure, includes, in a radial direction from the inside out, the following layers arranged sequentially: a channel layer, a tunneling layer, a charge trapping layer, a barrier layer, and a first high-dielectric layer.

13. The three-dimensional storage structure according to claim 10, wherein, The maximum dimension of the first conductive portion in the direction parallel to the semiconductor layer is greater than the maximum dimension of the second conductive portion in the direction parallel to the semiconductor layer.

14. The three-dimensional storage structure according to claim 10, wherein, Also includes: The channel structure, penetrating the stacked structure, includes, in order of radial arrangement from the inside to the outside of the channel structure: a channel layer, a tunneling layer, a charge trapping layer, and a barrier layer; as well as The second high dielectric layer is located between the gate layer and the insulating layer, and between the gate layer and the channel structure.

15. The three-dimensional storage structure according to claim 10, wherein, The three-dimensional storage structure also includes: A grid line slot partition structure that extends through the stacked structure along the alternating stacking direction.

16. The three-dimensional storage structure according to claim 10, wherein, In cross-sections along the directions perpendicular to and parallel to the semiconductor layer of the first conductive portion and the second conductive portion, the dimension of the first conductive portion in the direction parallel to the semiconductor layer is larger than the dimension of the second conductive portion in the direction parallel to the semiconductor layer.

17. A storage device, characterized in that, include: The three-dimensional storage structure as described in any one of claims 10 to 16, and the peripheral circuit structure electrically connected to the three-dimensional storage structure.

18. A storage system, characterized in that, include: The storage device of claim 17, and a storage controller coupled to the storage device, wherein the storage controller is configured to control the storage device to store data.

19. An electronic device, characterized in that, include: The storage system of claim 18.

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