Method for manufacturing memory device, memory device, and memory system

Abstract

The present application relates to a manufacturing method of a memory device, a memory device and a memory system. The manufacturing method comprises: providing a semiconductor structure, the semiconductor structure comprising a stack layer, the stack layer comprising alternately stacked sacrificial layers and dielectric layers, the semiconductor structure having opposite front and back surfaces; forming a gate layer in the stack layer; forming a plurality of first contact holes and a plurality of second contact holes into the semiconductor structure from the front and back surfaces of the semiconductor structure respectively, each of the first and second contact holes penetrating through a plurality of layers in the stack layer to reach the gate layer to a respective predetermined depth, the plurality of first contact holes and the plurality of second contact holes being located in a first region and a second region respectively, a projection of the first region and the second region along a stacking direction of the stack layer having an overlapping portion. The present application has the advantages of reducing the number of layers of the stack layer to be etched for forming the contact holes and saving the area of the step region for forming the contact holes.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a memory device and a method for manufacturing the same, as well as a system including the memory device. Background Technology

[0002] With the continuous development of 3D NAND technology, the number of layers that can be vertically stacked in memory devices is increasing, from 24 layers, 32 layers, 64 layers to high-order stacking layers exceeding 400 layers. Increasing the number of stacking layers can significantly improve storage density and reduce the price per unit of memory cell. 3D NAND flash memory consists of a core region and a stairstep (SS) region. The core region is used to form multiple memory strings, each containing multiple memory cells. The stairstep region is used to bring out contact structures from the word lines of each layer. The core region also includes contact structures extending from the top of the memory strings. These contact structures are connected to a controller, allowing control of the memory cells to perform operations such as programming, reading, and erasing / writing.

[0003] When forming a contact structure in the step region, the stacked layer needs to be etched to obtain multiple contact holes reaching their respective predetermined depths, and multiple contact structures that are electrically in contact with the gate layer at the predetermined depth are formed through the aforementioned multiple contact holes. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a method for manufacturing a memory device that can reduce the depth of the contact hole and save the area of ​​the semiconductor structure used to form the contact hole, as well as a memory device and system having a shallow contact structure and a small area occupied by the contact structure.

[0005] The technical solution adopted in this application to solve the above-mentioned technical problems is to provide a method for manufacturing a memory device, comprising: providing a semiconductor structure, the semiconductor structure including a stacked layer, the stacked layer including alternately stacked sacrificial layers and dielectric layers, the semiconductor structure having opposing front and back sides; removing the sacrificial layers in the stacked layer, and filling the gaps formed after removing the sacrificial layers with conductive material to form a gate layer; forming a plurality of first contact holes from the front side of the semiconductor structure toward the semiconductor structure, each first contact hole penetrating through several layers in the stacked layer to reach the gate layer at a respective predetermined depth, the plurality of first contact holes being located in a first region of the semiconductor structure; and forming a plurality of second contact holes from the back side of the semiconductor structure toward the semiconductor structure, each second contact hole penetrating through several layers in the stacked layer to reach the gate layer at a respective predetermined depth, the plurality of second contact holes being located in a second region of the semiconductor structure, wherein the projections of the first region and the second region along the stacking direction of the stacked layer overlap.

[0006] In one embodiment of this application, before forming a plurality of second contact holes from the back side of the semiconductor structure into the semiconductor structure, a first contact structure is formed in the plurality of first contact holes, each of the first contact structures being electrically contacted with the gate layer at a predetermined depth.

[0007] In one embodiment of this application, after forming the plurality of second contact holes from the back side of the semiconductor structure into the semiconductor structure, the method further includes forming second contact structures in the plurality of second contact holes, each of the second contact structures being electrically contacted with the gate layer at a respective predetermined depth.

[0008] In one embodiment of this application, the first contact structure and the second contact structure electrically contact different gate layers.

[0009] In one embodiment of this application, the step of forming the first contact structure in the plurality of first contact holes includes: forming an insulating layer on the sidewall and bottom of the first contact hole; removing the insulating layer at the bottom of the first contact hole to expose the gate layer; and filling the inner side of the insulating layer of the first contact hole with a conductive material, wherein the conductive material is in electrical contact with the exposed gate layer.

[0010] In one embodiment of this application, the step of forming the second contact structure in the plurality of second contact holes includes: forming an insulating layer on the sidewall and bottom of the second contact hole; removing the insulating layer at the bottom of the second contact hole to expose the gate layer; and filling the inner side of the insulating layer of the second contact hole with a conductive material, wherein the conductive material is in electrical contact with the exposed gate layer.

[0011] In one embodiment of this application, the plurality of second contact holes are aligned with the plurality of first contact holes in the stacking direction of the stacked layer.

[0012] In one embodiment of this application, before forming the plurality of first contact holes, the method further includes: forming a first hard mask layer on the stacked layer; covering the first hard mask layer with a first photoresist; and patterning the first hard mask layer with the first photoresist to form a plurality of first openings reaching the top gate layer in the gate layer.

[0013] In one embodiment of this application, the step of forming the plurality of first contact holes includes: coating a second photoresist on a first hard mask layer; cyclically performing the steps of trimming the second photoresist in a first direction, exposing a predetermined number of first openings, and etching a predetermined number of stacked layers through the exposed first openings, thereby forming the plurality of first contact holes using the plurality of first openings.

[0014] In one embodiment of this application, before forming the plurality of second contact holes, the method further includes: forming a second hard mask layer on the stacked layer; covering the second hard mask layer with a third photoresist; and patterning the second hard mask layer with the third photoresist to form a plurality of second openings reaching the top gate layer in the gate layer.

[0015] In one embodiment of this application, the step of forming the plurality of second contact holes includes: coating a fourth photoresist on the second hard mask layer; cyclically performing the steps of trimming the fourth photoresist in a first direction, exposing a predetermined number of second openings, and etching a predetermined number of stacked layers through the exposed second openings, thereby forming the plurality of second contact holes using the plurality of second openings.

[0016] In one embodiment of this application, a first interconnect layer is formed on the front side of the semiconductor structure.

[0017] In one embodiment of this application, the first interconnect layer is a first interconnect layer of a subsequent process.

[0018] In one embodiment of this application, a complementary metal-oxide-semiconductor circuit is formed on the first interconnect layer of the subsequent process.

[0019] To address the aforementioned problems, this application also provides a memory device, comprising: a stacked structure including alternately stacked gate layers and dielectric layers; a plurality of first contact structures, each first contact structure penetrating through several layers in the stacked structure to reach a gate layer at a predetermined depth, the plurality of first contact holes being located in a first region of the stacked structure; and a plurality of second contact structures, each second contact structure penetrating through several layers in the stacked structure to reach a gate layer at a predetermined depth, the plurality of second contact structures being located in a second region of the stacked structure, wherein the projections of the first region and the second region along the stacking direction of the stacked structure overlap.

[0020] In one embodiment of this application, the plurality of first contact structures are aligned with the plurality of second contact structures in the stacking direction of the stacked structure.

[0021] In one embodiment of this application, the depth variation trend of the first contact structure along the first direction is the same as the depth variation trend of the second contact structure along the first direction.

[0022] In one embodiment of this application, the depth variation trend of the first contact structure along the first direction is opposite to the depth variation trend of the second contact structure along the first direction.

[0023] In one embodiment of this application, a first interconnect layer located on one side of the stacked structure is also included.

[0024] In one embodiment of this application, the first interconnect layer is the first interconnect layer of the subsequent process.

[0025] In one embodiment of this application, a complementary metal-oxide-semiconductor circuit is also included on the first interconnect layer of the subsequent process.

[0026] To address the aforementioned problems, this application also provides a memory system comprising a memory device as described above, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

[0027] This application forms a first contact hole and a second contact hole to a predetermined depth inside the semiconductor structure, starting from the front and back sides respectively. Simultaneously, the projections of the first region containing the first contact structure and the second region containing the second contact structure in the stacking direction of the stacked layers overlap. This offers advantages such as fewer etching layers required for the stacked layers, a larger etching process window, and reduced area occupied by the contact holes. Attached Figure Description

[0028] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application; Figure 2A-2K This is a schematic cross-sectional view of a memory device in a manufacturing method according to an embodiment of this application; Figures 3A-3C This is a top view schematic diagram of a memory device in a manufacturing method according to an embodiment of this application; Figures 4A-4C This is a schematic cross-sectional view of a memory device in a manufacturing method according to an embodiment of this application; Figure 5A-5I This is a schematic cross-sectional view of a memory device in a manufacturing method according to an embodiment of this application; Figures 6A-6D This is a cross-sectional structural schematic diagram of a memory device according to an embodiment of this application. Detailed Implementation

[0029] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0030] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.

[0031] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0032] In detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0033] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0034] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this application.

[0036] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0037] As used herein, "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0038] As used in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0039] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0040] In the fabrication of semiconductor devices (such as 3D NAND), to connect the contact structure to word lines at a predetermined depth, an etching process is first used to form contact holes reaching the predetermined word line layer, and then the contact holes are filled to form the contact structure. As the number of 3D NAND layers increases, the depth of the contact holes also increases, placing very high demands on the etching process. The increased contact hole depth leads to a smaller etching process window, making it difficult to etch ideal contact holes. Furthermore, as the number of 3D NAND layers increases, the area of ​​the step region required to form the etched holes from one side of the semiconductor structure also increases, resulting in a larger memory device size.

[0041] The manufacturing method of the memory device in this application will be described below through specific implementation.

[0042] Figure 1 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application. (See reference...) Figure 1 As shown, the manufacturing method of this embodiment includes the following steps: Step S110: Provide a semiconductor structure including stacked layers, the stacked layers including alternately stacked sacrificial layers and dielectric layers, the semiconductor structure having opposing front and back sides; Step S120: Remove the sacrificial layer in the stacked layers, and fill the voids formed after removing the sacrificial layer with conductive material to form a gate layer; Step S130: A plurality of first contact holes are formed from the front side of the semiconductor structure into the semiconductor structure. Each first contact hole penetrates several layers in the stacked layers and reaches the gate layer at a predetermined depth. The plurality of first contact holes are located in the first region of the semiconductor structure. Step S140: A plurality of second contact holes are formed from the back side of the semiconductor structure into the semiconductor structure. Each second contact hole penetrates several layers in the stacked layers and reaches the gate layer at a predetermined depth. The plurality of second contact holes are located in the second region of the semiconductor structure, wherein the projections of the first region and the second region along the stacking direction of the stacked layers overlap.

[0043] Figure 2A-2K Images 4A-4C and 5A-5I are cross-sectional structural diagrams of a memory device in a manufacturing method according to an embodiment of this application; images 3A-3C are top views of a memory device according to an embodiment of this application; and images 6A-6D are cross-sectional structural diagrams of a memory device according to an embodiment of this application. Figure 2D , 2F 2H are respectively Figure 3A , 3B 3C cross-sectional view along the dotted line. Next, refer to the attached... Figure 2A-6D Steps S110-S140 are described in detail.

[0044] refer to Figure 2A As shown, in step S110, a semiconductor structure 100 is provided, which includes a stacked layer 110, comprising alternately stacked sacrificial layers 111 and dielectric layers 112. The materials of the sacrificial layers 111 and 112 include silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and combinations thereof. The sacrificial layers 111 and 112 have different etching selectivity ratios. For example, the sacrificial layers 111 and 112 can be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon. The methods for forming the sacrificial layers 111 and 112 include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and other methods.

[0045] In some embodiments of this application, the semiconductor structure 100 further includes a semiconductor layer 120. A stacked layer 110 is formed on the semiconductor layer 120. The bottom of the stacked layer 110, which is in contact with the semiconductor layer 120, is a dielectric layer 112.

[0046] In some embodiments, the semiconductor layer 120 may be a substrate. The substrate may include a silicon substrate (Si), a germanium substrate (Ge), a silicon germanide substrate (SiGe), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The materials may be doped or undoped, such as being doped with p-type or n-type dopants. In some embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It may also be a stacked structure, such as Si / SiGe. Other epitaxial structures may also be included, such as silicon-germanium-on-insulator (SGOI), etc.

[0047] In some embodiments of this application, the substrate material is, for example, silicon. The sacrificial layer 111 and the dielectric layer 112 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, silicon nitride and silicon oxide can be alternately deposited on the substrate sequentially using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stacked layer 110.

[0048] refer to Figure 2A As shown, the semiconductor structure has a third region 130 and a fourth region 140 distributed adjacent to each other along the first direction D1. This application does not limit the size or position of the third region 130 and the fourth region 140. For example, the third region 130 is the core region of the semiconductor structure, and the fourth region 140 is the word line connection region of the semiconductor structure.

[0049] refer to Figure 2A As shown, the third region 130 and the fourth region 140 include a channel structure 113 penetrating the stacked layer 110. The channel structure 113 may include a memory layer and a channel layer. Overall, the channel structure 113 includes a channel aperture, and the memory layer and the channel layer are arranged sequentially from the outside to the inside along the radial direction of the channel aperture. The memory layer may include a barrier layer, a charge trapping layer, and a tunneling layer arranged sequentially from the outside to the inside along the radial direction of the channel aperture. A filler layer may also be provided within the channel layer. The filler layer can act as a support. The material of the filler layer may be silicon oxide. The filler layer may be solid or hollow without affecting the device reliability. The vertical channel structure can be formed using one or more thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0050] In embodiments where the memory device is 3D NAND, the third region 130 includes a word line connection region, and the fourth region 140 includes a core memory region. The channel structure in the fourth region 140 constitutes a memory string. The channel structure in the third region 130 is a virtual channel structure that provides support. In some embodiments, the channel structure in the third region 130 differs from the channel structure in the fourth region 140. For example, the channel structure in the third region 130 may have a fill layer but no memory layer or channel layer.

[0051] In some embodiments disclosed in this application, a first dielectric layer and a second dielectric layer are sequentially formed on top of the stacked layers. (See reference...) Figure 2B As shown, a first dielectric layer 150 is provided on top of the stacked layer 110, and a second dielectric layer 160 covers the first dielectric layer 150 and covers the channel structure 113. In some embodiments, the material of the second dielectric layer 160 includes one or more of silicon oxide (SiO2), silicon oxynitride, aluminum oxide (Al2O3), and titanium nitride. For example, the material of the second dielectric layer 160 is silicon oxide (SiO2). The deposition method for forming the second dielectric layer 160 includes various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Referring to FIG3, in this embodiment, the second dielectric layer 160 uses the same material as the first dielectric layer 150 to avoid internal stress caused by the difference in thermal expansion coefficients, and the same pattern is used for identification in subsequent figures.

[0052] Forming a second dielectric layer on top of the stacked layers can prevent damage to the channel structure 113 due to subsequent process steps (such as chemical mechanical polishing, CMP).

[0053] refer to Figure 2A and Figure 2B As shown, in step S120, the sacrificial layer 111 in the stacked layer 110 is removed, and the void formed after removing the sacrificial layer 111 is filled with conductive material to form the gate layer 114.

[0054] In some embodiments of this application, the step of removing the sacrificial layer in the stacked layer and filling the void formed after removing the sacrificial layer with conductive material to form a gate layer includes: forming a gate line slot through the stacked layer along a first direction D1; removing the sacrificial layer in the stacked layer through the gate line slot; and filling the void formed after removing the sacrificial layer with conductive material to form a gate layer.

[0055] The specific process is as follows: A gate line slot (not shown) is formed along the first direction D1, penetrating the stacked layer. The sacrificial layer 111 in the stacked layer 110 is removed through the gate line slot. The void formed after removing the sacrificial layer 111 is filled with conductive material to form the gate layer 114. In some embodiments of this application, the gate line slot can extend all the way to the substrate 120 in a direction perpendicular to the substrate 120. The gate line slot has an elongated shape and is also referred to as a slit. The sacrificial layer 111 in the stacked layer 110 can be completely removed through the gate line slot. In this case, the sacrificial layer 111 serves as the gate sacrificial layer. Conductive material is then filled into the void formed after removing the sacrificial layer 111 using semiconductor processes to form the gate layer 114. This results in a structure in the stacked layer 110 that includes alternating stacked gate layers 114 and dielectric layers 112. For example, the sacrificial layer 111 is removed using a wet etching process. The material of the gate layer 114 can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or it can be polysilicon, doped silicon, or any combination thereof. In 3D NAND, gate layer 114 can serve as word lines for three-dimensional memory.

[0056] In some embodiments of this application, when the second dielectric layer 160 is not present on top of the stacked layer, the second dielectric layer 160 is formed on the first dielectric layer 150 on top of the stacked layer before the sacrificial layer in the stacked layer is removed.

[0057] refer to Figures 2C to 2J As shown, in step S130, a plurality of first contact holes 220 are formed from the front side of the semiconductor structure 100 into the semiconductor structure 100. Each first contact hole 220 penetrates several layers in the stacked layers to reach a gate layer at a predetermined depth. The plurality of first contact holes 220 are located in the first region 230 of the semiconductor structure. It should be noted that the front side of the semiconductor structure 100 refers to... Figure 2D The upper surface of the semiconductor structure 100 is placed in the middle. It can be understood that when the top layer structure or material of the semiconductor structure 100 changes, the upper surface of the semiconductor structure 100 will also change accordingly. In short, "forming a plurality of first contact holes 220 from the front side of the semiconductor structure 100 into the semiconductor structure 100" means forming the first contact holes 220 from the top of the semiconductor structure 100 into the interior of the semiconductor structure 100. Here, the first region 230 of the semiconductor structure 100 is a three-dimensional region near the front side of the semiconductor structure 100, and the first region 230 is located in the third region 130.

[0058] In one embodiment of this application, the steps prior to forming a plurality of first contact holes include: forming a hard mask layer on a stacked layer; covering the hard mask layer with a first photoresist; and patterning the hard mask layer with the first photoresist to form a plurality of first openings reaching the top gate layer in the gate layer.

[0059] refer to Figure 2C As shown, firstly, a hard mask layer 170 is formed on the surface of the second dielectric layer 160 located above the stacked layer 110. The material of the hard mask layer 170 includes aluminum oxide (Al2O3) and silicon oxynitride (SiO2). x N y The deposition methods for forming the hard mask layer 170 include various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0060] refer to Figure 2D and 3A As shown, a first photoresist layer 180 is then applied over the hard mask layer 170. The first photoresist layer 180 covers the third region 130 and the fourth region 140. The first photoresist layer 180 is patterned to form a mask for etching a plurality of first openings.

[0061] Continue to refer to Figure 2E As shown, a hard mask layer 170 is then patterned using a patterned first photoresist 180 as a mask to form a plurality of first openings 190 within a first region 230 that extend to the top gate layer 114 in the stacked layer 110. After forming the plurality of first openings 190, the first photoresist 180 is removed.

[0062] In one embodiment of this application, the step of forming a plurality of first contact holes includes: coating a second photoresist on a hard mask layer; cyclically performing the steps of trimming the second photoresist in a first direction, exposing a predetermined number of first openings, and etching a predetermined number of stacked layers through the exposed first openings, thereby forming a plurality of first contact holes using the plurality of first openings.

[0063] Figures 2F to 2J The manufacturing process described above is illustrated by way of example. (Reference) Figure 2F As shown, firstly, a second photoresist 210 is applied to the hard mask layer 170. It should be noted that when applying the second photoresist 210, the second photoresist 210 can cover the entire surface of the hard mask layer 170, or cover only a portion of the hard mask layer 170 within the first region 230. Figure 2F The reason why the second photoresist 210 shown does not cover the leftmost first opening 190a is that... Figure 2F The second photoresist 210 shown has been trimmed to expose the first opening 190a on the left side.

[0064] In the cyclical trimming-etching steps, Figure 2F The diagram shows the initial step of this cycle, where the second photoresist 210 is trimmed in the first direction D1 to expose a predetermined number of first openings 190. Combined with... Figure 3BAs shown in the top view of the semiconductor device 100, the leftmost column of first openings 190a is exposed.

[0065] refer to Figure 2G As shown, a predetermined number of stacked layers are etched beneath the first exposed opening 190a. Figure 2G In this embodiment, the predetermined number of layers is two, namely a gate layer 114 and a dielectric layer 112. After etching, the depth of the exposed first opening 190a increases downwards, reaching the gate layer 115a. It should be noted that the first opening 190a reaching the gate layer 115a means that, through controlled etching of the stacked layers, the gate layer 114 and dielectric layer 112 are etched, but the gate layer 115a is not etched. Due to the influence of the etching process, a portion of the thickness of the upper surface of the gate layer 115a reached by the first opening 190a may be etched. Therefore, the exposed first opening 190a may reach the interior of the gate layer 114a, but not penetrate the gate layer 114a. This paragraph describes other opening structures applicable to this application.

[0066] This application does not impose any restrictions on the number of predetermined layers.

[0067] refer to Figure 2H As shown, after etching the stacked layer through the first opening 190a, the second photoresist 210 is modified again to expose the first opening 190b adjacent to the first opening 190a. (Reference) Figure 3C The top view shown exposes a column of first openings 190b adjacent to the column containing the first opening 190a.

[0068] refer to Figure 2I As shown, the stacked layers below are simultaneously etched through the exposed first openings 190a and 190b, which represent a predetermined number of layers. After etching, the depth of the first opening 190a increases downward to the gate layer 115B, and the depth of the first opening 190b also increases downward to the gate layer 114b.

[0069] Figure 2F-2I This illustrates an example of the initial steps of a trim-etch cycle. As the trim-etch steps continue, the second photoresist 210 is progressively modified, gradually increasing the number of exposed first openings 190, until the exposed first openings are used to etch out an image as shown. Figure 2J The plurality of first contact holes 220 are shown. Among them, those located in... Figure 2JIn this embodiment, the depth of the leftmost first contact hole 220a reaches the gate layer 114c in the stacked layer 110, and the depth of the rightmost first contact hole 220b reaches the gate layer 114d at the top of the stacked layer 110. Furthermore, from left to right, the depths of the plurality of first contact holes 220 decrease sequentially, each reaching its predetermined depth in the gate layer 114, and the plurality of first contact holes 220 form a series of first contact holes with progressively decreasing depths along the first direction D1.

[0070] refer to Figure 2J As shown, it should be noted that in Figure 2J In the embodiment, the depth of the leftmost first contact hole 220a reaches the gate layer 114c. The gate layer 114c reached by the leftmost first contact hole 220a in this application is not limited to... Figure 2J The gate layer 114c is located in the first contact hole 220a. In some other embodiments of this application, the gate layer 114 reached by the first contact hole 220a may be a gate layer located above or below the gate layer 114c.

[0071] Before etching to form multiple contact holes, this application replaces the sacrificial layer-dielectric layer with a lower etching selectivity with the gate layer-dielectric layer with a higher etching selectivity by removing the sacrificial layer in the stacked layer and filling the gap formed by removing the sacrificial layer with the gate layer before the sacrificial layer is removed. This allows the first contact hole and the second contact hole (described later) to accurately reach the predetermined gate layer.

[0072] refer to Figure 2J As shown, after forming a plurality of first contact holes 220, the hard mask layer 170 is removed.

[0073] refer to Figures 5A-5D As shown, in step S140, a plurality of second contact holes 240 are formed from the back side of the semiconductor structure 100 into the semiconductor structure 100. Each second contact hole 240 penetrates several layers in the stacked layers 100 and reaches a gate layer 114 at a predetermined depth. The plurality of second contact holes 240 are located in the second region 250 of the semiconductor structure 100. Here, the second region 250 is a three-dimensional region in the semiconductor structure 100 near the back side, and the second region 250 is located in the third region 130. The projections of the first region 230 and the second region 250 along the stacking direction of the stacked layers 110 overlap. It can be understood that the back side of the semiconductor structure 100 refers to the surface opposite to the aforementioned front side along the stacking direction of the stacked layers 110. Figure 5A The semiconductor structure 100 shown is relative to Figure 2A The semiconductor structure 100 shown is flipped upside down, so the back side of the semiconductor structure 100 mentioned in step S140 refers to... Figure 5AThe semiconductor structure shown is located above the front side. Furthermore, the back side and front side in this application can be interchanged.

[0074] It should be noted that the overlapping projections of the first region 230 and the second region 250 along the stacking direction of the stacked layers mean that, firstly, the first region 230 and the second region 250 refer to the regions where the first contact hole and the second contact hole are located, respectively. These regions are not infinitely large or simply large regions containing either the first or second contact hole. For example, the first region is preferably a region containing the first contact hole and whose boundary is as close as possible to the distance between its boundary and the peripheral first contact hole. The concept of the second region is the same and will not be elaborated further. Next, the overlapping projections of the first region and the second region have the following effect on the positional relationship between the first and second contact holes: at least some of the extension lines of the first and second contact holes overlap or intersect in the stacking direction.

[0075] In the above embodiments, a first contact hole and a second contact hole, reaching a predetermined depth, are formed inside the semiconductor structure from the front and back sides, respectively. The projections of the first region containing the first contact structure and the second region containing the second contact structure in the stacking direction of the stacked layers overlap. The first contact hole and the second contact hole are respectively close to the outermost gate layer in the stacked layers along the stacking direction. Compared with forming contact holes from one side of the semiconductor structure, forming contact holes from the front and back sides reduces the number of stacked layers required to form contact holes, increases the etching process window, and also saves the area occupied by the contact holes.

[0076] refer to Figure 5A and Figure 5I As shown, before forming a plurality of second contact holes 240 from the back side of the semiconductor structure 100 into the semiconductor structure 100, the method further includes forming a first contact structure 260 in a plurality of first contact holes 220, each first contact structure 260 being electrically contacted with a gate layer 114 at a predetermined depth.

[0077] In one embodiment of this application, the step of forming a first contact structure in a plurality of first contact holes includes forming an insulating layer on the sidewall and bottom of the first contact hole; removing the insulating layer at the bottom of the first contact hole to expose the gate layer; and filling the inner side of the insulating layer of the first contact hole with a conductive material, wherein the conductive material is in electrical contact with the exposed gate layer.

[0078] refer to Figure 3A As shown, firstly, an insulating layer 221 is formed on the sidewalls and bottom of the first contact hole 220. The material of the insulating layer 221 includes oxides.

[0079] refer to Figure 4BAs shown, the insulating layer 221 at the bottom of the plurality of first contact holes 220 is then removed, while the insulating layer 221 on the sidewalls is retained, exposing the gate layer 114 beneath the plurality of first contact holes 220.

[0080] refer to Figure 5B and 5C As shown, a conductive material 222 is then filled inside the insulating layer 221 of the first contact hole 220. The conductive material 222 makes electrical contact with the exposed gate layer 114, forming a plurality of first contact structures 260. Since both the first contact structures 260 and the gate layer 114 are made of conductive materials, the gate layer 114 in contact with the first contact structure 260 can be electrically connected to external components.

[0081] It should be noted that the manufacturing method of the memory device of this application is applicable to forming unidirectional stepped contact structures, as well as other types of stepped contact structures, thereby achieving an effect similar to that of forming a stepped structure on a stacked layer in a conventional manner. For example, a partitioned stepped contact structure can achieve an effect similar to a staircase divide scheme (SDS), and also achieve the effect of a stepped structure formed by cutting and etching. In the partitioned stepped contact structure, the first contact structure 260 reaches different depths in a stepped manner in the first direction D1, and in the second direction D2 perpendicular to the first direction D1 (refer to...) Figure 2A In the direction perpendicular to the paper, the first contact structure 260 will reach different depths in the first direction D1, according to the depth variation formed by the cutting and etching.

[0082] refer to Figure 5A As shown, in one embodiment of this application, a first interconnect layer 270 is formed on the front side of the semiconductor structure 100. Exemplarily, the first interconnect layer 270 may be a back end of line (BEOL) first interconnect layer; furthermore, a complementary metal-oxide-semiconductor (CMOS) circuit may also be formed on the BEOL first interconnect layer. (See reference...) Figure 5C As shown, the channel structure 113 can be electrically connected to the first interconnect layer 270.

[0083] refer to Figure 5A and Figure 5B As shown, in one embodiment of this application, before forming a plurality of second contact holes, a second interconnect layer 290 is formed on the back side of the semiconductor structure 100, and the second interconnect layer 290 is planarized to obtain... Figure 5BThe diagram shows a thinned second interconnect layer 290. This second interconnect layer 290 can be used to connect the semiconductor structure 100 to other semiconductor devices. In some other embodiments, the second interconnect layer 290 can be implemented as a source layer.

[0084] refer to Figures 5C to 5E As shown, before forming the plurality of second contact holes 240, the process includes forming a second hard mask layer 310 on the stacked layer 110; covering the second hard mask layer 310 with a third photoresist 320; and patterning the second hard mask layer 310 with the third photoresist 320 to form a plurality of second openings 330 reaching the top gate layer in the gate layer 114. For details on this part, please refer to the preceding description of the process for forming the first contact hole, which will not be elaborated upon here.

[0085] refer to Figures 5B to 5I As shown, the step of forming a plurality of second contact holes 240 includes coating a fourth photoresist 340 on a second hard mask layer 310; cyclically performing the steps of trimming the fourth photoresist 340 in a first direction D1, exposing a predetermined number of second openings 330, and etching a predetermined number of stacked layers 110 through the exposed second openings 330, thereby forming a plurality of second contact holes 240 in a second region 250 using the plurality of second openings 330. In some embodiments of this application, after forming the plurality of second contact holes 240, the step further includes removing the fourth photoresist 340 and the second hard mask layer 310. For details of this part, please refer to the preceding description of the process for forming the first contact hole, which will not be elaborated here.

[0086] It should be noted that the reference Figure 2K and Figure 5I As shown, the number of first contact holes 220 and the number of second contact holes 240 can be the same, and their projections in the stacking direction of the stacking layer 110 overlap. Furthermore, the number of first contact holes 220 corresponding in the stacking direction is the same as the number of stacking layers through which the second contact holes 240 pass. It is understood that the number of first and second contact holes, their projection relationship in the stacking direction, and the number of stacking layers through which they pass in this application are not limited to the above embodiments and can be adjusted according to actual circumstances.

[0087] Preferably, in some embodiments of this application, a plurality of second contact holes are aligned with a plurality of first contact holes in the stacking direction of the stacked layers. This maximizes the saving of the area occupied by the step region for forming the contact holes.

[0088] refer to Figures 6A to 6CAs shown, in one embodiment of this application, after forming a plurality of second contact holes 240 from the back side of the semiconductor structure 100 into the semiconductor structure 100, the method further includes forming second contact structures 350 in the plurality of second contact holes 240, each second contact structure 350 being electrically contacted with a gate layer 114 at a predetermined depth.

[0089] refer to Figures 5I to 6B As shown, the steps for forming the second contact structure 350 include: forming an insulating layer 331 on the sidewalls and bottom of the second contact hole 240; removing the insulating layer 331 at the bottom of the second contact hole 240 to expose the gate layer 114; and filling the inner side of the insulating layer 331 of the second contact hole 240 with a conductive material 332, the conductive material 332 being in electrical contact with the exposed gate layer 114. For details regarding the second contact structure 350, please refer to the preceding description of the first contact structure 260, which will not be repeated here.

[0090] refer to Figure 6C As shown, the gate layer 114 electrically contacted by the first contact structure 260 and the second contact structure 350 is different. The gate layer 114 can be electrically connected to the outside through the first contact structure 260 and the second contact structure 350 that are electrically in contact with it.

[0091] refer to Figure 6C and 5D As shown, in Figure 6C In this embodiment, the depth variation trend of the first contact structure 260 along the first direction D1 is the same as the depth variation trend of the second contact structure 350 along the first direction D1. Figure 5D In this embodiment, the depth variation trend of the first contact structure 260 along the first direction D1 is opposite to the depth variation trend of the second contact structure 350 along the first direction D1. It is understood that the first contact hole and the second contact hole described above also have the above-mentioned characteristics, and will not be repeated here.

[0092] This application forms a first contact hole and a second contact hole, reaching predetermined depths, starting from the front and back sides of the semiconductor structure, respectively. Simultaneously, the projections of the first region containing the first contact structure and the second region containing the second contact structure overlap in the stacking direction of the stacked layers. Compared to forming contact holes starting from one side of the semiconductor structure, this application's method of forming contact holes from both the front and back sides has the advantage of reducing the number of stacked layers required for forming the contact holes, thus saving the area occupied by the contact holes.

[0093] This application also provides a memory device manufactured according to the manufacturing method described above. (Reference) Figure 6CAs shown, the memory device 200 includes a stacked layer 110 and a plurality of first contact structures 260 and second contact structures 350. The stacked layer 110 includes alternately stacked gate layers 114 and dielectric layers 112. Each first contact structure 260 penetrates several layers in the stacked layer 110 to reach a predetermined depth of the gate layer, and the plurality of first contact structures 260 are located in a first region 230. Each second contact structure 350 penetrates several layers in the stacked layer 110 to reach a predetermined depth of the gate layer 114, and the plurality of second contact structures 350 are located in a second region 250. The projections of the first region 230 and the second region 250 along the stacking direction of the stacked layer 110 overlap.

[0094] refer to Figure 6C As shown, in one embodiment of this application, a plurality of first contact structures 260 are aligned with a plurality of second contact structures 350 in the stacking direction of the stacking layer 110.

[0095] Continue to refer to Figure 6C As shown, in one embodiment of this application, the memory device 200 further includes a first interconnect layer 270 located on one side of the stacked layer 100. In some embodiments of this application, the first interconnect layer 270 may be a BEOL first interconnect layer, and the memory device 200 may further include CMOS circuitry 280 located on the BEOL first interconnect layer.

[0096] The memory device manufactured using the aforementioned method has a contact structure that is accurately electrically connected to the gate layer at a predetermined depth. Compared to forming contact holes from one side of the semiconductor structure, this method avoids the failure of the contact structure to electrically connect to the gate layer at the predetermined depth due to increased etching depth, and saves on the size of the semiconductor device.

[0097] This application also provides a memory system including a memory device as described above, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. In some embodiments of this application, the memory system further includes a host coupled to the memory controller.

[0098] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.

Claims

1. A method for manufacturing a memory device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a stacked layer comprising alternately stacked sacrificial layers and dielectric layers, the semiconductor structure having a front side and a back side opposite to each other along the stacking direction; Remove the sacrificial layer from the stacked layers, and fill the voids formed after removing the sacrificial layer with conductive material to form a gate layer; A plurality of first contact holes are formed from the front side of the semiconductor structure into the semiconductor structure. Each first contact hole penetrates several layers in the stacked layers and reaches the gate layer at a predetermined depth. The plurality of first contact holes are located in a first region of the semiconductor structure. as well as A plurality of second contact holes are formed from the back side of the semiconductor structure into the semiconductor structure. Each second contact hole penetrates several layers in the stacked layers and reaches the gate layer at a predetermined depth. The plurality of second contact holes are located in a second region of the semiconductor structure, wherein the projections of the first region and the second region along the stacking direction of the stacked layers overlap.

2. The manufacturing method as described in claim 1, characterized in that, Before forming a plurality of second contact holes from the back side of the semiconductor structure into the semiconductor structure, the method further includes forming a first contact structure in the plurality of first contact holes, each of the first contact structures being electrically contacted with the gate layer at a respective predetermined depth.

3. The manufacturing method as described in claim 2, characterized in that, After forming the plurality of second contact holes from the back side of the semiconductor structure into the semiconductor structure, the method further includes forming second contact structures in the plurality of second contact holes, each of the second contact structures being electrically contacted with the gate layer at a respective predetermined depth.

4. The manufacturing method as described in claim 3, characterized in that, The first contact structure and the second contact structure make electrical contact with different gate layers.

5. The manufacturing method as described in claim 2, characterized in that, The step of forming the first contact structure in the plurality of first contact holes includes: An insulating layer is formed on the sidewall and bottom of the first contact hole; Remove the insulating layer at the bottom of the first contact hole to expose the gate layer; A conductive material is filled inside the insulating layer of the first contact hole, and the conductive material is in electrical contact with the exposed gate layer.

6. The manufacturing method as described in claim 3, characterized in that, The step of forming the second contact structure in the plurality of second contact holes includes: An insulating layer is formed on the sidewall and bottom of the second contact hole; Remove the insulating layer at the bottom of the second contact hole to expose the gate layer; A conductive material is filled inside the insulating layer of the second contact hole, and the conductive material is in electrical contact with the exposed gate layer.

7. The manufacturing method as described in claim 1, characterized in that, The plurality of second contact holes are aligned with the plurality of first contact holes in the stacking direction of the stacked layer.

8. The manufacturing method as described in claim 1, characterized in that, Prior to forming the plurality of first contact holes, the method further includes: A first hard mask layer is formed on the stacked layers; A first photoresist is applied to the first hard mask layer; The first hard mask layer is patterned using the first photoresist to form a plurality of first openings that reach the top gate layer in the gate layer.

9. The manufacturing method as described in claim 8, characterized in that, The steps of forming the plurality of first contact holes include: A second photoresist is coated onto the first hard mask layer; The process involves repeatedly performing the steps of trimming the second photoresist in a first direction, exposing a predetermined number of first openings, and etching a predetermined number of stacked layers through the exposed first openings, thereby forming the plurality of first contact holes using the plurality of first openings.

10. The manufacturing method as described in claim 1, characterized in that, Before forming the plurality of second contact holes, the following is also included: A second hard mask layer is formed on the stacked layers; A third photoresist is coated on the second hard mask layer; The second hard mask layer is patterned using the third photoresist to form a plurality of second openings that reach the top gate layer in the gate layer.

11. The manufacturing method as described in claim 10, characterized in that, The steps of forming the plurality of second contact holes include: A fourth photoresist is coated onto the second hard mask layer; The process involves repeatedly performing the steps of trimming the fourth photoresist in a first direction, exposing a predetermined number of second openings, and etching a predetermined number of stacked layers through the exposed second openings, thereby forming the plurality of second contact holes using the plurality of second openings.

12. The manufacturing method as described in claim 1, characterized in that... Also includes: A first interconnect layer is formed on the front side of the semiconductor structure, and / or a second interconnect layer is formed on the back side of the semiconductor structure.

13. The manufacturing method as described in claim 12, characterized in that, The first interconnect layer is the first interconnect layer of the subsequent process.

14. The manufacturing method as described in claim 13, characterized in that, A complementary metal-oxide-semiconductor circuit is formed on the first interconnect layer in the subsequent process.

15. A memory device, characterized in that, include: A stacked structure comprising alternately stacked gate layers and dielectric layers, the stacked structure having a front side and a back side opposite each other along the stacking direction; A plurality of first contact structures, each of the first contact structures extending from the front side through several layers in the stacked structure to reach the gate layer at a predetermined depth, the plurality of first contact structures being located in a first region of the stacked structure; as well as A plurality of second contact structures, each second contact structure extending from the back side through several layers in the stacked structure to reach the gate layer at a predetermined depth, the plurality of second contact structures being located in a second region of the stacked structure, wherein the projections of the first region and the second region along the stacking direction of the stacked structure overlap.

16. The memory device as claimed in claim 15, characterized in that, The plurality of first contact structures are aligned with the plurality of second contact structures in the stacking direction of the stacked structure.

17. The memory device as claimed in claim 15, characterized in that, The depth variation trend of the first contact structure along the first direction is the same as the depth variation trend of the second contact structure along the first direction.

18. The memory device as claimed in claim 15, characterized in that, The depth variation trend of the first contact structure along the first direction is opposite to the depth variation trend of the second contact structure along the first direction.

19. The memory device as claimed in claim 15, characterized in that, It also includes a first interconnect layer located on one side of the stacked structure and / or a second interconnect layer located on the other side of the stacked structure.

20. The memory device as claimed in claim 19, characterized in that, The first interconnect layer is the first interconnect layer of the subsequent process.

21. The memory device as claimed in claim 20, characterized in that, It also includes complementary metal-oxide-semiconductor circuitry located on the first interconnect layer of the back-end process.

22. A memory system, characterized in that, Includes a memory device as described in any one of claims 15-21, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

23. The memory system as claimed in claim 22, characterized in that, It also includes a host coupled to the memory controller.

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