Three-dimensional memory and methods of making the same, and memory systems

Abstract

The application provides a three-dimensional memory, a preparation method thereof and a storage system. The three-dimensional memory comprises a stack structure, a storage channel structure and a top selection gate contact structure. The stack structure is formed on a substrate, and the stack structure comprises a top selection gate. A plurality of storage channel structures extend through the stack structure and reach the substrate. The top selection gate contact structure is located between two adjacent storage channel structures in a first direction, the top selection gate contact structure extends through the top selection gate and is electrically connected with the top selection gate. The first direction is an extension direction of the substrate. The three-dimensional memory and the preparation method thereof can effectively reduce the driving length of the top selection gate and improve the switching rate of the top selection gate by arranging the top selection gate contact structure in the core area.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of three-dimensional memory and its fabrication method. Background Technology

[0002] The improvement in memory density is closely related to advancements in semiconductor manufacturing processes. To further increase memory density, three-dimensional memories have been developed. Three-dimensional memories include a stacked structure formed by alternately stacking multiple gate layers and multiple dielectric layers, and multiple memory channel structures passing through the stacked structure. The memory channel structure can include memory strings, with the portions of the memory strings corresponding to gate layers and the corresponding gate layers forming memory cells.

[0003] Several gate layers at the top of the stacked structure typically serve as top-select gates to control the top-select transistors, thereby selecting the memory string. Other gate layers serve as control gates to control the memory cells, thus enabling the memory function.

[0004] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0005] This application provides a three-dimensional memory. The three-dimensional memory includes: a stacked structure formed on a substrate, the stacked structure including a top select gate; a memory channel structure, a plurality of memory channel structures penetrating the stacked structure and extending to the substrate; and a top select gate contact structure located between two adjacent memory channel structures in a first direction, the top select gate contact structure extending through to the top select gate and electrically connected to the top select gate; wherein, the first direction is the extension direction of the substrate.

[0006] In some implementations, the stacked structure has a core region and a stepped region; multiple top selection gate contact structures are located in the core region; or, multiple top selection gate contact structures are located in the core region and the stepped region.

[0007] In some embodiments, the three-dimensional memory further includes a top select gate tangent that penetrates the top select gate and extends along a first direction to divide the top select gate into multiple mutually insulated regions; a plurality of top select gate contact structures and a plurality of memory channel structures are located in each region.

[0008] In some embodiments, the stacked structure includes alternating gate layers and dielectric layers; a top select gate tangent passes through at least one gate layer, and a top select gate contact structure extends to at least one gate layer; wherein at least one gate layer constitutes a top select gate.

[0009] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure, the first stacked structure and the second stacked structure respectively including alternately stacked gate layers and dielectric layers; the memory channel structure includes a first memory channel structure and a second memory channel structure that respectively penetrate the first stacked structure and the second stacked structure, the first channel layer of the first memory channel structure and the second channel layer of the second memory channel structure are electrically connected; a top select gate tangent line passes through at least one gate layer of the second stacked structure, and a top select gate contact structure extends to at least one gate layer of the second stacked structure; wherein, at least one gate layer of the second stacked structure constitutes a top select gate.

[0010] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes an alternately stacked first gate layer and a first dielectric layer. The second stacked structure includes a stacked second gate layer and a second dielectric layer. The storage channel structure includes a first storage channel structure and a second storage channel structure that penetrate the first stacked structure and the second stacked structure, respectively. The first channel layer of the first storage channel structure and the second channel layer of the second storage channel structure are electrically connected. A top select gate tangent line penetrates the second stacked structure, and a top select gate contact structure extends to the second gate layer. The second gate layer constitutes a top select gate.

[0011] In some implementations, the material of the first gate layer is different from the material of the second gate layer.

[0012] In some embodiments, the first gate layer comprises a metallic conductive material, and the second gate layer comprises doped polysilicon.

[0013] In some implementations, the radial dimension of the second storage channel structure is smaller than the radial dimension of the first storage channel structure.

[0014] In some implementations, at least a portion of the top selected gate tangent is wavy in the first direction.

[0015] In some implementations, the three-dimensional memory further includes an interconnect structure electrically connected to a top select gate contact structure for signal transmission with external control circuitry.

[0016] In some implementations, a virtual channel structure is also included at the location corresponding to the top selected gate contact structure, extending through a portion of the stacked structure and into the substrate.

[0017] A method for fabricating a three-dimensional memory includes: forming a stacked structure including a top select gate and a memory channel structure on a substrate; and forming a top select gate contact structure between adjacent memory channel structures in a first direction, the top select gate contact structure extending to and electrically contacting the top select gate; wherein the first direction is the extension direction of the substrate.

[0018] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure; wherein the step of forming a stacked structure including a top select gate and a storage channel structure on a substrate includes: forming a first stacked structure including a first storage channel structure on a substrate, the first stacked structure including alternating first dielectric layers and first gate layers; and forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; wherein the channel layers of the first storage channel structure are electrically connected to the channel layers of the second storage channel structure, and at least one second gate layer constitutes a top select gate.

[0019] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure; wherein the step of forming a stacked structure including a top select gate and a storage channel structure on a substrate includes: forming a first stacked structure including a first storage channel structure on the substrate, the first stacked structure including alternating first dielectric layers and gate sacrificial layers; forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; and replacing the gate sacrificial layer in the first stacked structure with a first gate layer; wherein the alternating first dielectric layers and first gate layers constitute the first stacked structure, the channel layer of the first storage channel structure is electrically connected to the channel layer of the second storage channel structure, and at least one second gate layer constitutes a top select gate.

[0020] In some embodiments, the fabrication method further includes: forming a top select gate tangent through the top select gate, wherein the top select gate tangent extends along a first direction and divides the top select gate into a plurality of mutually insulated regions, wherein a plurality of top select gate contact structures and a plurality of memory channel structures are located in each region.

[0021] In some implementations, the material of the first gate layer is different from the material of the second gate layer.

[0022] In some embodiments, the first gate layer comprises a metallic conductive material, and the second gate layer comprises doped polysilicon.

[0023] In some embodiments, the fabrication method further includes forming an interconnect structure that is electrically connected to the top selected gate contact structure for signal transmission with an external control circuit.

[0024] A storage system includes: a three-dimensional memory as described above; and a controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory.

[0025] The three-dimensional memory and its fabrication method according to the exemplary embodiments of this application can effectively reduce the driving length of the top selection gate and improve the switching rate of the top selection gate by also setting the top selection gate contact structure in the core area including the memory string. Attached Figure Description

[0026] Other features, objects, and beneficial effects of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0027] Figure 1 This is a schematic partial top view of a three-dimensional memory according to some implementations of related technologies;

[0028] Figures 2 to 4 It is along Figure 1 A schematic partial cross-sectional view of a three-dimensional memory according to some embodiments of related technologies, taken by line AA'.

[0029] Figure 5 This is a schematic partial top view of a three-dimensional memory according to some embodiments of this application;

[0030] Figure 6 It is along Figure 5 A schematic partial cross-sectional view of a three-dimensional memory according to some embodiments of this application, taken by line BB'.

[0031] Figure 7 This is a flowchart of a method for fabricating a three-dimensional memory according to some embodiments of this application;

[0032] Figure 8 This is a flowchart of step S1 according to some embodiments of this application;

[0033] Figures 9A to 9D yes Figure 8 A partial schematic diagram of the device structure in the steps shown;

[0034] Figure 10 This is a flowchart of step S1 according to some other embodiments of this application;

[0035] Figures 11A to 11C yes Figure 10 A partial schematic diagram of the device structure in the steps shown;

[0036] Figure 12 This is a partial schematic diagram of the device structure in step S2 according to some embodiments of this application; and

[0037] Figure 13A and Figure 13B This is a schematic diagram of the structure of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0038] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals denote the same elements.

[0039] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0040] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "containing," and / or "comprise" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to indicate an example or illustration.

[0041] In addition, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0042] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formalized sense.

[0043] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] Figure 1 This is a schematic partial top view of a three-dimensional memory 10 according to some embodiments of related technologies. (Reference) Figure 1The three-dimensional memory 10 may include multiple gate line slits (GLS) 11 extending in the Y-axis direction. Two adjacent gate line slits 11 divide multiple memory channel structures 12 into a block region 13. A block region 13 includes multiple top selective gate cuts (TSG cuts) 14 extending in the Y-axis direction, which divide the block region 13 into multiple pointer regions 13a, and thus the top select gate (described below) of each pointer region 13a can be individually controlled. When a bit line 15 is selected, the top select transistor in a pointer region 13a is turned on, thus selecting the memory channel structure 12 connected to the bit line 15 in that pointer region 13a; when a word line (not shown) is selected, a memory cell in that memory channel structure 12 can be selected, thereby enabling the storage function of a single memory cell. For clarity, Figure 1 Only one bit line 15 is shown in the image; it should be understood that multiple bit lines 15 may exist.

[0045] Figure 2 It is along Figure 1 A schematic partial cross-sectional view of a three-dimensional memory 10 according to some embodiments of the related art, taken by line AA'.

[0046] refer to Figure 2 The three-dimensional memory 10 includes a stacked structure 18 composed of alternating gate layers 16 and dielectric layers 17, and a memory channel structure 12 penetrating the stacked structure 18. In the three-dimensional memory 10, at least one gate layer 16 located on top of the stacked structure 18 ( Figure 2 The four gate layers 16 shown can serve as top-selective gates (TSGs), and at least one field-effect transistor (also referred to as a "top-selective transistor") can be formed at the position corresponding to the top-selective gate in each memory channel structure 12.

[0047] In the three-dimensional memory 10, the remaining gate layers 16 in the stacked structure 18 can serve as control gates. A memory cell can be formed at the location corresponding to each control gate in the memory channel structure 12. The portion of the memory channel structure 12 surrounded by the control gate and the portion surrounded by the top select gate can have the same structure and radial dimensions.

[0048] The top select gate tangent 14 passes through the top select gate and the adjacent dielectric layer 17 to partition the top select gate, thereby enabling each memory region 13a to be driven separately (see [link to documentation]). Figure 1 The top selection gate in ) . For example Figure 2As shown, the top selection gate tangent 14 can be positioned between adjacent memory channel structures 12, but the implementation is not limited to this. For example, a virtual channel structure (not shown) can be added below the top selection gate tangent 14.

[0049] Figure 3 It is along Figure 1 A schematic partial cross-sectional view of a three-dimensional memory 20 according to some embodiments of the related art, taken by line AA'.

[0050] The difference between the three-dimensional memory 20 and the three-dimensional memory 10 is that the top selection gate is formed in a sub-stack structure. Specifically, as... Figure 3 As shown, the three-dimensional memory 20 includes a first stacked structure 21 and a second stacked structure 22, and a first memory channel structure 23 and a second memory channel structure 24 respectively penetrating the first stacked structure 21 and the second stacked structure 22. The first memory channel structure 23 and the second memory channel structure 24 may each include a first channel layer 25 and a second channel layer 26, and the first channel layer 25 and the second channel layer 26 can contact each other to achieve electrical communication. A top select gate tangent 14 is located between two adjacent second memory channel structures 24 and passes through at least one gate layer 16 of the second stacked structure 22, thereby forming a top select gate at the top of the second stacked structure 22. Figure 3 The diagram shows the top select gate tangent 14 passing through five gate layers 16. In practical applications, the number of gate layers 16 in the top select gate can be adjusted as needed, and this application does not impose any limitations on this. This allows for the separate driving of each pointer memory region 13a. Figure 1 ).

[0051] Figure 4 It is along Figure 1 A schematic partial cross-sectional view of a three-dimensional memory 30 according to some embodiments of the related art, taken by line AA'.

[0052] The difference between the three-dimensional memory 30 and the three-dimensional memory 20 is that the second stacked structure 31 includes only one gate layer 32 (top select gate) and two dielectric layers 33 adjacent to it on both sides, and the gate layer 32 in the second stacked structure 31 may include a different material than the gate layer 35 in the first stacked structure 34. The top select gate tangent 14 is located between two adjacent second memory channel structures 24 and runs through the second stacked structure 31 to partition the top select gate (gate layer 32), thereby enabling each pointer memory region 13a to be driven separately. Figure 1 The top selection gate in ).

[0053] It should be understood that Figures 2 to 4 The embodiments shown are merely examples, and the embodiments of the storage channel structure and the stacked structure are not limited thereto.

[0054] Refer again Figure 1 The top select gate tangent 14 divides the top select gate into multiple pointer regions 13a for individual control of each pointer region 13a. The three-dimensional memory 10 may also include a core region CA for forming multiple memory channel structures 12 and a step region SS excluding the memory channel structures 12, for forming various connection structures and word lines, etc. The multiple memory channel structures 12 may be arranged in a two-dimensional array on a plane parallel to the X-axis and Y-axis. In the step region SS, the three-dimensional memory 10 may include a top select gate contact structure 19. The top select gate contact structure 19 passes through the stacked structure 18 (see...). Figure 2 Part of or second stacked structure 22 (see) Figure 3 Part of, or second stacked structure 31 (see) Figure 4 ) and with the top selection gate (see Figure 2 and Figure 3 Gate layer 16 and Figure 4 The gate layer 32) is electrically contacted. The three-dimensional memory 10 may also include an interconnect structure (not shown) electrically contacting the top select gate contact structure 19 for signal transmission with an external control circuit to drive the top select gate of each memory region 13a. According to embodiments of the related art, the drive length of the top select gate contact structure 19 is DL0 in order to control the top select gate in a memory region 13a. Currently, in order to improve the storage capacity of the three-dimensional memory, multiple memory channel structures are usually provided in the direction of DL0. In other words, the relatively long DL0 needs to be driven by the top select gate contact structure 19 located in SS. The relatively long DL0 results in a relatively high resistance corresponding to the top select gate, which leads to a decrease in its switching speed and a reduction in memory performance. Especially when the top select gate is made of a material such as polysilicon, since the resistivity of polysilicon is approximately 20 times that of metals (e.g., tungsten), this further reduces the switching speed.

[0055] Based on this, an exemplary embodiment of the present application provides a three-dimensional memory, which includes a stacked structure, a storage channel structure, and a top select gate contact structure. The stacked structure is formed on a substrate, and the stacked structure includes a top select gate. A plurality of storage channel structures penetrate the stacked structure and extend to the substrate. The top select gate contact structure is located between two adjacent storage channel structures in a first direction. The top select gate contact structure penetrates and extends to the top select gate and is electrically connected to the top select gate. Here, the first direction is the extending direction of the substrate. In the above solution, by arranging the top select gate contact structure between two adjacent storage channel structures, the top select gate length between adjacent top select gate contact structures is short, and when controlling the top select gate of the stacked structure, the driving length of the top select gate contact structure can be reduced, so that the top select gate has a relatively small resistance, improving its switching speed and further improving the memory performance.

[0056] The above solution of the present application is applicable to various forms of stacked structures, such as Figure 2 the stacked structure 18 shown, or the stacked structure includes Figure 3 the first stacked structure 21 and the second stacked structure 22 shown, or the stacked structure includes Figure 4 the first stacked structure 34 and the second stacked structure 31 shown. Hereinafter, the present application will detail the technical solution of the present application in the form that the stacked structure includes Figure 4 the first stacked structure 34 (hereinafter referred to as the first stacked structure 120) and the second stacked structure 31 (hereinafter referred to as the second stacked structure 140) shown.

[0057] Figure 5 is a schematic partial top view of a three-dimensional memory 100 according to some embodiments of the present application.

[0058] Referring to Figure 5 , the three-dimensional memory 100 may include a plurality of top select gate contact structures 110 located in a core region CA, and the top select gate contact structures 110 are distributed in each finger storage region F to reduce the driving length DL1 of the top select gate contact structure 110 when respectively controlling the top select gates in the finger storage regions F. As Figure 5 shown, by arranging a plurality of top select gate contact structures 110 in each finger storage region F, DL1 < DL0 can be achieved. It should be understood that the arrangement manner of the plurality of top select gate contact structures 110 is not limited to Figure 5 the arrangement manner shown, but can be arranged in any manner that can reduce the driving length.

[0059] Figure 6 is along Figure 5A schematic partial cross-sectional view of a three-dimensional memory 100 according to some embodiments of this application, taken by line BB'.

[0060] refer to Figure 6 The three-dimensional memory 100 may include a first stacked structure 120 located on a substrate 101. In some embodiments, the substrate 101 may include polysilicon. The first stacked structure 120 may include a plurality of alternating first dielectric layers 121 and a plurality of first gate layers 122, wherein the first gate layers 122 may, for example, serve as control gates for leading out word lines (not shown). In some embodiments, the first gate layers 122 may include metallic conductive materials such as W, Co, Cu, Al, Ti, Ta, Ni, etc. In some embodiments, the first gate layers 122 may include polysilicon, doped silicon, or metal silicides (e.g., NiSi). x WSi x CoSi x and / or TiSi x The semiconductor material may be silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first dielectric layer 121 may include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first stacked structure 120 may include multiple pairs of first dielectric layers 121 and first gate layers 122, and the number of pairs may be selected according to various application scenarios. For example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256, or more.

[0061] In some embodiments, the three-dimensional memory 100 may include a first memory channel structure 130 extending through the first stacked structure 120. The first memory channel structure 130 may, for example, include a cylindrical (e.g., cylindrical) or inverted conical profile. The first memory channel structure 130 may, for example, include a functional layer, a first channel layer 131, and a first fill core 132 arranged sequentially from the outside in. The functional layer may, for example, include a first barrier layer 133, a memory layer 134, and a tunneling layer 135 arranged sequentially from the outside in. The first barrier layer 133 may, for example, include silicon oxide, silicon oxynitride, a high dielectric constant material, or any combination thereof. The memory layer 134 may, for example, include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer 135 may, for example, include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the functional layer may, for example, be a composite layer including silicon oxide / silicon oxynitride / silicon oxide (ONO). The first channel layer 131 may, for example, include semiconductor materials such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The first filling core 132 may include, for example, an insulating material such as silicon oxide.

[0062] In some embodiments, the first channel layer 131 may contact the substrate 101 such that the first channel layers 131 of the respective first memory channel structures 130 are interconnected. The first channel layer 131 may, for example, have a similar profile shape to the first memory channel structure 130. The first fill core 132 may, for example, be disposed in the space defined by the first channel layer 131 and occupy the bottom portion of that space near the substrate 101.

[0063] The first storage channel structure 130 may further include, for example, a first channel plug 136 located on its upper portion. The first channel plug 136 may be located on the side of the first filler core 132 away from the substrate 101, wherein the first channel plug 136 may contact an end of the first channel layer 131. The first channel plug 136 may also contact, for example, a sidewall of the first channel layer 131. The first channel plug 136 may comprise the same material as the first channel layer 131.

[0064] In some embodiments, the three-dimensional memory 100 may include a second stacked structure 140 located on the first stacked structure 120. The second stacked structure 140 may include at least one second gate layer 142 and at least two adjacent second dielectric layers 141, which are alternately stacked. In some embodiments, the second gate layer 142 may serve as a top select gate. It should be understood that the number of second gate layers 142 and adjacent second dielectric layers 141 may be set as needed. For example, the number of second gate layers 142 may be 1, 2, 4 or more.

[0065] In some embodiments, a second dielectric layer 141 of the second stacked structure 140 near the substrate 101 may be adjacent to a first dielectric layer 121 of the first stacked structure 120 away from the substrate 101. In some embodiments, the second dielectric layer 141 may comprise the same material as the first dielectric layer 121.

[0066] In some embodiments, the second gate layer 142 may include a metallic conductive material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., whose work function satisfies, for example, that when the second gate layer 142 is used as a top-select gate, the threshold voltage of the top-select transistor is positive, thereby turning off the controlled memory channel structure.

[0067] In some embodiments, the second gate layer 142 may further comprise materials such as polysilicon, doped silicon, or metal silicides (e.g., NiSi). x WSi x CoSi x and / or TiSi xThe second gate layer 142 may be a semiconductor material, such as a p-type doped (e.g., boron doped) polysilicon, such that when the second gate layer 142 acts as a top-select gate, the threshold voltage of the top-select transistor is positive, thereby turning off the controlled memory channel structure. Furthermore, when the second gate layer 142 is a semiconductor material, since the resistance of a semiconductor material is approximately 20 times that of a metal material, reducing the drive length DL1 of the top-select gate contact structure 110 is particularly advantageous for having a relatively small resistance corresponding to the top-select gate of the semiconductor material, thereby improving its switching speed and ultimately enhancing the performance of the three-dimensional memory.

[0068] In some embodiments, the material of the first gate layer 122 may be different from the material of the second gate layer 142. For example, the first gate layer 122 may include a metallic material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., while the second gate layer 142 may include a semiconductor material such as undoped polysilicon, doped polysilicon, or metal silicides. In some embodiments, the first gate layer 122 may include W, while the second gate layer 142 may include boron-doped polysilicon. In some embodiments, the material of the first gate layer 122 may be the same as the material of the second gate layer 142.

[0069] In some embodiments, the three-dimensional memory 100 may further include a second memory channel structure 150 extending through the second stacked structure 140. In some embodiments, the second memory channel structure 150 may extend through the second stacked structure 140 and terminate at the surface of the second dielectric layer 141 that contacts the first stacked structure 120. The second memory channel structure 150 may, for example, include a profile shape similar to the first memory channel structure 130. The radial dimension of the second memory channel structure 150 may be smaller than the radial dimension of the first memory channel structure 130. The second memory channel structure 150 may include a second barrier layer 151, a second channel layer 152, and a second filler core 153 disposed sequentially from the outside in. The second channel layer 152 may, for example, have a profile shape similar to the second memory channel structure 150. In some embodiments, the second channel layer 152 may extend into the first memory channel structure 130 and be electrically connected to the first channel layer 131. In some embodiments, the material of the second channel layer 152 may be the same as the material of the first channel layer 131. In one embodiment, the second channel layer 152 may contact the first channel plug 136, thereby being electrically connected to the first channel layer 131 via the first channel plug 136. The second filler core 153 may, for example, be disposed in the space defined by the second channel layer 152 and occupy the bottom portion of that space near the substrate 101.

[0070] The three-dimensional memory 100 may further include a second channel plug 154 located on the upper portion of the second memory channel structure 150. The second channel plug 154 may be located on the side of the second fill core 153 away from the substrate 101, wherein the second channel plug 154 may contact the end of the second channel layer 152. The second channel plug 154 may also contact the sidewall of the second channel layer 152. In some embodiments, the second channel plug 154 can increase the contact area and process window of the bit line contacts, and may also serve as part of the drain of the corresponding memory channel structure. In some embodiments, the material of the second channel plug 154 may be the same as the material of the second channel layer 152.

[0071] refer to Figure 5 and Figure 6 The three-dimensional memory 100 may further include a top select gate tangent 170 located between adjacent gate slot structures 160. The top select gate tangent 170 may, for example, be disposed between two adjacent second memory channel structures 150, and pass through the second gate layer 142 and terminate in a second dielectric layer 141 in contact with the first stacked structure 120, to divide the top select gate (at least one second gate layer 142) into multiple mutually insulated regions, thereby allowing for individual control of these regions. It should be noted that the multiple mutually insulated regions divided by the top select gate tangent 170 are the pointer regions F mentioned above. The top select gate tangent 170 may, for example, include any suitable insulating material.

[0072] refer to Figure 5 and Figure 6 The three-dimensional memory 100 may further include a plurality of top select gate contact structures 110. In some embodiments, the top select gate contact structures 110 may be disposed in each of the core region CA and the step region SS, and a plurality of top select gate contact structures 110 may be included in the core region CA of each memory region F. Alternatively, the plurality of top select gate contact structures 110 may also be located only in the core region CA.

[0073] The top-select gate contact structure 110 may extend, for example, through the upper portion of the second stacked structure 140 away from the substrate 101 and terminate in a second gate layer 142 (top-select gate) for electrical connection to the top-select gate. The top-select gate contact structure 110 may, for example, comprise the same material as the second gate layer 142. In some embodiments, the top-select gate contact structure 110 may comprise any suitable conductive material.

[0074] In some embodiments, the three-dimensional memory 100 may further include an interconnection structure 180 of the top select gate contact structure 110. The interconnection structure 180 is in electrical contact with the top select gate contact structure 110 and is used for signal transmission with an external control circuit, so as to drive the top select gates in each finger memory region F respectively. The interconnection structure 180 may include, for example, the same material as that of the top select gate contact structure 110. In some embodiments, the interconnection structure 180 may include any suitable conductive material. In some embodiments, at a position corresponding to the top select gate contact structure 110, a virtual channel structure 190 penetrating the first stacked structure 120 may further be included. It should be understood that in some other embodiments, the virtual channel structure 190 may be omitted.

[0075] According to an exemplary embodiment of the present application, since the top select gate contact structure 110 is disposed in the core area CA of each finger memory region F, and the top select gate contact structures 110 in the core area CA of each finger memory region F can be provided in multiple numbers, the effective driving length for controlling the top select gate is reduced (DL1 < DL0), the problem of the decrease in the switching rate caused by the need to drive a relatively long top select gate (with a relatively high resistivity) is avoided, and the performance of the three-dimensional memory is improved.

[0076] The exemplary embodiment of the present application may further provide a method for manufacturing a three-dimensional memory. Figure 7 is a flowchart of a method 1000 for manufacturing a three-dimensional memory according to some embodiments of the present application. As Figure 7 shown, the method 1000 for manufacturing a three-dimensional memory may include the following steps:

[0077] S1, forming a stacked structure including a top select gate and a memory channel structure on a substrate;

[0078] S2, forming a top select gate contact structure between adjacent memory channel structures in a first direction, the top select gate contact structure extending to the top select gate and being in electrical contact with the top select gate, the first direction being the extending direction of the substrate; and

[0079] S3, forming an interconnection structure of the top select gate contact structure.

[0080] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. In addition, unless explicitly defined or in conflict with the context, the specific steps included in the methods described in the present application do not have to be limited to the recorded order, but may be executed in any order or executed in parallel. Figures 8 to 12 is a partial schematic diagram of a device structure formed at each stage of a method 1000 for manufacturing a three-dimensional memory according to some embodiments of the present application. In addition, Figures 9A to 9D and Figures 11A to 11C yes Figure 5 The structure shown is a partial cross-sectional view in the X direction. Figure 12 yes Figure 5 The structure shown is a partial cross-sectional view in the Y direction. References will follow. Figures 8 to 12 as well as Figure 6 Detailed description of the preparation method 1000.

[0081] S1， A stacked structure including a top select gate and a memory channel structure is formed on the substrate. 。

[0082] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure. For example... Figure 8 As shown, step S1 includes:

[0083] S101. Forming a first stacked structure including a first memory channel structure on a substrate, the first stacked structure including alternating first dielectric layers and first gate layers; and

[0084] S102. A second stacked structure including a second memory channel structure is formed on the first stacked structure. The second stacked structure includes at least one second gate layer and at least two second dielectric layers adjacent to it.

[0085] The channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure, and at least one second gate layer constitutes the top select gate.

[0086] Reference Figure 9A In step S101, a first stacked structure 120' is formed on the substrate 101. The first stacked structure 120' includes alternating first dielectric layers 121 and gate sacrificial layers 122'. Then, a plurality of first memory channel structures 130 are formed through the first stacked structure 120'. Subsequently, gate line gaps 160' are formed through the first stacked structure 120', referring to... Figure 9B And after replacing the gate sacrificial layer 122' of the first stacked structure 120' with the first gate layer 122 via the gate line gap 160', the gate line gap 160' is filled to form the gate line gap structure 160, as shown in the figure. Figure 9C Thus, the alternately stacked first dielectric layer 121 and first gate layer 122 constitute the first stacked structure 120.

[0087] Reference Figure 9DIn step S102, a second stacked structure 140 is formed on the side of the first stacked structure 120 away from the substrate 101. The second stacked structure 140 includes at least one second gate layer 142 and at least two adjacent second dielectric layers 141. Exemplarily, the second dielectric layer 141, the second gate layer 142, and the second dielectric layer 141 are formed sequentially using a thin-film deposition process. Then, a plurality of second memory channel structures 150 are formed penetrating the second stacked structure 140. The channel layer of the first memory channel structure 130 is electrically connected to the channel layer of the second memory channel structure 150, and the second gate layer 142 constitutes the top select gate.

[0088] The material of the first gate layer 122 may differ from the material of the second gate layer 142. For example, the first gate layer 122 may include a metallic material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., while the second gate layer 142 may include a semiconductor material such as undoped polysilicon, doped polysilicon, or metal silicides. In some embodiments, the first gate layer 122 may include W, while the second gate layer 142 may include boron-doped polysilicon. In some embodiments, the material of the first gate layer 122 may be the same as the material of the second gate layer 142, both including metallic materials such as W.

[0089] In an alternative approach, the "gate replacement" step can be performed after the second stacked structure is formed, thereby replacing the gate sacrificial layer with the first gate layer.

[0090] Specifically, such as Figure 10 As shown, step S1 includes:

[0091] S101' Forming a first stacked structure including a first memory channel structure on a substrate, the first stacked structure including alternating first dielectric layers and gate sacrificial layers;

[0092] S102', A second stacked structure including a second memory channel structure is formed on the first stacked structure; the second stacked structure includes at least one second gate layer and at least two second dielectric layers adjacent to it; and

[0093] S103' Replace the gate sacrificial layer in the first stacked structure with the first gate layer;

[0094] In this structure, the alternating first dielectric layer and the first gate layer constitute a first stacked structure, the channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure, and at least one second gate layer constitutes a top select gate.

[0095] Similarly, refer to Figure 9AIn step S101', a first stacked structure 120' is formed on the substrate, the first stacked structure 120' including alternating first dielectric layers 121 and gate sacrificial layers 122'. Then, a plurality of first memory channel structures 130 are formed through the first stacked structure 120'.

[0096] Reference Figure 11A In step S102', a second stacked structure 140 is formed on the side of the first stacked structure 120' away from the substrate 101. The second stacked structure 140 includes at least one second gate layer 142 and at least two adjacent second dielectric layers 141. Exemplarily, the second dielectric layer 141, the second gate layer 142, and the second dielectric layer 141 are formed sequentially using a thin-film deposition process. Then, a plurality of second memory channel structures 150 are formed penetrating the second stacked structure 140. The channel layer of the first memory channel structure 130 is electrically connected to the channel layer of the second memory channel structure 150, and the second gate layer 142 constitutes the top select gate.

[0097] Subsequently, in step S103', a gate wire gap 160' is formed penetrating the first stacked structure 120' and the second stacked structure 140, referring to... Figure 11B After replacing the gate sacrificial layer 122' of the first stacked structure 120' with the first gate layer 122 via the gate gap 160', the gate gap 160' is filled to form the gate gap structure 160, as shown in the figure. Figure 11C Thus, the alternately stacked first dielectric layer 121 and first gate layer 122 constitute the first stacked structure 120.

[0098] In some embodiments, step S101 or S101' may further include forming a virtual channel structure 190 that penetrates the first stacked structure 120.

[0099] The aforementioned gate slot structure divides multiple first memory channel structures into a single block region. In some embodiments, after forming the stacked structure, a top select gate tangent is further formed through the top select gate, which divides the block region into multiple pointer regions F, and thus the top select gate (described below) of each pointer region F can be individually controlled. The top select gate tangent extends along the first direction and divides the top select gate into multiple mutually insulated regions (pointer regions F), with multiple top select gate contact structures and multiple memory channel structures located in each region.

[0100] S2, forming a top selection gate contact structure between adjacent memory channel structures. 。

[0101] refer to Figure 12In step S2, forming the top selection gate contact structure may include, but is not limited to: forming an insulating layer 200 on the second stacked structure 140; and forming an insulating layer 200 in the core region CA (reference). Figure 5 In some embodiments, a top select gate contact structure 110 is formed at multiple predetermined locations between adjacent second storage channel structures 150, penetrating portions of the insulating layer 200 and the second stacked structure 140, and ending in a second gate layer 142. In some embodiments, the top select gate contact structure 110 may also be formed in the step region SS. In some embodiments, step S2 may further include forming a contact structure 201 that penetrates the insulating layer 200 and makes electrical contact with the second channel plug 154 or the second channel layer 152.

[0102] S3 forms an interconnect structure for the top selected gate contact structure.

[0103] Refer again Figure 6 In step S3, forming the interconnect structure may include, but is not limited to, forming an interconnect layer 210 on the insulating layer 200, which includes an interconnect structure 180 including a top select gate contact structure 110. In some embodiments, the interconnect layer 210 may include contacts 202 connected to the contact structure 201 and an insulating material that electrically isolates the interconnect structure 180 from the contacts 202.

[0104] Table 1 shows the relationship between the number N of top select gate contact structures located in the same memory region F according to some embodiments of this application and the loss length L (μm) of the memory region and the effective drive length DL.

[0105]

[0106] Referring to Table 1, if the same memory area F includes three along the Y-axis (see Table 1), Figure 5 The case of top select gate contact structures spaced at equal intervals (N=3) is considered as having a loss length L of 0 and an effective drive length DL of 1 L0. Therefore, the case of N=5 is equivalent to losing two more unit lengths (0.3 μm) of memory area (L=0.6 μm) compared to N=3, but the effective drive length DL can be reduced to 1 / 2 L0. Similarly, the case of N=9 is equivalent to losing six more unit lengths (0.3 μm) of memory area (L=1.8 μm) compared to N=3, but the effective drive length DL can be reduced to 1 / 4 L0. It should be understood that the data listed in Table 1 are merely examples and are only used to illustrate the effect of setting multiple top select gate contact structures in the core area CA in reducing the effective drive length.

[0107] According to the exemplary embodiments of the three-dimensional memory and its fabrication method in this application, by also setting the top select gate contact structure in the core region, the effective drive length of the top select gate can be effectively reduced, thereby improving the switching rate of controlling the top select gate and improving memory performance.

[0108] It should be understood that, although in Figures 9A to 9D as well as Figures 11A to 11C The example described here is a three-dimensional memory comprising two sub-layer structures, but the concept of adding a top selection gate contact structure to the core region to reduce the effective drive length can be applied to any three-dimensional memory device.

[0109] Figure 13A and Figure 13B This is a schematic diagram of the structure of a storage system according to an exemplary embodiment of this application. For example... Figure 13A and Figure 13B As shown, the storage system 500 includes a three-dimensional memory 510 and a controller 520. The three-dimensional memory 510 is the three-dimensional memory 100 mentioned in the above embodiments. The controller 520 is electrically connected to the three-dimensional memory 510 and is used to control the three-dimensional memory 510.

[0110] In such Figure 13A In the example shown, the controller 520 and a single three-dimensional memory 510 can be integrated into the memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash memory cards (UFS), etc. The memory card may also include a memory card connector 530 that couples the memory card to a host (not shown).

[0111] In such Figure 13B In another example shown, the controller 520 and multiple 3D memories 510 can be integrated into a solid-state drive (SSD). The SSD may also include an SSD connector 530 that couples the SSD to a host (not shown). In some embodiments, the storage capacity and / or operating speed of the SSD is higher than... Figure 13A The storage capacity and / or operating speed of the memory card shown.

[0112] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, comprising: A stacked structure is formed on a substrate, the stacked structure including a top selection gate; A memory channel structure, wherein a plurality of said memory channel structures penetrate the stacked structure and extend to the substrate; as well as A top select gate contact structure is located between two adjacent memory channel structures in a first direction, the top select gate contact structure extends through to the top select gate and is electrically connected to the top select gate; Wherein, the first direction is the extension direction of the substrate, and the stacked structure has a core region and a step region; Multiple top selection gate contact structures are located in the core region; Alternatively, multiple of the top-selected gate contact structures may be located in the core region and the stepped region.

2. The three-dimensional memory according to claim 1, further comprising: A top selection gate tangent line penetrates the top selection gate and extends along the first direction to divide the top selection gate into multiple mutually insulated regions; Multiple top selection gate contact structures and multiple storage channel structures are located in each of the regions.

3. The three-dimensional memory according to claim 2, wherein: The stacked structure includes alternating gate layers and dielectric layers; The top-select gate tangent passes through at least one of the gate layers, and the top-select gate contact structure extends to the at least one of the gate layers; Wherein, at least one of the gate layers constitutes the top selected gate.

4. The three-dimensional memory according to claim 2, wherein: The stacked structure includes a first stacked structure and a second stacked structure, wherein the first stacked structure and the second stacked structure respectively include alternately stacked gate layers and dielectric layers; The storage channel structure includes a first storage channel structure and a second storage channel structure that respectively penetrate the first stacked structure and the second stacked structure, wherein the first channel layer of the first storage channel structure and the second channel layer of the second storage channel structure are electrically connected. The top-selected gate tangent passes through at least one of the gate layers of the second stacked structure, and the top-selected gate contact structure extends to at least one of the gate layers of the second stacked structure; Wherein, at least one of the gate layers of the second stacked structure constitutes the top selection gate.

5. The three-dimensional memory according to claim 2, wherein: The stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes alternately stacked first gate layers and first dielectric layers, and the second stacked structure includes stacked second gate layers and second dielectric layers. The storage channel structure includes a first storage channel structure and a second storage channel structure that respectively penetrate the first stacked structure and the second stacked structure, wherein the first channel layer of the first storage channel structure and the second channel layer of the second storage channel structure are electrically connected. The top selected gate tangent penetrates the second stacked structure, and the top selected gate contact structure extends to the second gate layer; The second gate layer constitutes the top selection gate.

6. The three-dimensional memory according to claim 5, wherein: The material of the first gate layer is different from the material of the second gate layer.

7. The three-dimensional memory according to claim 6, wherein: The first gate layer comprises a metallic conductive material, and the second gate layer comprises doped polysilicon.

8. The three-dimensional memory according to claim 5, wherein, The radial dimension of the second storage channel structure is smaller than the radial dimension of the first storage channel structure.

9. The three-dimensional memory according to claim 2, wherein, At least part of the top selected gate tangent is wavy in the first direction.

10. The three-dimensional memory according to claim 1, further comprising: An interconnect structure, electrically connected to the top selected gate contact structure, is used for signal transmission with external control circuitry.

11. The three-dimensional memory according to claim 1, wherein, At the location corresponding to the top selected gate contact structure, a virtual channel structure is also included, which passes through a portion of the stacked structure and extends to the substrate.

12. A method for fabricating a three-dimensional memory, comprising: A stacked structure including a top select gate and a memory channel structure is formed on a substrate, the stacked structure having a core region and a step region; as well as A top select gate contact structure is formed between adjacent memory channel structures in a first direction, the top select gate contact structure extending to and electrically contacting the top select gate, and a plurality of the top select gate contact structures are located in the core region; or, a plurality of the top select gate contact structures are located in the core region and the step region; Wherein, the first direction is the extension direction of the substrate.

13. The preparation method according to claim 12, wherein, The stacked structure includes a first stacked structure and a second stacked structure; The step of forming the stacked structure including the top select gate and the memory channel structure on the substrate includes: A first stacked structure including a first memory channel structure is formed on the substrate; the first stacked structure includes alternating first dielectric layers and first gate layers; and A second stacked structure including a second memory channel structure is formed on the first stacked structure. The second stacked structure includes at least one second gate layer and at least two second dielectric layers adjacent to it. Wherein, the channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure, and the at least one second gate layer constitutes the top select gate.

14. The preparation method according to claim 12, wherein, The stacked structure includes a first stacked structure and a second stacked structure; The step of forming the stacked structure including the top select gate and the memory channel structure on the substrate includes: A first stacked structure including a first memory channel structure is formed on the substrate, the first stacked structure including alternating first dielectric layers and gate sacrificial layers; A second stacked structure including a second memory channel structure is formed on the first stacked structure; the second stacked structure includes at least one second gate layer and at least two second dielectric layers adjacent thereto; and Replace the gate sacrificial layer in the first stacked structure with the first gate layer; The first dielectric layer and the first gate layer, which are alternately stacked, constitute the first stacked structure. The channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure. The at least one second gate layer constitutes the top select gate.

15. The preparation method according to claim 13 or 14, further comprising: A top select gate tangent is formed through the top select gate, wherein the top select gate tangent extends along the first direction and divides the top select gate into a plurality of mutually insulated regions, wherein a plurality of the top select gate contact structures and a plurality of the memory channel structures are located in each of the regions.

16. The preparation method according to claim 13 or 14, wherein: The material of the first gate layer is different from the material of the second gate layer.

17. The preparation method according to claim 16, wherein: The first gate layer comprises a metallic conductive material, and the second gate layer comprises doped polysilicon.

18. The preparation method according to claim 12, further comprising: An interconnect structure is formed that makes electrical contact with the top selected gate contact structure for signal transmission with external control circuitry.

19. A storage system, characterized in that, include: The three-dimensional memory as described in any one of claims 1-11; as well as A controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

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