Packaged components

Abstract

The embodiments disclosed herein provide a packaged element including a redistribution layer, a passive component integration layer, a first port, and a second port. The passive component integration layer contacts the redistribution layer. The passive component integration layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is disposed opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance value.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a packaged element, and more particularly to a packaged element including a passive element. Background Technology

[0002] In packaging technology, redistribution layers can be fabricated on large-size substrates for encapsulation and dicing, thereby enabling the simultaneous production of a large number of packaged components. As electronic devices trend towards lighter, thinner, shorter, and smaller designs, the application of packaged components in these devices continues to expand. With the increasing demands on electronic device applications and user habits and needs, the requirements for the structure, quality, and functional integration of packaged components are becoming more stringent, leading to various challenges. For example, packaged components including capacitors, due to structural asymmetry, exhibit asymmetrical electrical properties (or directionality) at different output terminals during high-frequency operation, thus limiting the application of packaged components, including passive components. Therefore, the research and development of packaged components requires continuous updates and adjustments. Summary of the Invention

[0003] This disclosure relates to a packaged element that has good electrical quality.

[0004] According to embodiments disclosed herein, the packaged element includes a redistribution layer, a passive component integration layer, a first port, and a second port. The passive component integration layer contacts the redistribution layer. The passive component integration layer includes at least one capacitor, and the capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is disposed opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance value.

[0005] In summary, in the packaged element of this embodiment, because the capacitance of the passive component integration layer is symmetrical, the resistance values ​​of the first port and the second port are substantially the same. With the above-described configuration, the scattering parameters measured at the first port or the second port can be substantially the same, thus achieving a symmetrical capacitor configuration. This avoids the problem of capacitor directionality and improves the electrical quality of the packaged element. Attached Figure Description

[0006] Figure 1 This is a top view schematic diagram of a packaged element according to an embodiment of this disclosure;

[0007] Figure 2A for Figure 1 A cross-sectional view of the packaged component along section line A-A';

[0008] Figure 2B for Figure 1 A cross-sectional view of the packaged component along section line B-B';

[0009] Figure 2C for Figure 1 A cross-sectional view of the packaged component along section line C-C';

[0010] Figure 3 for Figure 2B A magnified cross-sectional view of region R of the packaged component;

[0011] Figure 4 This is a top view schematic diagram of a packaged element according to another embodiment of this disclosure;

[0012] Figure 5A for Figure 4 A cross-sectional view of the packaged component along section line D-D';

[0013] Figure 5B for Figure 4 A cross-sectional view of the packaged component along section line E-E';

[0014] Figure 6 This is a top view schematic diagram of a packaged element according to yet another embodiment of this disclosure;

[0015] Figure 7A for Figure 6 A cross-sectional view of the packaged component along section line F-F';

[0016] Figure 7B for Figure 6 A cross-sectional view of the packaged component along section line G-G';

[0017] Figure 8 This is a top view schematic diagram of a packaged element according to another embodiment of the present disclosure;

[0018] Figures 9 to 12 This is a schematic cross-sectional view of an electronic device that discloses some embodiments. Detailed Implementation

[0019] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the packaged components, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0020] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that component manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that function identically but have different names. In the following specification and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0021] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0022] In this disclosure, the length and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image in an electron microscope, but is not limited to these methods.

[0023] The terms “approximately,” “equal to,” “same as,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value.

[0024] In this disclosure, a structure (or layer, component, substrate) located on top of another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate spacer) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In this disclosure, when a structure is disposed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0025] The terms "first," "second," etc., used in this disclosure may be used to describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, the terms "first element," "component," "region," "layer," or "portion" discussed below are used to distinguish them from "second element," "component," "region," "layer," or "portion," and are not used to define a sequence or specific element, component, region, layer, and / or portion. Furthermore, the term "first" as used in the specification paragraphs may be changed to "second" in the claims.

[0026] According to embodiments disclosed herein, the width, thickness, height, or area of ​​each element, or the distance or spacing between elements, can be measured using an optical microscopy (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image containing the elements to be measured, and the width, thickness, height, or area of ​​each element, or the distance or spacing between elements, can be measured. The element volume can then be obtained using a suitable method (e.g., integration).

[0027] In this disclosure, the various embodiments described below can be used in combination without departing from the spirit and scope of this disclosure. For example, some features of one embodiment can be combined with some features of another embodiment to form another embodiment.

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0029] The electronic devices disclosed herein may include, but are not limited to, display devices, packaging devices, semiconductor packaging devices, backlight devices, antenna devices, sensing devices, or splicing devices. The electronic devices may be bendable or flexible. Display devices may be non-emissive or emissive. Antenna devices may be liquid crystal type or non-liquid crystal type antenna devices. Sensing devices may be sensing devices for capacitance, light, heat, or ultrasound, but are not limited to these. Electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes (LEDs) or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited to these. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but are not limited to these. It should be noted that the electronic devices may be any combination of the foregoing, but are not limited to these. The following explanation of this disclosure will be conducted using an electronic device.

[0030] Figure 1 This is a top view schematic diagram of a packaged element according to an embodiment of this disclosure. Figure 2A for Figure 1 A cross-sectional view of the packaged component along section line A-A'. Figure 2B for Figure 1 A cross-sectional view of the packaged component along section line B-B'. Figure 2C for Figure 1 A cross-sectional view of the packaged component along section line C-C'. Figure 3 for Figure 2B The diagram shows a magnified cross-sectional view of a portion R of the packaged component. For clarity and ease of explanation, the accompanying drawings are provided. Figure 1 , Figure 2A , Figure 2B , Figure 2C and Figure 3 Several components are omitted from the diagram. The packaged components disclosed herein may, for example, utilize fan-out panel-level package (FOPLP) or fan-out wafer-level package (FOWLP) technologies. The following description uses fan-out panel-level package technology as an example, but is not limited thereto. Figure 1 , Figure 2A , Figure 2B , Figure 2CAs shown, the packaged element 10 disclosed herein includes a substrate 110. In this embodiment, the substrate 110 can be used to support components formed thereon during the fabrication of the packaged element 10. The substrate 110 may be, for example, a rigid substrate or a flexible substrate, and may include, for example, glass, polyimide (PI), polyethylene terephthalate (PET), silicon wafer, or other suitable materials. According to some embodiments of this disclosure, the packaged element 10 may include an integrated circuit substrate (IC substrate), but is not limited thereto. Please refer to... Figure 1 , Figure 2A , Figure 2B and Figure 2C The packaged element 10 includes an integrated passive device layer (IPD) 100, a redistribution layer 200, a first port P1, and a second port P2 disposed on a substrate 110, wherein the first port P1 and the second port P2 are disposed opposite each other. The passive device layer 100 may be, for example, a capacitor, an inductor, a resistor, other suitable components, or a combination thereof. Specifically, in some embodiments, along the Z-axis (i.e., the normal direction of the substrate 110), the passive device layer 100 includes a conductive layer M1, multiple insulating layers 120, 140, 160, 180, and multiple electrodes (such as M11, M12, M21, M22) disposed on the substrate 110, and a capacitor is formed through the design of insulating layer vias, but is not limited thereto. The passive device layer 100 contacts the redistribution layer 200. The passive component integration layer 100 includes at least one capacitor, which includes a first capacitor CP1, a second capacitor CP2, or a symmetrical capacitor SC formed by the first capacitor CP1 and the second capacitor CP2. A first port P1 and a second port P2 are electrically connected to the first capacitor CP1 and the second capacitor CP2, respectively. For example, the first port P1 may be connected to the first capacitor CP1 and the second capacitor CP2 at one end, while the second port P2 may be connected to the first capacitor CP1 and the second capacitor CP2 at the other end relative to the first end, such that the first capacitor CP1 and the second capacitor CP2 are connected in parallel. In one embodiment disclosed herein, since the passive component integration layer 100 has at least one symmetrical capacitor SC, the resistance values ​​of the first port P1 and the second port P2 are substantially the same. Under the above configuration, the scattering parameter (also known as the S-parameter) measured at each port can be substantially the same, thus achieving a symmetrical capacitor configuration. This avoids the problem of capacitor directionality. The electrical quality of the packaged element 10 can be improved.

[0031] In some embodiments disclosed herein, the Z-axis is perpendicular to both the X-axis and the Y-axis, with the X-axis perpendicular to the Y-axis. Capacitors and electrodes may have width on the X-axis and length on the Y-axis, but are not limited thereto.

[0032] A conductive layer M1 is disposed on the substrate 110. For example, the conductive layer M1 may be disposed on the entire surface of the substrate 110. The material of the conductive layer M1 may include molybdenum (Mo), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), other suitable metals, or alloys or combinations of the above materials. In some embodiments, the conductive layer M1 may be, for example, a single metal layer or a stacked structure having multiple sub-metal layers, but is not limited thereto.

[0033] Insulating layers 120, 140, and 160 are stacked sequentially along the Z-axis (i.e., the normal direction of the substrate 110). The materials of insulating layers 120, 140, and 160 may include organic or inorganic materials, such as silicon nitride (SiN). x ), silicon oxide (SiO) x Aluminum oxide (Al₂O₃), silicon oxynitride (SiO₂) x N y ( ), photosensitive polyimide, photosensitive polybenzoxazole (photosensitive PBO), benzocyclobutene (BCB), polyaromatic fluorocarbons, photosensitive polyphenylene ether (photosensitive PPE) or other suitable materials, but not limited thereto.

[0034] In some embodiments, through-holes V1 and V2 may be provided in insulating layers 120, 140, and 160. Through-holes V1 and V2 may penetrate insulating layers 120 and 140. In this embodiment, the encapsulation element 10 further includes a first conductive element 191 and a second conductive element 192. The first conductive element 191 may be used to connect to a first port P1 of the symmetrical capacitor SC. The second conductive element 192 may be used to connect to a second port P2 of the symmetrical capacitor SC. In some embodiments, the first conductive element 191 or the second conductive element 192 may be electrically connected to conductive layer M1, metal layers M11, M12, M21, or M22 through through-holes V1 and V2, as fully described in subsequent paragraphs of this disclosure.

[0035] Please refer to Figure 2B and Figure 2C A first metal layer M11 and M21 are disposed between insulating layer 120 and insulating layer 140. A second metal layer M12 and M22 are disposed between insulating layer 140 and insulating layer 160. Insulating layer 140 is located between the first metal layer M11 and M21 and the second metal layer M12 and M22. In some embodiments, a portion of the first metal layer M11 and the second metal layer M12 may constitute a first capacitor CP1, and a portion of the first metal layer M121 and the second metal layer M22 may constitute a second capacitor CP2, but this is not a limitation. The structures of the first capacitor CP1 and the second capacitor CP2 will be described in subsequent paragraphs. The materials of the first metal layer M11 and M21 and the second metal layer M12 and M22 are, for example, the same as those of the conductive layer M1, and will not be described again here.

[0036] Please refer to Figure 1 and Figure 2A ,in Figure 2A for Figure 1 The diagram shows a cross-sectional view of the packaged component along section line A-A'. The first port P1 and the second port P2 are disposed opposite each other on the insulating layer 160. For example, the first port P1 can be located on... Figure 1 The upper end of the packaged component 10, while the second port P2 can be set at... Figure 1 The lower end of the encapsulated component 10. A portion of the first port P1 may extend along the Y-axis and divide into two branches on the X-axis, including branch P11 and branch P12. A portion of the second port P2 may extend along the Y-axis and divide into two branches on the X-axis, including branch P21 and branch P22, wherein branch P21 and branch P22 may, for example, have curved edges, but are not limited thereto. The materials of the first port P1 and the second port P2 are, for example, the same as those of the conductive layer M1, and will not be described further here.

[0037] The first conductive element 191 (i.e., the first port P1) can be electrically connected to one of a plurality of electrodes through a through-hole V1 penetrating the insulating layers 120 and 140, such as one of the metal layers M11, M12, M21, or M22. The second conductive element 192 (i.e., the second port P2) can be electrically connected to one of a plurality of electrodes through a through-hole V2 penetrating the insulating layers 120 and 140, such as one of the metal layers M11, M12, M21, or M22.

[0038] Please refer to Figure 2B The passive component integration layer 100 includes a first capacitor CP1. The first capacitor CP1 includes portions of a first metal layer M11 and a second metal layer M12. The passive component integration layer 100 also includes a first electrode E11 and a second electrode E12. On the Z-axis of the package element 10 (i.e., the normal direction of the substrate 110), the outer edge M12' of the second metal layer M12 is inside the outer edge M11' of the first metal layer M11. That is, in a cross-sectional view, the width of the first metal layer M11 along the Y-axis is greater than the width of the second metal layer M12 along the Y-axis, wherein the Y-axis and the Z-axis are perpendicular to each other, but this is not a limitation. The first electrode E11 and the second electrode E12 are disposed on the insulating layer 160. In some embodiments, the first electrode E11 and the second electrode E12 may be disposed on the same layer as the first port P1 or the second port P2. In other embodiments, the first electrode E11 and the second electrode E12 may be disposed on a different layer from the first port P1 or the second port P2, but this is not a limitation. In some embodiments, the first electrode E11 is isolated from the second electrode E12. The materials of the first electrode E11 and the second electrode E12 are, for example, the same as those of the conductive layer M1, and therefore will not be described again here.

[0039] In some embodiments, branch P11 of the first port P1 can directly contact the first electrode E11, and branch P21 of the second port P2 can directly contact the second electrode E12. Alternatively, branch P11 and the first electrode E11 can be integrally formed. Branch P21 and the second electrode E12 can also be integrally formed. Or, branch P11 of the first port P1 can be electrically connected to the first electrode E11 through a contact hole, and branch P21 of the second port P2 can be electrically connected to the second electrode E12 through another contact hole, but this is not a limitation. Specifically, the first conductive element 191 (i.e., the first port P1) can be electrically connected to one of a plurality of electrodes through the first electrode E11 and through a through-hole V1 penetrating the insulating layers 120 and 140, such as one of the metal layers M11, M12, M21, or M22. The second conductive element 192 (i.e., the second port P2) can be electrically connected to one of a plurality of electrodes, such as one of the metal layers M11, M12, M21 or M22, through the second electrode E12 and the through hole V2 penetrating the insulating layers 120 and 140.

[0040] Along the Z-axis (i.e., in the normal direction of substrate 110), the first electrode E11 partially overlaps the conductive layer M1, the first metal layer M11, and the second metal layer M12. For example, the first metal layer M11 partially overlaps the conductive layer M1, and the second metal layer M12 partially overlaps the conductive layer M1, thus allowing charge to be stored between the first metal layer M11 and the conductive layer M1 to form a capacitor. The first electrode E11 is electrically connected to the first metal layer M11 through an opening O1 penetrating the insulating layer 140 and the insulating layer 160. The second electrode E12 partially overlaps the conductive layer M1, the first metal layer M11, and the second metal layer M12. The second electrode E12 is electrically connected to the second metal layer M12 through an opening O2 penetrating the insulating layer 140 and the insulating layer 160. With the above configuration, the first electrode E11 and the second electrode E12 are respectively electrically connected to the first capacitor CP1. The first capacitor CP1 has a structure comprising a conductive layer M1, an insulating layer 120, a first metal layer M11, an insulating layer 140, and a second metal layer M12, and can transfer the stored charge to the heavy-duty linear layer 200 through either the first electrode E11 or the second electrode E12. That is, the first capacitor CP1 can transfer the charge stored in the conductive layer M1, insulating layer 120, and first metal layer M11 to the heavy-duty linear layer 200 through the first electrode E11, and the first capacitor CP1 can transfer the charge stored in the first metal layer M11, insulating layer 140, and second metal layer M12 to the heavy-duty linear layer 200 through the second electrode E12. It is worth noting that opening O1 penetrates both insulating layers 140 and 160, but opening O2 only penetrates insulating layer 160. In other words, on the Z-axis (i.e., in the normal direction of the substrate 110), the height of opening O1 is different from the height of opening O2. Specifically, in... Figure 2B In the illustrated embodiment, the height of opening O1 can be greater than the height of opening O2, and the bottom width of opening O1 is approximately equal to the bottom width of opening O2, which can be considered as the bottom area of ​​opening O1 being approximately equal to the bottom area of ​​opening O2. Therefore, the volume of the first electrode E11 disposed within opening O1 will be different from (e.g., greater than) the volume of the second electrode E12 disposed within opening O2. The height of opening O1 can be, for example, the sum of the thicknesses of insulating layer 160 and insulating layer 140, and the height of opening O2 can be, for example, the thickness of insulating layer 160, but is not limited thereto. It should be understood that, under the above configuration, different electrode volumes within the openings result in different resistance values. Furthermore, the area of ​​the first metal layer M11 overlapping the conductive layer M1 is different from the area of ​​the second metal layer M12 overlapping the first metal layer M11, resulting in different stored charges. Under the above configuration, the resistance values ​​of the first electrode E11 and the second electrode E12 are also different.

[0041] Please refer to Figure 2CThe passive component integration layer 100 includes a second capacitor CP2. The second capacitor CP2 includes portions of a first metal layer M21 and a second metal layer M22. The passive component integration layer 100 also includes a third electrode E21 and a fourth electrode E22. On the Z-axis of the package element 10 (i.e., the normal direction of the substrate 110), the outer edge M22' of the second metal layer M22 is inside the outer edge M21' of the first metal layer M21. That is, in a cross-sectional view, the width of the first metal layer M21 along the Y-axis is greater than the width of the second metal layer M22 along the Y-axis, wherein the Y-axis and the Z-axis are perpendicular to each other, but this is not a limitation. The third electrode E21 and the fourth electrode E22 are disposed on the insulating layer 160. In some embodiments, the third electrode E21 and the fourth electrode E22 may be disposed on the same layer as the first port P1 or the second port P2. In other embodiments, the first electrode E11 and the second electrode E12 may be disposed on a different layer from the first port P1 or the second port P2, but this is not a limitation. In some embodiments, the third electrode E21 is isolated from the fourth electrode E22. The materials of the third electrode E21 and the fourth electrode E22 are, for example, the same as those of the conductive layer M1, and therefore will not be described again here. In some embodiments, the electrodes disclosed herein may, for example, have a curved edge design to avoid charge accumulation at the tips and thus affecting electrical quality, but this is not a limitation.

[0042] In some embodiments, branch P12 of the first port P1 can directly contact the third electrode E21. Branch P22 of the second port P2 can directly contact the fourth electrode E22. Alternatively, branch P12 and the third electrode E21 can be integrally formed. Branch P22 and the fourth electrode E22 can also be integrally formed. Or, branch P11 of the first port P1 can be electrically connected to the first electrode E11 through a contact hole, and branch P21 of the second port P2 can be electrically connected to the second electrode E12 through another contact hole, but this is not a limitation. Specifically, the first conductive element 191 (i.e., the first port P1) can be electrically connected to one of a plurality of electrodes through the third electrode E21 and through a through-hole V1 penetrating the insulating layers 120 and 140, such as one of the metal layers M11, M12, M21, or M22. The second conductive element 192 (i.e., the second port P2) can be electrically connected to one of a plurality of electrodes, such as one of the metal layers M11, M12, M21 or M22, through the fourth electrode E22 and the through hole V2 penetrating the insulating layers 120 and 140.

[0043] Along the Z-axis (i.e., in the normal direction of substrate 110), the third electrode E21 partially overlaps the conductive layer M1, the first metal layer M21, and the second metal layer M22. The third electrode E21 is electrically connected to the first metal layer M21 through an opening O3 penetrating the insulating layer 140 and the insulating layer 160. The fourth electrode E22 partially overlaps the conductive layer M1, the first metal layer M21, and the second metal layer M22. The fourth electrode E22 is electrically connected to the second metal layer M22 through an opening O4 penetrating the insulating layer 140 and the insulating layer 160. With the above configuration, the third electrode E21 and the fourth electrode E22 are electrically connected to the second capacitor CP2. The second capacitor CP2 has a structure consisting of a conductive layer M1, an insulating layer 120, a first metal layer M21, an insulating layer 140, and a second metal layer M22, and can transfer the stored charge to the core layer 200 through either the third electrode E21 or the fourth electrode E22. In other words, the second capacitor CP2 can transfer the charge stored in the conductive layer M1, insulating layer 120, and first metal layer M21 to the heavy-duty linear layer 200 through the third electrode E21, while the second capacitor CP1 can transfer the charge stored in the first metal layer M21, insulating layer 140, and second metal layer M22 to the heavy-duty linear layer 200 through the fourth electrode E22. It is worth noting that opening O4 penetrates both insulating layer 140 and insulating layer 160, but opening O3 only penetrates insulating layer 160. That is, on the Z-axis (i.e., in the normal direction of substrate 110), the height of opening O4 is different from the height of opening O3. Specifically, in... Figure 2C In the illustrated embodiment, the height of opening O4 can be greater than the height of opening O3, and the bottom width of opening O4 is approximately equal to the bottom width of opening O3, which can be considered as the bottom area of ​​opening O4 being approximately equal to the bottom area of ​​opening O3. Therefore, the volume of the fourth electrode E22 disposed within opening O4 will be different from (e.g., greater than) the volume of the third electrode E21 disposed within opening O3. The height of opening O4 can be, for example, the sum of the thicknesses of insulating layer 160 and insulating layer 140, and the height of opening O3 can be, for example, the thickness of insulating layer 160, but is not limited thereto. It should be understood that, under the above configuration, different electrode volumes within the openings result in different resistance values. Furthermore, the area of ​​the first metal layer M21 overlapping the conductive layer M1 is different from the area of ​​the second metal layer M22 overlapping the first metal layer M21, resulting in different stored charges. Under the above configuration, the resistance values ​​of the third electrode E21 and the fourth electrode E22 are also different.

[0044] Please refer to Figure 1 , Figure 2B and Figure 3 , Figure 3A partially magnified first capacitor CP1 is shown in region R. In some embodiments, in region R, the length W1 of the conductive layer M1 on the Y-axis is greater than the length W2 of the first metal layer M11 on the Y-axis, and the length W2 of the first metal layer M11 on the Y-axis is greater than the length W3 of the second metal layer M12 on the Y-axis. The length W2 of the first metal layer M11 can be defined as the maximum distance between its two ends. The length W3 of the second metal layer M12 can be defined as the maximum distance between its two ends. With the above configuration, the impact of process offset on the capacitor can be reduced. The reliability of the packaged element 10 can be improved.

[0045] In other embodiments, the height of the conductive layer M1 may be greater than or equal to 0.15 micrometers (μm) and less than or equal to 0.35 micrometers (μm), the height of the first metal layer M11 may be greater than or equal to 0.15 micrometers and less than or equal to 0.35 micrometers, and the height of the second metal layer M12 may be greater than or equal to 0.15 micrometers and less than or equal to 0.35 micrometers, but is not limited thereto.

[0046] In some embodiments, the height T1 of the second metal layer M12 can be defined as the maximum distance between the top and bottom surfaces of the second metal layer M12 along the Z-axis (i.e., the normal direction) of the package element 10 or substrate 110. The height T2 of the first electrode E11 can be defined as the maximum distance between the top surface of the first electrode E11 and the top surface of the insulating layer 160 along the Z-axis (i.e., the normal direction) of the package element 10 or substrate 110. In some embodiments, the height T2 of the first electrode E11 along the Z-axis (or, the height of the second electrode E12 along the Z-axis may be substantially the same as the height T2 of the first electrode E11) may be greater than the height T1 of the second metal layer M12 along the Z-axis (or, the height of the first metal layer M11 along the Z-axis may be substantially the same as the height T1 of the second metal layer M12), but is not limited thereto. In some embodiments, the height T2 of the first electrode E11 may be greater than or equal to 8 micrometers and less than or equal to 13 micrometers. In other embodiments, the height of the second electrode E12 may be greater than or equal to 8 micrometers and less than or equal to 13 micrometers, but is not limited thereto. With the above configuration, the height of the electrode (including the first electrode E11 or the second electrode E12) may be greater than the height of the conductive layer M1, the first metal layer M11, or the second metal layer M12. This reduces the resistance of the electrode, improving the electrical quality of the packaged element 10.

[0047] In some embodiments, the length W4 of the first electrode E11 is greater than the length W5 of the second electrode E12. The length W4 of the first electrode E11 can be defined as the maximum distance between its two ends on the Y-axis. The length W5 of the second electrode E12 can be defined as the maximum distance between its two ends on the Y-axis. In other words, the volume of the first electrode E11 can be greater than the volume of the second electrode E12, but is not limited thereto.

[0048] Please refer to Figure 1 and Figure 2C The second capacitor CP2 is similar to the first capacitor CP1, except that the length of the third electrode E21 connected to the first port P1 is shorter than the length of the fourth electrode E22 connected to the second port P2. In other words, the length of the fourth electrode E22 electrically connected to the first metal layer M21 is greater than the length of the third electrode E21 electrically connected to the second metal layer M22. The length of the third electrode E21 can be defined as the maximum distance between its two ends on the Y-axis. The length of the fourth electrode E22 can be defined as the maximum distance between its two ends on the Y-axis. In other words, the volume of the fourth electrode E22 can be larger than the volume of the third electrode E21, but is not limited to this. According to some embodiments, the length W4 of the first electrode E11 of the first capacitor CP1 is greater than the length W5 of the second electrode E12. The first electrode E11 is electrically connected to the first metal layer M11 through an opening O1 penetrating the insulating layer 140 and the insulating layer 160. The second electrode E12 is electrically connected to the second metal layer M12 through an opening O2 penetrating the insulating layer 160. The horizontal level of the opening O2 is above the horizontal level of the opening O1, but this is not a limitation. Therefore, the first capacitor CP1 will not be structurally symmetrical. As a result, the scattering parameters measured at the first electrode E11 will be different from those measured at the second electrode E12, thus affecting the asymmetry of the capacitance value of the first capacitor CP1.

[0049] This disclosure describes the electrical testing of packaged element 10, for example, using a network analyzer measurement architecture, which may include a network analyzer, a microscope probe platform, a high-frequency probe, a probe holder, or other suitable instruments. Specifically, scattering parameters can be obtained by measuring the "ports" (such as electrodes or ports as referred to in this disclosure) of packaged element 10 using a network analyzer. It should be noted that the term "port" as used herein can be defined as an electrode, pad, or conductive bump from which relevant electrical parameters can be derived and measured, but is not limited to this definition. In the steps described above for obtaining scattering parameters, one end of the probe of the network instrument measurement architecture contacts the first electrode E11 of the first capacitor CP1, and the other end contacts the second electrode E12 of the first capacitor CP1. When the probe contacting the first electrode E11 is grounded, the scattering parameters of the second electrode E12 can be obtained. Conversely, when the probe contacting the second electrode E12 is grounded, the scattering parameters of the first electrode E11 can be obtained. That is to say, when the scattering parameters of the first electrode E11 are not equal to the scattering parameters of the second electrode E12, the first capacitor CP1 can be, for example, an asymmetrical capacitor (or, in other words, a capacitor with directionality). Since there are conversion relationships between electrical parameters such as scattering parameters (S), impedance parameters (Z), resistance (R), reactance (X), and capacitance (C), when the measured scattering parameters of the first capacitor CP1 are asymmetrical, it means that the resistance value of the first capacitor CP1 is asymmetrical, and the capacitance value of the first capacitor CP1 is also asymmetrical.

[0050] Insulating layer 180 is disposed on insulating layer 160. The material of insulating layer 180 is similar to that of insulating layers 120, 140 and 160, so it will not be described in detail here.

[0051] Please refer to Figure 1 and Figure 2A The redistribution layer 200 comprises a stack of multiple circuit layers sequentially stacked along the Z-axis (i.e., the normal direction). Each circuit layer includes, but is not limited to, dielectric layers, conductive patterns, and conductive vias. The redistribution layer RDL is, for example, used to achieve redistribution circuitry in high-density integrated circuits (ICs), but is not limited to this. For example, the redistribution layer 200 includes dielectric layers 210, 220, 230, and 240 sequentially stacked on the insulating layer 180 of the passive component integration layer 100 along the normal direction (i.e., the Z-axis) of the substrate 110. The materials of dielectric layers 210, 220, 230, and 240 may include organic or inorganic materials, such as silicon nitride (SiN).x ), silicon oxide (SiO) x Aluminum oxide (Al₂O₃), silicon oxynitride (SiO₂) x N y ( ), photosensitive polyimide, photosensitive polybenzoxazole, benzocyclobutene, polyarylene fluorocarbon, photosensitive polyphenylene ether or other suitable materials, but not limited thereto.

[0052] Taking a single circuit layer as an example, the dielectric layer 210 is provided with conductive patterns 212 and conductive vias 214. The conductive pattern 212 may be, for example, a line or pad used for horizontal signal transmission in the redistribution layer 200, but is not limited thereto. The conductive via 214 may be, for example, a via vertically connecting different layers for vertical signal transmission, but is not limited thereto. For example, the conductive pattern 222 in the dielectric layer 220 is disposed on the dielectric layer 210, and the conductive via can electrically connect the conductive pattern 212 and the conductive pattern 222 in the Z-axis (i.e., the normal direction).

[0053] In other embodiments, conductive patterns 232 are provided in dielectric layer 230 and conductive patterns 242 are provided in dielectric layer 240. It should be noted that the redistribution layer 200 shown in this embodiment is, for example, a redistribution layer including four dielectric layers, but this disclosure is not limited thereto. In other embodiments, the redistribution layer 200 may have more than four layers or fewer than four layers.

[0054] like Figure 2AAs shown, the redistribution layer 200 is disposed on the passive component integration layer 100 and is electrically connected to the passive component integration layer 100. For example, the conductive pattern 212 of the redistribution layer 200 can be electrically connected to a first port P1 or a second port P2 through conductive vias (not shown) disposed in the insulating layer 180. In this way, the redistribution layer 200 can be electrically connected to the first electrode E11 through the first port P1, and the redistribution layer 200 can be electrically connected to the second electrode E12 through the second port P2. In other words, the first capacitor CP1 can be electrically connected to the redistribution layer 200 through either the first electrode E11 or the second electrode E12. In other embodiments, the redistribution layer 200 can be electrically connected to the third electrode E21 and the second capacitor CP2 through the first port P1. The redistribution layer 200 can be electrically connected to the fourth electrode E22 and the second capacitor CP2 through the second port P2. In other words, the second capacitor CP2 can be electrically connected to the redistribution layer 200 via the third electrode E21 or the fourth electrode E22. It is worth noting that the passive component integration layer 100 of the package element 10 in one embodiment of this disclosure has symmetry. Specifically, the first capacitor CP1 is connected to the first port P1 and the second port P2. The larger first electrode E11 of the first capacitor CP1 is connected to the first port P1, while the smaller second electrode E12 is connected to the second port P2. The second capacitor CP2 is connected to the first port P1 and the second port P2. The smaller third electrode E21 of the second capacitor CP2 is connected to the first port P1, while the larger fourth electrode E22 is connected to the second port P2. The first capacitor CP1 is connected in parallel with the second capacitor CP2. Thus, the symmetry of the passive component integration layer 100 can be defined as follows: when the first port P1 is grounded and the second port P2 receives a signal, the resistance values ​​measured at the first port P1 and the second port P2 are substantially the same as the resistance values ​​measured at the first port P1 and the second port P2 when the first port P1 receives a signal and the second port P2 is grounded. Therefore, the resistance value of the first port P1 is essentially the same as the resistance value of the second port P2.

[0055] Furthermore, when the first port P1 is grounded and the second port P2 receives a signal, the scattering parameters measured at the first port P1 and the second port P2 are substantially the same as those measured at the first port P1 and the second port P2 when the first port P1 receives a signal and the second port P2 is grounded. Additionally, the reactance and inductance (Q value) measured at the first port P1 and the second port P2 are also substantially the same under the two conditions described above (or, in other words, the direction of current flow). In this way, the directionality problem of the capacitor can be avoided. The electrical quality of the packaged element 10 can be improved. Furthermore, the measured capacitance value of the passive component integration layer is substantially the same when the first port P1 is grounded and the second port P2 receives a signal, or when the first port P1 receives a signal and the second port P2 is grounded. In this way, the electrical quality of the packaged element 10 can be improved.

[0056] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0057] Figure 4 This is a top view schematic diagram of a packaged element according to another embodiment of this disclosure. Figure 5A for Figure 4 A cross-sectional view of the packaged component along section line D-D'. Figure 5B for Figure 4 A cross-sectional view of the packaged component along section line E-E'. For clarity and ease of explanation, the accompanying drawings are shown. Figure 4 , Figure 5A and Figure 5B Several components are omitted from the diagram. The package element 10A in this embodiment is generally similar to... Figure 1 , Figure 2B and Figure 2CThe encapsulation element 10 is used, therefore, the same and similar components in both embodiments will not be repeated here. The main difference between this embodiment and encapsulation element 10 is that the symmetrical capacitor SC1 includes a first capacitor CP1' and a second capacitor CP2'. The smaller second electrode E12, electrically connected to the first capacitor CP1', is connected to branch P11 of the first port P1, and the larger first electrode E11, electrically connected to the first capacitor CP1', is connected to branch P21 of the second port P2. The smaller third electrode E21, electrically connected to the second capacitor CP2', is connected to branch P12 of the first port P1, and the larger fourth electrode E22, electrically connected to the second capacitor CP2', is connected to branch P22 of the second port P2. In other words, encapsulation element 10A has smaller electrodes E12 and E21 connected to the first port P1, while larger electrodes E11 and E22 are connected to the second port P2.

[0058] It is worth noting that there are multiple paths between the first port P1 and the second port P2 of the packaged element 10A in one embodiment of this disclosure. The resistance and reactance on different paths can be substantially the same. Therefore, the resistance, scattering parameters, reactance, inductance, or capacitance values ​​measured at the first port P1 and the second port P2 on different paths can be substantially the same, making the symmetrical capacitor SC1 of the passive component integration layer 100A symmetrical. The structure of the path and the current travel path will be briefly described below.

[0059] Please refer to this first. Figure 4 and Figure 5A The multiple paths between the first port P1 and the second port P2 include at least a first path and a second path. The first path, for example, includes a branch P11 of the first port P1, a second electrode E12 and a connected first capacitor CP1', conductive patterns 212A and 222A, a fourth electrode E22 and a connected second capacitor CP2', and a branch P22 of the second port P2. Specifically, a current signal can flow from the first port P1 into the second electrode E12 and the first capacitor CP1'.

[0060] Next, a current signal can enter the conductive pattern 212A through the via V3A. The via V3A is located between the second electrode E12 and the conductive pattern 212A. The conductive pattern 212A can interact with the conductive pattern 212 (shown in...). Figure 2A (In the same layer as the middle) but not limited to this.

[0061] Next, the current signal enters the conductive pattern 222A through the via V7A. The via V7A is located between the conductive pattern 212A and the conductive pattern 222A. The conductive pattern 222A can be located on the same layer as the conductive pattern 222A, but is not limited thereto.

[0062] Next, the current signal enters the fourth electrode E22 through the via V6A. The via V6A is located between the fourth electrode E22 and the conductive pattern 222A. The fourth electrode E22 is electrically connected to the second capacitor CP2'. Thus, the current signal can flow into the second capacitor CP2' electrically connected to the fourth electrode E22.

[0063] Next, the current signal can flow into branch P22 of the second port P2 through the fourth electrode E22.

[0064] Under the above configuration, the first capacitor CP1' or the second capacitor CP2' of the symmetrical capacitor SC1 of the passive component integration layer 100A can be electrically connected to the first port P1 or the second port P2 through the conductive patterns 212A and 222A of the redistribution layer 200A.

[0065] Please continue to refer to this. Figure 4 and Figure 5B The second path includes, for example, a branch P12 of the first port P1, a third electrode E21 and a connected second capacitor CP2', conductive patterns 222A' and 212A', a first electrode E11 and a connected first capacitor CP1', and a branch P21 of the second port P2. Specifically, a current signal can flow from the first port P1 into the third electrode E21 and the second capacitor CP2'.

[0066] Next, the current signal can enter the conductive pattern 222A' through the via V5A. The via V5A is located between the third electrode E21 and the conductive pattern 222A'. The conductive pattern 222A' can be located on the same layer as the conductive pattern 222, but is not limited thereto.

[0067] Next, the current signal enters the conductive pattern 212A' through the via V8A. The via V7A is located between the conductive pattern 212A' and the conductive pattern 222A'. The conductive pattern 212A' can interact with the conductive pattern 212 (shown in...). Figure 2A (In the same layer as the middle) but not limited to this.

[0068] Next, the current signal enters the first electrode E11 through the via V4A. The via V4A is located between the first electrode E11 and the conductive pattern 212A'. The first electrode E11 is electrically connected to the first capacitor CP1'. Thus, the current signal can flow into the first capacitor CP1' electrically connected to the first electrode E11.

[0069] Next, the current signal can flow through the first electrode E11 into the branch P21 of the second port P2.

[0070] Under the above configuration, the first capacitor CP1' or the second capacitor CP2' of the symmetrical capacitor SC1 of the passive component integration layer 100A can be electrically connected to the first port P1 or the second port P2 through the conductive patterns 212A and 222A of the redistribution layer 200A. Furthermore, the conductive patterns of the redistribution layer 200A in the first and second paths can be staggered or arranged in an X-shape, but are not limited thereto.

[0071] It is worth noting that the symmetry of one embodiment disclosed herein can be defined as the resistance value of the first port P1 connected to the first path being substantially the same as the resistance value of the first port P1 connected to the second path. Specifically, when the first port P1 is grounded and the second port P2 receives a signal, or when the first port P1 receives a signal and the second port P2 is grounded, the components on the first path can correspond to the components on the second path. For example, both the first and second paths include smaller electrodes E12 and E21 and larger electrodes E11 and E22. Specifically, the first capacitor CP1' and the second electrode E12 connected to the first capacitor CP1' are electrically connected to the second capacitor CP2' and the fourth electrode E22 connected to the second capacitor CP2' through the redistribution layer 200A, and the second capacitor CP2' and the third electrode E21 connected to the second capacitor CP2' are electrically connected to the first capacitor CP1' and the first electrode E11 connected to the first capacitor CP1' through the redistribution layer 200A. The first port P1 is connected to the second electrode E12 and the third electrode E21, and the second port P2 is connected to the first electrode E11 and the fourth electrode E22. Under the above configuration, the resistance value on the first path can be substantially the same as the resistance value on the second path. Furthermore, the resistance value connected to the second port P2 of the first path is substantially the same as the resistance value connected to the second port P2 of the second path. That is, the resistance values, scattering parameters, reactance, or inductance measured at the first port P1 and the second port P2 can be substantially the same. The capacitance values ​​of the first capacitor CP1' and the second capacitor CP2' can be substantially the same. In this way, the electrical quality of the packaged element 10A can be improved. Furthermore, the packaged element 10A can achieve similar excellent technical effects as in the above embodiment.

[0072] Figure 6 This is a top view schematic diagram of a packaged element according to yet another embodiment of this disclosure. Figure 7A for Figure 6 A cross-sectional view of the packaged component along section line F-F'. Figure 7B for Figure 6 A cross-sectional view of the packaged component along section line G-G'. For clarity and ease of explanation, the accompanying drawings are shown. Figure 6 , Figure 7A and Figure 7B Several components are omitted from the diagram. The package element 10B in this embodiment is generally similar to... Figure 4 , Figure 5A and Figure 5B The package element 10A is used, therefore, the same and similar components in both embodiments will not be repeated here. The main difference between this embodiment and package element 10A is that the symmetrical capacitor SC2 includes a first capacitor CP1' and a second capacitor CP2'. The first path and the second path of package element 10B include a three-layer conductive pattern to connect the first capacitor CP1' and the second capacitor CP2' to the first port P1 or the second port P2.

[0073] For details, please refer to [the relevant documentation / reference]. Figure 6 and Figure 7A The first path includes, for example, a branch P11 of the first port P1, a second electrode E12 and a connected first capacitor CP1', conductive patterns 222B, 212B, 222B, a fourth electrode E22 and a connected second capacitor CP2', and a branch P22 of the second port P2. Specifically, a current signal can flow from the first port P1 into the second electrode E12 and the first capacitor CP1'.

[0074] Next, the current signal can enter the conductive pattern 212 through the via V3B. The via V3B is located between the second electrode E12 and the conductive pattern 212. It then enters the conductive pattern 222B through the conductive via 214. The conductive pattern 222B can interact with the conductive pattern 222 (shown in...). Figure 2A (In the same layer as the middle) but not limited to this.

[0075] Next, the current signal enters the conductive pattern 212B through the via V7B. The via V7B is located between the conductive pattern 212B and the conductive pattern 222B. The conductive pattern 212B can be located on the same layer as the conductive pattern 212, but is not limited thereto.

[0076] Next, the current signal enters the conductive pattern 222B through the via V9B. The via V9B is located between the conductive pattern 212B and the conductive pattern 222B. The vias V7B and V9B can be located on the same layer as the conductive via 214, but are not limited thereto.

[0077] Next, the current signal enters the conductive pattern 212 through the conductive via 214, and then enters the fourth electrode E22 through the via V6B. The via V6B is located between the fourth electrode E22 and the conductive pattern 222B. The fourth electrode E22 is electrically connected to the second capacitor CP2'. Thus, the current signal can flow into the second capacitor CP2' electrically connected to the fourth electrode E22.

[0078] Next, the current signal can flow into branch P22 of the second port P2 through the fourth electrode E22.

[0079] Under the above configuration, the first capacitor CP1' or the second capacitor CP2' of the symmetrical capacitor SC2 of the passive component integration layer 100B can be electrically connected to the first port P1 or the second port P2 through the conductive patterns 222B and 212A of the redistribution layer 200B.

[0080] Please continue to refer to this. Figure 6 and Figure 7B The second path includes, for example, a branch P12 of the first port P1, a third electrode E21 and a connected second capacitor CP2', conductive patterns 222B', 232B', 222B', a first electrode E11 and a connected first capacitor CP1', and a branch P21 of the second port P2. Specifically, a current signal can flow from the first port P1 into the third electrode E21 and the second capacitor CP2'.

[0081] Next, the current signal can enter the conductive pattern 212 through the via V5B. The via V5B is located between the third electrode E21 and the conductive pattern 212. It then enters the conductive pattern 222B' through the conductive via 214. The conductive pattern 222B' can interact with the conductive pattern 222 (shown in...). Figure 2A (In the same layer as the middle) but not limited to this.

[0082] Next, the current signal enters the conductive pattern 232B' through the via V8B. The via V8A is disposed between the conductive pattern 232B' and the conductive pattern 222B'. The conductive pattern 232B' may be disposed on the same layer as the conductive pattern 232, but is not limited thereto. In some embodiments, please also refer to Figure 6 , Figure 7A and Figure 7B Conductive pattern 232B' can overlap conductive pattern 212B. That is, conductive pattern 222B and conductive pattern 222B' can achieve cross-layer bridging through conductive pattern 212B or conductive pattern 232B'.

[0083] Next, the current signal enters the conductive pattern 222B' through the via V10B. The via V10B is located between the conductive pattern 232B' and the conductive pattern 222B'. The vias V8B and V10B can be located on the same layer as the conductive via 214, but are not limited thereto.

[0084] Next, the current signal enters the conductive pattern 212 through the conductive via 214, and then enters the first electrode E11 through the via V4B. The via V4B is disposed between the first electrode E11 and the conductive pattern 212. The first electrode E11 is electrically connected to the first capacitor CP1'. In this way, the current signal can flow into the first capacitor CP1' electrically connected to the first electrode E11.

[0085] Next, the current signal can flow through the first electrode E11 into the branch P21 of the second port P2.

[0086] Under the above configuration, the first capacitor CP1' or the second capacitor CP2' of the symmetrical capacitor SC2 in the passive component integration layer 100B can be electrically connected to the first port P1 or the second port P2 through the three conductive patterns in the redistribution layer 200B, including the lower conductive pattern 212B, the upper conductive pattern 232B', and the conductive patterns 222B and 222B' located between the conductive patterns 212B and 232B'. Furthermore, the conductive patterns of the redistribution layer 200A in the first and second paths can be interleaved or arranged in an X-shape, but are not limited thereto.

[0087] Under the above configuration, the resistance value on the first path can be substantially the same as the resistance value on the second path. Furthermore, the resistance value connected to the second port P2 of the first path is substantially the same as the resistance value connected to the second port P2 of the second path. That is, the resistance values, scattering parameters, reactance, or inductance measured at the first port P1 and the second port P2 can be substantially the same. The capacitance values ​​of the first capacitor CP1' and the second capacitor CP2' can be substantially the same. In this way, the electrical quality of the packaged element 10B can be improved. Furthermore, the packaged element 10B can achieve electrical quality similar to that described in the above embodiment.

[0088] Figure 8 This is a top view schematic diagram of a packaged element according to another embodiment of this disclosure. For clarity and ease of explanation, Figure 8 Several components are omitted from the diagram. The package element 10C in this embodiment is generally similar to... Figure 1 The package element 10 is used, therefore, the same and similar components in both embodiments will not be repeated here. The main difference between this embodiment and the package element 10 is that the symmetrical capacitor of the passive component integration layer of the package element 10C includes more capacitors. For example, the symmetrical capacitor SC3 of the passive component integration layer includes a first capacitor CP1, a second capacitor CP2, and a third capacitor CP3. The first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 are respectively connected to the first port P1 or the second port P2. The first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 are connected in parallel with each other. It should be noted that the number of capacitors shown in this disclosed embodiment is only for illustrative purposes, and in reality, the symmetrical capacitor may contain three, four, five, or more capacitors, and is not limited to what is shown in the figures.

[0089] In detail, the first port P1 has three branches P11, P12, and P13. The second port P2 has three branches P21, P22, and P23. Branch P11 contacts the first electrode E11, and branch P12 contacts the second electrode E12. In this way, branches P11 and P21 are configured to correspond to the first capacitor CP1.

[0090] Branch P12 contacts the third electrode E21 and branch P22 contacts the fourth electrode E22. In this way, branches P12 and P22 are configured to correspond to the second capacitor CP2.

[0091] In some embodiments, the passive component integration layer further includes a fifth electrode E31 and a sixth electrode E32 corresponding to the third capacitor CP3. The fifth electrode E31 and the sixth electrode E32 may be similar to the first electrode E11 and the second electrode E12, respectively. In other words, the fifth electrode E31 and the sixth electrode E32 may overlap the first metal layer M31 of the third capacitor CP3. The three-electrode capacitor CP3 is, for example, a capacitor structure of a first metal layer M31, an insulating layer 140, and a second metal layer (not shown). The fifth electrode E31 may be electrically connected to the first metal layer M31, and the sixth electrode E32 may be electrically connected to the second metal layer, but this is not a limitation.

[0092] In some embodiments, the volume of the fifth electrode E31 may be larger than that of the sixth electrode E32, but this is not a limitation.

[0093] Branch P13 contacts the fifth electrode E31 and branch P22 contacts the sixth electrode E32. In this way, branches P13 and P23 are set to correspond to the third capacitor CP3.

[0094] Under the above configuration, the third capacitor CP3 is connected in parallel with either the first capacitor CP1 or the second capacitor CP2.

[0095] In this way, the resistance values ​​measured at the first port P1 and the second port P2 of the packaged element 10C are the same. Furthermore, the scattering parameters, reactance, or inductance measured at the first port P1 and the second port P2 of the packaged element 10C can be substantially the same. The capacitance values ​​of the first capacitor CP1, the second capacitor CP2, or the third capacitor CP3 can be substantially the same. In this way, the electrical quality of the packaged element 10C can be improved. Furthermore, the packaged element 10C can achieve electrical quality similar to that described in the above embodiment.

[0096] Figure 9This is a cross-sectional schematic diagram of an electronic device according to some embodiments disclosed herein. The electronic device 300 includes, for example, a passive component integration layer 310, a redistribution layer 320, an electronic component 330, a connector 340, and an encapsulation material 350. The passive component integration layer 310 can be implemented by the passive component integration layers 100, 100A, or 100B described in the above embodiments, and details of the passive component integration layer 310 can be found in the above description. The redistribution layer 320 can be implemented by the redistribution layers 200, 200A, or 200B described in the above embodiments, and details of the redistribution layer 320 can be found in the above description. Specifically, in this embodiment, the redistribution layer 320 is disposed on the electronic component 330, and the passive component integration layer 310 is disposed on the redistribution layer 320. The connector 340 is disposed between the electronic component 330 and the redistribution layer 320 to allow the electronic component 330 to be electrically connected to the redistribution layer 320. The encapsulation material 350 surrounds the electronic component 330 to encapsulate the electronic component 330.

[0097] In some embodiments, electronic component 330 may be an integrated circuit (IC). In some other embodiments, electronic component 330 may be a printed circuit board (PCB), a capacitor, etc. Furthermore, the encapsulation material 350 may be selectively omitted as needed by the design. In some embodiments, connector 340 may be a bonding pad formed on the surface of electronic component 330.

[0098] In some embodiments, the electronic device 300 can be manufactured using a chip-first process. Specifically, in the chip-first process, an electronic component 330 can be attached to a substrate (not shown) and encapsulated using an encapsulation material 350. A connector 340 is formed on the electronic component 330 and can be exposed by the encapsulation material 350. A redistribution layer 320 can be formed on the connector 340 to electrically connect to the electronic component 330 via the connector 340, and a passive component integration layer 310 can be formed on the redistribution layer 320. The electronic component 330 can be electrically connected to the passive component integration layer 310 via the redistribution layer 320, but is not limited thereto. Furthermore, after the passive component integration layer 310 is formed, the formed structure can be separated and decoupled from the substrate (not shown) to form the electronic device 300.

[0099] Figure 10 This is a schematic cross-sectional view of an electronic device that discloses some embodiments. Figure 10The electronic device 300A is similar to electronic device 300 and includes a passive component integration layer 310, a redistribution layer 320, electronic components 330, connectors 340, and packaging material 350. Specifically, electronic device 300A differs from electronic device 300 in the stacking order of the passive component integration layer 310 and the redistribution layer 320. In electronic device 300A, the passive component integration layer 310 is disposed between the redistribution layer 320 and the electronic components 330. Electronic device 300A can be manufactured using a chip-first process, and the passive component integration layer 310 is formed before the redistribution layer 320.

[0100] Figure 11 This is a schematic cross-sectional view of an electronic device that discloses some embodiments. Figure 11 Electronic device 300B is similar to electronic device 300A and includes a passive component integration layer 310, a redistribution layer 320, two electronic components 330, a connector 340, and an encapsulation material 350. Specifically, electronic device 300B differs from electronic device 300A in the number of electronic components 330. In electronic device 300B, the two electronic components 330 are encapsulated by the encapsulation material 350, and the passive component integration layer 310 and the redistribution layer 320 are formed on the two electronic components 330. In some embodiments, the number of electronic components 330 may be varied based on the desired circuit design and / or functionality.

[0101] Figure 12 This is a cross-sectional schematic diagram of an electronic device according to some embodiments disclosed herein. The electronic device 400 includes, for example, a passive component integration layer 410, a redistribution layer 420, an electronic component 430, and a connector 440. The passive component integration layer 410 may be implemented by the passive component integration layers 100, 100A, or 100B described in the above embodiments, and details of the passive component integration layer 410 can be found in the above description. The redistribution layer 420 may be implemented by the redistribution layers 200, 200A, or 200B described in the above embodiments, and details of the redistribution layer 420 can be found in the above description. Specifically, in this embodiment, the redistribution layer 420 is disposed on the passive component integration layer 410, and the electronic component 430 is disposed on the redistribution layer 420. The connector 440 is disposed between the electronic component 430 and the redistribution layer 420 to allow the electronic component 430 to be electrically connected to the redistribution layer 420. Furthermore, in some embodiments, the stacking order of the passive component integration layer 410 and the redistribution layer 420 may be changed.

[0102] In summary, in the electronic device or packaged element of this disclosure embodiment, due to the symmetry of the passive component integration layer, the resistance values ​​of the first port and the second port are substantially the same. With the above-described configuration, the scattering parameters measured at the first port or the second port can be substantially the same, thus achieving a symmetrical capacitor configuration. This avoids the problem of capacitor directionality. Furthermore, when the first port is grounded and the second port receives a signal, or when the first port receives a signal and the second port is grounded, the resistance, scattering parameters, reactance, inductance, or capacitance values ​​measured at the first port and the second port can be substantially the same. Moreover, the resistance and reactance on different paths can be substantially the same, therefore the resistance, scattering parameters, reactance, inductance, or capacitance values ​​measured at the first port and the second port on different paths can be substantially the same. The electrical quality of the packaged element can be improved.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaged element, characterized in that, include: Rewire layer; A passive component integration layer, in contact with the redistribution layer, the passive component integration layer having at least one capacitor, the at least one capacitor comprising: First capacitor; and Second capacitor; A first port, electrically connected to the first capacitor and the second capacitor; and A second port is configured relative to the first port, and the second port is electrically connected to both the first capacitor and the second capacitor. The resistance values ​​of the first port and the second port are the same.

2. The packaging element according to claim 1, characterized in that, The rewiring layer is electrically connected to the first port or the second port.

3. The packaging element according to claim 1, characterized in that, The first capacitor is connected in parallel with the second capacitor.

4. The packaging element according to claim 1, characterized in that, The passive component integration layer further includes a first electrode and a second electrode, which are electrically connected to the first port and the second port, respectively, and the first capacitor is electrically connected to the redistribution layer through the first electrode or the second electrode.

5. The packaging element according to claim 4, characterized in that, The length of the first electrode is greater than the length of the second electrode.

6. The packaging element according to claim 4, characterized in that, The first capacitor includes a first metal layer and a second metal layer, wherein, in the normal direction of the package element, the outer edge of the second metal layer is inside the outer edge of the first metal layer.

7. The packaging element according to claim 6, characterized in that, The height of the first electrode in the normal direction is greater than the height of the first metal layer in the normal direction.

8. The packaging element according to claim 1, characterized in that, The passive component integration layer also includes a third capacitor connected to the first port and the second port, wherein the resistance values ​​of the first port and the second port are the same, and the third capacitor is connected in parallel to the first capacitor or the second capacitor.

9. The packaging element according to claim 4, characterized in that, The passive component integration layer further includes a third electrode and a fourth electrode, which are electrically connected to the first port and the second port, respectively, and the second capacitor is electrically connected to the redistribution layer through the third electrode or the fourth electrode.

10. The packaging element according to claim 9, characterized in that, The first capacitor and the second electrode connected to the first capacitor are electrically connected to the second capacitor and the fourth electrode connected to the second capacitor through the redistribution layer, and the second capacitor and the third electrode connected to the second capacitor are electrically connected to the first capacitor and the first electrode connected to the first capacitor through the redistribution layer, wherein the first port is connected to the second electrode and the third electrode, and the second port is connected to the first electrode and the fourth electrode.

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