Memory cell and method of making the same

Abstract

The present disclosure provides a storage unit and a manufacturing method thereof. The storage unit comprises a transistor and a capacitor structure connected in sequence in a direction away from a substrate, the capacitor structure comprising: an inner electrode connected with the transistor, the inner electrode comprising a first inner electrode and a second inner electrode located on both sides of the transistor, the first inner electrode extending in a first direction parallel to the substrate, and the second inner electrode extending in a second direction opposite to the first direction; an outer electrode arranged at least at the outer periphery of the inner electrode; and a dielectric layer arranged at least between the inner electrode and the outer electrode. Since the first inner electrode and the second inner electrode extend in a direction parallel to the substrate, the outer electrode is located at the outer periphery of the dielectric layer, and the dielectric layer is located between the inner electrode and the outer electrode, thereby fully utilizing the size of the substrate to expand the capacitor structure in a direction parallel to the substrate, ensuring that the overall process size remains unchanged, while increasing the storage capacity by increasing the size of the capacitor structure, thereby improving the working efficiency of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory cell and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) cells consist of capacitors for storing charge and transistors for accessing the capacitors. DRAM stores data in the form of charge on the capacitors, so the capacitors need to be regularly recharged every few milliseconds. The larger the capacitance of the capacitor, the longer the data stored in the DRAM can be retained.

[0003] As the size of semiconductor devices shrinks, the structure of memory cells also shrinks significantly. However, due to the limitations of current DRAM structures, it is difficult to further break through the limits of capacitor structure size. This affects the ability of DRAM to store charge, resulting in lower DRAM operating efficiency. Summary of the Invention

[0004] The main objective of this disclosure is to provide a storage unit and a method for manufacturing the same, in order to solve the problem of low operating efficiency of existing memory.

[0005] To achieve the above objectives, according to one aspect of this disclosure, a memory cell is provided, comprising a transistor and a capacitor structure sequentially connected in a direction away from a substrate. The capacitor structure includes: an inner electrode connected to the transistor, the inner electrode including a first inner electrode and a second inner electrode located on both sides of the transistor, the first inner electrode extending in a first direction parallel to the substrate, and the second inner electrode extending in a second direction opposite to the first direction; an outer electrode disposed at least on the outer periphery of the inner electrode; and a dielectric layer disposed at least between the inner electrode and the outer electrode.

[0006] Optionally, the transistor includes a source region, a drain region, a channel region, and a gate structure. The channel region is located between the source region and the drain region, and the gate structure is disposed around the channel region. The memory cell further includes: a first conductive portion disposed between the channel region and the substrate, with the source region located in the first conductive portion; a second conductive portion disposed on the side of the channel region away from the first conductive portion, with the drain region located in the second conductive portion, and internal electrodes located on both sides of the second conductive portion.

[0007] Optionally, the inner electrode has a first surface and a second surface opposite to each other, the first surface being located on the side of the second surface closer to the substrate, the dielectric layer covering at least the first surface and the second surface, and the outer electrode covering the dielectric layer.

[0008] Optionally, the memory cell further includes: insulating sidewalls located on both sides of the second conductive portion in the extending direction, wherein in the first direction, the thickness of the insulating sidewalls is greater than the thickness of the gate structure, the side of the inner electrode having a first surface is the first side, and a portion of the dielectric layer and a portion of the outer electrode located on the first side are isolated from the second conductive portion by the insulating sidewalls.

[0009] Optionally, the external electrode includes: a first external electrode located on the outer periphery of the first internal electrode; and a second external electrode located on the outer periphery of the second internal electrode.

[0010] Optionally, the external electrode further includes a connecting portion located on the side of the second conductive portion away from the channel region, and the first external electrode is connected to the second external electrode through the connecting portion.

[0011] Optionally, the first conductive portion, the channel region, and the second conductive portion extend along a third direction, which is perpendicular to the first direction and parallel to the substrate.

[0012] Optionally, the storage unit further includes a metal silicide layer disposed between the second conductive portion and the internal electrode.

[0013] According to another aspect of this disclosure, a method for fabricating a memory cell is provided, including the steps of forming a transistor and a capacitor structure on a substrate, wherein the step of forming the capacitor structure includes: forming an inner electrode connected to the transistor on the substrate, the inner electrode including a first inner electrode and a second inner electrode located on both sides of the transistor, the first inner electrode extending along a first direction parallel to the substrate, and the second inner electrode extending along a second direction opposite to the first direction; and sequentially forming a dielectric layer and an outer electrode on the outer periphery of the inner electrode, the dielectric layer being disposed at least between the inner electrode and the outer electrode.

[0014] Optionally, the step of forming a transistor on a substrate includes: forming a first conductive portion on the substrate, forming a source region in the first conductive portion; sequentially forming a channel region and a gate structure on the first conductive portion, such that the gate structure is disposed around the channel region; forming a second conductive portion on the channel region, forming a drain region in the second conductive portion.

[0015] Optionally, the fabrication method further includes: before forming the second conductive portion, forming an interlayer dielectric layer on a substrate, the interlayer dielectric layer at least covering the gate structure; after forming the second conductive portion, covering both sides of the second conductive portion with insulating sidewalls; covering the interlayer dielectric layer with a sacrificial layer so that the insulating sidewalls are located between the second conductive portion and the sacrificial layer; etching back the insulating sidewalls to expose a portion of the second conductive portion; and forming a metal silicide layer in the etched-back area of ​​the insulating sidewalls.

[0016] Optionally, the insulating sidewall and the second conductive portion have a first etch selectivity ratio, and the sacrificial layer and the second conductive portion have a second etch selectivity ratio, wherein the first etch selectivity ratio is less than the second etch selectivity ratio.

[0017] Optionally, the step of forming an internal electrode connected to the transistor includes: forming trenches on both sides of the second conductive portion in a sacrificial layer, wherein the trench on one side of the second conductive portion extends to the metal silicide layer in a first direction, and the trench on the other side of the second conductive portion extends to the metal silicide layer in a second direction, wherein the portion of the sacrificial layer other than the trenches has a third surface; covering the sacrificial layer with internal electrode material so that a portion of the internal electrode material fills the trenches; and sequentially removing the portion of the internal electrode material located on the third surface and the sacrificial layer, wherein the remaining internal electrode material constitutes the internal electrode.

[0018] Optionally, the second conductive portion has a fourth surface on the side away from the channel region, and the step of forming the dielectric layer and the outer electrode includes: covering the exposed surface of the inner electrode and the fourth surface with the dielectric layer; and covering the surface of the dielectric layer with the outer electrode.

[0019] Optionally, the second conductive portion has a fourth surface on the side away from the channel region. The steps of forming the dielectric layer and the outer electrode include: covering the exposed surface of the inner electrode and the fourth surface with a dielectric material; removing a portion of the dielectric material located on the fourth surface to expose the fourth surface, with the remaining dielectric material constituting the dielectric layer; covering the surface of the dielectric layer and the fourth surface with an outer electrode material; removing a portion of the outer electrode material located on the fourth surface, with the remaining outer electrode material constituting the outer electrode.

[0020] By applying the technical solution of this disclosure, a memory cell is provided, comprising a transistor and a capacitor structure sequentially connected along a direction away from the substrate. The capacitor structure includes an inner electrode, an outer electrode, and a dielectric layer. The inner electrode is connected to the transistor. Since the inner electrode includes a first inner electrode extending along a first direction parallel to the substrate and a second inner electrode extending along a second direction parallel to the substrate, and the outer electrode is at least disposed on the outer periphery of the dielectric layer, and the dielectric layer is at least disposed between the first inner electrode and the outer electrode, and between the second inner electrode and the outer electrode, the original substrate size can be fully utilized to expand the capacitor structure along a direction parallel to the substrate. This allows for increased storage capacity by increasing the size of the capacitor structure while maintaining the overall process dimensions, thereby improving the memory's operating efficiency. Furthermore, the fabrication process of this memory cell is simpler, eliminating the need to consider aspect ratio. Attached Figure Description

[0021] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:

[0022] Figures 1 to 3The diagram shows a cross-sectional, top, and side view of a storage cell according to an embodiment of the present disclosure.

[0023] Figures 4 to 6 Cross-sectional, top, and side view structural schematic diagrams of another storage cell according to embodiments of the present disclosure are shown respectively;

[0024] Figure 7 and Figure 8 The images show cross-sectional and top views of the substrate after bit lines are formed on a substrate in a method for fabricating a memory cell according to an embodiment of the present disclosure.

[0025] Figure 9 and Figure 10 The cross-sectional and top view schematic diagrams of the substrate after the first conductive portion is formed on the substrate are shown respectively;

[0026] Figure 11 and Figure 12 Cross-sectional and top view schematic diagrams of the substrate after forming trenches that penetrate the substrate are shown respectively;

[0027] Figure 13 and Figure 14 The diagram shows a cross-sectional and top view of the substrate after the first conductive portion located in the trench is formed on the substrate.

[0028] Figure 15 and Figure 16 The diagram shows a cross-sectional and top view of the substrate after the first interlayer dielectric layer is covered on the site line and the second insulating layer;

[0029] Figure 17 and Figure 18 A cross-sectional and top view schematic diagram of the substrate after the gate structure surrounds the outer periphery of the above-mentioned nanowire channel is shown;

[0030] Figure 19 and Figure 20 The diagram shows a cross-sectional and top view of the substrate after the second conductive portion is formed on the channel region;

[0031] Figure 21 and Figure 22 The diagram shows a cross-sectional and top view of the substrate after the insulating sidewalls covering both sides of the second conductive part are formed and the sacrificial layer is formed;

[0032] Figure 23 and Figure 24 The diagram shows a cross-section and top view of the substrate after the back-etched insulating sidewalls are shown;

[0033] Figure 25 and Figure 26 The diagram shows a cross-sectional and top view of the substrate after a metal silicide layer is formed in the etched area of ​​the insulating sidewall;

[0034] Figures 27 to 30 The diagram shows a cross-sectional, top, and side view of the substrate after grooves are formed on both sides of the second conductive portion in the sacrificial layer.

[0035] Figures 31 to 33 The diagram shows a cross-sectional, top, and side view of the substrate after a portion of the internal electrode material has been filled into the groove.

[0036] Figures 34 to 36 The diagram shows cross-sectional, top, and side views of the substrate after sequential removal of the portion of the inner electrode material located on the third surface and the sacrificial layer.

[0037] Figures 37 to 39 The diagram shows a cross-sectional, top, and side view of the substrate after the exposed surface of the inner electrode and the fourth surface are covered with a dielectric layer.

[0038] Figure 40 This diagram shows a cross-sectional structure of the substrate after a third interlayer dielectric layer is applied to the surface of the outer electrode.

[0039] Figure 41 and Figure 42 A cross-sectional and top view of the substrate are shown after a portion of the dielectric material located on the fourth surface has been removed to expose the fourth surface.

[0040] Figure 43 and Figure 44 The diagram shows a cross-sectional and top view of the substrate after the outer electrode material is covered on the surface of the dielectric layer and the fourth surface;

[0041] Figure 45 A schematic cross-sectional view of the substrate is shown after a third interlayer dielectric layer is coated on the surface of the outer electrode.

[0042] The above figures include the following reference numerals:

[0043] 10. First conductive portion; 100. Substrate; 101. First insulating layer; 102. Second insulating layer; 103. Bit line; 104. First interlayer dielectric layer; 110. Trench; 201. First mask layer; 210. Channel region; 220. Gate structure; 30. Second conductive portion; 301. Second interlayer dielectric layer; 302. Sacrificial layer; 303. Metal silicide layer; 304. Second mask layer; 305. Groove; 311. Insulating sidewall; 312. Third surface; 40. Inner electrode; 401. Inner electrode material; 410. First inner electrode; 420. Second inner electrode; 50. Dielectric layer; 60. Outer electrode; 610. First outer electrode; 620. Second outer electrode; 630. Connector; 70. Third interlayer dielectric layer. Detailed Implementation

[0044] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] In some embodiments, the limits of capacitor structure size are difficult to further overcome due to the limitations of current DRAM structures, which affects the ability of DRAM to store charge, resulting in lower DRAM operating efficiency.

[0048] The inventors of this disclosure have studied the above-mentioned problems and, in one embodiment of this disclosure, proposed a storage unit, such as... Figures 1 to 3 As shown, a transistor and capacitor structure are sequentially connected along a direction away from the substrate 100. The capacitor structure includes: an inner electrode 40 connected to the transistor, the inner electrode 40 including a first inner electrode 410 and a second inner electrode 420 located on both sides of the transistor, the first inner electrode 410 extending along a first direction A parallel to the substrate 100, and the second inner electrode 420 extending along a second direction B opposite to the first direction A; an outer electrode 60 disposed at least on the outer periphery of the inner electrode 40; and a dielectric layer 50 disposed at least between the inner electrode 40 and the outer electrode 60.

[0049] Because the internal electrode 40 in the aforementioned memory cell includes a first internal electrode 410 extending along a first direction A parallel to the substrate 100 and a second internal electrode 420 extending along a second direction B parallel to the substrate 100, and the external electrode 60 is at least disposed on the outer periphery of the dielectric layer 50, with the dielectric layer 50 at least disposed between the first internal electrode 410 and the external electrode 60 and between the second internal electrode 420 and the external electrode 60, the original size of the substrate 100 can be fully utilized to expand the capacitor structure along a direction parallel to the substrate 100. This allows for increased storage capacity by increasing the size of the capacitor structure while maintaining the overall process dimensions, thereby improving the memory's operating efficiency. Furthermore, the fabrication process of this memory cell is simpler, eliminating the need to consider aspect ratio.

[0050] The transistor described above may include a source region, a drain region, a channel region 210, and a gate structure 220, such as Figures 1 to 4 As shown, the channel region 210 is located between the source region and the drain region, and the gate structure 220 is disposed around the channel region 210. In an optional embodiment, the memory cell further includes a first conductive portion 10 and a second conductive portion 30. The first conductive portion 10 is disposed between the channel region 210 and the substrate 100, the source region is located in the first conductive portion 10, the second conductive portion 30 is disposed on the side of the channel region 210 away from the first conductive portion 10, the drain region is located in the second conductive portion 30, and the internal electrode 40 is located on both sides of the second conductive portion 30.

[0051] In the above optional embodiments, the materials forming the first conductive portion 10 and the second conductive portion 30 can both be semiconductor materials, and the first conductive portion 10 and the second conductive portion 30 are connected by a semiconductor structure located between them. Ion implantation is performed on the first conductive portion 10 and the second conductive portion 30 respectively to form the source region and the drain region, thereby forming a channel region 210 in the semiconductor structure located between the first conductive portion 10 and the second conductive portion 30. The implanted ions can be boron, boron fluoride, indium, or gallium, or the implanted ions can be phosphorus, arsenic, or antimony, etc.

[0052] In the above optional embodiments, the gate structure 220 may include a gate oxide layer and a gate layer. The gate oxide layer is disposed around the channel region 210, and the gate layer encapsulates the gate oxide layer. The gate oxide layer may be SiO2, and the material of the gate layer may be polycrystalline silicon or titanium nitride, but is not limited to these types. Those skilled in the art can make reasonable selections according to actual needs.

[0053] For example, the semiconductor structure described above is a nanowire structure, which allows the channel region 210 to form a nanowire channel. In this case, the gate structure 220 can completely surround the outer periphery of the nanowire channel, forming a gate-all-around FET (GAAFET). Compared to a fin FET where the channel region 210 is only covered by the gate structure 220 on three sides, the GAAFET, because the channel region 210 is completely surrounded by the gate structure 220, can have higher electrostatic characteristics and stronger channel control capabilities, which is beneficial for further miniaturization of the device size.

[0054] In the above optional embodiments, the transistor can be connected to the bit line 103 via the first conductive portion 10, such as... Figure 1 and Figure 2 As shown. In a direction parallel to the substrate 100, the extension direction of the bit line 103 intersects the extension direction of the first conductive portion 10, so that the bit line 103 can contact the first conductive portion 10 in the plurality of memory cells, thereby enabling the transistors in the plurality of memory cells to be connected to the same bit line 103 through the first conductive portion 10 therein.

[0055] In the above optional embodiments, the first conductive portion 10, the channel region 210, and the second conductive portion 30 can each extend along a third direction C, which is perpendicular to the first direction A and parallel to the substrate 100, thereby forming a vertical transistor structure, such as... Figure 2 and Figure 5 As shown, where, Figure 2 and Figure 5 The third-party C shown in the figure are respectively Figure 1 and Figure 4 The direction perpendicular to the paper, i.e. Figure 1 and Figure 4 The middle channel region 210 and the second conductive portion 30 extend in a direction perpendicular to the plane of the paper. This vertical transistor structure facilitates the growth of the channel region 210, thereby helping to avoid short-channel effects.

[0056] A dielectric layer 50 is disposed at least between the inner electrode 40 and the outer electrode 60. In an optional embodiment, the inner electrode 40 has opposing first and second surfaces, with the first surface located on the side of the second surface closer to the substrate 100. The dielectric layer 50 covers at least the first and second surfaces, and the outer electrode 60 covers the dielectric layer 50.

[0057] In the above optional embodiments, the inner electrode 40 and the outer electrode 60 can be titanium nitride (TiN) layers. However, they are not limited to the above types, and the materials of the inner electrode 40 and the outer electrode 60 can also be independently selected from other types of metals or metal compounds.

[0058] In the above optional embodiments, the dielectric layer 50 can be a high-k dielectric layer. For example, the high-k dielectric layer can be a titanium oxide layer (TiO₂). x ) or zirconium oxide layer (ZrO) x However, it is not limited to the above types, and those skilled in the art can make reasonable selections according to actual needs.

[0059] In an optional implementation, the storage unit of this embodiment further includes an insulating sidewall 311, such as... Figure 1 and Figure 3 As shown, the insulating sidewalls 311 are located on both sides of the second conductive portion 30 in the extending direction. In the first direction A parallel to the substrate 100, the thickness of the insulating sidewalls 311 is greater than the thickness of the gate structure 220. The side of the inner electrode 40 with the first surface is the first side. A portion of the dielectric layer 50 and a portion of the outer electrode 60 located on the first side are isolated from the second conductive portion 30 by the insulating sidewalls 311. Both the second conductive portion 30 and the channel region 210 extend along the third direction C. By making the width of the insulating sidewalls 311 in the first direction A greater than the width of the gate structure 220, it is possible to prevent the outer electrode 60 and the gate structure 220 from overlapping in the direction perpendicular to the first direction A, thereby reducing parasitic capacitance.

[0060] In one optional embodiment, the external electrode 60 includes a first external electrode 610, a second external electrode 620, and a connecting portion 630. The connecting portion 630 is located on the side of the second conductive portion 30 away from the channel region 210. The first external electrode 610 is connected to the second external electrode 620 through the connecting portion 630. Figures 1 to 3 As shown, in such Figure 3 In the side view shown, the outer electrode 60 completely encloses the dielectric layer 50. At this time, the dielectric layer 50 is located between the outer electrode 60, the first inner electrode 410, and the second inner electrode 420, forming a capacitor structure. The first outer electrode 610, the second outer electrode 620, and the connecting portion 630 can be integrally formed from the same conductive material.

[0061] According to another embodiment of this disclosure, the provided storage unit is as follows: Figures 4 to 6 As shown, the inner electrode 40 includes a first inner electrode 410 and a second inner electrode 420 located on both sides of the transistor. The outer electrode 60 includes a first outer electrode 610 and a second outer electrode 620. The first outer electrode 610 is located on the outer periphery of the first inner electrode 410, and the second outer electrode 620 is located on the outer periphery of the second inner electrode 420. At this time, a portion of the dielectric layer 50 is located between the first outer electrode 610 and the first inner electrode 410, and another portion of the dielectric layer 50 is located between the second outer electrode 620 and the second inner electrode 420, thereby forming two capacitor structures respectively.

[0062] In the memory cells of the different embodiments described above, a metal silicide layer 303 may also be disposed between the second conductive portion 30 and the inner electrode 40, such as... Figures 1 to 6 As shown. The aforementioned metal silicide layer 303 can reduce the contact resistance of the device, thereby reducing leakage current. For example, the aforementioned metal silicide layer 303 is a cobalt silicide layer (CoSi). x ).

[0063] According to another embodiment of this disclosure, a method for fabricating a memory cell is also provided, including the steps of forming a transistor and a capacitor structure on a substrate 100, wherein the step of forming the capacitor structure includes: forming an inner electrode 40 connected to the transistor on the substrate 100, the inner electrode 40 including a first inner electrode 410 and a second inner electrode 420 located on both sides of the transistor, the first inner electrode 410 extending along a first direction A parallel to the substrate 100, and the second inner electrode 420 extending along a second direction B opposite to the first direction A; and sequentially forming a dielectric layer 50 and an outer electrode 60 on the outer periphery of the inner electrode 40, the dielectric layer 50 being at least disposed between the inner electrode 40 and the outer electrode 60.

[0064] Exemplary embodiments of the method for manufacturing a storage cell according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0065] First, a substrate 100 is provided, and a transistor is formed on the substrate 100.

[0066] The substrate 100 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0067] In one optional embodiment, a bit line 103 extending along a first direction A is formed on the substrate 100. The formation process may include: sequentially depositing a first insulating layer 101, a second insulating layer 102, and a polysilicon layer on the surface of the substrate 100; and then etching the polysilicon layer to form the bit line 103 extending along the first direction A. Figure 7 and Figure 8 As shown. Using polycrystalline silicon to form the bit line 103 helps to avoid severe leakage and increased resistance caused by a strong electric field when the metal bit line 103 contacts the gate structure 220.

[0068] In one alternative embodiment, the step of forming a transistor on the substrate 100 includes: forming a first conductive portion 10 on the substrate 100, and forming a source region in the first conductive portion 10, such as... Figures 9 to 14 As shown; a channel region 210 and a gate structure 220 are sequentially formed on the first conductive portion 10, such that the gate structure 220 is disposed around the channel region 210, as shown. Figures 15 to 18 As shown; a second conductive portion 30 is formed on the channel region 210, and a drain region is formed in the second conductive portion 30, as shown. Figure 19 and Figure 20 As shown.

[0069] For example, the step of forming the first conductive portion 10 includes: covering a first mask layer 201 on a substrate 100 on which the bit line 103 is formed, the first mask layer 201 having a through region corresponding to the pre-formed first conductive portion 10, the through region extending along a third direction C, and the third direction C being perpendicular to the first direction A, such as... Figure 9 and Figure 10 As shown, where, Figure 10 The third party C shown in the figure is Figure 9 The direction perpendicular to the paper, i.e. Figure 9 The through-region extends perpendicular to the plane of the paper; then, bit lines 103, the second insulating layer 102, and the first insulating layer 101 are sequentially etched through this through-region to expose a portion of the surface of the substrate 100, thereby forming a trench 110 penetrating the substrate 100, as shown below. Figure 11 and Figure 12 As shown; a conductive material is deposited on the exposed surface of the substrate 100 to form a first conductive portion 10 partially located in the trench 110, as shown. Figure 13 and Figure 14 As shown.

[0070] In the above optional embodiments, a first interlayer dielectric layer 104 may also be covered on the exposed surfaces of the bit line 103 and the second insulating layer 102, such as... Figure 15 and Figure 16 As shown. The aforementioned first interlayer dielectric layer 104 is used to wrap the exposed sidewalls of the first conductive portion 10, facilitating the implementation of subsequent transistor processes. The aforementioned first interlayer dielectric layer 104 can be an insulating material, such as silicon nitride.

[0071] For example, the steps of forming the channel region 210 and the gate structure 220 may include: forming a semiconductor structure on the first conductive portion 10, the semiconductor structure being a nanowire structure extending in the third direction C, and then forming a gate structure 220 that surrounds the outer periphery of the nanowire structure, such as... Figure 17 and Figure 18 As shown, where, Figure 18 The third party C shown in the figure is Figure 17 The direction perpendicular to the paper, i.e. Figure 17 The nanowire structure (i.e., channel region 210) extends in a direction perpendicular to the plane of the paper. It should be noted that after the second conductive portion 30 is subsequently formed, and ion implantation of the source / drain regions is performed in the first conductive portion 10 and the second conductive portion 30, the semiconductor structure located between the source / drain regions serves as the channel region 210 of the transistor.

[0072] In the above example, the gate structure 220 can completely surround the outer periphery of the nanowire channel, forming a gate-all-around FET (GAAFET). Compared to the FinFET, where the channel region 210 is only covered by the gate structure 220 on three sides, the GAAFET, because the channel region 210 is completely surrounded by the gate structure 220, can have higher electrostatic characteristics and stronger channel control capabilities, which is beneficial for further miniaturization of the device size.

[0073] After forming the channel region 210 and the gate structure 220, a second conductive portion 30 is formed on the channel region 210. The second conductive portion 30 can also extend along a third direction C, thereby forming a vertical transistor structure, such as... Figures 19 to 20 As shown. The above-described vertical transistor structure facilitates the growth of the channel region 210, thereby helping to avoid short-channel effects.

[0074] Following the steps described above for forming the second conductive portion 30, in an optional embodiment, an insulating material is deposited on the exposed surface of the first interlayer dielectric layer 104 to form a second interlayer dielectric layer 301. A portion of the second interlayer dielectric layer 301 covers both sides of the second conductive portion 30 to form insulating sidewalls 311. A sacrificial layer 302 is then deposited on the second interlayer dielectric layer 301 so that the insulating sidewalls 311 are located between the second conductive portion 30 and the sacrificial layer 302. Figure 21 and Figure 22 As shown; the insulating sidewall 311 is etched back to expose a portion of the second conductive part 30, as shown. Figure 23 and Figure 24 As shown; a metal silicide layer 303 is formed in the etched-back region of the insulating sidewall 311, such as Figure 25 and Figure 26 As shown.

[0075] For example, the sacrificial layer 302 is made of borosilicate glass, which is silicon dioxide doped with boron and phosphorus. Borosilicate glass has excellent pore-filling ability, which is beneficial for the planarization of the material surface after deposition.

[0076] In the above optional embodiments, the metal silicide layer 303 can reduce the contact resistance of the device, thereby reducing leakage current. For example, the metal silicide layer 303 is a cobalt silicide layer (CoSi). x ).

[0077] After the step of forming the transistor described above, an internal electrode 40 connected to the transistor is formed on the substrate 100, such as... Figures 34 to 36 As shown, the internal electrode 40 includes a first internal electrode 410 and a second internal electrode 420 located on both sides of the transistor. The first internal electrode 410 extends along a first direction A parallel to the substrate 100, and the second internal electrode 420 extends along a second direction B opposite to the first direction A.

[0078] In one optional embodiment, the step of forming the internal electrode 40 connected to the transistor includes: forming grooves 305 on both sides of the second conductive portion 30 in the sacrificial layer 302, one side of the groove 305 extending along a first direction A to the metal silicide layer 303, and the other side of the groove 305 extending along a second direction B to the metal silicide layer 303, wherein the portion of the sacrificial layer 302 other than the grooves 305 has a third surface 312, such as... Figures 27 to 30 As shown; an inner electrode material 401 is covered on the sacrificial layer 302, so that a portion of the inner electrode material 401 fills the space. Figure 30 In the groove 305 shown, as Figures 31 to 33 As shown; the portion of the inner electrode material 401 located on the third surface 312 and the sacrificial layer 302 are removed sequentially, and the remaining inner electrode material constitutes the inner electrode 40, as shown. Figures 34 to 36 As shown.

[0079] For example, the step of forming the above-mentioned groove 305 includes: forming a second mask layer 304 on the surface of the sacrificial layer 302, the second mask layer 304 having a through region extending into the sacrificial layer 302, such as... Figure 27 and Figure 28 As shown; the sacrificial layer 302 is etched through the aforementioned through-region to form grooves 305 located on both sides of the second conductive portion 30, as shown. Figure 29 and Figure 30 As shown.

[0080] For example, the step of forming the inner electrode 40 includes: depositing inner electrode material in the groove 305 and on the third surface 312, such that a portion of the inner electrode material 401 fills the groove 305 and protrudes from the groove 305, and another portion of the inner electrode material 401 covers the third surface 312, as shown. Figure 33 As shown; the inner electrode material 401 located on the third surface 312 is removed by etching, and the remaining inner electrode material 401 constitutes the inner electrode 40. Then, the sacrificial layer 302 is removed by etching. Figure 36As shown. The above deposition process can be chemical vapor deposition or ion beam sputtering, and the above etching process can be wet etching or ion beam etching. This disclosure does not make any specific limitations.

[0081] In one optional embodiment, the insulating sidewall 311 and the second conductive portion 30 have a first etching selectivity ratio, and the sacrificial layer 302 and the second conductive portion 30 have a second etching selectivity ratio, wherein the first etching selectivity ratio is smaller than the second etching selectivity ratio. For example, the insulating sidewall 311 is a SiN layer, and the sacrificial layer 302 is a SiO2 layer. Since SiN is more difficult to etch, wet etching can be used to etch away the SiO2.

[0082] After forming the inner electrode 40, a dielectric layer 50 and an outer electrode 60 are sequentially formed on the outer periphery of the inner electrode 40, with the dielectric layer 50 disposed at least between the inner electrode 40 and the outer electrode 60.

[0083] In an optional embodiment, the second conductive portion 30 has a fourth surface on the side away from the channel region 210, and the step of forming the dielectric layer 50 and the outer electrode 60 includes: covering the exposed surface of the inner electrode 40 and the fourth surface with the dielectric layer 50, such as... Figures 37 to 39 As shown; an external electrode 60 is covered on the surface of the dielectric layer 50, such as... Figures 1 to 3 As shown.

[0084] In one alternative embodiment, the thickness of the insulating sidewall 311 is greater than the thickness of the gate structure 220 in a first direction A parallel to the substrate 100, such as... Figures 1 to 3 As shown. By making the width of the insulating sidewall 311 in the first direction A greater than the width of the gate structure 220, it is possible to prevent the external electrode 60 and the gate structure 220 from having an overlapping area in the direction perpendicular to the first direction A, thereby reducing parasitic capacitance.

[0085] In an optional embodiment, the method for fabricating the memory cell may further include the step of covering the outer electrode surface with a third interlayer dielectric layer 70, such as... Figure 40 As shown. The aforementioned third interlayer dielectric layer 70 can be used to protect the capacitor structure located thereunder, and a new capacitor structure can be further formed in the aforementioned third interlayer dielectric layer 70 to form a stacked capacitor structure.

[0086] According to another embodiment of this disclosure, a method for manufacturing a memory cell is also provided, which differs from the aforementioned embodiment in that the step of forming a dielectric layer 50 and an external electrode 60 is included.

[0087] In the above embodiment, the second conductive portion 30 has a fourth surface on the side away from the channel region 210. The step of forming the dielectric layer 50 and the outer electrode 60 includes: covering the exposed surface of the inner electrode 40 and the fourth surface with a dielectric material, such as... Figures 37 to 39 As shown; the portion of the dielectric material located on the fourth surface is removed to expose the fourth surface, and the remaining dielectric material constitutes the dielectric layer 50, as shown. Figure 41 and Figure 42 As shown; an external electrode material is covered on the surface of the dielectric layer 50 and the fourth surface, such as Figure 43 and Figure 44 As shown; after removing the portion of the external electrode material located on the fourth surface, the remaining external electrode material constitutes the external electrode 60, as shown. Figures 4 to 6 As shown.

[0088] In the above embodiments, the fabrication method may also include the step of covering the outer electrode surface with a third interlayer dielectric layer 70, such as... Figure 45 As shown. The aforementioned third interlayer dielectric layer 70 can be used to protect the capacitor structure located thereunder, and a new capacitor structure can be further formed in the aforementioned third interlayer dielectric layer 70 to form a stacked capacitor structure.

[0089] According to another embodiment of this disclosure, a memory is also provided, including a plurality of memory cells as described in the above embodiments and a plurality of bit line structures, wherein: the memory cells are arranged in an array; the plurality of bit line structures extend along a first direction A and are spaced apart along a third direction C, and the bit line structures are electrically connected to transistors in the memory cells.

[0090] According to another embodiment of this disclosure, a method for manufacturing a memory is also provided, comprising the following steps:

[0091] Multiple bit line structures are formed on the substrate, and the multiple bit line structures extend along a first direction A and are spaced apart along a third direction C;

[0092] Multiple memory cells are formed using the method for fabricating memory cells in the above embodiments. The memory cells are arranged in an array, and the transistors in the memory cells are electrically connected to the bit line structure.

[0093] As can be seen from the above description, the embodiments of this disclosure achieve the following technical effects:

[0094] The memory cell includes a transistor and a capacitor structure sequentially connected in a direction away from the substrate. The capacitor structure includes an inner electrode, an outer electrode, and a dielectric layer. The inner electrode is connected to the transistor. Since the inner electrode extends in a direction parallel to the substrate, the outer electrode is disposed at least on the outer periphery of the dielectric layer, and the dielectric layer is disposed at least between the inner and outer electrodes. This allows the original substrate size to be fully utilized to expand the capacitor structure in a direction parallel to the substrate. As a result, the storage capacity can be increased by increasing the size of the capacitor structure while keeping the overall process size unchanged, thereby improving the operating efficiency of the memory.

[0095] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage unit, characterized in that, The system includes a transistor and a capacitor structure sequentially connected in a direction away from the substrate. The transistor includes a source region, a drain region, a channel region, and a gate structure. The channel region is located between the source region and the drain region. The gate structure is disposed around the channel region. The capacitor structure includes: An internal electrode is connected to the transistor. The internal electrode includes a first internal electrode and a second internal electrode located on both sides of the transistor. The first internal electrode extends along a first direction parallel to the substrate, and the second internal electrode extends along a second direction opposite to the first direction. An outer electrode layer is disposed at least on the outer periphery of the inner electrode; A dielectric layer is disposed at least between the inner electrode and the outer electrode layer; A first conductive portion is disposed between the channel region and the substrate, and the source region is located in the first conductive portion; The second conductive portion is disposed on the side of the channel region away from the first conductive portion, the drain region is located in the second conductive portion, and the inner electrode is located on both sides of the second conductive portion; The first internal electrode is electrically connected to the drain region, and the second internal electrode is electrically connected to the drain region.

2. The storage unit according to claim 1, characterized in that, The inner electrode has a first surface and a second surface opposite to each other, the first surface being located on the side of the second surface closer to the substrate, the dielectric layer covering at least the first surface and the second surface, and the outer electrode layer covering the dielectric layer.

3. The storage unit according to claim 2, characterized in that, The storage unit further includes: An insulating sidewall is located on both sides of the second conductive portion in the extending direction. In the first direction, the thickness of the insulating sidewall is greater than the thickness of the gate structure. The side of the inner electrode having the first surface is the first side. A portion of the dielectric layer and a portion of the outer electrode layer located on the first side are isolated from the second conductive portion by the insulating sidewall.

4. The storage unit according to claim 3, characterized in that, The outer electrode layer includes: The first external electrode is located on the outer periphery of the first internal electrode; The second outer electrode is located on the outer periphery of the second inner electrode.

5. The storage unit according to claim 4, characterized in that, The outer electrode layer further includes: A connecting portion is located on the side of the second conductive portion away from the channel region, and the first external electrode is connected to the second external electrode through the connecting portion.

6. The storage unit according to claim 1, characterized in that, The first conductive portion, the channel region, and the second conductive portion extend along a third direction, which is perpendicular to the first direction and parallel to the substrate.

7. The storage unit according to claim 1, characterized in that, Also includes: A metal silicide layer is disposed between the second conductive portion and the inner electrode.

8. A method for manufacturing a storage unit, characterized in that, The method includes the step of forming a transistor and a capacitor structure on a substrate, wherein the step of forming the capacitor structure includes: An internal electrode connected to the transistor is formed on the substrate. The internal electrode includes a first internal electrode and a second internal electrode located on both sides of the transistor. The first internal electrode extends along a first direction parallel to the substrate, and the second internal electrode extends along a second direction opposite to the first direction. A dielectric layer and an outer electrode layer are sequentially formed on the outer periphery of the inner electrode, wherein the dielectric layer is disposed at least between the inner electrode and the outer electrode layer; The step of forming the transistor on the substrate includes: A first conductive portion is formed on the substrate, and a source region is formed in the first conductive portion; A channel region and a gate structure are sequentially formed on the first conductive portion, such that the gate structure is disposed around the channel region; A second conductive portion is formed on the channel region, and a drain region is formed in the second conductive portion; The first internal electrode is electrically connected to the drain region, and the second internal electrode is electrically connected to the drain region.

9. The manufacturing method according to claim 8, characterized in that, The manufacturing method further includes: Prior to the step of forming the second conductive portion, an interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer at least encapsulating the gate structure; After the step of forming the second conductive portion, insulating sidewalls are covered on both sides of the second conductive portion; A sacrificial layer is covered on the interlayer dielectric layer so that the insulating sidewall is located between the second conductive portion and the sacrificial layer; The insulating sidewall is etched back to expose a portion of the second conductive part; A metal silicide layer is formed in the etched area of ​​the insulating sidewall.

10. The manufacturing method according to claim 9, characterized in that, The insulating sidewall and the second conductive portion have a first etching selectivity ratio, and the sacrificial layer and the second conductive portion have a second etching selectivity ratio, wherein the first etching selectivity ratio is less than the second etching selectivity ratio.

11. The manufacturing method according to claim 9, characterized in that, The step of forming the internal electrode connected to the transistor includes: Trenches are formed in the sacrificial layer on both sides of the second conductive portion. The trench on one side of the second conductive portion extends to the metal silicide layer along the first direction, and the trench on the other side of the second conductive portion extends to the metal silicide layer along the second direction. The portion of the sacrificial layer other than the trenches has a third surface. An inner electrode material is covered on the sacrificial layer so that a portion of the inner electrode material fills the trench; The portion of the inner electrode material located on the third surface and the sacrificial layer are removed sequentially, and the remaining inner electrode material constitutes the inner electrode.

12. The manufacturing method according to claim 11, characterized in that, The second conductive portion has a fourth surface on the side away from the channel region, and the steps of forming the dielectric layer and the outer electrode layer include: The dielectric layer covers the exposed surface of the inner electrode and the fourth surface; The outer electrode layer covers the surface of the dielectric layer.

13. The manufacturing method according to claim 11, characterized in that, The second conductive portion has a fourth surface on the side away from the channel region, and the steps of forming the dielectric layer and the outer electrode layer include: The exposed surface of the inner electrode and the fourth surface are covered with a dielectric material; The portion of the dielectric material located on the fourth surface is removed to expose the fourth surface, and the remaining dielectric material constitutes the dielectric layer. An outer electrode layer material is covered on the surface of the dielectric layer and the fourth surface; The portion of the outer electrode layer material located on the fourth surface is removed, and the remaining outer electrode layer material constitutes the outer electrode layer.

Images