Semiconductor structures, three-dimensional memory and methods of making the same, and memory systems

Abstract

The application discloses a semiconductor structure, a three-dimensional memory, a preparation method of the three-dimensional memory, and a memory system. According to an embodiment of the application, the preparation method of the three-dimensional memory can include: forming a stack structure including a first sacrificial layer, a second sacrificial layer, and a dielectric layer on a substrate; forming a channel hole penetrating through the stack structure; oxidizing the first sacrificial layer and the second sacrificial layer exposed through the channel hole by an oxidation treatment through the channel hole to form a barrier layer with a groove structure in the channel hole; and forming a charge trapping layer at the groove structure. According to the preparation method of the three-dimensional memory of the application, the groove structure can be formed at the same time when the barrier layer is formed, and the process step of etching on the surface of the barrier layer after the barrier layer is formed is omitted, thereby simplifying the process step of preparing the three-dimensional memory and improving the loss of the channel hole density caused by the groove structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to semiconductor structures, the structure of three-dimensional memory (3D NAND) and its fabrication methods, and memory systems. Background Technology

[0002] With the rise of artificial intelligence, big data, and the Internet of Things, as well as the development of mobile communications, mobile devices, and cloud storage, the demand for memory capacity has exploded. 3D memory, due to its high integration and low power consumption, has gradually become the mainstream semiconductor memory and has attracted widespread attention.

[0003] To improve the storage performance of storage devices, existing 3D memory fabrication processes typically employ a vertically stacked multilayer storage cell structure. Specifically, a multilayer structure is formed on a substrate, with channel holes formed within the stack. Functional layers or other related layer structures are then deposited on the inner walls of the channel holes. The functional layer, as a key structure for the 3D memory to perform its storage function, achieves this function by trapping electrical charges.

[0004] In three-dimensional memory, charge-capture flash memory (CTF) offers advantages over traditional floating-gate (FG) memory, including lower technical difficulty and superior storage performance, making it a crucial technology for future development. However, as the ONO structure stacking layers in CTF fabrication become thinner, charge retention and coupling issues become increasingly severe. While isolated capture-time memory (ITS) can partially address these problems, current ITS still suffer from other drawbacks. For instance, the fabrication process for forming grooves within ITS channel vias is difficult to control, and the presence of these grooves leads to a loss of channel density.

[0005] Therefore, how to improve charge retention and coupling without affecting the performance of 3D memory and ensuring its fabrication process is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a semiconductor structure, a three-dimensional memory, a method for fabricating the same, and a memory system that can at least partially solve the aforementioned problems existing in the related technologies.

[0007] On one hand, this application provides a method for fabricating a three-dimensional memory, comprising: forming a stacked structure including a first sacrificial layer, a second sacrificial layer and a dielectric layer on a substrate; forming a channel hole through the stacked structure; oxidizing the first sacrificial layer and the second sacrificial layer exposed through the channel hole to form a barrier layer with a groove structure in the channel hole; and forming a charge trapping layer at the groove structure.

[0008] In some exemplary embodiments, the stacked structure may include an alternately stacked first initial stack pair and a second initial stack pair, wherein the first initial stack pair includes the dielectric layer and the first sacrificial layer, and the second initial stack pair includes the dielectric layer and the second sacrificial layer.

[0009] In some exemplary embodiments, the fabrication method may further include: forming a gate line gap through the stacked structure; and removing the second sacrificial layer through the gate line gap to form a gate gap.

[0010] In some exemplary embodiments, in a stacking direction perpendicular to the stacked structure, the thickness of the barrier layer at the second sacrificial layer may be greater than the thickness of the barrier layer at the first sacrificial layer.

[0011] In some exemplary embodiments, forming the charge trapping layer at the groove structure may include: depositing an initial charge trapping layer on the side of the barrier layer having the groove structure; and removing the portion of the initial charge trapping layer outside the groove structure.

[0012] In some exemplary embodiments, removing the portion of the initial charge trapping layer located outside the groove structure may include removing the portion of the initial charge trapping layer located outside the groove structure by wet etching.

[0013] In some exemplary embodiments, the preparation method may further include: sequentially forming a tunneling layer, a channel layer, and a channel dielectric structure within the channel hole.

[0014] In some exemplary embodiments, the fabrication method may further include: forming a gate line gap through the stacked structure; removing the first sacrificial layer through the gate line gap to form a void; and forming a gate conductive layer within the void.

[0015] In some exemplary embodiments, forming a gate conductive layer within the gap may include: forming a high dielectric constant layer and an adhesive layer within the gap; and forming the gate conductive layer on the adhesive layer.

[0016] In some exemplary embodiments, the first sacrificial layer may include a nitride.

[0017] In some exemplary embodiments, at least one of the dielectric layer, the barrier layer, the tunneling layer, and the channel dielectric structure may include an oxide.

[0018] In some exemplary embodiments, the adhesive layer may include a nitride, and the gate conductive layer may include at least one of tungsten and aluminum.

[0019] In some exemplary embodiments, the preparation method may further include: filling the gate wire gaps with a dielectric material.

[0020] On the other hand, this application provides a semiconductor structure that may include a stacked structure and a channel structure. The stacked structure may include an alternately stacked first stacked pair and a second stacked pair. The first stacked pair may include a gate layer and a first dielectric layer, while the second stacked pair may include a gate gap and a second dielectric layer. The channel structure extends through the stacked structure and may include a barrier layer adjacent to the stacked structure and a charge trapping layer discontinuously disposed along the barrier layer.

[0021] In some exemplary embodiments, the thickness of the barrier layer at the gate gap may be greater than the thickness of the barrier layer at the gate layer in the stacking direction perpendicular to the stacked structure.

[0022] In some exemplary embodiments, the channel structure may further include a tunneling layer, a channel layer, and a channel dielectric structure.

[0023] In some exemplary embodiments, the gate layer may include: a gate conductive layer; an adhesive layer covering the gate conductive layer; and a high dielectric constant layer covering the adhesive layer.

[0024] In some exemplary embodiments, the semiconductor structure may further include a filling structure that runs through the stacked structure, wherein the material of the filling structure may include a dielectric material.

[0025] In another aspect, this application also provides a three-dimensional memory, which includes a semiconductor structure and a peripheral circuit semiconductor structure bonded to the semiconductor structure. The semiconductor structure may include a stacked structure and a channel structure. The stacked structure may include an alternately stacked first stacked pair and a second stacked pair, the first stacked pair including a gate layer and a first dielectric layer, and the second stacked pair including a gate gap and a second dielectric layer. The channel structure extends through the stacked structure, and the channel structure may include a barrier layer adjacent to the stacked structure and a charge trapping layer discontinuously disposed along the barrier layer.

[0026] In another aspect, this application also provides a memory system comprising a three-dimensional memory as described above and a controller electrically connected to the three-dimensional memory and used to control the three-dimensional memory.

[0027] The semiconductor structure, three-dimensional memory, and method for fabricating the three-dimensional memory according to one or more embodiments of this application may have at least one of the following advantages:

[0028] 1) By utilizing the difference in oxidation rates between semiconductor materials and nitrides, a trench structure can be formed simultaneously with the formation of a barrier layer, thereby simplifying the process steps;

[0029] 2) When forming the groove structure, compared to traditional wet etching which enlarges the channel size, the oxidation method causes the first and second sacrificial layers to grow inward, thereby reducing the occupied area and increasing the channel density while maintaining the same channel size; and

[0030] 3) Remove semiconductor material to form an air gap between adjacent gate layers, thereby reducing capacitance and delay of electrical signals in the circuit. Attached Figure Description

[0031] The above and other advantages of embodiments of this application will become apparent from the following detailed description with reference to the accompanying drawings, which are intended to illustrate exemplary embodiments of this application and not to limit them. In the drawings:

[0032] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown schematically;

[0033] Figures 2 to 11 This is a schematic diagram of the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0034] Figure 12 This is a schematic cross-sectional view of a semiconductor structure according to an exemplary embodiment of this application;

[0035] Figure 13 This is a block diagram of an exemplary system having a memory device according to an exemplary embodiment of this application;

[0036] Figure 14A This is a schematic diagram of an exemplary memory card having a memory device according to an exemplary embodiment of this application; and

[0037] Figure 14B This is a schematic diagram of an exemplary solid-state drive (SSD) having a memory device according to an exemplary embodiment of this application. Detailed Implementation

[0038] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Furthermore, for clarity and conciseness, descriptions of features well-known in the art may be omitted.

[0039] Throughout the accompanying drawings and detailed embodiments, the same reference numerals refer to the same elements. For purposes of clarity, illustration, and convenience, the drawings may not be drawn to scale, and the relative dimensions, scale, and depiction of elements in the drawings may be exaggerated.

[0040] It should be noted that in this specification, the terms "first," "second," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this application, the first dielectric layer discussed below may be referred to as the second dielectric layer, and similarly, the second dielectric layer may also be referred to as the first dielectric layer.

[0041] It should be understood that, in this application, when an element or layer is described as being “on,” “connected to,” or “attached to” another element or layer, it may be directly on, directly connected to, or attached to the other element or layer, or there may be an intermediate element or layer. When an element is described as being “directly located” on, directly connected to, or directly attached to another element or layer, there is no intermediate element or layer. Throughout the specification, the same reference numerals refer to the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0042] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized sense, unless expressly so defined herein.

[0044] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure, or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface.

[0045] The various aspects of this application will now be described in more detail with reference to the accompanying drawings.

[0046] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown. Figure 1 As shown, the fabrication method 1000 of a three-dimensional memory according to some embodiments of this application begins in step S1100, where a stacked structure including a first sacrificial layer, a second sacrificial layer, and a dielectric layer is formed on a substrate. Next, in step S1200, a channel hole is formed penetrating the stacked structure. In step S1300, the first and second sacrificial layers exposed through the channel hole are oxidized to form a barrier layer with a groove structure within the channel hole, and in step S1400, a charge trapping layer is formed at the groove structure.

[0047] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 1 The execution is performed in the order shown.

[0048] Figures 2 to 6 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 2 to 6 The above steps S1100 to S1400 are further described.

[0049] S1100, a stacked structure including a first sacrificial layer, a second sacrificial layer and a dielectric layer is formed on the substrate.

[0050] In step S1100, a stacked structure 200 including a first sacrificial layer 210, a second sacrificial layer 220, and a dielectric layer 230 can be formed on the substrate 100, such as... Figure 2As shown. The substrate 100 may be made of materials such as silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof. The stacked structure 200 may include a plurality of first sacrificial layers 210, a plurality of second sacrificial layers 220, and a plurality of dielectric layers 230 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 100 (Z direction). Exemplarily, the stacked structure 200 may be formed on the substrate 100 by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that the number of layers in the stacked structure 200 is not limited to the number shown in the figure, but the number of stacked layers and the stacking height of the stacked structure 200 may be designed according to actual needs, and this application does not specifically limit this.

[0051] The stacked structure 200 may include alternating first initial stack pair 200a and second initial stack pair 200b. The first initial stack pair 200a may include a dielectric layer 230 and a first sacrificial layer 210, while the second initial stack pair 200b may include a dielectric layer 230 and a second sacrificial layer. The first initial stack pair 200a and the second initial stack pair 200b are stacked alternately such that a dielectric layer 230 is disposed between each adjacent first sacrificial layer 210 and second sacrificial layer 220. Furthermore, both the topmost and bottommost layers of the stacked structure 200 may be dielectric layers 230.

[0052] In an exemplary embodiment, the thickness of the first sacrificial layer 210 may be greater than or equal to the thickness of the dielectric layer 230, the thickness of the second sacrificial layer 220 may be greater than or equal to the thickness of the dielectric layer 230, and the thickness of the first sacrificial layer 210 may be approximately the same as the thickness of the second sacrificial layer 220. In other embodiments, the thickness of each of the above layers may not be limited, and each layer may have an appropriate thickness according to actual circumstances without departing from the scope of the teachings disclosed in this application.

[0053] For example, the material of the first sacrificial layer 210 may include, for example, a nitride (such as silicon nitride), the material of the second sacrificial layer 220 may include, for example, a semiconductor material such as silicon (such as amorphous silicon, polycrystalline silicon, monocrystalline silicon), and the material of the dielectric layer 230 may include, for example, an oxide (such as silicon oxide).

[0054] In an exemplary embodiment, the stacked structure 200 according to this application may have a structure in which silicon oxide, silicon nitride, silicon oxide and polysilicon are deposited sequentially as stacked layers.

[0055] For example, as described above and below, substrate 100 may be used in steps S1100 to S1400 to provide mechanical support for structures such as stacked structures, barrier layers, channel structures, or fill structures formed thereon. It should be understood that substrate 100 may be removed in subsequent processes, which will be described in detail below.

[0056] S1200 forms a channel hole that penetrates the stacked structure.

[0057] In step S1200, a channel hole 300 is formed through the laminated structure 200. For example... Figure 3 As shown, the channel hole 300 penetrates the stacked structure 200 and extends to the substrate 100 in a direction toward the substrate 100 (e.g., perpendicular to the substrate 100). Exemplarily, the channel hole 300 may have a generally cylindrical, frustum-shaped, or prism-shaped profile. In some exemplary embodiments, the channel hole 300 may be formed by photolithography and etching processes (e.g., dry or wet etching processes). Figure 3 Only one channel hole 300 is shown as an example, but it should be understood that multiple channel holes 300 penetrating the stacked structure 200 can be formed in step S1200. Exemplarily, the multiple channel holes 300 can be arranged in a two-dimensional array on a plane parallel to the substrate 100.

[0058] S1300, through channel hole oxidation treatment of the first and second sacrificial layers exposed via the channel holes, to in the channel A barrier layer with a groove structure is formed inside the channel.

[0059] In step S1300, the first sacrificial layer 210 and the second sacrificial layer 220 exposed through the channel hole 300 are oxidized to form a barrier layer 400 with a groove structure 410 within the channel hole 300. Figure 4As shown, the barrier layer 400 formed within the channel hole 300 may have multiple groove structures 410, and the groove structures 410 are located at positions corresponding to the first sacrificial layer 210. Exemplarily, the first sacrificial layer 210 and the second sacrificial layer 220 exposed by the channel hole 300 can be treated by an in-situ oxidation process, and the barrier layer 400 is formed on the portions of the first and second sacrificial layers 210 and 220 exposed in the channel hole 300. Since the oxidation rate of the second sacrificial layer 220 is faster than that of the first sacrificial layer 210, the thickness T1 of the barrier layer 400 formed on the second sacrificial layer 220 can be greater than the thickness T2 of the barrier layer 400 formed on the first sacrificial layer 210, thus forming groove structures 410 on the sidewall of the channel hole 300. In other words, in the stacking direction perpendicular to the stacked structure 200 (e.g., any direction in the plane defined by XY), the thickness T1 of the barrier layer 400 at the second sacrificial layer 220 is greater than the thickness T2 of the barrier layer 400 at the first sacrificial layer 210.

[0060] In an exemplary embodiment, the oxidation rate of the second sacrificial layer 220 can be adjusted by changing the doping (e.g., doping type, dopant ions, doping concentration, etc.). By adjusting the oxidation rate of the second sacrificial layer 220, the recess depth of the groove structure 410 from the channel hole 300 into the stacked structure 200 can be effectively controlled. In other words, by adjusting the oxidation rate of the second sacrificial layer 220, the difference between thickness T1 and thickness T2 can be effectively controlled. Exemplarily, the second sacrificial layer 220 may be doped with at least one of boron ions and phosphorus ions.

[0061] For example, the material of the barrier layer 400 may include oxides (such as silicon oxide).

[0062] According to the fabrication method of the three-dimensional memory according to the exemplary embodiment of this application, by utilizing the difference in oxidation rates between the second sacrificial layer and the first sacrificial layer, a groove structure can be naturally formed while forming the barrier layer, thereby simplifying the fabrication process steps of the three-dimensional memory. Furthermore, when forming the groove structure, compared to the conventional wet etching method which enlarges the channel size, the oxidation method causes the first and second sacrificial layers to grow inwards, thereby reducing the occupied area and increasing the channel density while maintaining the same channel size.

[0063] S1400 forms a charge trapping layer at the groove structure.

[0064] In step S1400, a charge trapping layer 500 is formed at the groove structure 410 (see...). Figure 6 See also Figure 5An initial charge trapping layer 500a is deposited on one side of the barrier layer 400 having the groove structure 410. The initial charge trapping layer 500a may cover the entire surface of the barrier layer 400 exposed to the channel via 300 and may completely fill the groove structure 410. In an exemplary embodiment, the initial charge trapping layer 500a may be formed on the barrier layer 400 by, for example, CVD, PVD, ALD, or any combination thereof. Subsequently, the portion of the initial charge trapping layer 500a outside the groove structure 410 is removed to form a charge trapping layer 500 that is discontinuous in a direction perpendicular or substantially perpendicular to the substrate 100 (Z direction), such as... Figure 6 As shown. In an exemplary embodiment, the portion of the initial charge trapping layer 500a located outside the groove structure 410 can be removed by an etching process, thereby forming a discontinuous charge trapping layer 500. Specifically, a process such as wet etching can be used to remove the initial charge trapping layer 500a located outside the groove structure 410. The processed charge trapping layer 500 is entirely located within the groove structure 410 and is separated by the barrier layer 400. The charge trapping layer 500 processed by the wet etching process can be flush with the protruding surface of the barrier layer 400.

[0065] For example, the material of the charge trapping layer 500 may include nitrides (such as silicon nitride).

[0066] The method for fabricating a three-dimensional memory according to an exemplary embodiment of this application may further include, as follows: Figures 7 to 11 The process steps will be described below. Figures 7 to 11 Detailed description.

[0067] After forming a charge trapping layer 500 that is discontinuous in a direction perpendicular or substantially perpendicular to the substrate 100 (Z direction), a channel via 300 (see...) can be formed. Figure 3 A tunneling layer 610, a channel layer 620, and a channel dielectric structure 630 are sequentially formed within the channel hole 300, as shown in FIG7. In an exemplary embodiment, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form the tunneling layer 610 and the channel layer 620 within the channel hole 300 where the barrier layer 400 and the charge trapping layer 500 are formed. Optionally, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the channel hole 300 where the tunneling layer 610 and the channel layer 620 are formed with a dielectric material such as an oxide to form the channel dielectric structure 630. Specifically, a thin film deposition process can be used to fill the channel hole 300 where the tunneling layer 610 and the channel layer 620 are formed with silicon oxide until the space within the channel layer 620 is completely filled to form the channel dielectric structure 630.

[0068] Exemplarily, the material of the tunneling layer 610 may include, for example, an oxide (such as silicon oxide). The materials of the barrier layer 400, the charge trapping layer 500, and the tunneling layer 610 may respectively include, for example, silicon oxide, silicon nitride, and silicon oxide, thereby forming a silicon oxide-silicon nitride-silicon oxide structure (ONO structure). Specifically, the barrier layer 400, the charge trapping layer 500, and the tunneling layer 610 may form an ONO structure in a planar direction parallel to the substrate plane (e.g., any direction within the plane defined by XY). The material of the channel layer 620 may include semiconductor materials such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon).

[0069] As described above, multiple channel holes 300 can be formed through the stacked structure 200 (see above). Figure 3 Subsequently, a barrier layer 400, a charge trapping layer 500, a tunneling layer 610, a channel layer 620, and a channel dielectric structure 630 can be sequentially formed in each channel hole 300, such as... Figure 8 As shown.

[0070] In an exemplary embodiment, the method for fabricating a three-dimensional memory may further include forming gate slots 900 extending in a stacking direction (e.g., the Y direction) substantially perpendicular to the stacking structure 200 (see [link to documentation]). Figure 10 For example, the gate slot 900 may include a plurality of sub-gate slots extending along the Y direction, and the plurality of sub-gate slots may be spaced apart along the X direction. The gate slot 900 may expose the first sacrificial layer 210 and the second sacrificial layer 220 in the stack structure 200. As an example, the gate slot 900 may extend through the stack structure 200 to the surface of the substrate 100 or to the interior of the substrate 100.

[0071] In some examples, the same mask can be used to form the channel aperture 300 and the grid line slot 900. That is, the channel aperture 300 and the grid line slot 900 can be formed simultaneously in the same process.

[0072] In an exemplary embodiment, the method for fabricating a three-dimensional memory may further include removing the first sacrificial layer 210 through the gate gap 900 (see...). Figure 8 To form a void (not shown). Then, a gate conductive layer 710 is formed within the void, as shown. Figure 9As shown. As an example, a high-dielectric-constant layer 730, an adhesive layer 720, and a gate conductive layer 710 can be sequentially formed within the gap via the gate line slot 900, such that the gate conductive layer 710 can be covered by the adhesive layer 720, and the adhesive layer 720 can be covered by the high-dielectric-constant layer 730. Exemplarily, the first sacrificial layer 210 in the stacked structure 200 can be removed via wet etching through the gate line slot 900 to form the gap, after which the high-dielectric-constant layer 730, the adhesive layer 720, and the gate conductive layer 710 can be sequentially deposited within the gap using a thin-film deposition process such as CVD, PVD, ALD, or any combination thereof. In the exemplary embodiment, the sequentially deposited high-dielectric-constant layer 730, adhesive layer 720, and gate conductive layer 710 can completely fill the gap.

[0073] For example, the high dielectric constant layer 730 may be made of materials such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium silicate oxide. Using a high dielectric constant material, the high dielectric constant layer 730 can effectively reduce gate capacitance. The adhesive layer 720 may be made of materials such as titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The gate conductive layer 710 may be made of conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0074] The adhesive layer 720 according to an exemplary embodiment of this application can provide deposition sites during the deposition of the gate conductive layer 710, and can also be used to bond the gate conductive layer 710 to the high dielectric constant layer 730 and prevent the diffusion of conductive material of the gate conductive layer 710.

[0075] In an exemplary embodiment, the method for fabricating a three-dimensional memory may further include removing the second sacrificial layer 220 through the gate gap 900 (see [link]). Figure 8 To form a gate gap 800, such as Figure 10 As shown. Exemplarily, the second sacrificial layer 220 can be removed through the gate line gap 900 by dry etching to form the gate gap 800. The gate gap 800 according to the exemplary embodiment of this application can reduce the stress inside the stacked structure on the one hand, and reduce the gate capacitance on the other hand, thereby reducing the delay of electrical signals in the circuit.

[0076] In an exemplary embodiment, the method for fabricating a three-dimensional memory may further include filling the gate gaps 900 with a dielectric material (see [link to documentation]). Figure 10As shown in FIG11, a filling structure 910 is formed by removing the first sacrificial layer 210 to form a void. Similarly, in the step of removing the second sacrificial layer 220 to form a gate gap 800, the second sacrificial layer 220 can also be removed through the gate line gap 900 of the stacked structure 200 to form the gate gap 800. After forming the gate gap 800, a dielectric material can be used to fill the gate line gap 900 to form the filling structure 910. Optionally, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the gate line gap 900 with a dielectric material such as oxide to form the filling structure 910. Specifically, a thin film deposition process can be used to fill the gate line gap 900 with silicon oxide until the gate line gap 900 is completely filled to form the filling structure 910.

[0077] Subsequent processes in the fabrication of three-dimensional memory include steps such as forming peripheral circuitry within the three-dimensional memory. The embodiments and process flows described in this application only illustrate an intermediate step in forming a three-dimensional memory with gate gaps.

[0078] Figure 12 A schematic cross-sectional view of a semiconductor structure 10 according to an exemplary embodiment of this application is shown.

[0079] like Figure 12 As shown, the semiconductor structure 10 according to an exemplary embodiment of this application may include a stacked structure 200' and a plurality of channel structures 600.

[0080] In an exemplary embodiment, the stacked structure 200' may include an alternately stacked first stacked pair 200a' and a second stacked pair 200b'. The first stacked pair 200a' may include a gate layer 700 and a first dielectric layer 230a, while the second stacked pair 200b' may include a gate gap 800 and a second dielectric layer 230b. In the example, the first dielectric layer 230a and the second dielectric layer 230b may be the same, and both may be the same as the dielectric layer 230 described above. The first stacked pair 200a' and the second stacked pair 200b' are stacked alternately in sequence, such that a dielectric layer is disposed between each adjacent gate layer 700 and gate gap 800. In addition, the topmost and bottommost layers of the stacked structure 200' may both be dielectric layers. It should be understood that the number of layers in the stacked structure 200' is not limited to the number of layers shown in the figure, but can be designed according to actual needs to determine the number of stacked layers and the stacking height of the stacked structure 200'. This application does not impose specific limitations on this.

[0081] The semiconductor structure according to the exemplary embodiments of this application may have a gate gap between adjacent gate layers. This gate gap helps to reduce the stress inside the stacked structure and can also reduce the gate capacitance, thereby helping to reduce the delay of electrical signals in the circuit.

[0082] In the example, the gate layer 700 has a gate conductive layer 710. Additionally, in some exemplary embodiments, the gate layer 700 may further include an adhesive layer 720 and a high-dielectric-constant layer 730, wherein the adhesive layer 720 may cover the gate conductive layer 710, and the high-dielectric-constant layer 730 may cover the adhesive layer 720. In other words, in some exemplary embodiments, the gate layer 700 may be implemented as a gate stack including the gate conductive layer 710, the adhesive layer 720, and the high-dielectric-constant layer 730.

[0083] For example, the material of the high dielectric constant layer 730 may include, for example, high dielectric constant materials such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium silicate oxide. The material of the adhesive layer 720 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The material of the gate conductive layer 710 may include, for example, conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0084] like Figure 12 As shown, each channel structure 600 may include a barrier layer 400 and a charge trapping layer 500. The barrier layer 400 may be located on the outer periphery of the channel structure 600 and adjacent to the stacked structure 200'. In other words, the barrier layer 400 may be disposed on the outermost side of the channel structure 600 for blocking the charge trapping layer 500 and other layers inside the channel structure 600 (e.g., but not limited to...). Figure 12 The tunneling layer 610, channel layer 620, and channel dielectric structure 630 shown are separated from the stacked structure 200'. The material of the barrier layer 400 may include, for example, oxides (such as silicon oxide). The barrier layer 400 may have different thicknesses along a stacking direction perpendicular to or substantially perpendicular to the stacking direction of the stacked structure 200'. Specifically, the thickness T1 of the barrier layer 400 located at the position corresponding to the gate gap 800 may be greater than the thickness T2 of the barrier layer 400 located at the position corresponding to the gate layer 700. The thickness difference of the barrier layer 400 at different locations is naturally formed due to the formation of the barrier layer 400 using an oxidation process.

[0085] As an example, the charge trapping layer 500 may be discontinuously disposed along the barrier layer 400. In other words, the charge trapping layer 500 may be discontinuously arranged in a direction perpendicular or substantially perpendicular to the substrate 100. Exemplarily, the material of the charge trapping layer 500 may include, for example, nitrides (such as silicon nitride).

[0086] Each channel structure 600 may further include a tunneling layer 610, a channel layer 620, and a channel dielectric structure 630 sequentially disposed from the barrier layer 400 toward the interior of the channel structure 600. Exemplarily, the material of the tunneling layer 610 may include, for example, an oxide (such as silicon oxide). The material of the channel layer 620 may include, for example, a semiconductor material such as silicon (such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon). The material of the channel dielectric structure 630 may include, for example, an oxide (such as silicon oxide).

[0087] In an exemplary embodiment, the materials of the barrier layer 400, the charge trapping layer 500, and the tunneling layer 610 may include, for example, silicon oxide, silicon nitride, and silicon oxide, respectively, thereby forming an ONO structure. Specifically, the barrier layer 400, the charge trapping layer 500, and the tunneling layer 610 may form an ONO structure in a stacking direction (e.g., the X direction) that is substantially perpendicular to the stacking direction of the stacked structure 200'.

[0088] Additionally, the semiconductor structure 10 according to an exemplary embodiment of this application may further include a fill structure 910. The fill structure 910 may extend along a stacking direction (e.g., the Y direction) generally perpendicular to the stacking direction of the stacked structure 200. In an exemplary embodiment, the fill structure 910 may extend through the stacked structure 200'. Exemplarily, the material of the fill structure 910 may include a dielectric material, such as an oxide (e.g., silicon oxide).

[0089] In some embodiments, the dielectric layer 230, barrier layer 400, tunneling layer 610, channel dielectric structure 630, and filler structure 910 may be made of the same material. Specifically, the dielectric layer 230, barrier layer 400, tunneling layer 610, channel dielectric structure 630, and filler structure 910 may all be made of silicon oxide.

[0090] This application also provides a three-dimensional memory including the semiconductor structure 10 as described above. The three-dimensional memory may include the semiconductor structure 10 and a peripheral circuit semiconductor structure (not shown) bonded to the semiconductor structure 10. The peripheral circuit semiconductor structure may include peripheral devices, such as transistor devices. As an example, the peripheral circuit semiconductor structure may be bonded to the semiconductor structure 10 on the side of the stacked structure 200' away from the substrate 100. After the semiconductor structure 10 is bonded to the peripheral circuit semiconductor structure, the substrate 100 may be removed using, for example, chemical mechanical planarization and etching processes. For example, most of the substrate 100 may be removed by rough grinding, followed by fine chemical mechanical grinding to remove a portion of the substrate 100.

[0091] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0092] Although exemplary fabrication methods and structures of three-dimensional memory are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. Furthermore, the materials of the layers described are merely exemplary.

[0093] Figure 13 A block diagram of an exemplary system 1300 with a memory device according to an exemplary embodiment of this application is shown. System 1300 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 13 As shown, system 1300 may include a host 1308 and a memory system 1302, the memory system 1302 having one or more memory devices 1304 and a memory controller 1206. The host 1308 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1308 may be configured to send data to or receive data from the memory device 1304.

[0094] The memory device 1304 can be any memory device disclosed in this application, such as the three-dimensional memory including the semiconductor structure 10 described above.

[0095] According to some embodiments, memory controller 1306 is coupled to memory device 1304 and host 1308 and is configured to control memory device 1304. Memory controller 1306 can manage data stored in memory device 1304 and communicate with host 1308. In some embodiments, memory controller 1306 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 1306 is designed to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Memory controller 1306 can be configured to control the operation of memory device 1304, such as read, erase, and program operations.

[0096] The memory controller 1306 can also be configured to manage various functions relating to data stored or to be stored in the memory device 1304, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1306 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 1304. The memory controller 1306 can also perform any other suitable functions, such as formatting the memory device 1304. The memory controller 1306 can communicate with external devices (e.g., host 1308) according to specific communication protocols. For example, the memory controller 1306 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial ATA, parallel ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, etc.

[0097] The memory controller 1306 and one or more memory devices 1304 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1302 can be implemented and packaged into different types of end electronic products. Figure 14AIn one example shown, the memory controller 1306 and a single memory device 1304 can be integrated into the memory card 2302. The memory card 2302 may include a PC card (PCMCIA (Personal Computer Memory Card International Association), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2302 may also include a memory card connector 2304 configured to couple the memory card 2302 to a host computer (e.g., ...). Figure 13 (Host 1308 in the middle). In such Figure 14B In another example shown, the memory controller 1306 and multiple memory devices 1304 may be integrated into the SSD 2306. The SSD 2306 may also include an SSD connector 2308 configured to couple the SSD 2306 to a host computer (e.g., ...). Figure 13 (The host 1308 in the memory card). In some implementations, the storage capacity and / or operating speed of the SSD 2306 is greater than that of the memory card 2302.

[0098] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, including: A stacked structure comprising a first sacrificial layer, a second sacrificial layer, and a dielectric layer is formed on a substrate; Forming channel holes that penetrate the stacked structure; The first and second sacrificial layers exposed through the channel holes are oxidized to form a barrier layer with a groove structure located at a position corresponding to the first sacrificial layer but not at a position corresponding to the second sacrificial layer. as well as A charge trapping layer is formed at the groove structure.

2. The preparation method according to claim 1, wherein, The stacked structure includes an alternately stacked first initial stack pair and a second initial stack pair, wherein the first initial stack pair includes the dielectric layer and the first sacrificial layer, and the second initial stack pair includes the dielectric layer and the second sacrificial layer.

3. The preparation method according to claim 2, wherein, The preparation method further includes: Forming grid line gaps that penetrate the stacked structure; and The second sacrificial layer is removed through the gate line gap to form a gate gap.

4. The preparation method according to claim 1, wherein, In the stacking direction perpendicular to the stacked structure, the thickness of the barrier layer at the second sacrificial layer is greater than the thickness of the barrier layer at the first sacrificial layer.

5. The preparation method according to claim 1, wherein, Forming the charge trapping layer at the groove structure includes: An initial charge trapping layer is deposited on the side of the barrier layer away from the described stacked structure; and Remove the portion of the initial charge trapping layer located outside the groove structure.

6. The preparation method according to claim 5, wherein, Removing the portion of the initial charge trapping layer located outside the groove structure includes: The portion of the initial charge trapping layer located outside the groove structure is removed by wet etching.

7. The preparation method according to claim 1, wherein, The preparation method further includes: A tunneling layer, a channel layer, and a channel dielectric structure are sequentially formed within the channel hole.

8. The preparation method according to claim 1, wherein, The preparation method further includes: Forming grid line gaps that penetrate the stacked structure; The first sacrificial layer is removed through the grid line gaps to form voids; and A gate conductive layer is formed within the gap.

9. The preparation method according to claim 8, wherein, Forming a gate conductive layer within the gap includes: A high dielectric constant layer and an adhesive layer are formed within the void; and The gate conductive layer is formed on the adhesive layer.

10. The preparation method according to claim 1, wherein, The first sacrificial layer comprises nitride.

11. The preparation method according to claim 7, wherein, At least one of the dielectric layer, the barrier layer, the tunneling layer, and the channel dielectric structure comprises an oxide.

12. The preparation method according to claim 9, wherein, The adhesive layer comprises nitride, and The gate conductive layer includes at least one of tungsten and aluminum.

13. The preparation method according to claim 3 or 8, wherein, The preparation method further includes: The gaps in the grid lines are filled with a dielectric material.

14. Semiconductor structures, including: A stacked structure includes an alternately stacked first stacked pair and a second stacked pair, wherein the first stacked pair includes a gate layer and a first dielectric layer, and the second stacked pair includes a gate gap and a second dielectric layer; as well as A channel structure extends through the stacked structure, the channel structure including intermittently disposed charge trapping layers located at positions corresponding to the gate layer but not at positions corresponding to the gate gap.

15. The semiconductor structure according to claim 14, wherein, The channel structure includes a barrier layer adjacent to the stacked structure; In the stacking direction perpendicular to the stacked structure, the thickness of the barrier layer at the gate gap is greater than the thickness of the barrier layer at the gate layer.

16. The semiconductor structure according to claim 14, wherein, The channel structure also includes a tunneling layer, a channel layer, and a channel dielectric structure.

17. The semiconductor structure according to claim 14, wherein, The gate layer includes: Gate conductive layer; An adhesive layer covering the gate conductive layer; and A high dielectric constant layer covers the adhesive layer.

18. The semiconductor structure according to claim 14, wherein, The semiconductor structure also includes: A filling structure extending through the stacked structure, wherein the material of the filling structure includes a dielectric material.

19. A three-dimensional memory, comprising a semiconductor structure and peripheral circuitry connected to said semiconductor structure, wherein, The semiconductor structure includes: A stacked structure, comprising an alternately stacked first stacked pair and a second stacked pair, wherein the first stacked pair includes a gate layer and a first dielectric layer, and the second stacked pair includes a gate gap and a second dielectric layer; and A channel structure extending through the stacked structure, and the channel structure comprising: A barrier layer, adjacent to the stacked structure; and A charge trapping layer is intermittently disposed along the barrier layer, the charge trapping layer being located at a position corresponding to the gate layer but not at a position corresponding to the gate gap.

20. A memory system, comprising: The three-dimensional memory as described in claim 19; as well as A controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

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