Semiconductor structures, methods of fabrication, devices, systems, and storage devices

Abstract

A semiconductor structure, a fabrication method, a device, a system, and a storage device are provided. A method of fabricating a semiconductor structure includes forming a stack structure of dielectric layers and gate sacrificial layers stacked in sequence, wherein the stack structure includes a memory array region and a peripheral region; forming gate line slits, peripheral contact holes, and / or sealing trenches through the stack structure in a direction of the stack, wherein the gate line slits are formed in the memory array region, and the peripheral contact holes and the sealing trenches are formed in the peripheral region; and forming a plurality of self-aligned contact holes in the memory array region, the plurality of self-aligned contact holes respectively extending to gate sacrificial layers of different numbers of stacked layers within the stack structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor structure (3D NAND), a method for fabricating the semiconductor structure, a semiconductor device, a semiconductor system, and a storage device. Background Technology

[0002] As the number of stacked layers in 3D NAND memory continues to increase, the etching depth required for contact holes (CTs) extending to different word lines (WLs) becomes increasingly greater, placing higher demands on the CT etching process and the etching stop layer process. To reduce process complexity and simplify process steps, the SCT (self-align contact) architecture has been proposed in related technologies. The SCT process uses a stair step (SS) cutting process to precisely stop the contact holes on each WL layer, thereby merging the SS and CT processes.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, characterized in that the method includes: forming a stacked structure of a dielectric layer and a gate sacrificial layer stacked sequentially, wherein the stacked structure includes a memory array region and a peripheral region; forming a gate line slot, a peripheral contact hole, and / or a sealing trench that penetrate the stacked structure along the stacking direction, wherein the gate line slot is formed in the memory array region, and the peripheral contact hole and the sealing trench are formed in the peripheral region; and forming a plurality of self-aligned contact holes located in the memory array region, wherein the plurality of self-aligned contact holes extend within the stacked structure to gate sacrificial layers with different stacking layers.

[0005] In one embodiment, the grid line gaps, the peripheral contact holes, and / or the sealing grooves are formed in the same process.

[0006] In one embodiment, the method further includes: removing a portion of the gate sacrificial layer via the gate line gap to form a void, and forming a gate layer within the void; removing at least a portion of the remaining portion of the gate sacrificial layer via the self-aligned contact hole to form a gap exposing the gate layer; and forming a conductive layer connected to the gate layer within the gap and the self-aligned contact hole.

[0007] In one embodiment, the memory array region includes a core region and a non-core region, at least a portion of the gate line slots extend from the core region to the non-core region, the portion of the gate line slots located in the core region is a first gate line slot, the portion located in the non-core region is a second gate line slot, and the step of removing a portion of the gate sacrificial layer to form the void includes: forming sacrificial filler in the gate line slots, the peripheral contact holes, and the sealing trenches; removing the sacrificial filler located in the first gate line slots; and removing the portion of the gate sacrificial layer located in the core region via the first gate line slots to form the first void.

[0008] In one embodiment, the step of removing a portion of the gate sacrificial layer to form the void further includes: removing the sacrificial filler located within the second gate line gap; and removing a portion of the gate sacrificial layer located in the non-core region via the second gate line gap to form a second void adjacent to the first void.

[0009] In one embodiment, the step of forming the gate layer within the gap includes: forming the gate layer within the first gap and the second gap, wherein, after forming the conductive layer, the conductive layer is connected to the portion of the gate layer located within the second gap.

[0010] In one embodiment, the step of removing the sacrificial filler located within the first grid line gap includes: providing a mask layer on the portion of the sacrificial filler located within the second grid line gap, the portion located within the peripheral contact hole, and the portion located within the sealing groove; and removing the portion of the sacrificial filler not covered by the mask layer.

[0011] In one embodiment, the step of forming the self-aligned contact hole includes: removing a portion of the stacked structure located in the non-core region to form a self-aligned contact hole exposing the remaining portion of the gate sacrificial layer; and the step of forming a gap exposing the gate layer includes: removing the exposed portion of the gate sacrificial layer via the self-aligned contact hole, and removing the portion of the gate sacrificial layer located between the exposed portion and the gate layer to form the gap.

[0012] In one embodiment, after forming the self-aligned contact hole, the method further includes removing the sacrificial filler located within the peripheral contact hole and the sealing groove.

[0013] In one embodiment, prior to forming the gap, the method further includes forming an isolation layer on the sidewalls of the self-aligning contact hole, the peripheral contact hole, and the sealing trench.

[0014] In one embodiment, the method further includes forming a peripheral contact portion and a sealing ring in the peripheral contact hole and the sealing groove, respectively, wherein the conductive layer, the peripheral contact portion, and the sealing ring are formed in the same process.

[0015] In one embodiment, after forming the self-aligned contact hole, the method further includes: removing a first portion of the gate sacrificial layer via the gate line gap; removing a second portion of the gate sacrificial layer via the self-aligned contact hole; and filling the interconnected space formed after removing the first and second portions of the gate sacrificial layer and the self-aligned contact hole with a conductive material.

[0016] This application provides another aspect of a semiconductor structure, characterized in that the semiconductor structure comprises: a stacked structure including a memory array region and a peripheral region, wherein the portion of the stacked structure located in the memory array region includes alternately stacked dielectric layers and gate layers; a peripheral contact portion and a sealing ring located in the peripheral region and passing through the stacked structure along the stacking direction of the stacked structure, the sealing ring surrounding the peripheral contact portion and the memory array region; and a plurality of self-aligned contact structures passing through a first surface of the stacked structure located in the memory array region and extending to gate layers with different numbers of stacked layers, wherein each of the self-aligned contact structures includes a conductive layer and a fill layer, the conductive layer being connected to a corresponding gate layer and surrounding the fill layer, and at least a portion of the conductive layer being exposed on the first surface.

[0017] In one embodiment, the semiconductor structure further includes a channel structure extending through a portion of the stacked structure located in the memory array region, wherein the critical dimension of the channel structure is smaller than the critical dimension of the self-aligned contact structure.

[0018] In one embodiment, the memory array region includes a core region and a non-core region. The portion of the stacked structure located in the core region includes alternately stacked dielectric and gate layers, and the portion of the stacked structure located in the non-core region includes the gate layer, the dielectric layer, and a reserved sacrificial layer. The gate layer and the reserved sacrificial layer are located on the same stacked layer, and the dielectric layer is alternately stacked with the gate layer and the reserved sacrificial layer.

[0019] In one embodiment, the self-aligned contact structure is located in the non-core region, and the conductive layer is connected to the portion of the gate layer located in the non-core region.

[0020] In one embodiment, the conductive layer includes a first conductive layer and a second conductive layer connected to the first conductive layer, the first conductive layer being connected to the gate layer, the second conductive layer being at least partially exposed on the first surface, and the semiconductor structure further includes an isolation layer located between the second conductive layer and the stacked structure, and surrounding the second conductive layer.

[0021] In one embodiment, the projection of the second conductive layer lies within the projection of the first conductive layer on a plane perpendicular to the stacking direction of the dielectric layer and the gate layer.

[0022] In another aspect, this application provides a semiconductor device, including: a semiconductor structure as described in any of the above embodiments; and a logic process compatible device.

[0023] In another aspect, this application provides a semiconductor system comprising: a semiconductor device as described in the above embodiments; and a controller electrically connected to the semiconductor device and configured to control the semiconductor device to perform at least one of a read operation, a program operation, and an erase operation.

[0024] In another aspect, this application provides a storage device, comprising: a semiconductor system as described in the above embodiments; and a housing for housing the semiconductor system.

[0025] The method for fabricating the semiconductor structure provided in this application can have at least one of the following beneficial effects:

[0026] According to some embodiments of this application, the increase in SR defects and the failure of SR caused by the joint preparation of SCT, SR and PC can be avoided.

[0027] According to some embodiments of this application, fabricating SR, PC and gate line slit (GLS) together can save wafer area and reduce the number of etching steps in the SCT process. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0029] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of this application;

[0030] Figure 2 This is a process diagram illustrating the formation of a stacked structure from a semiconductor structure according to an exemplary embodiment of this application;

[0031] Figure 3This is a process diagram illustrating the formation of a channel structure in a semiconductor structure according to an exemplary embodiment of this application;

[0032] Figure 4a A process diagram illustrating the formation of gate gaps, sealing trenches, and peripheral contact holes in a semiconductor structure according to an exemplary embodiment of this application ( Figure 4b yes Figure 4a (Cross-section view along the AA direction)

[0033] Figures 5 to 8 This is a schematic diagram of the process for forming a gate layer in a semiconductor structure according to an exemplary embodiment of this application;

[0034] Figures 9a to 11 This is a process diagram illustrating the formation of a conductive layer in a semiconductor structure according to an exemplary embodiment of this application. Figure 9b yes Figure 9a (Cross-sectional view along the DD direction)

[0035] Figure 12 This is a process diagram illustrating the formation of a filling layer in a semiconductor structure according to an exemplary embodiment of the fundamental application;

[0036] Figure 13a This is a schematic diagram of a partial structure of a semiconductor structure according to an exemplary embodiment of the fundamental application. Figure 13b yes Figure 13a (Cross-section view along the EE direction)

[0037] Figure 14 This is a schematic diagram of a partial structure of a semiconductor structure according to an exemplary embodiment of the fundamental application; and

[0038] Figure 15 This is a schematic diagram of a storage device according to an exemplary embodiment of the fundamental application. Detailed Implementation

[0039] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first conductive layer discussed herein may also be referred to as the second conductive layer, and vice versa.

[0041] In this specification, references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., indicate that the described embodiment may include a specific feature, structure, or characteristic; however, each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0042] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the laminated structure depicted in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0043] It should be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0044] It should also be understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top” means not only “above” or “on top” something but also includes “above” or “on top” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0045] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] The features, principles and other aspects of this application are described in detail below.

[0048] The inventors of this application have discovered that in some SCT fabrication processes, to ensure the SCT accurately stops on each WL layer, it is typically necessary to enlarge the critical size of the contact holes. The critical size of the contact holes in the SCT architecture can be up to six times that of ordinary contact holes. To reduce manufacturing steps, the SCT fabrication process often fabricates the sealing ring (SR) and the peripheral contact (PC) together. The combined fabrication of SCT, SR, and PC presents several problems: First, the presence of the SCT requires the SR and PC to occupy more wafer area; second, SCT, SR, and PC are generally made of conductive materials (e.g., tungsten metal). When wet etching is used to process the tungsten metal on the sides of the SCT structure, the wet etching material (e.g., phosphoric acid) can come into contact with the tungsten metal in the SR and extend into cracks or defects in the SR, potentially causing SR failure; third, since the SCT is formed through multiple etching processes, the presence of SR and PC increases the manufacturing complexity of the SCT.

[0049] This application proposes a semiconductor structure and its manufacturing method, which can at least partially improve or solve the above-mentioned problems. It avoids the increase in SR defects and SR failure caused by the joint fabrication of SCT, SR, and PC. Using a joint fabrication process of SR, PC, and gate line slits (GLS) can save wafer area and reduce the number of etching steps in the SCT process.

[0050] Figure 1 This is a flowchart of a semiconductor structure fabrication method 1000 according to an embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a semiconductor structure, comprising:

[0051] Step S1100: A stacked structure is formed by sequentially stacking a dielectric layer and a gate sacrificial layer, wherein the stacked structure includes a memory array region and a peripheral region;

[0052] Step S1200: Forming gate wire slots, peripheral contact holes, and / or sealing trenches that penetrate the stacked structure along the stacking direction, wherein the gate wire slots are formed in the memory array region, and the peripheral contact holes and sealing trenches are formed in the peripheral region; and

[0053] In step S1300, multiple self-aligned contact holes are formed in the memory array region, and the multiple self-aligned contact holes extend to gate sacrificial layers with different stacking layers within the stacked structure.

[0054] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 1 The execution is performed in the order shown.

[0055] Figures 2 to 11 This is a schematic diagram of the process for fabricating a semiconductor structure according to an embodiment of this application. It should be noted that the semiconductor structure described in this application context can be a three-dimensional memory, or a portion thereof. The following is in conjunction with... Figures 2 to 12 The above steps S1100 to S1300 are further described.

[0056] Step S1100: A stacked structure is formed by sequentially stacking a dielectric layer and a gate sacrificial layer, wherein the stacked structure includes... It includes the storage array area and the peripheral area.

[0057] like Figure 2 As shown, in step S1100, a stacked structure 120 may be formed on the substrate 110. The stacked structure 120 may be formed by sequentially stacking a dielectric layer 121 and a gate sacrificial layer 122. In some embodiments, the material of the substrate 110 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some examples, the substrate 110 may include a substrate 111 and a composite layer 112 located on the substrate, wherein the substrate 111 has a certain thickness and can serve as a structural support for the device structure (e.g., the stacked structure 120) formed thereon. Alternatively, the substrate 111 may be removed in some subsequent process steps.

[0058] In some embodiments, the stacked structure 120 may include a direction perpendicular to or substantially perpendicular to the substrate 110. z A plurality of dielectric layers 121 and a plurality of gate sacrificial layers 122 are alternately stacked in the direction of the dielectric layer 121. In some examples, the material for the gate sacrificial layer 122 includes, for example, silicon nitride, and the material for the dielectric layer 121 includes silicon oxide.

[0059] For example, a stacked structure 120 may be formed on substrate 110 by alternately forming a plurality of gate sacrificial layers 122 and dielectric layers 121 through thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0060] It should be understood that the number of layers in the stacked structure 120 is not limited to the number shown in the figure. Rather, the number of stacked layers and the stacking height of the stacked structure 120 can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0061] Figure 3 This is a schematic diagram illustrating the formation of a channel structure in a semiconductor structure according to an exemplary embodiment of this application. For example... Figure 3 As shown, multiple channel structures 130 can be formed in the stacked structure 120. Exemplarily, a method for forming the channel structure 130 may include first forming a channel aperture within the stacked structure 120, and then sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer within the channel aperture to form the channel structure 130. Exemplarily, the barrier layer, charge trapping layer, and tunneling layer may be deposited sequentially using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), and then the channel layer may be deposited on the side of the tunneling layer away from the channel aperture.

[0062] In some embodiments, the stacked structure 120 includes a memory array region 10 and a peripheral region 20. The peripheral region 20 is adjacent to the memory array region 10, and a channel structure 130 penetrates the portion of the stacked structure 120 located in the memory array region 10 and extends into the substrate 110. Exemplarily, a plurality of channel structures 130 may form an array penetrating different regions of the stacked structure 120, and the regions penetrated by the channel structures 130 form a plurality of memory array regions 10, which are surrounded and isolated by the peripheral region 20.

[0063] Step S1200: Forming grid wire gaps, peripheral contact holes, and / or seals that penetrate the stacked structure along the stacking direction. The trench includes a grid line slot formed in the storage array area, and peripheral contact holes and sealing trenches formed in the peripheral area.

[0064] Figure 4a This is a schematic diagram of a semiconductor structure forming a gate gap, peripheral contact hole, and sealing trench according to an exemplary embodiment of this application; Figure 4b yes Figure 4a Cross-sectional view along the AA direction. (Combined with...) Figure 4a and Figure 4b As shown, the grid line slot 140, the peripheral contact hole 150, and the sealing groove 160 can be formed in the same process. The grid line slot 140 is formed in the memory array region 10, and the peripheral contact hole 150 and the sealing groove 160 are formed in the peripheral region 20.

[0065] In other embodiments, the grid line slot 140 and the peripheral contact hole 150 may be formed in the same process; or the grid line slot 140 and the sealing groove 160 may be formed in the same process. It is understood that forming either the peripheral contact hole 150 or the sealing groove 160 together with the grid line slot 140 can improve some of the problems existing in the above-mentioned related technologies.

[0066] In some embodiments, the sealing groove 160 is along z The sealing groove 160 extends through the stacked structure 120 in the opposite direction and forms a ring-shaped closed structure. The sealing groove 160 surrounds the peripheral contact hole 150 and the portion of the stacked structure 120 located in the memory array region 10. The number and arrangement of the sealing groove 160 and the peripheral contact hole 150 are not limited to those shown in the figure. Those skilled in the art can design them as needed, and this application does not impose any specific limitations on them. Exemplarily, the steps of forming the gate line gap 140, the peripheral contact hole 150, and the sealing groove 160 include: on the stacked structure 120 ( z A mask (not shown) with a planar pattern of gate line slot 140, peripheral contact hole 150 and sealing trench 160 is provided in the direction of the stacked structure. Then, the stacked structure is repeatedly etched and trimmed through the mask to form the gate line slot 140, peripheral contact hole 150 and sealing trench 160 through the stacked structure 120 and extending to the substrate 110.

[0067] In some embodiments, the sealing trench 160 and the peripheral contact hole 150 penetrate the stacked structure 120 and extend into the semiconductor material (e.g., polysilicon) within the substrate 110. In other embodiments, the substrate 110 is composed of a base 111 and a composite layer 112 located on the base, with the sealing trench 160 and the peripheral contact hole 150 penetrating the stacked structure 120 and extending into the semiconductor material (e.g., polysilicon) within the composite layer 112.

[0068] In some implementations, the array memory region 10 may include a core region 11 and a non-core region 12. A stacked structure 120 located in the core region 11 extends through a channel structure 130, while a stacked structure 120 located in the non-core region 12 reserves empty areas 180 (i.e., areas not extending through the channel structure 130) required for subsequent SCT processes. The number of gate line slots 140 may be multiple, with some gate line slots 140 extending from the core region 11 to the non-core region 12, and others located only within the core region 11.

[0069] Step S1300: Forming multiple self-aligned contact holes located in the memory array area, the multiple self-aligned contact holes in the stack-up The structure extends to gate sacrificial layers with different stacking numbers.

[0070] Figures 5 to 8 This is a process diagram illustrating the formation of a gate layer in a semiconductor structure according to an exemplary embodiment of this application. (See diagram for example.) Figure 5As shown, sacrificial filler 170 can be deposited within the gate line gaps 140, peripheral contact holes 150, and sealing trenches 160. Exemplarily, the sacrificial filler 170 can be formed using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The material of the sacrificial filler 170 may include polycrystalline silicon or carbon materials.

[0071] like Figure 6a As shown, after the sacrificial filler 170 is formed, the portion of the sacrificial filler 170 located within the grid line slots 140 needs to be removed to expose the grid line slots 140. This re-exposure of the grid line slots 140 can be achieved by providing a mask layer 180. For example, a mask layer 180 can be applied to the stacked structure 120, having a planar pattern of the grid line slots 140. The sacrificial filler 170 within the peripheral contact holes 150 and sealing trenches 160 is covered by the mask layer 180, allowing the portion within the peripheral contact holes 150 and sealing trenches 160 to be retained during the etching of the sacrificial filler 170 via the planar pattern of the grid line slots 140.

[0072] In some embodiments, the removal of the sacrificial filler 170 from the grid gaps 140 is performed in steps. The sacrificial filler 170 in the grid gaps 140 located within the core region 11 may be removed first to form the first grid gap 141 (e.g., Figure 6b As shown, Figure 6a for Figure 6b (Cross-sectional view along the BB direction), then remove the sacrificial filler 170 from the grid line slots 140 located in the non-core region 12 to form the second grid line slot 142 (as shown in the diagram). Figure 7a (As shown). By exposing different portions of the gate line gap 140 in stages, the amount of gate sacrificial layer 122 removed in the core region 11 and the non-core region 12 can be controlled separately.

[0073] In other embodiments, the order of the fabrication processes for the first gate line slot 141 and the second gate line slot 142 can be interchanged. Only one process sequence is described in detail here. First, a planar pattern corresponding only to the portion of the gate line slot 140 within the core region 11 is formed in the mask layer 180, so that during the etching process of the sacrificial filler 170, only the portion of the sacrificial filler 170 located within the core region 11 can be removed, exposing the first gate line slot 141. Then, as... Figure 7b As shown, a mask layer 180' can be provided on the stacked structure 120. Figure 7b for Figure 7a (Cross-sectional view along the CC direction). The mask layer 180' has only a planar pattern corresponding to the portion of the gate line slot 140 in the non-core region 12. Through this pattern, an etching process is performed to remove the portion of the sacrificial filler 170 located in the non-core region 12, exposing the second gate line slot 142.

[0074] It should be noted that the step of forming the first gate line gap 141 further includes completely removing the gate sacrificial layer 122 located in the core region 11 to form the first gap 191; and the step of forming the second gate line gap 142 further includes removing a portion of the gate sacrificial layer 122 located in the non-core region 12 to form the second gap 192. The portion of the gate sacrificial layer 122 to be removed includes the portion extending from the second gate line gap 142 into the empty region 180 required for the SCT process. The first gap 191 and the second gap 192 together constitute the gap 190. It should also be noted that the channel structure 130 located in the non-core region 12 may only serve a mechanical support function.

[0075] In some embodiments, the gap 190 is further filled with a gate layer 200. The gate layer 200 may contact all the channel structures 130 located in the core region 11, and the channel structures 130 located in the second gate line gap 142 and the empty region 180 in the non-core region 12. Figure 8 Is Figure 7b This is a schematic diagram showing the formation of a gate layer 200 within the second gap 192. (See diagram below.) Figure 8 As shown, after forming the gate layer 200, the method further includes filling the gate line gap 140 with, for example, an insulating material to form a gate line gap structure 140'.

[0076] In some embodiments, a high-dielectric-constant layer (not shown) may be formed in the void 190 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), and then a gate layer 200 may be formed inside the high-dielectric-constant layer. The high-dielectric-constant layer covers the gate layer 200 and contacts the gate sacrificial layer 122 located in the same layer within the non-core region 12.

[0077] In other embodiments, a high-dielectric-constant layer, an adhesive layer (not shown), and a gate layer 200 may be sequentially formed in the void 190 formed by removing a portion of the gate sacrificial layer 122 using, for example, a thin-film deposition process. Exemplarily, the high-dielectric-constant layer may be formed of a high-dielectric-constant material, such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium silicate oxide. A high-dielectric-constant layer using a high-dielectric-constant material can effectively reduce gate capacitance. The adhesive layer material may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The gate layer 200 may be formed of a conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0078] The adhesive layer according to the exemplary embodiments of this application can provide deposition sites during the deposition of the gate layer 200, and can also be used to bond the gate layer 200 to the high dielectric constant layer, and can prevent the diffusion of the conductive material forming the gate layer 200.

[0079] Figures 9a to 11 This is a schematic diagram of a semiconductor structure forming a conductive layer according to an exemplary embodiment of this application; Figure 9b yes Figure 9a Cross-sectional view along the DD direction. (Combined with...) Figure 9a and Figure 9b As shown, after the gate layer 200 is formed, a portion of the gate sacrificial layer 122 located in the non-core region 12 is not removed. A portion of the gate sacrificial layer 122 and a portion of the dielectric layer 121 located in the empty region 180 can be retained to form a self-aligned contact hole 211. The self-aligned contact hole 211 exposes the upper surface of the gate sacrificial layer 122 at a predetermined depth. Exemplarily, a combination of photolithography and etching processes can be used to repeatedly etch the stacked structure in the empty region 180 to form the self-aligned contact hole 211. The self-aligned contact hole 211 can reach a predetermined depth by adjusting etching process parameters such as etching time and etching temperature, thereby exposing the gate sacrificial layer 122 located below the self-aligned contact hole 211.

[0080] In some embodiments, the method further includes removing the sacrificial filler 170 located within the peripheral contact hole 150 and the sealing groove 160. A mask with a corresponding pattern can be formed on the peripheral contact hole 150 and the sealing groove 160, and the sacrificial filler 170 located within the peripheral contact hole 150 and the sealing groove 160 can be removed using, for example, an etching process, thereby re-exposing the peripheral contact hole 150 and the sealing groove 160 (e.g., ...). Figure 10 (As shown).

[0081] In some embodiments, after re-exposing the peripheral contact hole 150 and the sealing groove 160, an isolation layer 220 is further formed on the sidewall of the self-aligning contact hole 211. The isolation layer 220 surrounds... z The axial direction completely covers the sidewalls of the self-aligned contact hole 211. Then, the exposed portion of the gate sacrificial layer 122 is removed via the remaining portion of the self-aligned contact hole 211 using a process such as wet etching. After the exposed portion of the gate sacrificial layer 122 is completely removed, the etching process continues to form a gap 212 that connects to the gate layer 200. Figure 10 The portion shown in the dashed box, once removed, becomes gap 212. After the isolation layer 220 is formed, the remaining space of the self-aligned contact hole 211 and gap 212 together constitute the space to be filled 210 (see reference). Figure 11 (The area indicated by the dashed box).

[0082] In some embodiments, the SCT process further includes forming a conductive layer 230 within the space 210 to be filled. The step of forming the conductive layer 230 includes depositing conductive material within the gap 212 and on the sidewalls of the insulating layer 220. Because the conductive material to be filled within the gap 212 is relatively thin, when the gap 212 is completely filled, the conductive material formed on the sidewalls of the insulating layer 220 will not completely fill the self-aligned contact hole 211, thereby forming… Figure 11 The conductive layer 230 is shown. In subsequent processes, insulating material can be filled into the unfilled areas of the space 210 to form a filling layer 240. Figure 12 (As shown). It is understood that the structure formed by the composite material of conductive layer 230 and filler layer 240 can alleviate stress changes in structures formed by single materials and reduce defects caused by stress changes. The material of conductive layer 220 includes, for example, tungsten, aluminum, silver, copper, tungsten alloy, aluminum alloy, silver alloy, copper alloy, or any combination thereof, and the material of filler layer 240 includes, for example, silicon oxide.

[0083] In other embodiments, after forming the gate line gap 140 and the self-aligned contact hole 211, a first portion of the gate sacrificial layer 122, including the portion of the gate sacrificial layer 122 located within the core region 11, may be removed via the gate line gap 140; and a second portion of the gate sacrificial layer 122, including the portion of the gate sacrificial layer 122 located within the non-core region 12 near the self-aligned contact hole 211, may be removed via the self-aligned contact hole 211, with the first portion connected to the second portion; and a gate layer (composed of the gate layer 200 described above and the first conductive layer 231 described below) may be formed by filling the space formed by removing the first and second portions with conductive material. For example, the conductive material filled in the space formed by removing the first and second portions may include tungsten or the like.

[0084] In some embodiments, the conductive layer 230 is wound around z The direction completely surrounds the isolation layer 220, and the upper surface of the conductive layer ( z (Direction) Exposed. One end of the conductive layer 230 is connected to the gate layer 200, through which a channel structure 130 extends. The exposed upper surface of the conductive layer 230 can be connected to an external interconnect structure, thereby allowing external circuitry to regulate the voltage state of the gate layer 200 via the conductive layer 230. In some embodiments, the critical dimension of the conductive layer 230 is larger than the critical dimension of the channel structure 130.

[0085] In some embodiments, the conductive layer 230, the peripheral contact 150', and the sealing ring 160' are formed in the same process (e.g., a deposition process). It is understood that by using a single process, the materials used to form the conductive layer 230, the peripheral contact 150', and the sealing ring 160' can be the same. Specifically, in the step of forming the conductive layer 230, conductive material can also be filled into the re-exposed peripheral contact hole 150 and sealing trench 160 to form the peripheral contact 150' and sealing ring 160', respectively. The presence of the sealing ring 160' prevents damage to the internal circuitry of the semiconductor structure caused by electrostatic discharge. Furthermore, when the semiconductor structure is diced, a well-functioning sealing ring 160' protects the semiconductor structure from cutting stress and moisture intrusion. Exemplarily, one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof) can be used to form the conductive layer 230, the peripheral contact 150', and the sealing ring 160'.

[0086] Another aspect of this application provides a semiconductor structure. This semiconductor structure can be fabricated using the methods described in any of the above embodiments. It should be noted that the semiconductor structure described in this application can be a three-dimensional memory, or a portion thereof.

[0087] Figure 13a This is a schematic diagram of a partial structure of a semiconductor structure according to an exemplary embodiment of this application; Figure 13b yes Figure 13a Cross-sectional view along the EE direction. (Combined with...) Figure 13a and Figure 13bAs shown, the semiconductor structure includes a stacked structure 120', a peripheral contact 150', a sealing ring 160', and a self-aligned contact structure 280. The stacked structure 120' may include a memory array region 10 and a peripheral region 20, with the peripheral region 20 surrounding the memory array region 10. The portion of the stacked structure 120' located within the memory array region 10 is composed of alternately stacked dielectric layers 121 and gate layers 200. The peripheral contact 150' penetrates the portion of the stacked structure 120' located in the peripheral region 20, and the sealing ring 160' penetrates the portion of the stacked structure 120' located in the peripheral region 10, surrounding both the peripheral contact 150' and the portion of the stacked structure 120' located in the memory array region 10. The self-aligned contact structure 280 penetrates the first surface A1 of the stacked structure 120' located in the memory array region 10 and extends to the gate layer 200. The memory array region 10 may have multiple self-aligned contact structures 280, each extending to a predetermined depth of the gate layer 200. In other words, each self-aligned contact structure 280 can be connected to the gate layer 200 located on different layers. The self-aligned contact structure 280 can be composed of a fill layer 240 and a conductive layer 230. The conductive layer 230 is connected to the gate layer 200 and surrounds all parts of the fill layer 240 except for the portion exposed to the first surface A1. The upper end of the conductive layer 230 is exposed to the first surface A1.

[0088] In some implementations, the storage array region 10 may include a core region 11 and a non-core region 12, which are connected and run along... y The stacked structure 120' is arranged in a specific direction. The portion of the stacked structure 120' located within the core region 11 consists of alternately stacked dielectric layers 121 and gate layers 200; the portion of the stacked structure 120' located within the non-core region 12 can be composed of alternately stacked dielectric layers 121 and gate layers 200, as well as alternately stacked dielectric layers 121 and gate sacrificial layers 122. A portion of the gate layers 200 on the same layer number is located within the non-core region 12, and another portion is located within the core region 11.

[0089] In some embodiments, the semiconductor structure further includes a channel structure 130. The channel structure 130 may extend through portions of the stacked structure 120' located in the core region 11 and the non-core region 12, respectively. The channel structure 130 located in the core region 11 is connected to the gate layer 200 and has a storage function, while the channel structure 130 located in the non-core region 12 may not be connected to peripheral circuits and only serve a mechanical support function. A self-aligned contact structure 280 is connected to the portion of the gate layer 200 located in the non-core region 12 and may be connected to peripheral circuits via, for example, a conductive metal, thereby enabling regulation of the voltage state on the gate layer 200. The critical dimension of the self-aligned contact structure 280 is larger than the critical dimension of the channel structure 130; for example, the critical dimension of the self-aligned contact structure 280 may be six times the critical dimension of the channel structure 130.

[0090] In some embodiments, the conductive layer 230 may include a first conductive layer 231 and a second conductive layer 232 connected to the first conductive layer 231. The first conductive layer 231 may be located between two dielectric layers 121 and connected to the gate layer 200 located on the same layer number. The second conductive layer 232 may be located above the first conductive layer 231, with its upper end exposed to the first surface A1. The semiconductor structure also includes an isolation layer 220, which is located between the stacked structure 120' and the second conductive layer 232, and surrounds... z The second conductive layer 232 is surrounded in the axial direction. The isolation layer 220 completely isolates the second conductive layer 232 from the stacked structure 120'.

[0091] In some embodiments, the semiconductor structure further includes a semiconductor layer 110'. The channel structure 130', the peripheral contact 150', and the sealing ring 160' can all penetrate the stacked structure 120' and extend into the semiconductor layer 110'. The projection of the second conductive layer 232 onto the semiconductor layer 110' lies within the projection of the first conductive layer 231; in other words, the first conductive layer 231... x The dimension in one direction is larger than the dimension of the second conductive layer 231 in the same direction. In some embodiments, the second conductive layer 232 is not a solid structure, but is filled with a filler layer 240. The second conductive layer 232 can be wound around... z The shaft surrounds the sidewalls of the filler layer 240, and the upper end of the filler layer 240 is exposed by the first surface A1.

[0092] In some embodiments, the semiconductor structure may include a plurality of spaced-apart memory array regions 10, with a peripheral region 20 adjacent to and surrounding each memory array region 10 (see reference). Figure 14(As shown). Both the peripheral contact portion 150' and the sealing ring 160' are located within the peripheral region 20. The sealing ring 160' can be a ring-shaped closed structure, surrounding the portion of the stacked structure 120' located within the array region 10 and the peripheral structure portion 150'. There can be multiple peripheral contact portions 150', arranged along a certain direction. There can also be multiple sealing rings 160', which can form... Figure 4a The ring-shaped closed structures shown are of different sizes, with the larger of the sealing rings 160' surrounding the smaller ones.

[0093] In some embodiments, the semiconductor structure further includes a gate line gap structure 140'. The gate line gap structure 140' can be along... y The direction extends from the core region 11 to the non-core region 10, or it can exist independently within the core region 11. The gate wire slot structure 140' extends along... z The gate line slot structure 140' extends through the stacked structure 120' in the opposite direction and extends to the semiconductor layer 110'. Multiple self-aligned contact structures 280 may exist between two adjacent gate line slot structures 140'. Multiple peripheral contact structures 150' may extend along the extension direction of the gate line slot structure 140' (e.g., ...). y Arranged in order of direction.

[0094] Another aspect of this application provides a semiconductor device 300 (reference 300). Figure 15 The semiconductor device 300 may include semiconductor structure and logic process compatible devices as described in any of the above embodiments. Logic process compatible devices may include, for example, random access memory (RAM) and processors.

[0095] In some embodiments, the semiconductor device 300 further includes a first bonding layer having a plurality of first bonding contacts, a second bonding layer having a plurality of second bonding contacts, and a bonding interface connecting the first and second bonding layers. The semiconductor structure is connected to the first bonding contacts, the logic process compatible device is connected to the second bonding contacts, and the semiconductor structure and the logic process compatible device can be interconnected via the bonding interface.

[0096] Another aspect of this application provides a semiconductor system, which includes the semiconductor structure 300 and controller 301 (see reference) in any embodiment of this application. Figure 15 (As shown). The semiconductor structure 300 includes multiple memory strings with storage functions, each memory string being composed of multiple memory cells. The controller 301 is electrically connected to the semiconductor structure 300 via peripheral circuitry and is configured to control the operation of the memory strings.

[0097] In some embodiments, the semiconductor structure 300 is electrically connected to and controlled by the controller 301. The controller 301 may, for example, control the application of different voltage signals to the memory cells (not shown) in the memory 300 to achieve the effect of controlling the memory 300 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0098] In some implementations, controller 301 may be configured to control operations of memory 300, such as read, program, and erase operations. Controller 301 may also be configured to manage various functions related to data stored in or to be stored in memory 300, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0099] In some embodiments, the semiconductor structure 300 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the semiconductor system also includes a connector 302, which can be connected to a device such as a host computer for transmitting data.

[0100] This application further provides a storage device 400 (see references to follow) Figure 15 It includes the semiconductor system described above and the housing 401 that carries the system.

[0101] In some implementations, storage device 400 may include solid-state drives (SSDs), memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, universal flash memory (UFS) cards, or any combination thereof.

[0102] In some implementations, the controller 301 and the memory 300 may be integrated onto the storage device 400 (e.g., an SSD). The storage capacity and / or operating speed of the SSD may be higher than that of the memory card.

[0103] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A stacked structure is formed by sequentially stacking a dielectric layer and a gate sacrificial layer, wherein the stacked structure includes a memory array region and a peripheral region; A gate wire slot, peripheral contact hole, and sealing trench are formed along the stacking direction through the stacked structure, wherein the gate wire slot is formed in the memory array region, the peripheral contact hole and the sealing trench are formed in the peripheral region, and the gate wire slot, peripheral contact hole and sealing trench are formed in the same process; and Multiple self-aligned contact holes are formed in the memory array region, and the multiple self-aligned contact holes extend to gate sacrificial layers with different stacking layers within the stacked structure.

2. The method according to claim 1, wherein, The method further includes: A portion of the gate sacrificial layer is removed through the gate line gap to form a void, and a gate layer is formed within the void; At least a portion of the remaining portion of the gate sacrificial layer is removed via the self-aligned contact hole, forming a gap exposing the gate layer; and A conductive layer connected to the gate layer is formed within the gap and the self-aligned contact hole.

3. The method according to claim 2, wherein, The storage array region includes a core region and a non-core region. At least a portion of the gate line slots extend from the core region to the non-core region. The portion of the gate line slot located in the core region is a first gate line slot, and the portion located in the non-core region is a second gate line slot. The step of removing a portion of the gate sacrificial layer to form the void includes: Sacrificial filler is formed in the grid wire gaps, the peripheral contact holes, and the sealing grooves; Remove the sacrificial filler located within the first grid line gap; and A first void is formed by removing a portion of the gate sacrificial layer located in the core region via the first gate line gap.

4. The method according to claim 3, wherein, The step of removing a portion of the gate sacrificial layer to form the void further includes: Remove the sacrificial filler located within the second grid line gap; and A portion of the gate sacrificial layer located in the non-core region is removed via the second gate line gap to form a second gap that is connected to the first gap.

5. The method according to claim 4, wherein, The step of forming the gate layer within the gap includes: The gate layer is formed within the first gap and the second gap. Wherein, after the conductive layer is formed, the conductive layer is connected to the portion of the gate layer located within the second gap.

6. The method according to claim 3, wherein, The step of removing the sacrificial filler located within the first grid line gap includes: A mask layer is provided on the portion of the sacrificial filler located within the second grid gap, the portion located within the peripheral contact hole, and the portion located within the sealing groove; and Remove the portion of the sacrificial filler that is not covered by the mask layer.

7. The method according to claim 3, wherein, The steps for forming the self-aligned contact hole include: Remove a portion of the stacked structure located in the non-core region to form a self-aligned contact hole exposing the remaining portion of the gate sacrificial layer; and The step of forming the gap exposing the gate layer includes: The gap is formed by removing the exposed portion of the gate sacrificial layer via the self-aligned contact hole and removing the portion of the gate sacrificial layer between the exposed portion and the gate layer.

8. The method according to claim 7, wherein, After forming the self-aligned contact hole, the method further includes: Remove the sacrificial filler located in the peripheral contact hole and the sealing groove.

9. The method according to claim 8, wherein, Before forming the gap, the method further includes: An isolation layer is formed on the sidewalls of the self-aligning contact hole, the peripheral contact hole, and the sealing groove.

10. The method of claim 9, further comprising: A peripheral contact portion and a sealing ring are respectively formed in the peripheral contact hole and the sealing groove. The conductive layer, the peripheral contact portion, and the sealing ring are formed in the same process.

11. The method according to claim 1, wherein, After forming the self-aligned contact hole, the method further includes: A first portion of the gate sacrificial layer is removed via the gate line gap; The second portion of the gate sacrificial layer is removed via the self-aligned contact hole; and The interconnected space formed after removing the first and second portions of the gate sacrificial layer, as well as the self-aligned contact hole, are filled with conductive material.

12. A semiconductor structure, characterized in that, The semiconductor structure includes: A stacked structure includes a memory array region and a peripheral region, wherein the portion of the stacked structure located in the memory array region includes alternately stacked dielectric layers and gate layers; A semiconductor layer is located on one side of the stacked structure along the stacking direction of the stacked structure; A peripheral contact portion and a sealing ring are located in the peripheral region, and extend through the stacking structure along the stacking direction of the stacking structure and into the semiconductor layer. The sealing ring surrounds the peripheral contact portion and the memory array region. A gate line slot structure is located in the memory array region, extends through the stacked structure along the stacking direction, and extends into the semiconductor layer; and Multiple self-aligned contact structures are located between adjacent gate line gap structures. These self-aligned contact structures pass through the first surface of the stacked structure located in the memory array region and extend to gate layers with different numbers of stacked layers. Each of the self-aligned contact structures includes a conductive layer and a fill layer, the conductive layer being connected to and surrounding the corresponding gate layer, and at least a portion of the conductive layer being exposed on the first surface.

13. The semiconductor structure according to claim 12, wherein, The semiconductor structure also includes: A channel structure extending through the portion of the stacked structure located in the memory array region, wherein the critical dimension of the channel structure is smaller than the critical dimension of the self-aligned contact structure.

14. The semiconductor structure according to claim 12, wherein, The memory array region includes a core region and a non-core region. The portion of the stacked structure located in the core region includes alternately stacked dielectric layers and gate layers. The portion of the stacked structure located in the non-core region includes the gate layer, the dielectric layer, and the reserved sacrificial layer. The gate layer and the reserved sacrificial layer are located on the same stacked layer, and the dielectric layer is stacked alternately with the gate layer and the reserved sacrificial layer.

15. The semiconductor structure according to claim 14, wherein, The self-aligned contact structure is located in the non-core region, and the conductive layer is connected to the portion of the gate layer located in the non-core region.

16. The semiconductor structure according to claim 15, wherein, The conductive layer includes a first conductive layer and a second conductive layer connected to the first conductive layer. The first conductive layer is connected to the gate layer, and at least a portion of the second conductive layer is exposed on the first surface. The semiconductor structure also includes: An isolation layer is located between the second conductive layer and the stacked structure, and surrounds the second conductive layer.

17. The semiconductor structure according to claim 16, wherein, On a plane perpendicular to the stacking direction of the dielectric layer and the gate layer, the projection of the second conductive layer lies within the projection of the first conductive layer.

18. A semiconductor device, comprising: The semiconductor structure as described in any one of claims 12-17; as well as Logic process compatible devices.

19. A semiconductor system, comprising: The semiconductor device as described in claim 18; as well as A controller, electrically connected to the semiconductor device, is configured to control the semiconductor device to perform at least one of a read operation, a program operation, and an erase operation.

20. A storage device, comprising: The semiconductor system as described in claim 19; as well as A housing for supporting the semiconductor system.

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