Three-dimensional memory and methods of making the same, memory systems

Abstract

Some embodiments of the present application provide a three-dimensional memory and a method of manufacturing the same, a memory system. The method comprises: sequentially forming a first semiconductor layer, a second semiconductor layer and a stack structure on one side of a substrate; forming a channel hole penetrating through the stack structure to the substrate; forming a first additional layer on the surface of the second semiconductor layer exposed by the sidewall of the channel hole, wherein, along the radial direction of the channel hole, the first additional layer protrudes towards the axis of the channel hole; and forming a functional layer in the channel hole, and forming a channel layer in the channel hole where the functional layer is formed, wherein the channel layer is spaced apart from the first additional layer by the functional layer, and the bottom of the channel layer is located on the side of the first additional layer away from the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication method and memory system. Background Technology

[0002] To increase storage capacity per unit area, three-dimensional memory (e.g., 3D NAND) that extends vertically has emerged. However, as the number of stacked layers increases, challenges arise in controlling the contour of the formed channels during the fabrication process of three-dimensional memory, such as ensuring the uniformity of the channels. Summary of the Invention

[0003] This application provides a method for fabricating a three-dimensional memory, which includes: sequentially forming a first semiconductor layer, a second semiconductor layer, and a stacked structure on one side of a substrate; forming a channel hole penetrating the stacked structure into the substrate; forming a first additional layer on the surface of the second semiconductor layer exposed on the sidewall of the channel hole, wherein the first additional layer protrudes toward the axis of the channel hole along the radial direction of the channel hole; and forming a functional layer in the channel hole and forming a channel layer in the channel hole in which the functional layer is formed, wherein the channel layer and the first additional layer are separated by the functional layer, and the bottom of the channel layer is located on the side of the first additional layer away from the substrate.

[0004] In some embodiments, forming a first semiconductor layer, a second semiconductor layer, and a stacked structure sequentially on one side of a substrate includes: doping the second semiconductor layer before forming the stacked structure.

[0005] In some embodiments, forming a first additional layer on the surface of the second semiconductor layer exposed on the sidewall of the channel hole includes: oxidizing the first semiconductor layer and the second semiconductor layer exposed on the sidewall of the channel hole, wherein the oxidized portion of the second semiconductor layer forms the first additional layer, and the oxidized portion of the first semiconductor layer forms the second additional layer.

[0006] In some embodiments, the method further includes forming a stop layer between the substrate and the first semiconductor layer.

[0007] In some embodiments, after forming a channel layer within a channel hole in which a functional layer is formed, the method further includes removing the substrate and a portion of the functional layer extending into the substrate to a stop layer.

[0008] In some embodiments, after forming a channel layer within a channel via in which a functional layer is formed, the method further includes: exposing the channel layer by removing a stop layer and a portion of the functional layer; and forming a third semiconductor layer connected to the channel layer.

[0009] In some implementations, during the process of removing a portion of the functional layer, a second additional layer is removed, or a first additional layer and a second additional layer are removed.

[0010] In some embodiments, after forming a channel layer within a channel hole in which a functional layer is formed, the method further includes connecting a peripheral circuit semiconductor structure on the side away from the substrate.

[0011] In some embodiments, after forming a channel layer within a channel hole in which a functional layer is formed, the method further includes: forming a gate wire slot structure extending through the stacked structure into a substrate, wherein the gate wire slot structure comprises an insulating layer and a conductive layer sequentially from the outside to the inside; and removing portions of the insulating layer located on both sides of the conductive layer during the process of exposing the channel layer by removing a stop layer and a portion of the functional layer.

[0012] This application also provides a three-dimensional memory, which includes: a first semiconductor layer; a second semiconductor layer located on one side of the first semiconductor layer; a stacked structure located on one side of the first semiconductor layer; and a channel structure passing through the stacked structure and including a functional layer and a channel layer disposed sequentially from the outside to the inside, wherein the end face of the channel layer near the first semiconductor layer and the end face of the functional layer near the first semiconductor layer are both recessed relative to the surface of the stacked structure near the first semiconductor layer.

[0013] In some embodiments, the end face of the channel layer near the first semiconductor layer is located between the end face of the functional layer near the first semiconductor layer and the surface of the stacked structure near the first semiconductor layer.

[0014] In some embodiments, the three-dimensional memory further includes a third semiconductor layer located on the side of the first semiconductor layer away from the stacked structure and connected to the channel layer through the first semiconductor layer.

[0015] In some embodiments, the third semiconductor layer includes a first part and a second part connected together, the first part being located on the side of the first semiconductor layer away from the stacked structure, and the second part passing through the first semiconductor layer and connected to the channel layer.

[0016] In some embodiments, the three-dimensional memory further includes a first additional layer located between the second portion and the second semiconductor layer.

[0017] In some embodiments, the second part has a recessed portion with the opening of the recessed portion facing away from the channel layer.

[0018] In some implementations, the surface of the second part that is away from the stacked structure is flush with the surface of the first part that is away from the stacked structure.

[0019] In some implementations, the second semiconductor layer is made of the same material as the third semiconductor layer.

[0020] In some embodiments, the three-dimensional memory further includes a peripheral circuit semiconductor structure located on the side of the stacked structure away from the first semiconductor layer.

[0021] In some implementations, there are multiple channel structures, and the end faces of each channel layer in the multiple channel structures that are close to the first semiconductor layer are flush.

[0022] This application also provides a memory system comprising: a three-dimensional memory as described in any of the above embodiments; and a controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory.

[0023] According to at least one embodiment of this application, the three-dimensional memory and its fabrication method and memory system provided by this application, by forming a second semiconductor layer and forming a first additional layer on the surface of the second semiconductor layer, reduces the size of the channel hole corresponding to the first additional layer in the direction perpendicular to the extension of the channel hole, thereby forming a channel layer on the side of the first additional layer away from the substrate, and ensuring that the end face of the channel layer near the substrate has a controllable spacing distance (functional layer thickness) with the substrate, thereby ensuring the consistency and uniformity of the end faces of each channel layer near the substrate, and being compatible with the subsequent process of removing the substrate and part of the functional layer until the channel layer is exposed, as well as forming a third semiconductor layer connected to the channel layer, thereby improving the electrical connection performance between the semiconductor layer and the channel layer. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0025] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0026] Figures 2A to 2K It is based on Figure 1 The diagram shows some exemplary cross-sectional views of the fabrication process of the three-dimensional memory using the fabrication method shown.

[0027] Figures 3A to 3C It is based on Figure 1 Further exemplary cross-sectional schematic diagrams of the fabrication process of the three-dimensional memory shown in the illustration;

[0028] Figures 4A to 4B It is based on Figure 1 Further exemplary cross-sectional schematic diagrams of the fabrication process of the three-dimensional memory shown in the illustration;

[0029] Figure 5This is a top view schematic diagram of a three-dimensional memory having two storage blocks according to an embodiment of this application;

[0030] Figure 6A and Figure 6B This is a top view schematic diagram of a three-dimensional memory having four storage planes according to an embodiment of this application;

[0031] Figure 7 This is a system block diagram of a memory system according to an embodiment of this application; and

[0032] Figure 8A and Figure 8B This is a schematic diagram of a memory system according to an embodiment of this application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first semiconductor layer discussed herein may also be referred to as the second semiconductor layer, the first additional layer may also be referred to as the second additional layer, and the first part may also be referred to as the second part, and vice versa.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0036] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Furthermore, in this application, the term "connection" may refer to direct or indirect contact between corresponding components, unless otherwise expressly defined or deduced from the context.

[0040] In the various figures of this application, the x and y directions illustrate two vertical directions in a three-dimensional memory. For example, the x direction may be the word line direction, the y direction may be the bit line direction, and the z direction may be the stacking direction. The spatial relationships of the three-dimensional memory are exemplarily described below using the x, y, and z directions.

[0041] This application provides a method 100 for fabricating a three-dimensional memory. Figure 1 This is a flowchart of a method 100 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 1 As shown, the preparation method 100 includes steps S110 to S170. Figures 2A to 2K It is based on Figure 1 The diagram shows some exemplary cross-sectional views of the three-dimensional memory fabricated using method 100. It should be understood that the steps shown in method 100 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps shown]. Figure 1 The execution order is shown below. (Followed by...) Figures 2A to 2K The steps S110 to S170 described above are further described.

[0042] Step S110

[0043] Figure 2AA cross-sectional schematic diagram of a three-dimensional memory 200a is shown after a first semiconductor layer 214, a second semiconductor layer 212, and a stacked structure (e.g., a first stacked portion 220-1) and a channel via (e.g., a first channel via 230-1) are sequentially formed on one side of a substrate 211.

[0044] like Figure 2A As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form, for example, a stop layer 216, a first semiconductor layer 214, a second semiconductor layer 212, and a first stacked portion 220-1 on the substrate 211. Exemplarily, the material of the substrate 211 may include, but is not limited to, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any other suitable material.

[0045] For example, the first stacking portion 220-1 may be a stacking structure 220 (see reference). Figure 2C The portion close to the substrate 211. For example, the number of gate dielectric layer (e.g., 221) and gate sacrificial layer (e.g., 222) pairs included in the first stack 220-1 may be half the number of gate dielectric layer (e.g., 221) and gate sacrificial layer (e.g., 222) pairs included in the stack structure 220.

[0046] In some examples, such as Figure 2A As shown, a stop layer 216 may be formed between the first semiconductor layer 214 and the substrate 211. The stop layer 216 can, for example, stop the removal of the substrate 211 on its surface during subsequent removal processes, thereby reducing the control difficulty of the substrate removal process. When the substrate 211 is made of silicon, the stop layer 216 may be made of, for example, silicon oxide.

[0047] Step S120

[0048] In step S120, in some examples, continue to refer to Figure 2A A first channel hole 230-1, for example, can be formed by using a wet etching process or a dry etching process, penetrating sequentially along the z-direction through the first stacked portion 220-1, the second semiconductor layer 212, the first semiconductor layer 214, and the stop layer 216 to the substrate 211. Exemplarily, the first channel hole 230-1 can be a channel hole (see reference). Figure 2CThe outer contour space of the channel structure 233 shown penetrates a portion of the first stack 220-1. The first channel hole 230-1 may include a first hole 231 corresponding to the first stack 220-1 and a connection hole 232 corresponding to the second semiconductor layer 212. Optionally, the first channel hole 230-1 may also include a second hole 237 corresponding to the first semiconductor layer 214. In other words, the first stack 220-1 is exposed to the first hole 231, the second semiconductor layer 212 is exposed to the connection hole 232, and the first semiconductor layer 214 is exposed to the second hole 237. The first channel via 230-1 may pass through, for example, a portion of the stop layer 216 and the substrate 211 and extend into the interior of the substrate 211. Thus, the first channel via 230-1 may also include, for example, a bottom via 234 corresponding to the stop layer 216 and the substrate 211. The bottom via 234 may include a sidewall and a bottom surface defined by the substrate 211, and the bottom surface of the bottom via 234 may be the bottom surface of the channel via (e.g., the first channel via 230-1). In some examples, the number of channel vias (e.g., the first channel via 230-1) may be multiple. Multiple channel vias (e.g., the first channel via 230-1) may be distributed in a two-dimensional array relative to the xy plane. The number of channel vias (e.g., the first channel via 230-1) may be determined according to actual storage requirements.

[0049] In some examples, along with, for example, a first stack 220-1 or a stack structure 220 (see reference) Figure 2C As the number of stacked layers increases, the difficulty of controlling the profile of the channel hole (e.g., the depth of the bottom hole 234) also increases. Figure 2A As shown, during the process of forming multiple channel holes (e.g., first channel hole 230-1), the depth of the multiple bottom holes (e.g., 234) in each channel hole (e.g., first channel hole 230-1) may exhibit poor uniformity. In other words, in the z-direction, the bottom surfaces of the multiple channel holes (e.g., first channel hole 230-1) may not be on the same plane. In other words, during the process of forming multiple first channel holes (e.g., 230-1), the depth of the multiple bottom holes (e.g., 234) in each first channel hole (e.g., 230-1) may exhibit poor uniformity.

[0050] like Figure 2A As shown, a first semiconductor layer 214 may be formed between a second semiconductor layer 212 and, for example, a stop layer 216. The first semiconductor layer 214 may, for example, cause removal to stop on its surface during a subsequent process for removing the functional layer 235, thereby helping to reduce the removal of portions of the functional layer 235 (see reference). Figure 2C The difficulty of controlling the process. For example, the material of the first semiconductor layer 214 may be a material with a different etching selectivity than that of the functional layer 235, such as polysilicon.

[0051] In some examples, the doping concentration of the second semiconductor layer 212 may be greater than that of the first semiconductor layer 214. For example, the second semiconductor layer 212 may be doped polysilicon, and the first semiconductor layer 214 may be undoped polysilicon. Exemplarily, the second semiconductor layer 212 and the first semiconductor layer 214 with doped concentrations may be implemented by an in-situ doping thin film deposition process, or by a doping process after the thin film deposition process.

[0052] Step S130

[0053] Figure 2B A cross-sectional schematic diagram of a three-dimensional memory 200b after the formation of the first additional layer 213 is shown.

[0054] In step S130, as Figure 2B As shown, a first additional layer 213 can be formed on the surface of the second semiconductor layer 212 exposed to the connection hole 232 using the first channel hole 230-1 formed in step S120. That is, the first additional layer 213 is formed on the surface of the second semiconductor layer 212 exposed on the sidewall of the first channel hole 230-1. The first additional layer 213 can be formed gradually along the extension axis direction toward the first channel hole 230-1, which will cause the size of the connection hole 232 in the direction perpendicular to its extension axis to gradually decrease, so that after the formation of the first additional layer 213, the size of the connection hole 232 is smaller than the size of the first hole 231 in the extension direction perpendicular to the channel hole 230. For example, when the first channel hole 230-1 has a cylindrical outer contour shape, the first additional layer 213 can be formed by gradually forming a protrusion on the surface of the second semiconductor layer 212 along the radial direction of the first channel hole 230-1 toward the central axis, so that after the formation of the first additional layer 213, the aperture of the connection hole 232 is smaller than the aperture of the first hole 231.

[0055] In some examples, since the first stacking portion 220-1 can be a stacking structure 220 (see reference) Figure 2C The first channel hole 230-1 is located near a portion of the substrate 211, and the channel hole 230-1 can be a portion of the first stacked portion 220-1. In this way, the distance between the second semiconductor layer 212 exposed by the connecting hole 232 and the hole opening is relatively small, which helps to further reduce the process difficulty of forming the first additional layer 213 using the first channel hole 230-1.

[0056] In some examples, such as Figure 2BAs shown, when the doping concentration of the second semiconductor layer 212 is greater than that of the first semiconductor layer 214, an oxidation process can be used in the same process to process the second semiconductor layer 212 and the first semiconductor layer 214 exposed on the sidewall of the first channel hole 230-1, so that the oxidized part of the second semiconductor layer 212 is transformed into the first additional layer 213, and the oxidized part of the first semiconductor layer 214 is transformed into the second additional layer 215.

[0057] It should be noted that, since the doping concentration of the second semiconductor layer 212 is greater than that of the first semiconductor layer 214, when both are oxidized in the same process, the oxidation rate of the second semiconductor layer 212 with a higher doping concentration is greater than that of the first semiconductor layer 214 with a lower doping concentration. This results in the first additional layer 213, grown along the extension axis towards the first channel hole 230-1, having a larger protrusion size than the second additional layer 215 within the same processing time. Thus, after the formation of the first additional layer 213, the size of the connecting hole 232 in the extension direction perpendicular to the first channel hole 230-1 is smaller than the sizes of the first hole 231 and the second hole 237. Exemplarily, by controlling the processing time of the oxidation process, the size of the connecting hole 232 defined by the inner surface of the first additional layer 213 in the extension direction perpendicular to the channel hole (e.g., the first channel hole 230-1) is controlled to meet the requirements of the subsequent step S140. Exemplarily, the materials of both the first additional layer 213 and the second additional layer 215 can be oxides, such as silicon oxide.

[0058] After the above-described process, the first additional layer 213 can be a ring-shaped structure similar to that surrounding the connecting hole 232, and the inner surface of the first additional layer 213 can serve as the sidewall of the connecting hole 232. For example, the dimension of the connecting hole 232 in the extension direction perpendicular to the channel hole 230 is positively correlated with the thickness of the functional layer 235 formed in the subsequent step S140.

[0059] In some examples, a plurality of first additional layers (e.g., 212) may be formed on the surface of a plurality of second semiconductor layers (e.g., 212) exposed by a connection hole (e.g., 232) of a plurality of channel holes (e.g., first channel holes 230-1). The surfaces of the plurality of first additional layers (e.g., 213) away from the substrate 211 may be in the same plane.

[0060] In some examples, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used, for example, to fill a sacrificial layer (not shown) within the first channel via 230-1. Further, a second stack 220-2 (refer to) covering the sacrificial layer is formed on the first stack 220-1. Figure 2CFurthermore, a second channel hole, penetrating the second stacked portion 220-2 and communicating with the first channel hole 230-1, can be formed using, for example, a dry etching process or a wet etching process, and the sacrificial layer within the first channel hole 230-1 can be removed. The first channel hole 230-1 and the second channel hole can be referred to as channel holes. In other examples, the stacked structure and the channel hole penetrating the stacked structure into the substrate can be formed in a single process. This application does not limit the specific embodiments for forming the channel hole and forming the first additional layer using the channel hole.

[0061] Step S140

[0062] Figure 2C A cross-sectional schematic diagram of a three-dimensional memory 200c after the formation of the channel structure 233 is shown.

[0063] like Figure 2B and 2C As shown, a functional layer 235 can be formed on the inner wall of the channel hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, the functional layer 235 can be formed on the bottom surface and sidewalls of the bottom hole 234, the sidewalls of the second hole 237, the sidewalls of the connecting hole 232, and the sidewalls of the first hole 231. Since the first additional layer 213 formed in step S130 can reduce the size of the connecting hole 232 in the direction perpendicular to the extension of the channel hole, the connecting hole 232 can be completely filled with the functional layer 235, while there is still space to be filled after the functional layer 235 is formed on the sidewall of the first hole 231. Further, a channel layer 236 can be formed in the first hole 231 where the functional layer 235 is formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, i.e., the channel layer 236 is formed on the surface of the functional layer 435 in the first hole 231. In other words, the channel layer 236 and the first additional layer 213 are separated by a functional layer 235. The bottom of the channel layer 236 is located on the side of the first additional layer 213 away from the substrate 211, thereby ensuring that the end face of the channel layer 236 near the substrate 211 has a controllable distance (thickness of the functional layer 235) from the substrate 211.

[0064] In some examples, multiple functional layers (e.g., 235) may be formed within each via in the same process. Further, multiple channel layers (e.g., 236) may be formed within each first via (e.g., 231). The end faces of each channel layer 236 near the substrate 211 may have a consistent, controllable distance from the substrate 211, such that the end faces of each channel layer (e.g., 236) near the substrate 211 are located in substantially the same plane, thereby facilitating the maintenance of consistency and uniformity in the horizontal position of each channel layer (e.g., 236).

[0065] In some examples, such as Figure 2C As shown, functional layer 235 can be a composite layer structure. From the outside in, functional layer 235 may sequentially include a charge blocking layer, a charge trapping layer, and a tunneling layer. Exemplarily, the materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include silicon oxide, silicon nitride, and silicon oxide. The material of channel layer 236 may include semiconductor materials such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon.

[0066] In some exemplary embodiments, after forming the channel holes, the functional layer and the channel layer are formed directly within the channel holes, when the bottom surfaces of multiple channel holes are not on the same plane (see reference). Figure 2A The distance between the end face of the channel layer near the substrate and the substrate depends on the depth of the channel hole extending into the substrate. Thus, the distance between the end face of the channel layer near the substrate and the substrate cannot be accurately controlled, and it is difficult to maintain uniformity and consistency of the end faces of multiple channel layers near the substrate.

[0067] According to some embodiments of this application, the fabrication method 100 of a three-dimensional memory is provided. By forming a second semiconductor layer and forming a first additional layer on the surface of the second semiconductor layer, the size of the channel hole corresponding to the first additional layer is reduced in the direction perpendicular to the extension of the channel hole. This results in the formation of a channel layer on the side of the first additional layer away from the substrate. It also ensures that the end face of the channel layer near the substrate has a controllable spacing distance (functional layer thickness) with the substrate. This ensures that the end faces of each channel layer near the substrate maintain consistency and uniformity. It is also compatible with subsequent processes such as removing the substrate and part of the functional layer until the channel layer is exposed, and forming a third semiconductor layer connected to the channel layer. This improves the electrical connection performance between the third semiconductor layer and the channel layer.

[0068] In some examples, a capping layer 217 may be formed on the side of the stacked structure 220 away from the substrate 211 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to cover the end face of the channel structure 233 away from the substrate 211. Optionally, the material of the capping layer 217 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0069] In some examples, after step S140, the fabrication method 100 may further include forming a gate gap structure and attaching multiple gate sacrificial layers (e.g., 222 (reference)) in the stacked structure 220. Figure 2A The step of replacing the gate layer with multiple gate layers. Figure 2D A cross-sectional schematic diagram of a three-dimensional memory 200d after the formation of the gate slot structure 240 is illustrated. For example, as shown... Figure 2DAs shown, gate line gaps penetrating the stacked structure 220 to the substrate 211 can be formed using, for example, wet etching or dry etching processes. These gate line gaps serve as channels for etching material (e.g., etching solution) to remove multiple gate sacrificial layers (e.g., 222 (reference)) in the stacked structure 220. Figure 2A Multiple sacrificial gaps are formed. Further, a high-dielectric-constant layer 241 can be formed on the inner walls of the multiple sacrificial gaps and gate line gaps using a thin-film deposition process. Optionally, an adhesive layer 2231 can be formed within the multiple sacrificial gaps where the high-dielectric-constant layer 241 is formed. Further, a conductive layer (e.g., a first conductive layer 2232) can be filled within the multiple sacrificial gaps. For example, within each sacrificial gap, a portion of the high-dielectric-constant layer 241, the adhesive layer 2231, and the first conductive layer 2232 together constitute the gate layer 223. Optionally, the material of the high-dielectric-constant layer 241 may include, but is not limited to, alumina, hafnium oxide, etc. The material of the adhesive layer 2231 may include, but is not limited to, titanium, titanium nitride, or combinations thereof. The material of the first conductive layer 2232 may include, but is not limited to, tungsten, cobalt, copper, aluminum, doped crystalline silicon, silicides, or combinations thereof. In other examples, conductive material can be directly filled within the multiple sacrificial gaps to form the gate layer.

[0070] For example, the portion of the high dielectric constant layer 241 that contacts the substrate 211 can be removed. Further, an insulating layer 242 and a conductive layer (e.g., a second conductive layer 243) can be sequentially formed within the gate gap using a thin-film deposition process. For example, portions of the high dielectric constant layer 241, the insulating layer 242, and the second conductive layer 243 located on the sidewalls of the gate gap together constitute the gate gap structure 240. Optionally, the material of the insulating layer 242 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The material of the second conductive layer 243 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicides, or combinations thereof.

[0071] Figure 2E A cross-sectional schematic diagram of a three-dimensional memory 200e connected to a peripheral circuit semiconductor structure 250 is shown. In some examples, such as... Figure 2EAs shown, after forming the gate gap structure 240, the peripheral circuit semiconductor structure 250 can be connected to the side of the stacked structure 220 away from the substrate 211, for example, via multiple interconnect contacts (e.g., 251). Exemplarily, the peripheral circuit semiconductor structure 250 can be placed on the surface of the memory array semiconductor structure (e.g., including the substrate 241 and structures such as the stacked structure 220 and channel structure 233 formed on one side thereon) where multiple interconnect contacts (e.g., 251) are formed. Then, an alignment step is performed (e.g., aligning the interconnect contacts on the memory array semiconductor structure with the corresponding interconnect contacts on the peripheral circuit semiconductor structure 250), and the peripheral circuit semiconductor structure 250 is bonded to the surface of the memory array semiconductor structure exposing multiple interconnect contacts, for example, using a bonding process. It should be noted that the bonding process can be any suitable bonding connection technology such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, adhesive bonding, or eutectic bonding.

[0072] In some examples, the peripheral devices and other structures within the peripheral circuit semiconductor structure 250 may be fabricated according to any conventional processes known in the art, which will not be elaborated upon herein. Exemplarily, the peripheral circuit may include one or more of page buffers, decoders (e.g., row decoders and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuit.

[0073] Step S150

[0074] Figure 2F A cross-sectional schematic diagram of a three-dimensional memory 200f is shown after removing the substrate and a portion of the functional layer 235 extending into the substrate.

[0075] like Figure 2E and 2F As shown, a chemical mechanical polishing (CMP) process can be used, for example, to remove the substrate 211 and portions of the functional layers 235 (i.e., the portion of the functional layer 235 located in the bottom hole 234) within the various channel structures (e.g., 233) extending into the substrate 211, such that the multiple channel structures (e.g., 233) are flush with the end faces away from the peripheral circuit semiconductor structure 250. In some examples, where a stop layer 216 is formed between the substrate 211 and the first semiconductor layer 214, the CMP process can be stopped, for example, at the surface of the stop layer 216, which helps to reduce the control difficulty of the process of removing the substrate 211 and the portion of the functional layers 235.

[0076] In some examples, during step S150, the end of the gate line slot structure 240 remote from the peripheral circuit semiconductor structure 250 may be removed, such that the end face of the gate line slot structure 240 remote from the peripheral circuit semiconductor structure 250 is flush with the end faces of the plurality of channel structures (e.g., 233) remote from the peripheral circuit semiconductor structure 250. For example, in step S150, the portion of the gate line slot structure 240 remote from the peripheral circuit semiconductor structure 250 and surrounding the second conductive layer 243 is removed, exposing the second conductive layer 243.

[0077] Step S160

[0078] Figure 2G A cross-sectional schematic diagram of a three-dimensional memory 200g is shown, after removing part of the functional layer 235 to expose the channel layer 236.

[0079] like Figure 2F and 2G As shown, the bottom hole 234 (see reference) can be removed, for example, using a wet etching process or a dry etching process. Figure 2B Another functional layer 235 within the second hole 237 (see reference) Figure 2B Part of the functional layer 235 within the ) and located in the connection hole 232 (reference) Figure 2B The functional layer 235 within the first hole 231 (see reference) Figure 2B A portion of the functional layer 235 within the stacked structure 220 is removed until the end of the channel layer 236 away from the peripheral circuit semiconductor structure 250 is exposed. After the above process, the end faces of the functional layer 235 and the channel layer 236 are recessed relative to the surface of the stacked structure 220. The first semiconductor layer 214 remains on the surface of the second semiconductor layer 212 away from the peripheral circuit semiconductor structure 250. The first semiconductor layer 214 can serve as a stop layer for removing a portion of the functional layer 235, which helps to reduce the control difficulty of the process of removing a portion of the functional layer 235. When step S160 is performed on multiple channel structures (e.g., 233), since the end faces of each channel layer (e.g., 236) away from the peripheral circuit semiconductor structure 250 are in the same plane, or in other words, the end face of each channel layer away from the peripheral circuit semiconductor structure 250 is at a distance of from the substrate 211 (reference) Figure 2E The process is controllable, which effectively reduces the difficulty of process control in removing part of the functional layer 235 to expose the channel layer 236 due to physical differences in the channel layer (e.g., 236).

[0080] In some examples, during the removal of a portion of the functional layer 235, a portion of the second additional layer 215 and a portion of the extension axis of the first additional layer 213 toward the channel structure 233 may be removed. Optionally, if a stop layer 216 is formed between the substrate 211 and the first semiconductor layer 214, the stop layer 216 may be removed during the removal of the portion of the functional layer 235. After the above process, the three-dimensional memory 200g may have a recess corresponding to the channel structure 233.

[0081] In some examples, during the removal of part of the functional layer 235, part of the insulating layer 242 on both sides of the second conductive layer 243 of the gate gap structure 240 may be removed to form a gap on both sides of the second conductive layer 243.

[0082] In some examples, Figure 2H A cross-sectional schematic diagram of a three-dimensional memory 200h is shown, illustrating the doping treatment of the ends of the channel layer 236 and the second conductive layer 243. (See attached diagram.) Figure 2H As shown, the ends of the channel layer 236 and the second conductive layer 243 away from the stacked structure 220 can be doped, for example, using an ion implantation process. For example, in the z-direction, the region where the ends of the channel layer 236 away from the stacked structure 220 are doped can span at least one gate layer 223 to adjust the threshold voltage of, for example, a selection transistor corresponding to the gate layer 223.

[0083] Step S170

[0084] Figure 2I A cross-sectional schematic diagram of a three-dimensional memory 200i after the formation of the third semiconductor layer 261 is shown.

[0085] like Figure 2H and 2IAs shown, a third semiconductor layer 261, connected to the channel layer 236, can be formed on the side of the first semiconductor layer 214 away from the stacked structure 220 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the third semiconductor layer 261 may also be connected to the second conductive layer 243 and extend to both sides of the end of the second conductive layer 243 away from the stacked structure 220, thereby surrounding the second conductive layer 243. Exemplarily, the material of the third semiconductor layer 261 may include, but is not limited to, silicon (monocrystalline silicon, polycrystalline silicon, amorphous silicon), such as doped polycrystalline silicon. Exemplarily, the third semiconductor layer 261 formed in this step may be treated using, for example, high-temperature annealing and / or laser annealing processes to improve the film quality of the doped third semiconductor layer 261. The third semiconductor layer 261 is electrically connected to multiple channel layers (e.g., 236) in multiple channel structures (e.g., 233), and may serve, for example, as a common source for multiple channel structures (e.g., 233).

[0086] After the above process, part of the third semiconductor layer 261 contacts the first semiconductor layer 214, and part of the third semiconductor layer 261 is located on the inner wall of the recess corresponding to the channel structure 233. When the first semiconductor layer 214 and the third semiconductor layer 261 are made of the same material, the deposition thickness of the third semiconductor layer 261 can be reduced while meeting the thickness requirements.

[0087] In some examples, Figure 2J A cross-sectional schematic diagram of the three-dimensional memory 200j after the formation of the insulating capping layer 262 is shown. (See attached diagram.) Figure 2J As shown, an insulating capping layer 262 can be formed on the side of the third semiconductor layer 261 away from the stacked structure 220 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The insulating capping layer 262 can fill the aforementioned recess where the third semiconductor layer 261 has been formed. Exemplarily, the material of the insulating capping layer 262 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Optionally, a CMP process can be used to planarize the surface of the insulating capping layer 262 away from the stacked structure 220.

[0088] In some examples, Figure 2K A cross-sectional schematic diagram of a three-dimensional memory 200k is shown after the formation of conductive contacts 265 and back-end process interconnect layer 264. (See attached diagram.) Figure 2K As shown, one or more conductive contacts (e.g., 265) may be formed through the insulating capping layer 262 and connected to the third semiconductor layer 261. The conductive contacts (e.g., 265) may be used, for example, to bring out the third semiconductor layer 261. Further, a back-end process interconnect layer 264 may be provided on the side of the insulating capping layer 262 away from the stack structure 420.

[0089] according to Figure 1 In addition to the preparation method 100 shown, this application also provides other specific structures of three-dimensional memory in the preparation process. Figures 3A to 3C It is based on Figure 1 The diagram shows some other exemplary cross-sectional views of the fabrication process of the three-dimensional memory using the fabrication method shown. In this embodiment, steps S110 to S150 are the same as in the above embodiment, and will not be repeated here.

[0090] Step S160

[0091] Figure 3A A cross-sectional schematic diagram of a three-dimensional memory 300a is shown, after removing part of the functional layer 335 to expose the channel layer 336.

[0092] like Figure 2F and 3A As shown, the bottom hole 234 (see reference) can be removed, for example, using a wet etching process or a dry etching process. Figure 2B Another functional layer 335 within the second hole 237 (see reference) Figure 2B Part of the functional layer 335 within the ) is located at the connection hole 232 (reference) Figure 2B The functional layer 335 within the first hole 231 (reference) Figure 2B A portion of the functional layer 335 is removed until the end of the channel layer 336 away from the peripheral circuit semiconductor structure 350 is exposed. During the removal of the portion of the functional layer 335, the second additional layer 215 and the first additional layer 213 can be removed. In other words, all of the first additional layer 213 can be removed, thereby forming an annular groove defined by the first semiconductor layer 314, the second semiconductor layer 312, and the stacked structure 320, with the opening facing the extending axis of the channel structure 333.

[0093] Step S170

[0094] Figure 3B A cross-sectional schematic diagram of a three-dimensional memory 300b after the formation of the third semiconductor layer 361 is shown. Figure 3B As shown, a third semiconductor layer 361, connected to the channel layer 336, can be formed on the side of the first semiconductor layer 314 away from the stacked structure 320 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The third semiconductor layer 361 may extend to the point where the first additional layer 213 (see reference) is removed. Figure 2F The annular groove formed afterward.

[0095] In some examples, Figure 3CA cross-sectional view of a three-dimensional memory 300c is shown, illustrating the formation of an insulating capping layer 362, conductive contacts 365, and a back-end interconnect layer 364 after the formation of the third semiconductor layer 361. The specific fabrication process of the above structure is the same as the embodiment described above, and will not be repeated here.

[0096] according to Figure 1 In addition to the preparation method 100 shown, this application also provides some specific structures of three-dimensional memory in the preparation process. Figures 4A to 4B It is based on Figure 1 The diagram shows some further exemplary cross-sectional views of the fabrication process of the three-dimensional memory using the fabrication method shown. In this embodiment, steps S110 to S160 are the same as in the above embodiment, and will not be repeated here.

[0097] Step S170

[0098] Figure 4A A cross-sectional schematic diagram of a three-dimensional memory 400a after the formation of the third semiconductor layer 461 is shown. Figure 4A As shown, a third semiconductor layer 461, connected to the channel layer 436, can be formed on the side of the first semiconductor layer 414 away from the stacked structure 420 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The third semiconductor layer 461 can fill the recess corresponding to the channel structure 433 (see reference). Figure 2H Within. After the above process, the surface of the third semiconductor layer 461, which is away from the stacked structure 420 and corresponds to each channel structure (e.g., 463), can be flush.

[0099] In some examples, Figure 4B A cross-sectional view of a three-dimensional memory 400b is shown after the formation of the third semiconductor layer 461, followed by the sequential formation of an insulating capping layer 462, conductive contacts 465, and a back-end interconnect layer 464. The specific fabrication process of the above structure is the same as the embodiment described above, and will not be repeated here. It should be noted that when the surface of the third semiconductor layer 461 is flush with the surface of the stacked structure 420, a larger process window can be provided for the formation of the conductive contacts 465, thereby optimizing the process for forming the conductive contacts 465.

[0100] Some embodiments of this application provide a three-dimensional memory, for example... Figure 2K The three-dimensional memory shown is 200k. Figure 3C The three-dimensional memory 300c shown is or Figure 4B The three-dimensional memory 400b is shown. Figure 5This is a top view schematic diagram of a three-dimensional memory 500 having two storage blocks 501 according to an embodiment of this application. The three-dimensional memories 200k, 300c, and 400b can be arranged along... Figure 5 Some examples of cross-sectional structures cut by section line I-I' are shown below. For example, a three-dimensional memory (e.g., 200k, 300c, or 400b) can be formed according to fabrication method 100. The following is in conjunction with... Figure 2K , Figure 3C as well as Figure 4B The internal structure of the three-dimensional memory in each embodiment is further explained.

[0101] In some implementations, such as Figure 2K As shown, the three-dimensional memory 400k includes a first semiconductor layer 214, a second semiconductor layer 212, a stacked structure 220, and a channel structure 233. The first semiconductor layer 214 is a discrete thin-film structure, all located at the same height or height range in the z-direction. The second semiconductor layer 212 is located on one side of the first semiconductor layer 214 and is also a discrete thin-film structure, all located at the same height or height range in the z-direction. Exemplarily, the materials of the first semiconductor layer 214 and the second semiconductor layer 212 may include, but are not limited to, silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), silicon-germanium (SiGe), and germanium (Ge). For example, the first semiconductor layer 214 and the second semiconductor layer 212 may include a doped polycrystalline silicon layer.

[0102] The stacked structure 220 is located on the side of the second semiconductor layer 212 away from the first semiconductor layer 214. Exemplarily, the stacked structure 220 includes a plurality of alternately stacked gate dielectric layers (e.g., 221) and a plurality of gate layers (e.g., 223). Exemplarily, the material of the gate dielectric layer 221 may include, but is not limited to, silicon oxide. The gate layer 223 may be a composite layer structure; for example, each gate layer (e.g., 223) may include a conductive layer (e.g., a first conductive layer 2232) located at the core, and an adhesive layer 2231 and a high-dielectric-constant layer 241 sequentially at least partially surrounding the first conductive layer 2232. Optionally, the material of the high-dielectric-constant layer 241 may include, but is not limited to, aluminum oxide, hafnium oxide, etc. The material of the adhesive layer 2231 may include, but is not limited to, titanium, titanium nitride, or combinations thereof. The material of the first conductive layer 2232 may include, but is not limited to, tungsten, cobalt, copper, aluminum, doped crystalline silicon, silicides, or combinations thereof. In other examples, each gate layer may not have an adhesive layer and a high-dielectric-constant layer. Multiple gate layers (e.g., 223) can serve as word lines for a 200k three-dimensional memory.

[0103] The channel structure 233 can pass through the stacked structure 220 and includes a functional layer 235 and a channel layer 236 arranged sequentially from the outside to the inside, for example, the functional layer 235 surrounds the channel layer 236. The end face of the channel layer 236 near the first semiconductor layer 214 and the end face of the functional layer 235 near the first semiconductor layer 214 are recessed relative to the surface of the stacked structure 220 near the first semiconductor layer 214. In other words, the stacked structure 220 has a recess on the side near the first semiconductor layer 214, and the channel structure 233 passes through the stacked structure 220 at a location corresponding to the recess. Exemplarily, the end face of the functional layer 235 is flush with the bottom surface of the recess, and the channel layer 236 protrudes from the bottom surface of the recess in the stacked structure 220. In other words, the end face of the channel layer 236 near the first semiconductor layer 214 is located between the end face of the functional layer 235 near the first semiconductor layer 214 and the surface of the stacked structure 220 near the first semiconductor layer 214.

[0104] During the fabrication process described above, the end face of the channel layer 236 near the first semiconductor layer 214 and the surface of the stacked structure 220 near the first semiconductor layer 214 are at a controllable distance, thereby ensuring good consistency of the surface of the channel layer 236 near the first semiconductor layer 214. In some examples, such as Figure 5 As shown, multiple channel structures (e.g., 533) are distributed in a two-dimensional array relative to the xy plane. For example, several channel structures (e.g., 533) are arranged in rows along the x-direction, and several rows of channel structures are arranged alternately along the y-direction. The internal structure of each channel structure (e.g., 533) can be similar to that of channel structure 233, so that the surfaces of each channel layer near the first semiconductor layer can maintain consistency and uniformity.

[0105] In some examples, such as Figure 2K As shown, the three-dimensional memory 200k may further include a third semiconductor layer 261, which is located on the side of the first semiconductor layer 214 away from the stacked structure 220 and is connected to the channel layer 236 through the second semiconductor layer 212. Exemplarily, the material of the third semiconductor layer 261 includes, but is not limited to, polysilicon. For example, the first semiconductor layer 214 and the third semiconductor layer 261 may together serve as a common source for multiple channel structures (e.g., 233).

[0106] Exemplarily, the third semiconductor layer 261 may include a first portion 261-1 and a second portion 261-2 connected to each other. The first portion 261-1 is located on the side of the first semiconductor layer 214 away from the stacked structure 220, and the second portion 261-2 passes through the first semiconductor layer 214 and is connected to the channel layer 236. For example, the first portion 261-1 and the second portion 261-2 are alternately connected to each other to make the third semiconductor layer 261 a continuous thin film structure. When the third semiconductor layer 261 is connected to multiple channel layers 236, the third semiconductor layer 261 can serve as a common source for multiple channel structures (e.g., 233). Furthermore, since the surface of each channel layer (e.g., 236) near the first semiconductor layer 214 has good consistency and uniformity, the electrical connection performance between the third semiconductor layer 261 and the channel layers (e.g., 236) can be improved.

[0107] In some examples, the second portion 261-2 of the third semiconductor layer 261 may have a recess 261-21 with an opening facing away from the channel layer 236. In other words, the surface of the second portion 261-2 away from the stacked structure 220 is not flush with the surface of the first portion 261 away from the stacked structure 220.

[0108] In some examples, the three-dimensional memory 200k may also include a first additional layer 213. Exemplarily, the first additional layer 213 is a discrete thin-film structure, all located at the same height or height range in the z-direction. The first additional layer 213 may be located between the second semiconductor layer 212 and the second portion 261-2 of the third semiconductor layer 261. For example, the first additional layer 213 may be located within the space defined by the second semiconductor layer 212, the second portion 261-2, and the first semiconductor layer 214.

[0109] In some examples, such as Figure 2K As shown, the three-dimensional memory 200k also includes a gate line slot structure 240 extending through the stacked structure 220 along, for example, the z-direction. The gate line slot structure 240 may include an insulating layer 242 and a conductive layer (e.g., a second conductive layer 243) from the outside in. Exemplarily, a high-dielectric-constant layer 241 is present between the insulating layer 242 and a plurality of gate dielectric layers (e.g., 221) in the stacked structure 220. Optionally, the material of the insulating layer 242 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The material of the second conductive layer 243 may include, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or combinations thereof. The portion of the second conductive layer 243 in the gate line slot structure 240 adjacent to the third semiconductor layer 261 is surrounded by the third semiconductor layer 261.

[0110] In some examples, reference Figure 5 Grid line slot structure 240 (i.e. Figure 5The gate slot structure 540 shown may extend discontinuously along the x-direction. Other gate slot structures 570 may extend continuously along the x-direction. Exemplarily, in the y-direction, for example, two discontinuously extending gate slot structures 540 may be located between adjacent and continuously extending gate slot structures 570. A memory block 501 may be defined by adjacent and continuously extending gate slot structures 570, and a finger-shaped memory region 502 may be defined by continuously extending gate slot structures 570 and discontinuously extending gate slot structures 540, or by adjacent and discontinuously extending gate slot structures 540. Exemplarily, for discontinuously extending gate slot structures 540, the discontinuity may allow the respective gate layers in the stacked structure located on either side of it in the y-direction not to be cut off. In other words, the respective gate layers within the memory block 501 may be electrically connected to cooperate with the three-dimensional memory 500 to perform operations (e.g., erase operations) on a per-block basis 5701.

[0111] In some examples, such as Figure 2K As shown, the three-dimensional memory 200k also includes a peripheral circuit semiconductor structure 250, which is located on the side of the memory array semiconductor structure (e.g., including a substrate 241 and a stacked structure 220, a channel structure 233, etc. located on one side thereof) away from the third semiconductor layer 261. Exemplarily, the peripheral circuit semiconductor structure 250 is electrically connected to the channel structure 233 in the memory array semiconductor structure via a plurality of interconnect contacts (e.g., 251). Exemplarily, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry.

[0112] In some examples, such as Figure 2K As shown, the 3D memory 200k also includes an insulating capping layer 262 disposed on the side of the third semiconductor layer 261 away from the stacked structure 220, conductive contacts (e.g., 265) penetrating the insulating capping layer 262 and connected to the third semiconductor layer 261, and a back-end interconnect layer 264 located on the side of the insulating capping layer 262 away from the stacked structure 220 and connected to the conductive contacts (e.g., 265). The back-end interconnect layer 264 can be used, for example, to electrically connect the 3D memory 200k to external devices and transmit signals via a pad structure (not shown).

[0113] In some implementations, such as Figure 3C As shown, the three-dimensional memory 300c differs from the three-dimensional memory 200k described above in that the three-dimensional memory 300c does not include a first additional layer (e.g., Figure 2KThe first additional layer 213 is shown. The semiconductor layer 361 (e.g., the second part 361-2) extends to, for example... Figure 2K The space occupied by the first additional layer 213 is shown.

[0114] In some implementations, such as Figure 4B As shown, the three-dimensional memory 400b differs from the three-dimensional memory 200k described above in that the second portion 461-2 of the third semiconductor layer 461 does not have a recess. In other words, the surface of the second portion 461-2 away from the stacked structure 420 is flush with the surface of the first portion 461 away from the stacked structure 420. It is understood that the term "flush" as used in this application includes process tolerances.

[0115] Figure 6A and Figure 6B This is a top view schematic diagram of a three-dimensional memory 600a or 600b having four storage planes 603a or 603b according to an embodiment of this application.

[0116] like Figure 6A As shown, the three-dimensional memory 600a may include, for example, four memory planes (e.g., 603a). Memory plane 603a may include a core region CA for forming a plurality of channel structures and a connection region SA for forming electrical connection structures leading out a plurality of word lines within the core region CA. The connection region SA may be located between two core regions CA in the x-direction. Optionally, the connection region SA may be located in the middle of two core regions CA, or the two core regions CA may have unequal dimensions in the x-direction.

[0117] like Figure 6B As shown, the three-dimensional memory 600b may include, for example, four memory planes (e.g., 603b). Memory plane 603b may include a core region CA for forming a plurality of channel structures and a connection region SA for forming electrical connection structures leading out a plurality of word lines within the core region CA. The connection region SA may be located on opposite sides of the core region CA in the x-direction.

[0118] It should be noted that each core area CA may include multiple, for example... Figure 5 The storage block 501 is shown. Furthermore, the number of storage planes (e.g., 603a, 603b) included in the three-dimensional memory 600a is exemplary. In other examples, the three-dimensional memory may also include, for example, two or eight storage planes; this application does not limit the specific number of storage planes included in the three-dimensional memory.

[0119] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as needed. Furthermore, the materials of the layers described are merely exemplary.

[0120] Since the content and structure described above regarding the fabrication method 100 of the three-dimensional memory can be fully or partially applied to the three-dimensional memory described herein, related or similar content will not be repeated.

[0121] Some embodiments of this application also provide a memory system 12. Figure 7 This is a block diagram of a system 10 having a memory system 12 according to an embodiment of this application.

[0122] System 10 may be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 7 As shown, system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0123] The three-dimensional memory 14 may be any of the three-dimensional memories described in any of the embodiments disclosed herein, for example, Figure 2K The three-dimensional memory shown is 200k. Figure 3C The three-dimensional memory 300c shown is or Figure 4B The illustrated three-dimensional memory 400b. In some embodiments, each three-dimensional memory 14 may include a memory cell semiconductor structure and a peripheral circuit semiconductor structure for the memory cell array. Exemplarily, the memory cell array chip and the peripheral circuit chip may be stacked on top of each other in different planes.

[0124] According to some embodiments, controller 16 is coupled to 3D memory 14 and host 18 and is configured to control 3D memory 14. Controller 16 can manage data stored in 3D memory 14 and communicate with host 18. In some embodiments, controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 16 can be configured to control the operation of 3D memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0125] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 8A In one example shown, the controller 16 and a single 3D memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 7 The host 18) is coupled to the memory card connector 24. In such a way... Figure 8B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 7 The host 26 is coupled to the SSD connector 28. In some implementations, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0126] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, wherein, include: A first semiconductor layer, a second semiconductor layer, and a stacked structure are sequentially formed on one side of the substrate; Forming a channel hole that extends through the stacked structure into the substrate; A first additional layer is formed on the surface of the second semiconductor layer exposed on the sidewall of the channel hole, wherein the first additional layer protrudes toward the axis of the channel hole in the radial direction of the channel hole; and A functional layer is formed within the channel hole, and a channel layer is formed within the channel hole in which the functional layer is formed, wherein the channel layer and the first additional layer are separated by the functional layer, and the bottom of the channel layer is located on the side of the first additional layer away from the substrate.

2. The preparation method according to claim 1, wherein, A first semiconductor layer, a second semiconductor layer, and a stacked structure are sequentially formed on one side of the substrate, including: Before forming the stacked structure, the second semiconductor layer is doped.

3. The preparation method according to claim 2, wherein, Forming a first additional layer on the surface of the second semiconductor layer exposed on the sidewall of the channel hole includes: The first semiconductor layer and the second semiconductor layer exposed on the sidewall of the channel hole are oxidized, wherein the oxidized portion of the second semiconductor layer forms the first additional layer, and the oxidized portion of the first semiconductor layer forms the second additional layer.

4. The preparation method according to claim 1, wherein, The method further includes: A stop layer is formed between the substrate and the first semiconductor layer.

5. The preparation method according to claim 4, wherein, After forming a channel layer within the channel hole where the functional layer is formed, the method further includes: Remove the substrate and a portion of the functional layer extending into the substrate to the stop layer.

6. The preparation method according to claim 3, wherein, After forming a channel layer within the channel hole where the functional layer is formed, the method further includes: The channel layer is exposed by removing a portion of the functional layer; and A third semiconductor layer is formed that is connected to the channel layer.

7. The preparation method according to claim 6, wherein, During the removal of a portion of the functional layers, the second additional layer is removed, or the first additional layer and the second additional layer are removed.

8. The preparation method according to claim 1, wherein, After forming a channel layer within the channel hole where the functional layer is formed, the method further includes: A peripheral circuit semiconductor structure is connected on the side away from the substrate.

9. The preparation method according to claim 5, wherein, After forming a channel layer within the channel hole where the functional layer is formed, the method further includes: A gate line slot structure is formed extending through the stacked structure to the substrate, wherein the gate line slot structure comprises, from the outside to the inside, an insulating layer and a conductive layer; and During the process of exposing the channel layer by removing the stop layer and a portion of the functional layer, a portion of the insulating layer located on both sides of the conductive layer is removed.

10. A three-dimensional memory, characterized in that, include: First semiconductor layer; The second semiconductor layer is located on one side of the first semiconductor layer; A stacked structure is located on the side of the second semiconductor layer away from the first semiconductor layer; as well as A channel structure passes through the stacked structure and includes a functional layer and a channel layer arranged sequentially from the outside to the inside, wherein the end face of the channel layer near the first semiconductor layer and the end face of the functional layer near the first semiconductor layer are both recessed relative to the surface of the stacked structure near the first semiconductor layer. The second semiconductor layer includes an annular sidewall, the radial dimension of which is greater than the radial dimension of the channel structure located in the stacked structure and close to the second semiconductor layer.

11. The three-dimensional memory according to claim 10, wherein, The end face of the channel layer near the first semiconductor layer is located between the end face of the functional layer near the first semiconductor layer and the surface of the stacked structure near the first semiconductor layer.

12. The three-dimensional memory according to claim 10, wherein, Also includes: The third semiconductor layer is located on the side of the first semiconductor layer away from the stacked structure and is connected to the channel layer through the first semiconductor layer.

13. The three-dimensional memory according to claim 12, wherein, The third semiconductor layer includes a first part and a second part connected together. The first part is located on the side of the first semiconductor layer away from the stacked structure, and the second part passes through the first semiconductor layer and is connected to the channel layer.

14. The three-dimensional memory according to claim 13, further comprising: A first additional layer is located between the second part and the second semiconductor layer.

15. The three-dimensional memory according to claim 13, wherein, The second part has a recessed portion, the opening of which faces away from the channel layer.

16. The three-dimensional memory according to claim 13, wherein, The surface of the second part that is away from the stacked structure is flush with the surface of the first part that is away from the stacked structure.

17. The three-dimensional memory according to claim 12, wherein, The second semiconductor layer is made of the same material as the third semiconductor layer.

18. The three-dimensional memory according to claim 10, further comprising: The peripheral circuit semiconductor structure is located on the side of the stacked structure away from the first semiconductor layer.

19. The three-dimensional memory according to claim 10, wherein, The number of the channel structures is multiple, and the end face of each channel layer in the multiple channel structures that is close to the first semiconductor layer is flush.

20. A memory system, characterized in that, include: The three-dimensional memory as described in any one of claims 10 to 19; as well as A controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

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