Array substrate and its fabrication method, display panel

Abstract

This application provides an array substrate, a method for fabricating the same, and a display panel. The array substrate includes a substrate, a first protective layer, an active layer, a gate insulating layer, and a gate. The first protective layer is disposed on the substrate. The active layer is disposed on the side of the first protective layer away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. A second protective layer is disposed on the side of the gate away from the substrate. The first and second protective layers are in contact, such that the first and second protective layers together encapsulate the active layer, the gate insulating layer, and the gate, thereby preventing hydrogen from entering the active layer, the gate insulating layer, or the gate. The first and second protective layers of this array substrate can prevent hydrogen from being injected into the active layer and other structures, enabling the display panel using this array substrate to operate stably.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] Amorphous oxide thin-film transistors (SMTs) are widely used in array substrates due to their high mobility, good uniformity, excellent visible light transmittance, and low-temperature fabrication process. Amorphous oxide semiconductors, in particular, possess high carrier concentration and strong charge transport capabilities, making them effective active layers for driving thin-film transistor devices.

[0003] However, amorphous oxide semiconductors are sensitive to hydrogen. Hydrogen injection into the active layer can significantly negatively bias the threshold voltage of the amorphous oxide thin-film transistor, leading to increased current flow through the display panel mounted on the array substrate and potentially damaging the panel. Therefore, preventing hydrogen injection into the active layer is crucial for the proper functioning of the display panel. Summary of the Invention

[0004] This application provides an array substrate and its fabrication method, as well as a display panel. The first protective layer and the second protective layer of the array substrate can prevent hydrogen elements from being injected into structures such as the active layer, so that the display panel using the array substrate can operate stably.

[0005] This application provides an array substrate, including:

[0006] Substrate;

[0007] A first protective layer is disposed on the substrate;

[0008] An active layer is disposed on the side of the first protective layer away from the substrate;

[0009] A gate insulating layer, wherein the gate insulating layer is disposed on the side of the active layer away from the substrate;

[0010] A gate, the gate being disposed on the side of the gate insulating layer away from the substrate;

[0011] A second protective layer is disposed on the side of the gate away from the substrate and extends to the first protective layer, such that the first protective layer and the second protective layer together enclose the active layer, the gate insulating layer and the gate, to prevent hydrogen from entering the active layer, the gate insulating layer or the gate.

[0012] In some embodiments, the material of the first protective layer or the second protective layer comprises at least a dense metal oxide.

[0013] In some embodiments, the thickness of the first protective layer or the second protective layer is . to

[0014] In some embodiments, the orthographic projection of the active layer on the substrate lies within the orthographic projection of the first protective layer on the substrate.

[0015] This application also provides a method for fabricating an array substrate, comprising:

[0016] Provide a substrate;

[0017] A first protective layer is formed on the substrate;

[0018] An active layer is formed on the side of the first protective layer away from the substrate;

[0019] A gate insulating layer is formed on the side of the active layer away from the substrate;

[0020] A gate is formed on the side of the gate insulating layer away from the substrate;

[0021] A second protective layer is provided on the side of the gate away from the substrate, and the second protective layer extends to the first protective layer, such that the first protective layer and the second protective layer together enclose the active layer, the gate insulating layer and the gate, so as to prevent hydrogen from entering the active layer, the gate insulating layer or the gate.

[0022] In some embodiments, after forming an active layer on the side of the first protective layer away from the substrate, the first protective layer and the active layer are further etched using an etching acid.

[0023] In some embodiments, the etching acid is at least one of aluminic acid, oxalic acid acetate, and oxalic acid.

[0024] In some embodiments, a first protective layer is formed on the substrate, comprising:

[0025] A first target material is provided, wherein the first target material is made of aluminum;

[0026] Aluminum atoms sputtered from the first target are deposited on the substrate to form a first aluminum layer;

[0027] The first aluminum layer is oxidized to form a first protective layer.

[0028] In some embodiments, a second protective layer is provided on the side of the gate away from the substrate, including providing a second target material, wherein the material of the second target material is aluminum;

[0029] Aluminum atoms sputtered from the second target are deposited on the side of the gate away from the substrate to form a second aluminum layer;

[0030] The second aluminum layer is oxidized to form a second protective layer.

[0031] This application embodiment also provides a display panel, including an array substrate and a light-emitting layer disposed on the array substrate, wherein the array substrate is the array substrate described above or an array substrate prepared by the above-described array substrate preparation method.

[0032] The array substrate provided in this application includes a substrate, a first protective layer, an active layer, a gate insulating layer, a gate, and a second protective layer. The first and second protective layers are connected to jointly encapsulate the active layer, the gate insulating layer, and the gate, thereby preventing hydrogen from entering these structures. Therefore, by providing the first and second protective layers that jointly encapsulate the active layer, the gate insulating layer, and the gate in the array substrate, hydrogen can be prevented from being injected into the active layer and other structures, enabling the display panel using this array substrate to operate stably. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a first structure of a display panel provided in the embodiments of this application.

[0035] Figure 2 This is a schematic diagram of a first structure of an array substrate provided in an embodiment of this application.

[0036] Figure 3 This is a schematic diagram of a second structure of the array substrate provided in an embodiment of this application.

[0037] Figure 4 This is a process flow diagram of the array substrate provided in the embodiments of this application.

[0038] Figure 5 This is a schematic flowchart illustrating the fabrication method of the array substrate provided in an embodiment of this application.

[0039] Figure 6 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] With the technological advancements in Organic Light-Emitting Diode (OLED) and Light-Emitting Diode (LED) panels, the use of Indium Gallium Zinc Oxide (IGZO) as an active layer in display panels has become very popular.

[0042] Indium gallium zinc oxide (IGZO) exhibits lower leakage current and better mobility than a-Si (amorphous silicon), making it suitable as the active layer in top-gate devices for driving display panels. However, the technology for large-size display panels using IGZO as the active layer is not yet mature due to the poor reliability of flexible display panels. (See also...) Figure 1 , Figure 1 This is a schematic diagram of a first structure of a display panel provided in the embodiments of this application.

[0043] The display panel 10 includes a substrate 101, an array substrate 100, a light-emitting layer 200, and an encapsulation layer 300, which are sequentially stacked. The array substrate 100 includes at least one buffer layer. During the fabrication of the display panel 10, the substrate 101 and the buffer layer require a laser lift-off (LLO) process, which generates hydrogen. The encapsulation layer 300 is made of silicon nitride (SiN). x ), silicon dioxide (SiO) x Thin films made of materials such as SiNO or other similar materials can also generate hydrogen. However, the IGZO in the array substrate 100 is quite sensitive to hydrogen. When the current passing through the display panel 10, which is mounted on the array substrate 100, increases, it can damage the display panel 10. For example, during high-temperature and high-humidity reliability verification (RA), as time increases, hydrogen diffuses into the IGZO, causing the device to become electrically negatively biased, resulting in increased current and burn-out of the display panel 10. Therefore, preventing hydrogen injection into the active layer 103 is crucial for the proper operation of the display panel 10.

[0044] This application provides an array substrate 100 and its preparation method, and a display panel 10. The first protective layer 102 and the second protective layer 106 of the array substrate 100 can prevent hydrogen elements from being injected into structures such as the active layer 103, so that the display panel 10 using the array substrate 100 can operate stably.

[0045] Please see Figure 2 , Figure 2 This is a schematic diagram of a first structure of an array substrate provided in an embodiment of this application.

[0046] This application provides an array substrate 100, which includes a substrate 101, a first protective layer 102, an active layer 103, a gate insulating layer 104, a gate 105, and a second protective layer 106. The first protective layer 102 is disposed on the substrate 101. The active layer 103 is disposed on the side of the first protective layer 102 away from the substrate 101. The gate insulating layer 104 is disposed on the side of the active layer 103 away from the substrate 101. The gate 105 is disposed on the side of the gate insulating layer 104 away from the substrate 101. The second protective layer 106 is disposed on the side of the gate 105 away from the substrate 101. The second protective layer 106 extends to the first protective layer 102, such that the first protective layer 102 and the second protective layer 106 together enclose the active layer 103, the gate insulating layer 104, and the gate 105 to prevent hydrogen from entering the active layer 103, the gate insulating layer 104, and the gate 105.

[0047] Because a first protective layer 102 and a second protective layer 106 are provided in the array substrate 100 to jointly enclose the active layer 103, the gate insulating layer 104 and the gate 105, the first protective layer 102 and the second protective layer 106 can prevent hydrogen elements from being injected into the active layer 103 and other structures, so that the display panel 10 using the array substrate 100 can operate stably.

[0048] It is worth noting that the hydrogen element can be generated by other structures within the array substrate 100, or by external structures of the array substrate 100 or by the external environment. For example, water vapor in the air.

[0049] The substrate 101 can be divided into a rigid substrate and a flexible substrate. The rigid substrate can be a traditional glass substrate, and the flexible substrate can be a polyimide (PI) substrate. The preparation process of the flexible substrate 1 generally uses a glass substrate as a rigid substrate, prepares a flexible substrate on the glass substrate, and then separates the flexible substrate from the glass substrate to finally obtain the flexible substrate.

[0050] The active layer 103 can be made of at least one of ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide). In this embodiment, the active layer 103 is made of IGZO.

[0051] The material of the first protective layer 102 or the second protective layer 106 may include a dense metal oxide, such as Al2O3 (aluminum oxide), TiO2 (titanium dioxide), or Cr2O3 (chromium oxide). Taking Al2O3 as an example, since aluminum is an active metal, it begins to oxidize upon contact with oxygen in the air at room temperature, forming an aluminum oxide film. Because aluminum oxide is relatively dense, the oxidation process stops when the thickness reaches a certain level (micrometer level), and the aluminum oxide layer formed on the surface becomes the protective layer. Based on the dense nature of aluminum oxide, using aluminum oxide as the material of the first protective layer 102 or the second protective layer 106 can achieve a hydrogen blocking rate of over 85%, effectively preventing hydrogen from further injecting into the internal structure of the array substrate 100, such as the active layer 103. Understandably, since a dense layer of aluminum oxide readily forms on the surface of aluminum, the first protective layer 102 or the second protective layer 106 can be fabricated by sputtering, physical vapor deposition, or other processes, placing aluminum above or below the active layer 103, the gate insulating layer 104, and the gate 105. The aluminum rapidly oxidizes with oxygen in the air, forming a dense layer of aluminum oxide on its surface. The thickness of the first protective layer 102 or the second protective layer 106 is... to

[0052] In some embodiments, the orthographic projection of the active layer 103 onto the substrate 101 lies within the orthographic projection of the first protective layer 102 onto the substrate 101. When the thin-film transistors in the array substrate 100 are top-gate structures, the gate insulating layer 104 is disposed on the side of the active layer 103 away from the substrate 101, and the orthographic projection of the gate insulating layer 104 onto the substrate 101 lies within the orthographic projection of the active layer 103 onto the substrate 101; the gate 105 is disposed on the side of the gate insulating layer 104 away from the substrate 101, and the orthographic projection of the gate 105 onto the substrate 101 lies within the orthographic projection of the gate insulating layer 104 onto the substrate 101. That is, from the substrate 101 to the gate 105, the areas of the orthographic projections of the first protective layer 102, the active layer 103, the gate insulating layer 104, and the gate 105 onto the substrate 101 gradually decrease. When the second protective layer 106 is disposed on the side of the gate 105 away from the substrate 101, the second protective layer 106 can be sequentially attached to the gate 105, the gate insulating layer 104, the active layer 103, and the first protective layer 102. That is, when the first protective layer 102 is disposed on the side of the gate 105 away from the substrate 101, no gap will be generated between the second protective layer 106 and the gate 105, the gate insulating layer 104, the active layer 103, and the first protective layer 102. On the one hand, this is beneficial to reduce the volume of the array substrate 100, and on the other hand, it is beneficial to prevent hydrogen in the air from diffusing into the active layer 103 when air enters the gap.

[0053] The array substrate 100 further includes a light-shielding (LS) layer 107, a first buffer layer 108, and a second buffer layer 109 sequentially disposed therefrom. The light-shielding layer 107, the first buffer layer 108, and the second buffer layer 109 are disposed between the substrate 101 and the first protective layer 102. Optionally, the light-shielding layer 107 is disposed on the substrate 101, the first buffer layer 108 is disposed on the side of the light-shielding layer 107 away from the substrate 101, and the second buffer layer 109 is disposed on the side of the first buffer layer 108 away from the substrate 101. Optionally, the light-shielding layer 107 can be one or more of copper (Cu) and molybdenum-titanium alloy (MoTi). When the light-shielding layer 107 has a multilayer structure, that is, the light-shielding layer 107 includes a first sub-light-shielding layer and a second sub-light-shielding layer, the first sub-light-shielding layer is made of molybdenum-titanium alloy and is disposed on the substrate 101, and the second sub-light-shielding layer is made of copper and is disposed on the side of the first sub-light-shielding layer away from the substrate 101. Optionally, the first buffer layer 108 is made of silicon nitride (SiN). x The material of the second buffer layer 109 is silicon dioxide (SiO2). x ).

[0054] The first buffer layer 108 can be prepared using plasma-enhanced chemical vapor deposition (PECVD). This first buffer layer 108 is typically prepared by reacting nitrogen (N2) and silane (SiH4) with hydrogen (H2) and nitrogen (N2) as diluent gases. Therefore, the silicon nitride in this first buffer layer 108 is not stoichiometric Si3N4, but rather amorphous silicon nitride containing a certain amount of hydrogen; strictly speaking, it should be called hydrogenated silicon nitride, usually written as SiN. x :H, or abbreviated as SiN x .

[0055] Table 1

[0056] <![CDATA[E g ]]> band gap 5.3eV <![CDATA[E b ]]> Breakdown strength 1000V / μm H％ Hydrogen concentration (atomic ratio) ＜25％ εr Relative permittivity 6.5～7.5 n Refractive index 1.9～2.05 ρ Resistivity (at 300K) <![CDATA[10 12 Ohm]]>

[0057] Please refer to Table 1, which shows typical characteristic parameters of device-grade silicon nitride. As shown in Table 1, this silicon nitride has a certain hydrogen content. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of a second structure of the array substrate provided in an embodiment of this application. When the material of the first buffer layer 108 is silicon nitride and there is no first protective layer 102, hydrogen elements in the silicon nitride may diffuse into the active layer 103. Please refer to the embodiments in this application. Figure 2 In order to prevent hydrogen from diffusing into the active layer 103 in silicon nitride, a first protective layer 102 is provided between the first buffer layer 108 and the active layer 103. The first protective layer 102 can prevent hydrogen from diffusing into the active layer 103 in the first buffer layer 108.

[0058] The second buffer layer 109 can be formed using a high-temperature silicon oxidation process. Similar to the preparation of silicon nitride, silicon oxide is also prepared using plasma-enhanced chemical vapor deposition. Silicon oxide is generally prepared by reacting nitrous oxide (N₂O) with silane, and is an amorphous hydrogen-containing silicon oxide (SiOx:H), usually abbreviated as SiOx.

[0059] Table 2

[0060] <![CDATA[E g ]]> band gap 9.0 eV <![CDATA[E b ]]> Breakdown strength 1000V / μm H％ Hydrogen concentration (atomic ratio) ＜5％ εr Relative permittivity Approximately 3.9 n Refractive index 1.46 ρ Resistivity (at 300K) <![CDATA[10 12 ~10 14 Ohm]]>

[0061] Please refer to Table 2, which shows the typical characteristic parameters of device-grade silicon oxide. As shown in Table 2, this silicon oxide has a certain hydrogen content. Please continue reading... Figure 3 Therefore, when the material of the second buffer layer 109 is silicon oxide, if there is no first protective layer 102, the second buffer layer 109 will directly contact the active layer 103, and the hydrogen element in the silicon oxide is very likely to diffuse into the active layer 103. Please refer to the embodiments in this application. Figure 2After a first protective layer 102 is provided between the second buffer layer 109 and the active layer 103, the first protective layer 102 can prevent hydrogen from the second buffer layer 109 from diffusing into the active layer 103.

[0062] The array substrate 100 further includes an interlayer dielectric layer 112 (ILD), which is disposed on the side of the second protective layer 106 away from the substrate 101. The interlayer dielectric layer 112 has a first via 1121 and a second via 1122. The array substrate 100 also includes a source 110 (S) and a drain 111 (D), which are disposed on the interlayer dielectric layer 112. The source 110 is connected to the active layer 103 through the first via 1121, and the drain 111 is connected to the active layer 103 through the second via 1122.

[0063] The array substrate 100 further includes a passivation (PV) layer 113 and a pad 114. The passivation layer 113 is disposed on the side of the source 110, drain 111, and interlayer dielectric layer 112 away from the substrate 101. A third via 1131 is provided on the passivation layer 113, and the pad 114 is disposed on the side of the passivation layer 113 away from the substrate 101. The pad 114 is connected to the drain 111 through the third via 1131. The material of the pad 114 includes Cu / Mo, Cu / MoTi, or Mo / Al / Mo composite materials or other metallic materials.

[0064] The array substrate 100 also includes a planarization layer 115 and a pixel electrode 116 disposed on the side of the planarization layer 115 away from the substrate 101. The planarization layer 115 is disposed on the side of the pad 114 and the passivation layer 113 away from the substrate 101. A fourth via 1151 is disposed on the planarization layer 115. The pixel electrode 116 is disposed on the side of the planarization layer 115 away from the substrate 101. The pixel electrode 116 is connected to the pad 114 through the fourth via 1151.

[0065] The array substrate 100 also includes pixel bank pillars 117, which are disposed on the side of the pixel electrode 116 and the planarization layer 115 away from the substrate 101 to reduce light leakage between pixels in the light-emitting layer 200. The gaps between the plurality of bank pillars 117 form isolation holes 1171, which can be used to fill the light-emitting layer 200.

[0066] Please see Figure 4 as well as Figure 5 , Figure 4 This is a process flow diagram of the array substrate provided in the embodiments of this application. Figure 5 This is a schematic flowchart illustrating the fabrication method of the array substrate provided in an embodiment of this application.

[0067] This application also provides a method for fabricating an array substrate 100, which can at least fabricate the array substrate 100 in the above embodiments. The specific method for fabricating the array substrate 100 is as follows.

[0068] Step S1: Provide a substrate 101.

[0069] The substrate 101 can be divided into a rigid substrate and a flexible substrate. The rigid substrate can be a traditional glass substrate, and the flexible substrate can be a polyimide (PI) substrate. The preparation process of the flexible substrate generally uses a glass substrate as a rigid substrate, prepares the flexible substrate on the glass substrate, and then separates the flexible substrate from the glass substrate to finally obtain the flexible substrate.

[0070] Step S2: Form a first protective layer 102 on the substrate 101.

[0071] Step S3: An active layer 103 is formed on the side of the first protective layer 102 away from the substrate 101.

[0072] An active layer 103 can be formed on the side of the first protective layer 102 away from the substrate 101 using a first photomask. The active layer 103 can be made of at least one of ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide). In this embodiment, the active layer 103 is made of IGZO.

[0073] Step S4: Form a gate insulating layer 104 on the side of the active layer 103 away from the substrate 101.

[0074] In this process, a second photomask can be used to form a gate insulating layer 104 on the side of the active layer 103 away from the substrate 101.

[0075] Step S5: Form a gate 105 on the side of the gate insulating layer 104 away from the substrate 101.

[0076] The gate 105 includes a first gate layer and a second gate layer. Optionally, the first gate layer is made of molybdenum-titanium alloy, and the second gate layer is made of copper. The step of forming the gate 105 on the side of the gate insulating layer 104 away from the substrate 101 is described in the method for fabricating the array substrate 100, which includes forming the first gate layer on the side of the gate insulating layer 104 away from the substrate 101, and forming the second gate layer on the side of the first gate layer away from the substrate 101. Then, the gate 105 and the gate insulating layer 104 are patterned using a PHO / WET / Dry process.

[0077] Step S6: A second protective layer 106 is provided on the side of the gate 105 away from the substrate 101, and the second protective layer 106 is extended to the first protective layer 102, so that the first protective layer 102 and the second protective layer 106 together wrap the active layer 103, the gate insulating layer 104 and the gate 105 to prevent hydrogen from entering the active layer 103, the gate insulating layer 104 or the gate 105.

[0078] The material of the first protective layer 102 or the second protective layer 106 may include a dense metal oxide, such as Al2O3 (aluminum oxide), TiO2 (titanium dioxide), or Cr2O3 (chromium oxide). Taking Al2O3 as an example, since aluminum is an active metal, it begins to oxidize upon contact with oxygen in the air at room temperature, forming an aluminum oxide film. Because aluminum oxide is relatively dense, the oxidation process stops when the thickness reaches a certain level (micrometer level), and the aluminum oxide layer formed on the surface becomes the protective layer. Based on the dense nature of aluminum oxide, using an aluminum oxide layer as the material of the first protective layer 102 or the second protective layer 106 can effectively prevent hydrogen from being further injected into the internal structure of the array substrate 100, such as the active layer 103. Understandably, since a dense aluminum oxide layer can easily form on the surface of aluminum, the first protective layer 102 or the second protective layer 106 can be formed by sputtering, physical vapor deposition, or other processes, placing aluminum above or below the active layer 103, the gate insulating layer 104, and the gate 105. The aluminum rapidly oxidizes with oxygen in the air, forming a dense aluminum oxide layer on its surface. The thickness of the first protective layer 102 or the second protective layer 106 is... to

[0079] In some embodiments, after forming an active layer 103 on the side of the first protective layer 102 away from the substrate 101, the method for fabricating the array substrate 100 further includes etching the first protective layer 102 and the active layer 103 with an etching acid. The etching acid is at least one of aluminic acid, oxalic acid acetate, and oxalic acid.

[0080] It is understandable that, since the first protective layer 102 comprises at least a metal oxide, and taking the material of the first protective layer 102 as aluminum oxide, the material of the active layer 103 as IGZO, and the etching acid as aluminic acid as an example, the aluminic acid can etch both the first protective layer 102 and the active layer 103. Furthermore, the etching rate of the aluminic acid on the active layer 103 is faster than that on the first protective layer 102. Therefore, when the etching of both the active layer 103 and the first protective layer 102 by the aluminic acid is complete, the orthographic projection of the active layer 103 onto the substrate 101 lies within the orthographic projection of the first protective layer 102 onto the substrate 101. In subsequent steps, a second protective layer 106 is provided on the side of the active layer 103 away from the first protective layer 102. The second protective layer 106 can be sequentially attached to the active layer 103 and the first protective layer 102. That is, when the first protective layer 102 is provided on the side of the active layer 103 away from the first protective layer 102, no gap will be generated between the second protective layer 106 and the active layer 103 and the first protective layer 102. This is beneficial to reducing the volume of the array substrate 100 and to reducing the diffusion of hydrogen from the air to the active layer 103 when air enters the gap.

[0081] In some embodiments, the step of forming a first protective layer 102 on a substrate 101 is described in the method for fabricating the array substrate 100, which includes providing a first target material, the material of which is aluminum; depositing aluminum atoms sputtered from the first target material on the substrate 101 to form a first aluminum layer; and oxidizing the first aluminum layer to form the first protective layer 102.

[0082] The step of forming the first protective layer 102 on the substrate 101 is a sputtering process, which is a type of physical vapor deposition. Sputtering is a thin film deposition method in which charged particles in a high vacuum (around 50 Pa) are given high energy by an excitation source and bombarded with the surface of a target material, so that the components (atoms or molecules) on the target surface gain enough energy to be sputtered and landed on the surface of another medium.

[0083] The oxidation process of the first aluminum layer can be either natural oxidation in the air or oxidation in a space with a high oxygen content (higher than the oxygen content in the air).

[0084] In some embodiments, the step of forming a second protective layer 106 on the side of the gate 105 away from the substrate 101 is described in the method for fabricating the array substrate 100, which includes providing a second target material made of aluminum; depositing aluminum atoms sputtered from the second target material on the side of the gate 105 away from the substrate 101 to form a second aluminum layer; and oxidizing the second aluminum layer to form the second protective layer 106.

[0085] The oxidation process of the second aluminum layer can be either natural oxidation in the air or oxidation in a space with a high oxygen content (higher than the oxygen content in the air).

[0086] In some embodiments, after providing a substrate 101, the method for fabricating the array substrate 100 further includes depositing a light-shielding layer 107 on the substrate 101, then etching the light-shielding layer 107 to form a pattern of the light-shielding layer 107; depositing a first buffer layer 108 on the side of the light-shielding layer 107 away from the substrate 101; depositing a second buffer layer 109 on the side of the first buffer layer 108 away from the substrate 101; the first buffer layer 108 is made of silicon nitride, and the second buffer layer 109 is made of silicon oxide. Then, a first protective layer 102 is deposited on the side of the second buffer layer 109 away from the substrate 101, followed by subsequent steps.

[0087] In the step of etching the light-shielding layer 107, the array substrate 100 can be prepared by selectively etching the light-shielding layer 107 using a third photomask to form a pattern of the light-shielding layer 107.

[0088] The light-shielding layer 107 includes a first sub-light-shielding layer and a second sub-light-shielding layer. Optionally, the material of the first sub-light-shielding layer is a molybdenum-titanium alloy, and the material of the second sub-light-shielding layer is copper. The step of depositing the light-shielding layer 107 on the substrate 101, and the method for fabricating the array substrate 100, includes forming a first sub-light-shielding layer on the substrate 101 and forming a second sub-light-shielding layer on the side of the first sub-light-shielding layer away from the substrate 101.

[0089] The deposition method for the first buffer layer 108 and the second buffer layer 109 is chemical vapor deposition (CVD). The first buffer layer 108 is formed by chemical vapor deposition on the substrate 101, and the thickness of the first buffer layer 108 is [missing information]. to A second buffer layer 109 is formed by chemical vapor deposition on the side of the first buffer layer 108 away from the substrate 101, the thickness of which is [missing information]. to

[0090] In some embodiments, after a second protective layer 106 is formed on the side of the gate 105 away from the substrate 101, the method for fabricating the array substrate 100 further includes forming an interlayer dielectric layer 112 on the side of the second protective layer 106 away from the substrate 101, and forming a first via 1121 and a second via 1122 on the interlayer dielectric layer 112.

[0091] The step of forming a first via 1121 and a second via 1122 on the interlayer dielectric layer 112 is part of the fabrication method of the array substrate 100, which includes forming the first via 1121 and the second via 1122 on the interlayer dielectric layer 112 using a fourth photomask and a fifth photomask and a PHO / Dry process.

[0092] In some embodiments, after forming a first via 1121 and a second via 1122 on the interlayer dielectric layer 112, the method for fabricating the array substrate 100 includes disposing a source electrode 110 and a drain electrode 111 on the side of the interlayer dielectric layer 112 away from the substrate 101. The source electrode 110 is connected to the active layer 103 through the first via 1121, and the drain electrode 111 is connected to the active layer 103 through the second via 1122. Optionally, a sixth photomask is used to dispose of the source electrode 110 and the drain electrode 111 on the side of the interlayer dielectric layer 112 away from the substrate 101.

[0093] In some embodiments, after the source 110 and drain 111 are disposed on the side of the interlayer dielectric layer 112 away from the substrate 101, the method for fabricating the array substrate 100 further includes disposing a passivation layer 113 on the source 110, drain 111 and the side of the interlayer dielectric layer 112 away from the substrate 101, and forming a third via 1131 on the passivation layer 113.

[0094] The method for fabricating the array substrate 100 includes forming a third via 1131 on the passivation layer 113, and further includes patterning the passivation layer 113 using a seventh photomask to form the third via 1131 on the passivation layer 113.

[0095] In some embodiments, a pad 114 is provided on the side of the passivation layer 113 away from the substrate 101, and the pad 114 is connected to the drain 111 through a third via 1131. The material of the pad 114 can be a composite material of MoTi, Cu / Mo, Cu / MoTi, or Mo / Al / Mo, or other metallic materials. Optionally, an eighth photomask is used to provide the pad 114 on the side of the passivation layer 113 away from the substrate 101.

[0096] In some embodiments, after a pad 114 is provided on the side of the passivation layer 113 away from the substrate 101, the method for fabricating the array substrate 100 further includes providing a planarization layer 115 on the side of the pad 114 and the passivation layer 113 away from the substrate 101, and forming a fourth via 1151 on the planarization layer 115.

[0097] The method for fabricating the array substrate 100 includes forming a fourth via 1151 on the planarization layer 115, and further includes patterning the planarization layer 115 using a ninth photomask to form the fourth via 1151 on the planarization layer 115.

[0098] In some embodiments, after a planarization layer 115 is formed on the side of the pad 114 and passivation layer 113 away from the substrate 101, the method for fabricating the array substrate 100 further includes forming a pixel electrode 116 on the side of the planarization layer 115 away from the substrate 101, the pixel electrode 116 being connected to the pad 114 through a fourth via 1151. Optionally, a tenth photomask is used to form the pad 114 on the side of the passivation layer 113 away from the substrate 101.

[0099] In some embodiments, after the pixel electrode 116 is disposed on the side of the planarization layer 115 away from the substrate 101, the method for fabricating the array substrate 100 further includes disposing of a plurality of isolation pillars 117 on the side of the pixel electrode 116 and the planarization layer 115 away from the substrate 101, the gaps between the plurality of isolation pillars 117 forming isolation holes 1171, which can be used to fill the light-emitting layer 200. Optionally, an eleventh photomask is used to dispose of a plurality of isolation pillars 117 on the side of the pixel electrode 116 and the planarization layer 115 away from the substrate 101.

[0100] This application also provides a display panel 10, please refer to... Figure 6 , Figure 6 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application.

[0101] The display panel 10 includes an array substrate 100 and a light-emitting layer 200 (EL) disposed on the array substrate. The array substrate 100 can be the array substrate 100 in the above embodiments, or it can be an array substrate 100 prepared by the preparation method of the array substrate 100 in the above embodiments. The light-emitting layer 200 is electrically connected to the pixel electrode 116 to achieve light emission.

[0102] Please continue reading. Figure 6 The display panel 10 also includes an encapsulation layer 300, which is disposed on the side of the light-emitting layer 200 (EL) away from the substrate 101. The encapsulation layer 300 can be fabricated using thin-film encapsulation (TFE) technology. The material of the encapsulation layer 300 is one or more of silicon nitride (SiNx), silicon oxide (SiOx), and SiNO. As mentioned above, silicon nitride (SiNx), silicon oxide (SiOx), and SiNO have a certain hydrogen content, so when the material of the encapsulation layer 300 is silicon nitride, hydrogen elements in the silicon nitride may diffuse into the active layer 103. In this embodiment, to prevent hydrogen elements in the silicon nitride from diffusing into the active layer 103, a second protective layer 106 is provided between the encapsulation layer 300 and the active layer 103. This second protective layer 106 can prevent hydrogen elements in the encapsulation layer 300 from diffusing into the active layer 103.

[0103] This application also provides a method for manufacturing a display panel 10, which further includes providing an array substrate 100; forming a light-emitting layer 200 on the array substrate 100, the light-emitting layer 200 being electrically connected to a pixel electrode 116; and forming an encapsulation layer 300 on the side of the light-emitting layer 200 away from the array substrate 100.

[0104] The array substrate 100 provided in this embodiment includes a substrate 101, a first protective layer 102, an active layer 103, a gate insulating layer 104, a gate 105, and a second protective layer 106. The first protective layer 102 and the second protective layer 106 are connected to jointly enclose the active layer 103, the gate insulating layer 104, and the gate 105, thereby preventing hydrogen from entering the active layer 103, the gate insulating layer 104, and the gate 105. Therefore, because the first protective layer 102 and the second protective layer 106 are provided in the array substrate 100 to jointly enclose the active layer 103, the gate insulating layer 104, and the gate 105, the first protective layer 102 and the second protective layer 106 can prevent hydrogen from being injected into the active layer 103 and other structures, enabling the display panel 10 using the array substrate 100 to operate stably.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0106] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0107] The array substrate, its fabrication method, and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized by, The application relates to a thin film transistor, which comprises the following parts: a substrate; a first protective layer arranged on the substrate, the material of the first protective layer comprising aluminum oxide; an active layer arranged on the side of the first protective layer away from the substrate, the material of the active layer comprising indium gallium zinc oxide; a gate insulating layer arranged on the side of the active layer away from the substrate; a gate arranged on the side of the gate insulating layer away from the substrate; a second protective layer arranged on the side of the gate away from the substrate, the second protective layer extending to the first protective layer, so that the first protective layer and the second protective layer jointly wrap the active layer, the gate insulating layer and the gate to prevent hydrogen from entering the active layer, the gate insulating layer or the gate; wherein the orthographic projection of the active layer on the substrate is located in the orthographic projection of the first protective layer on the substrate; wherein the areas of the orthographic projections of the first protective layer, the active layer, the gate insulating layer and the gate on the substrate gradually decrease, and the second protective layer is arranged in close contact with the gate, the gate insulating layer, the active layer and the first protective layer in sequence.

2. The array substrate of claim 1, wherein, The material of the first protective layer or the second protective layer at least comprises dense metal oxide.

3. The array substrate of claim 1, wherein, The thickness of the first protective layer or the second protective layer is 100-1000 angstrom.

4. A method for fabricating an array substrate, characterized in that, The application relates to a method for manufacturing a thin film transistor, which comprises the following steps: providing a substrate; forming a first protective layer on the substrate, the material of the first protective layer comprising aluminum oxide; forming an active layer on the side of the first protective layer away from the substrate, the material of the active layer comprising indium gallium zinc oxide, and the orthographic projection of the active layer on the substrate being located in the orthographic projection of the first protective layer on the substrate; forming a gate insulating layer on the side of the active layer away from the substrate; forming a gate on the side of the gate insulating layer away from the substrate; arranging a second protective layer on the side of the gate away from the substrate, and extending the second protective layer to the first protective layer, so that the first protective layer and the second protective layer jointly wrap the active layer, the gate insulating layer and the gate to prevent hydrogen from entering the active layer, the gate insulating layer or the gate; wherein the areas of the orthographic projections of the first protective layer, the active layer, the gate insulating layer and the gate on the substrate gradually decrease, and the second protective layer is arranged in close contact with the gate, the gate insulating layer, the active layer and the first protective layer in sequence.

5. The method of manufacturing an array substrate according to claim 4, wherein In the step of forming the active layer on the side of the first protective layer away from the substrate, the first protective layer and the active layer are formed by etching with etching acid.

6. The method of manufacturing an array substrate according to claim 5, wherein The etching acid is at least one of aluminate acid, acetic acid, oxalic acid and oxalic acid.

7. The method of manufacturing an array substrate according to claim 4, wherein The step of forming the first protective layer on the substrate comprises the following steps: providing a first target material, the material of the first target material being aluminum; depositing aluminum atoms sputtered from the first target material on the substrate to form a first aluminum layer; oxidizing the first aluminum layer to form the first protective layer.

8. The method of manufacturing an array substrate according to claim 4, wherein A second protective layer is provided on the side of the gate electrode away from the substrate, comprising A second target material is provided, the material of the second target material being aluminum; Aluminum atoms sputtered from the second target material are deposited on the side of the gate electrode away from the substrate to form a second aluminum layer; The second aluminum layer is oxidized to form a second protective layer.

9. A display panel, characterized by, An array substrate and a light emitting layer provided on the array substrate, the array substrate being the array substrate of any one of claims 1 to 3 or being prepared by the preparation method of any one of claims 4 to 8.

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