A high power density gallium nitride high electron mobility transistor and manufacturing method

Abstract

The present invention discloses a high-power-density gallium nitride high electron mobility transistor and a manufacturing method thereof, wherein the transistor comprises a plurality of gate power cells, a plurality of pairs of gate power cells form a power unit, metal connections are used between gate islands of the gate power cells, and the gate ends of two adjacent power units are resistively isolated, and a plurality of power units are connected in parallel. In the present invention, the gate power cell structure is optimized, and a plurality of gate power cell structures are connected in parallel to form a power unit. On a gate bar with a gate length of 0.25 microns, after connecting the power units in parallel, a GaN transistor with a large gate width and high density with low parasitic effects is finally designed, realizing a high-power tube core of 120 watts that can be used in the X-band, effectively solving the contradiction between the operating voltage and the on-resistance, comprehensively improving the output power and conversion efficiency of the device, having a positive significance for improving the characteristic frequency of the device, and promoting the development of transistors in the direction of high frequency, high power and broadband.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a high-power density gallium nitride high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] The RF field is an industry with a high penetration rate of gallium nitride (GaN) and great future development prospects, especially for base station construction and transformation. Since the heat dissipation and power characteristics of GaN materials can better meet the requirements of 5G base stations, and with the decline in the cost of GaN devices and the maturity of the process, GaN materials will become the mainstream material for base station PAs. At the same time, in the base station field, millimeter waves, small base stations, Massive MIMO, wave shaping, carrier aggregation and other needs all require the use of GaN-related devices. With the advancement of these new 5G technologies, the proportion of GaN in semiconductor devices used in the entire base station is also increasing.

[0003] GaN HEMT has the advantages of high breakdown voltage, high power density and high power added efficiency. Multi-cell power synthesis technology can improve the input and output impedance characteristics of GaN HEMT devices, solve the impedance matching problem of large gate width devices when designing power amplifiers, and increase the output power of the device.

[0004] GaN HEMT has a higher two-dimensional electron gas concentration, ns>1E13 / cm 2 , two-dimensional electron gas can be caused by polarization and surface states, and the barrier layer does not need to be doped, which can achieve high concentration, high mobility, and no need for bias maintenance, such as Figure 1 shown.

[0005] When 2DEG exists, when the drain-source voltage Vds>0 is applied, a drain-source current Ids flows. Since the gate-source voltage Vgs can adjust the concentration of 2DEG, Ids can be controlled. For general GaN HEMT, Vt<0, it is a normally-on device and requires a negative gate voltage to turn off the drain current. A small change in Vgs can cause a large change in Ids, thereby realizing the signal amplification of the output current Ids to the input voltage Vgs, such as Figure 2 shown.

[0006] Usually, GaN HEMT devices have a large current collapse effect, which is caused by the hot electron injection and capture effect in the buffer layer. The surface of the gate-drain channel access region will trap and capture electrons, causing the AlGaN surface energy band in this region to rise, resulting in a virtual gate model ( Figure 3 ), resulting in device degradation and damage. Usually, in terms of physical structure, current collapse is suppressed by increasing the gate-drain distance and using field plates to reduce the channel electric field, reduce its ability to capture hot electrons, and reduce the electrostatic induction effect of the captured hot electrons. Summary of the invention

[0007] In order to solve the technical problems existing in the prior art, the object of the present invention is to provide a high power density gallium nitride high electron mobility transistor and a manufacturing method thereof.

[0008] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0009] A high-power-density gallium nitride high-electron-mobility transistor includes a plurality of gate power cells. Multiple pairs of gate power cells form a power unit to ground. The gate islands of the gate power cells are connected by metal. The gate ends of two adjacent power cells are isolated by resistance. The multiple power cells are connected in parallel.

[0010] Furthermore, every four pairs of the gate power cells form a ground-facing power unit, each ground-facing power unit integrates eight gate fingers, and the four pairs of gate power cells include eight gate islands in total.

[0011] Furthermore, the gate terminals of two adjacent power units are isolated by using a resistor of 8-12 ohms.

[0012] Furthermore, the gate power cell is made on the epitaxial layer of the GaN structure, and the gate power cell includes a silicon nitride thin film structure, a drain electrode, a source electrode, a T-shaped metal low-resistance gate, a metal 0 layer, a field plate, a metal 1 field plate, a metal 1 layer and a metal 2 layer arranged on the epitaxial layer. The GaN structure includes a silicon substrate and an epitaxial layer, and the epitaxial layer includes a GaN layer and an Al-GaN layer.

[0013] Furthermore, the silicon nitride film structure includes four layers of a first silicon nitride film, a second silicon nitride film, a third silicon nitride film and a fourth silicon nitride film, a drain electrode, a source electrode, a T-shaped metal low-resistance gate and a first silicon nitride film are arranged on the upper surface of the Al-GaN layer, a source electrode is arranged between two adjacent drain electrodes, a first silicon nitride film is arranged between the drain electrode and the source electrode, and two ends of the first silicon nitride film located between the drain electrode and the source electrode extend toward the drain electrode and the source electrode respectively and ride on the drain electrode and the source electrode respectively. On the electrode, a second silicon nitride film is arranged on the first silicon nitride film and a T-shaped metal low-resistance gate is arranged between the two, the T-shaped head of the T-shaped metal low-resistance gate rides on the first silicon nitride film, the T-shaped metal low-resistance gate passes through the first silicon nitride film and is arranged on the Al-GaN layer, a third silicon nitride film is arranged on the second silicon nitride film and a field plate is arranged between the two, a metal 1 field plate and a fourth silicon nitride film are arranged on the third silicon nitride film, a metal 0 layer is arranged on the drain electrode, a metal 0 layer is arranged on the source electrode, and a metal 0 layer is arranged on the metal 0 layer There is a metal 1 layer, the metal 1 layer is connected to the metal 0 layer to form an electrode, the metal 1 field plate is located above the metal 0 layer, a third silicon nitride film is arranged between the metal 1 field plate and the metal 1 layer, the metal 1 field plate is in contact with the metal 0 layer and the third silicon nitride film below, the first silicon nitride film located between the drain electrode and the source electrode and the two ends of the second silicon nitride film directly above the first silicon nitride film are in contact with the metal 0 layer respectively, and one end of the third silicon nitride film located directly above the second silicon nitride film is in contact with the metal 1 layer, The other end of the third silicon nitride film is in contact with the metal 0 layer, a fourth silicon nitride film is arranged on the third silicon nitride film and a metal 1 field plate is arranged between the two, a metal 2 layer is arranged at both ends and above the fourth silicon nitride film, the metal 2 layer at both ends of the fourth silicon nitride film is deep into the metal 1 layer, the metal 2 layer is connected to the metal 1 layer to form an electrode, a silicon nitride passivation film is arranged above the metal 2 layer, a polyimide passivation layer is arranged above the silicon nitride passivation film, and the middle part of the fourth silicon nitride film is not in contact with the metal 2 layer, and is connected through an air bridge.

[0014] Furthermore, the metal 0 layer uses 0.6 micron gold.

[0015] Furthermore, the metal layer 1 is made of 1.1 micron gold.

[0016] Furthermore, the metal 2 layer is made of 4 microns of gold.

[0017] A method for manufacturing a high power density gallium nitride high electron mobility transistor comprises the following steps:

[0018] 1) First, a silicon substrate is selected, and a GaN layer and an Al-GaN layer of appropriate thickness are formed on the silicon substrate. The area where an ohmic contact is required is photolithographically carved out on the Al-GaN layer, and metal deposition for the ohmic contact is performed. Then, a lift-off stripping process is used to form a contact area between a drain electrode and a source electrode and the Al-GaN layer, and then a metal alloy process is performed to form an ohmic contact layer of the source and drain regions;

[0019] 2) Make the active area

[0020] Photolithography to form the active area, followed by multiple ion implantations to isolate the device;

[0021] 3) depositing a first silicon nitride film, performing photolithography, etching an ohmic contact area, and using the first silicon nitride film for surface protection in other areas;

[0022] 4) Formation of T-shaped metal low-resistance gate

[0023] Photolithography, etching the first silicon nitride film to form a groove with a line width of 0.25 microns, the bottom of the groove is in direct contact with the Al-GaN layer, metal deposition is performed at the groove, photolithography, and stripping is performed to form a T-shaped metal low-resistance gate;

[0024] 5) Deposition of a second silicon nitride film, photolithography, etching of an ohmic contact area, and use of a second silicon nitride film for surface protection of other areas;

[0025] 6) Photolithography, 0.6 micron gold is deposited on the drain electrode and source electrode to form a metal 0 layer, and then peeled off;

[0026] 7) Photolithography, metal TaN deposition, stripping, forming 8-12 ohm TaN thin film resistor;

[0027] 8) Photolithography, deposition of thin metal layers, formation of field plates, and stripping;

[0028] 9) Photolithography, gold 1.1 microns are deposited on the metal 0 layer to form a metal 1 layer, the metal 1 layer is connected to the metal 0 layer, a third silicon nitride film is deposited, photolithography is performed, and etching is performed to the metal 1 layer; a lift-off process is used to form a metal 1 field plate;

[0029] 10) Photoresist spin coating process forms the bridge bottom;

[0030] 11) Deposition of the fourth silicon nitride film; photolithography, deposition of the metal 2 layer, stripping, connection between the metal 1 layer and the metal 2 layer, removal of the photoresist at the bottom of the bridge formed by the photoresist spin coating process, and formation of an air bridge;

[0031] 12) Surface passivation

[0032] Deposition forms a silicon nitride passivation film, spin coating forms a polyimide passivation layer, photolithography, and etching out leads;

[0033] 13) Back side process

[0034] Thinning, photolithography back holes, plasma etching holes, 5 micron metal electroplating on the back, and then photolithography and etching process to carve out the scribe lines.

[0035] Furthermore, the deposition thickness of the first silicon nitride film is 50 nm, the deposition thickness of the second silicon nitride film is 100 nm, and the deposition thickness of the third silicon nitride film is 80 nm.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. By using the T-shaped metal low-resistance gate and the layout of multiple metal field plates, the gate power cell structure is optimized, and then multiple gate power cell structures are connected in parallel to form a power unit. On the gate bar with a gate length of 0.25 microns, the power units are connected in parallel, and finally a GaN transistor with a large gate width and high density with low parasitic effects is designed, realizing a high-power tube core of 120 watts that can be used in the X-band.

[0038] 2. Through the coordinated use of multi-metal field plates, air bridges, silicon nitride passivation films and polyimide passivation layers, and the rational integration of power units, the contradiction between the operating voltage and the on-resistance is effectively resolved, and the output power and conversion efficiency of the device are comprehensively improved, which has a positive significance for improving the characteristic frequency of the device.

[0039] 3. The single-tube power of the transistor has reached 120W, which improves the single-tube output power, power conversion efficiency and device anti-mismatch capability of the device, and promotes the development of transistors towards high frequency, high power and broadband. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is the heterojunction two-dimensional electron gas energy band;

[0041] Figure 2 What is needed to enable GaN?

[0042] Figure 3 It is a virtual grid model;

[0043] Figure 4 It is a schematic diagram of the structure of a pair of gate power cells;

[0044] Figure 5 It is a power unit integrating 8 gate fingers;

[0045] Figure 6 It is the gate connection diagram of two adjacent power units;

[0046] Figure 7A 120W die formed by connecting multiple power units in parallel;

[0047] Figure 8 It is a cross-sectional structural diagram of the present invention. DETAILED DESCRIPTION

[0048] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0049] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0050] Example 1

[0051] like Figure 1-8 As shown, a high power density gallium nitride high electron mobility transistor includes a plurality of gate power cells, each of which is composed of four pairs of gate power cells to form a power unit to ground, each of which is integrated with eight gate fingers, and the four pairs of gate power cells contain a total of eight gate islands, the gate islands of the four pairs of gate power cells are connected in parallel to form a gate bar group by metal connection, the gate ends of two adjacent power cells are isolated by resistors, and the resistance of the resistor used is 8-12 ohms, and multiple power cells are connected in parallel to eventually form a large gate width gallium nitride high power transistor with low parasitic effects, and a high-power tube core of 120W in the X band can be made on a gate bar with a gate length of 0.25 microns, covering products in the 8-12 GHz frequency band, and achieving an efficiency of more than 45%.

[0052] The gate power cell is made of a T-shaped metal low-resistance gate 6 and a multi-metal field plate. The gate power cell is obtained by a process performed on an epitaxial layer of a GaN structure. The GaN structure includes a silicon substrate 1 and an epitaxial layer. The epitaxial layer includes a GaN layer 2 and an Al-GaN layer 3. The gate power cell includes a silicon nitride thin film structure, a drain electrode 4, a source electrode 5, a T-shaped metal low-resistance gate 6, a metal 0 layer 7, a field plate 8, a metal 1 field plate 9 and a metal 1 layer 10. The silicon nitride thin film structure includes a first silicon nitride thin film 12, a second silicon nitride thin film 13, a third silicon nitride thin film 14 and a fourth silicon nitride thin film 15. The upper surface of the Al-GaN layer 3 is provided with a drain electrode 4, a source electrode 5, a T-shaped metal low-resistance gate 6, a metal 0 layer 7, a field plate 8, a metal 1 field plate 9 and a metal 1 layer 10. A low-resistance gate 6 and a first silicon nitride film 12, a source electrode 5 is arranged between two adjacent drain electrodes 4, a first silicon nitride film 12 is arranged between the drain electrode 4 and the source electrode 5, two ends of the first silicon nitride film 12 located between the drain electrode 4 and the source electrode 5 extend toward the drain electrode 4 and the source electrode 5 respectively and ride on the drain electrode 4 and the source electrode 5 respectively, a second silicon nitride film 13 is arranged on the first silicon nitride film 12 and a T-shaped metal low-resistance gate 6 is arranged between the two, a T-shaped head of the T-shaped metal low-resistance gate 6 rides on the first silicon nitride film 12, the T-shaped metal low-resistance gate 6 passes through the first silicon nitride film 12 and is arranged on the Al-GaN layer 3, a third silicon nitride film 13 is arranged on the second silicon nitride film 13 A metal 1 field plate 9 and a fourth silicon nitride film 15 are arranged on the third silicon nitride film 14, a metal 0 layer 7 is arranged on the drain electrode 4, a metal 1 layer 10 is arranged on the metal 0 layer 7, and a metal 0 layer 7 is arranged on the source electrode 5. The metal 1 field plate 9 is located above the metal 0 layer 7, and a third silicon nitride film 14 is arranged between the metal 1 field plate 9 and the metal 1 layer 10. The metal 1 field plate 9 is in contact with the metal 0 layer 7 and the third silicon nitride film 14 below. The first silicon nitride film 12 located between the drain electrode 4 and the source electrode 5 and the second silicon nitride film 13 directly above the first silicon nitride film 12 are in contact with the metal 0 layer 7 at both ends, and the metal 0 layer 7 is located at the third silicon nitride film 14. One end of the third silicon nitride film 14 directly above the silicon dinitride film 13 is in contact with the metal 1 layer 10, and the other end of the third silicon nitride film 14 is in contact with the metal 0 layer 7. A fourth silicon nitride film 15 is arranged on the third silicon nitride film 14 and a metal 1 field plate 9 is arranged between the two. A metal 2 layer 16 is arranged at both ends and above the fourth silicon nitride film 15. The metal 2 layer 16 at both ends of the fourth silicon nitride film 15 is deep to the metal 1 layer 10. A silicon nitride passivation film 17 is arranged above the metal 2 layer 16, and a polyimide passivation layer 18 is arranged above the silicon nitride passivation film 17. The middle part of the fourth silicon nitride film 15 is not in contact with the metal 2 layer 16, and is connected by an air bridge 11 to reduce parasitic capacitance.

[0053] The metal 0 layer 7 is mainly used to contact the drain electrode 4 and the source electrode 5, and uses 0.6 micron gold.

[0054] The metal 1 layer 10 is used to make capacitors. The metal 1 layer 10 is connected to the metal 0 layer 7 to form electrodes. The metal 1 layer 10 uses 1.1 microns of gold.

[0055] The metal 2 layer 16 is connected to the metal 1 layer 10 to form an electrode, and in order to withstand large currents, 4 microns of gold are used.

[0056] After the deposition and etching processes of the silicon nitride film, metal vapor deposition is performed to form metal layers of different thicknesses, and metal 0 layer 7, field plate 8, metal 1 field plate 9, metal 1 layer 10 and metal 2 layer 16 are manufactured on the film in a peeling manner, ultimately forming a multi-metal field plate structure of a T-shaped metal low-resistance gate 6 + field plate 8 + metal 1 field plate 9.

[0057] The manufacturing process of the multi-metal field plate structure mainly includes the following steps:

[0058] 1) providing a silicon substrate 1, wherein the silicon substrate 1 is made of silicon carbide or the like, and forming a GaN layer 2 and an Al-GaN layer 3 on the silicon substrate 1;

[0059] 2) depositing a Ti-Al layer on the Al-GaN layer 3 to form an ohmic contact layer of the drain electrode 4 and the source electrode 5, and depositing a first silicon nitride film 12 by LPCVD method with a deposition thickness of 50 nm;

[0060] 3) wet-etching the first silicon nitride film 12 to form a groove;

[0061] 4) Using a lift-off process to deposit metal at the groove to form a T-shaped metal low-resistance gate 6;

[0062] 5) Depositing a second silicon nitride film 13 with a deposition thickness of 100 nm;

[0063] 6) Photolithography, 0.6 micron gold is deposited on the drain electrode 4 and the source electrode 5 to form a metal 0 layer 7, and a lift-off process is used to form a field plate 8;

[0064] 7) Photolithography, gold 1.1 microns are deposited on the metal 0 layer 7 to form the metal 1 layer 10, and the third silicon nitride film 14 is deposited with a thickness of 80 nm, and is etched to the metal 1 layer 10;

[0065] 8) Using a lift-off process to form a metal 1 field plate 9;

[0066] 9) Depositing a fourth silicon nitride film 15, the deposition thickness of which can be flexibly selected according to actual needs;

[0067] 10) Photolithography: 4 microns of gold are deposited on the fourth silicon nitride film 15 to form a metal 2 layer 16, and finally a multi-metal field plate structure is formed.

[0068] The multi-metal field plate structure, the metal 2 layer 16, the silicon nitride passivation film 17 and the polyimide passivation layer 18 are compositely arranged to form a gate power cell. The polyimide passivation layer 18, the silicon nitride passivation film 17 and the metal 2 layer 16 are sequentially arranged above the multi-metal field plate structure from top to bottom. An air bridge 11 is used between the metal 1 layer and the metal 2 layer to achieve cross-connection.

[0069] A method for manufacturing a high power density gallium nitride high electron mobility transistor comprises the following steps:

[0070] 1) First, a silicon substrate 1 is selected, and a GaN layer 2 and an Al-GaN layer 3 of appropriate thickness are formed on the silicon substrate 1. An area where an ohmic contact is required is photolithographically formed on the Al-GaN layer 3, and metal deposition for the ohmic contact is performed. Then, a lift-off stripping process is used to form a contact area between a drain electrode 4 and a source electrode 5 and the Al-GaN layer 3, and then a metal alloy process is performed to form ohmic contact layers of the source and drain regions;

[0071] 2) Make the active area

[0072] Photolithography to form the active area, followed by multiple ion implantations to isolate the device;

[0073] 3) Depositing the first silicon nitride film 12, photolithography, etching out the ohmic contact area, and using the first silicon nitride film 12 for surface protection in other areas;

[0074] 4) Formation of T-shaped metal low-resistance gate 6

[0075] Photolithography, etching the first silicon nitride film 12 to form a groove with a line width of 0.25 microns, the bottom of the groove is in direct contact with the Al-GaN layer 3, metal deposition is performed at the groove, photolithography, and stripping is performed to form a T-shaped metal low-resistance gate 6;

[0076] 5) Deposition of the second silicon nitride film 13, photolithography, etching of the ohmic contact area, and surface protection of other areas using the second silicon nitride film 13;

[0077] 6) Photolithography, 0.6 micron gold is deposited on the drain electrode 4 and the source electrode 5 to form a metal 0 layer 7, which is then peeled off;

[0078] 7) Photolithography, metal TaN deposition, stripping, forming 8-12 ohm TaN thin film resistor;

[0079] 8) Photolithography, deposition of a thin metal layer to form a field plate 8, and stripping;

[0080] 9) Photolithography, gold 1.1 microns are deposited on the metal 0 layer 7 to form a metal 1 layer 10, the metal 1 layer 10 is connected to the metal 0 layer 7, a third silicon nitride film 14 is deposited, photolithography is performed, and etching is performed to the metal 1 layer 10; a lift-off process is used to form a metal 1 field plate 9;

[0081] 10) Photoresist spin coating process forms the bridge bottom;

[0082] 11) Deposition of the fourth silicon nitride film 15; photolithography, deposition of the metal 2 layer 16, stripping, connection between the metal 1 layer 10 and the metal 2 layer 16, removal of the photoresist formed at the bottom of the bridge by the photoresist spin coating process, and formation of the air bridge 11;

[0083] 12) Surface passivation

[0084] Deposition to form a silicon nitride passivation film 17, spin coating to form a polyimide passivation layer 18, photolithography, etching out the leads;

[0085] 13) Back side process

[0086] Thinning, photolithography back holes, plasma etching holes, 5 micron metal electroplating on the back, and then photolithography and etching process to carve out the scribe lines.

[0087] It should be noted that, in the present invention, a ground-to-ground power unit may also be composed of other logarithmic gate power cells, which may be flexibly adjusted according to actual needs.

[0088] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0089] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high power density gallium nitride high electron mobility transistor, characterized in that: It includes a plurality of gate power cells, wherein a plurality of pairs of gate power cells form a power unit to ground, the gate islands of the gate power cells are connected by metal, the gate ends of two adjacent power cells are isolated by resistors, and a plurality of power cells are connected in parallel; The gate power cell is made on the epitaxial layer of the GaN structure, and the gate power cell includes a silicon nitride thin film structure, a drain electrode, a source electrode, a T-shaped metal low-resistance gate, a metal 0 layer, a field plate, a metal 1 field plate, a metal 1 layer and a metal 2 layer arranged on the epitaxial layer, and the GaN structure includes a silicon substrate and an epitaxial layer, and the epitaxial layer includes a GaN layer and an Al-GaN layer; The silicon nitride film structure comprises four layers of a first silicon nitride film, a second silicon nitride film, a third silicon nitride film and a fourth silicon nitride film. A drain electrode, a source electrode, a T-shaped metal low-resistance gate and a first silicon nitride film are arranged on the upper surface of the Al-GaN layer. A source electrode is arranged between two adjacent drain electrodes. A first silicon nitride film is arranged between the drain electrode and the source electrode. Two ends of the first silicon nitride film located between the drain electrode and the source electrode extend toward the drain electrode and the source electrode respectively and ride on the drain electrode and the source electrode respectively. A second silicon nitride film is disposed on the first silicon nitride film and a T-shaped metal low-resistance gate is disposed between the two. The T-shaped head of the T-shaped metal low-resistance gate rides on the first silicon nitride film. The T-shaped metal low-resistance gate passes through the first silicon nitride film and is disposed on the Al-GaN layer. A third silicon nitride film is disposed on the second silicon nitride film and a field plate is disposed between the two. A metal 1 field plate and a fourth silicon nitride film are disposed on the third silicon nitride film. A metal 0 layer is disposed on the drain electrode. A metal 0 layer is disposed on the source electrode. A gold The metal 1 layer is connected to the metal 0 layer to form an electrode, the metal 1 field plate is located above the metal 0 layer, a third silicon nitride film is arranged between the metal 1 field plate and the metal 1 layer, the metal 1 field plate is in contact with the metal 0 layer and the third silicon nitride film below, the first silicon nitride film located between the drain electrode and the source electrode and the second silicon nitride film directly above the first silicon nitride film are in contact with the metal 0 layer at both ends respectively, one end of the third silicon nitride film located directly above the second silicon nitride film is in contact with the metal 1 layer, and the third silicon nitride film is in contact with the metal 0 layer. The other end of the three silicon nitride films is in contact with the metal 0 layer, a fourth silicon nitride film is arranged on the third silicon nitride film, and a metal 1 field plate is arranged between the two, a metal 2 layer is arranged at both ends and above the fourth silicon nitride film, the metal 2 layer at both ends of the fourth silicon nitride film is deep into the metal 1 layer, the metal 2 layer is connected to the metal 1 layer to form an electrode, a silicon nitride passivation film is arranged above the metal 2 layer, a polyimide passivation layer is arranged above the silicon nitride passivation film, and the middle part of the fourth silicon nitride film is not in contact with the metal 2 layer, and is connected through an air bridge.

2. The high power density gallium nitride high electron mobility transistor according to claim 1, characterized in that: Every four pairs of the gate power cells form a power unit facing the ground, each power unit facing the ground integrates eight gate fingers, and the four pairs of gate power cells contain eight gate islands in total.

3. The high power density gallium nitride high electron mobility transistor according to claim 1, characterized in that: The gate terminals of two adjacent power units are isolated by using 8-12 ohm resistors.

4. The high power density gallium nitride high electron mobility transistor according to claim 1, characterized in that: The metal 0 layer uses 0.6 micron gold.

5. The high power density gallium nitride high electron mobility transistor according to claim 1, characterized in that: The metal 1 layer is made of 1.1 micron gold.

6. The high power density gallium nitride high electron mobility transistor according to claim 1, characterized in that: The metal 2 layer is made of 4 microns of gold.

7. A method for manufacturing a high power density gallium nitride high electron mobility transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) First, a silicon substrate is selected, and a GaN layer and an Al-GaN layer of appropriate thickness are formed on the silicon substrate. The area where an ohmic contact is required is photolithographically carved out on the Al-GaN layer, and metal deposition for the ohmic contact is performed. Then, a lift-off process is used to form the contact area between the drain electrode and the source electrode and the Al-GaN layer, and then a metal alloy process is performed to form the ohmic contact layer of the source and drain regions; 2) Make the active area Photolithography to form the active area, followed by multiple ion implantations to isolate the device; 3) depositing a first silicon nitride film, performing photolithography, etching an ohmic contact area, and using the first silicon nitride film for surface protection in other areas; 4) Formation of T-shaped metal low-resistance gate Photolithography, etching the first silicon nitride film to form a groove, the bottom of the groove is in direct contact with the Al-GaN layer, metal deposition is performed at the groove, photolithography is performed, and stripping is performed to form a T-shaped metal low-resistance gate; 5) Deposition of a second silicon nitride film, photolithography, etching of an ohmic contact area, and use of a second silicon nitride film for surface protection of other areas; 6) Photolithography, metal is deposited on the drain electrode and the source electrode to form a metal 0 layer, and then peeled off; 7) Photolithography, metal TaN deposition, stripping, forming 8-12 ohm TaN thin film resistor; 8) Photolithography, deposition of thin metal layers, formation of field plates, and stripping; 9) Photolithography, metal is deposited on the metal 0 layer to form a metal 1 layer, the metal 1 layer is connected to the metal 0 layer, a third silicon nitride film is deposited, photolithography is performed, and etching is performed to the metal 1 layer; a lift-off process is used to form a metal 1 field plate; 10) Photoresist spin coating process forms the bridge bottom; 11) Fourth silicon nitride film deposition; Photolithography, deposition of metal 2 layer, stripping, connection between metal 1 layer and metal 2 layer, elimination of photoresist at the bottom of the bridge formed by photoresist spin coating process, and formation of air bridge; 12) Surface passivation Deposition forms a silicon nitride passivation film, spin coating forms a polyimide passivation layer, photolithography, and etching out leads; 13) Back side process Thinning, photolithography back hole, plasma etching hole, back metal electroplating, and then photolithography and etching process to carve out the scribe line.

8. The method for manufacturing a high power density gallium nitride high electron mobility transistor according to claim 7, characterized in that: The deposition thickness of the first silicon nitride film is 50 nm, the deposition thickness of the second silicon nitride film is 100 nm, and the deposition thickness of the third silicon nitride film is 80 nm.

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