NMOS-based negative charge pump circuit

Abstract

A negative charge pump circuit based on NMOS includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first clock signal and the second clock signal have different duty cycles, with the duty cycle of the second clock signal being less than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. A control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inversion of the first clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent No. 63 / 156,000, filed March 3, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to charge pump circuits, and in particular, to charge pump circuits configured to generate a negative output voltage. Background Technology

[0004] A voltage charge pump is a DC-DC voltage converter that operates to convert an input voltage into an output voltage with an amplitude higher than the input voltage. In many cases, the input is the circuit's power supply voltage. Such charge pump circuits typically use capacitors as energy storage devices. The capacitors switch in the manner in which the desired voltage conversion occurs. Circuits for both positive and negative voltage generation are known in the art.

[0005] Charge pumps are used in many different types of circuits, including low-voltage circuits, dynamic random access memory circuits, switched capacitor circuits, EEPROMs, and transceivers. For example, charge pumps are critical in non-volatile memories because they are used to generate the high voltages (positive and / or negative) required to perform programming and erasing operations.

[0006] Figure 1 An example of a prior art negative voltage charge pump circuit stage 10 is shown. This circuit 10 uses complementary metal-oxide-semiconductor (CMOS) technology to form a latch circuit comprising two cross-coupled CMOS inverter circuits 12 and 14. The source terminal of the p-channel MOS transistor in each latch circuit is connected to the input node A (receiving the input voltage VIN), and the source terminal of the n-channel MOS transistor in each latch circuit is connected to the output node B (generating the output voltage VOUT, where VOUT is a voltage more negative than the input voltage). Capacitors C are coupled to each pair of connected drain terminals of the CMOS transistors in the latch circuit. The first capacitor C coupled to inverter circuit 12 is configured to receive a clock signal ck, and the second capacitor C coupled to inverter circuit 14 is configured to receive a clock signal ckn (which is the logical inversion of the clock signal ck). The operation of this circuit 10 in response to clock signals ck and ckn to receive ground voltage Gnd at node A and output a negative voltage of approximately -Vdd (where Vdd is the supply voltage of inverter circuits 12 and 14) is well known to those skilled in the art. Each latching circuit's p-channel MOS transistor operates in a body effect (a positive bias voltage is applied to the transistor body via diode circuit 18).

[0007] To generate a higher amplitude negative voltage, such as Figure 2 As shown, multiple charge pump circuits 10(1)-10(2) stages can be coupled in series. However, as each successive stage generates a higher negative voltage, the p-channel MOS transistor of that stage becomes weaker, and the voltage conversion efficiency decreases. In addition, there is an increase in the bulk-to-source / drain voltage in the downstream stage, which may lead to breakdown at relatively high negative voltages.

[0008] Figure 3 Example of another prior art negative voltage charge pump circuit 20 is shown. This circuit 20, referred to in the art as a Dickson charge pump, is based on the use of diodes (formed here using n-channel MOS transistors 22 in diode configuration) and capacitor C. The diodes are connected in series with multiple stages 24(1)-24(4) between the input voltage VIN node and the output voltage VOUT node, and capacitor C is connected to each stage 24 of the circuit 20 and driven by a clock signal. More specifically, a two-phase clock (ck and ckn, where ckn is the logical inversion of ck) is used, where clock ck is applied to odd-numbered stages 24(1), 24(3), and clock ckn is applied to even-numbered stages 24(2), 24(4). One problem with the charge pump circuit is the voltage drop in each stage 24 (due to the diode configuration), resulting in poor voltage efficiency; with an output voltage of:

[0009] VOUT = -N(Vdd - Vth),

[0010] Where N is the number of stages 24, and Vth is the threshold voltage drop across each diode.

[0011] Figure 4Example of another prior art negative voltage charge pump circuit 30 is shown. This circuit 30 utilizes multiple clock signals to achieve bootstrapping. More specifically, four non-overlapping clock signals (ck1, ck2, ck3, ck4) are applied to the series connection of charge pump stages 32(1)-32(3). Each stage 32 includes two n-channel MOS transistors M1, M2 and two capacitors C1, C2. The source-drain path of the first n-channel MOS transistor is coupled between the stage input and output nodes. The source-drain path of the second n-channel MOS transistor is coupled between the output node and gate of the first n-channel MOS transistor. The first capacitor C1 has a terminal coupled to the output node of the stage and a second terminal configured to receive a phase of the clock signal. The second capacitor C2 has a terminal coupled to the gate of the first n-channel MOS transistor M1 and a second terminal configured to receive another phase of the clock signal. For the first stage 32(1) of circuit 30, the gate of the second n-channel MOS transistor M2 is coupled to receive another phase of the clock signal. In all other stages 32, the gate of the second n-channel MOS transistor M2 is coupled to the stage output node of the previous stage.

[0012] The clock signal comprises four phases. In the first stage 32(1), the gate of the second n-channel MOS transistor M2 receives the second phase clock ck2. In the odd-numbered stages 32(1) and 32(3), the first phase clock ck1 is applied to the first capacitor C1, and the third phase clock C3 is applied to the second capacitor C2. Conversely, in the even-numbered stage 32(2), the fourth phase clock ck4 is applied to the first capacitor C1, and the second phase clock C2 is applied to the second capacitor C2.

[0013] and Figure 3 Compared to circuit 20, Figure 4 Circuit 30 provides improved voltage efficiency. However, the high output impedance of circuit 30 limits the output current drive capability. This is due to the fact that only one voltage boost can be provided per cycle of the four-phase clock. Another drawback of circuit 30 is that the use of a four-phase clock imposes a limitation on the use of high clock frequencies.

[0014] Therefore, there is a need in the art for a negative charge pump circuit that solves the following problem: Figures 1 to 4 The problems, concerns, and limitations of existing negative charge pump circuits are illustrated. Summary of the Invention

[0015] In one embodiment, a circuit includes: a first transistor having a source-drain path coupled between an input node and a first node, the input node being configured to receive a first voltage; a second transistor having a source-drain path coupled between the first node and an output node, the output node being configured to generate a second voltage that is more negative than the first voltage; a third transistor having a source-drain path coupled between the first node and a first control terminal of the first transistor; a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal; wherein a logic inversion of the first clock signal is applied to a second control terminal of the second transistor; a first bootstrap capacitor having a first plate coupled to the first control terminal and a second plate coupled to receive a second clock signal; and wherein the first clock signal and the second clock signal have the same frequency but different duty cycles.

[0016] In one embodiment, a circuit includes: a first input transistor having a source-drain path coupled between an input node and a first node, the input node being configured to receive a first voltage; a second input transistor having a source-drain path coupled between the input node and a second node; a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal; a first bootstrap circuit coupled between the first node and a first control terminal of the first input transistor, the first bootstrap capacitor being controlled by a logic inversion of the first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles; a second boost capacitor having a first plate coupled to the second node and a second plate coupled to receive a third clock signal; and a second bootstrap circuit coupled between the second node and a second control terminal of the second input transistor, the second bootstrap capacitor being controlled by a logic inversion of the third clock signal and a fourth clock signal, wherein the third clock signal and the fourth clock signal have the same frequency but different duty cycles.

[0017] In one embodiment, a circuit includes: a boost capacitor driven by a first clock signal and coupled to a boost node; a bootstrap capacitor driven by a second clock signal and coupled to an intermediate node; wherein the first clock signal and the second clock signal have different duty cycles, wherein the duty cycle of the second clock signal is less than the duty cycle of the first clock signal; an input transistor coupled between an input node and a boost node, wherein a control terminal of the input transistor is coupled to the intermediate node; and a bootstrap transistor coupled between the boost node and the control terminal of the input transistor, wherein the control terminal of the bootstrap transistor is driven by a logic inversion of the first clock signal. Attached Figure Description

[0018] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, in which:

[0019] Figure 1 This is a circuit diagram of a current negative voltage charge pump circuit stage;

[0020] Figure 2 Is it used as Figure 1 The circuit diagram of the cascaded charge pump circuit shown.

[0021] Figure 3 This is a circuit diagram of a prior art negative voltage charge pump circuit;

[0022] Figure 4 This is a circuit diagram of a prior art negative voltage charge pump circuit;

[0023] Figure 5 This is a circuit diagram of a negative voltage charge pump circuit;

[0024] Figure 6 It is used for driving Figure 5 Timing diagram of the clock phase signal and other node signals of the negative voltage charge pump circuit;

[0025] Figure 7 Is it used as Figure 5 The circuit diagram of the cascaded charge pump circuit shown.

[0026] Figure 8 It is a logic diagram of a circuit that generates a clock phase signal to drive... Figure 5 Negative voltage charge pump circuit;

[0027] Figure 9 This is a circuit diagram of another embodiment of the negative voltage charge pump circuit; and

[0028] Figure 10 This is a circuit diagram of another embodiment of the negative voltage charge pump circuit. Detailed Implementation

[0029] Now refer to the circuit diagram showing the negative voltage charge pump circuit stage 100. Figure 5 Circuit stage 100 includes an n-channel MOS transistor MN1 having a drain terminal coupled (preferably directly connected) to input node A and a source terminal coupled (preferably directly connected) to node S1 (i.e., the source-drain path of the transistor is coupled between node A and node S1). Stage 100 also includes an n-channel MOS transistor MN2 having a drain terminal coupled (preferably directly connected) to input node A and a source terminal coupled (preferably directly connected) to node S1b (i.e., the source-drain path of the transistor is coupled between node A and node S1b). Node A is configured to receive an input voltage VIN from which a more negative output voltage VOUT is generated.

[0030] The first boost capacitor C1 has one terminal coupled (preferably directly connected) to node S1 and another terminal configured to receive clock phase signal ck1. The second boost capacitor C2 has one terminal coupled (preferably directly connected) to node S1b and another terminal configured to receive clock phase signal ck3 (which is the logical inversion of clock phase signal ck1). The voltage waveforms of clock phase signals ck1 and ck3 are as follows: Figure 6 As shown.

[0031] Stage 100 also includes an n-channel MOS transistor MN3 having a source terminal coupled (preferably directly connected) to node S1 and a drain terminal coupled (preferably directly connected) to the gate of transistor MN1 at node Ng1 (i.e., the source-drain path of the transistor is coupled between nodes S1 and Ng1). The gate of transistor MN3 is configured to receive a logic inversion (ck1b) of clock phase signal ck1. Stage 100 also includes an n-channel MOS transistor MN4 having a source terminal coupled (preferably directly connected) to node S1b and a drain terminal coupled (preferably directly connected) to the gate of transistor MN2 at node Ng2 (i.e., the source-drain path of the transistor is coupled between nodes S1b and Ng2). The gate of transistor MN4 is configured to receive a logic inversion (ck3b) of clock phase signal ck3.

[0032] The first bootstrap capacitor Cbs1 has one terminal coupled (preferably directly connected) to node Ng1 and another terminal configured to receive clock phase signal ck2. The second bootstrap capacitor Cbs2 has one terminal coupled (preferably directly connected) to node Ng2 and another terminal configured to receive clock phase signal ck4. The voltage waveforms of clock phase signals ck2 and ck4 are as follows: Figure 6 As shown.

[0033] Clock signals ck1 and ck2 have the same frequency but different duty cycles, with the duty cycle of clock phase signal ck1 being greater than that of clock phase signal ck2 (and clock phase signal ck2 should be precisely contained within clock phase signal ck1). Clock signals ck3 and ck4 have the same frequency but different duty cycles, with the duty cycle of clock phase signal ck3 being greater than that of clock phase signal ck4 (and clock phase signal ck4 should be precisely contained within clock phase signal ck2, i.e., the timing of the pulse of ck4 is within the timing of the pulse of ck2). In this configuration, clock phase signals ck1 and ck3 are 180 degrees out of phase with each other. Furthermore, clock phase signals ck1 and ck4 do not overlap. Additionally, clock phase signals ck2 and ck3 do not overlap.

[0034] Stage 100 further includes an n-channel MOS transistor MN5 having a source terminal coupled (preferably directly connected) to the output node B and a drain terminal coupled (preferably directly connected) to the node S1 (i.e., the source-drain path of the transistor is coupled between nodes B and S1); and an n-channel MOS transistor MN6 having a source terminal coupled (preferably directly connected) to the node B and a drain terminal coupled (preferably directly connected) to the node S1b. Transistors MN5 and MN6 are cross-coupled, with the gate terminal of transistor MN5 coupled (preferably directly connected) to the drain terminal of transistor MN6 at node S1b, and the gate terminal of transistor MN6 coupled (preferably directly connected) to the drain terminal of transistor MN5 at node S1. Node B is configured to generate an output voltage VOUT that is more negative than the input voltage VIN. In an example implementation with an input voltage of 0V (Gnd), the output voltage is ideally equal to -Vdd (where Vdd is the logic high voltage of the clock phase signals ck1, ck2, ck3, and ck4). However, in actual implementation, there is a voltage deviation from the ideal voltage due to the parasitic capacitance of the switching and routing loads, as well as the voltage drop (Vpar) caused by the frequency of the load current and clock phase signal.

[0035] Transistors MN1 and MN2 are alternately actuated input transistors. Transistor MN3 and capacitor Cbs1 form the first bootstrap circuit. Transistor MN4 and capacitor Cbs2 constitute the second bootstrap circuit. Capacitors C1 and C2 are boost capacitors. Transistors MN1 and MN2 are alternately actuated output transistors.

[0036] The operation for level 100 is as follows.

[0037] First, assume that all nodes are grounded.

[0038] 1) Once the clock phase signal is applied to the circuit, the clock phase signal ck1 transitions from 0 to 1 at time t1. Here, logic "0" refers to ground, and logic "1" refers to the power supply voltage Vdd. In response to the transition of the clock phase signal ck1 from 0 to 1, due to the coupling effect between capacitors C1, node S1 on the upper plate of capacitor C1 will attempt to move from ground to the Vdd voltage level. However, node S1 will not be able to reach the Vdd voltage level because the body-drain junction of transistor MN1 will be forward biased. This is because the source of transistor MN1 is connected to its body, and the drain is connected to the input voltage VIN at the ground (Gnd) voltage level. Therefore, node S1 will reach the threshold voltage of the body-drain junction. The gate control signal ck1b, which is the logic inversion of the clock phase signal ck1, will simultaneously transition from 1 to 0, which will keep transistor MN3 in the off state.

[0039] 2) In the next step, the clock phase signal ck2 transitions from logic 0 to 1 at time t2. Due to the coupling effect on the bootstrap capacitor Cbs1, the voltage at node Ng1 will become the positive Vdd voltage level. When node Ng1 transitions to the Vdd voltage level, it will cause transistor MN1 to turn on (because its gate has reached a positive voltage). When transistor MN1 is in the on state, the voltage at node S1 will discharge to the ground voltage level at input VIN. Therefore, the voltage at node S1 will stabilize to the GND voltage level. 3) At time t3, the clock phase signal ck2 transitions from 1 to 0. During this transition, the coupling effect on the bootstrap capacitor Cbs1 will again have an effect, bringing the voltage at node Ng1 from the Vdd voltage level to the ground voltage level. Since Ng1 will be grounded (due to the coupling effect), it will again control transistor MN1 to be in the off state.

[0040] 4) Next, at time t4, the clock phase signal ck1 transitions from 1 to 0. Simultaneously, the gate control signal ck1b, which is the logic inversion of the clock phase signal ck1, transitions from 0 to 1. Since the gate of transistor MN3 is now at the Vdd voltage level, it switches transistor MN3 to the on state and connects node S1 to node NG1. As the clock phase signal ck1 transitions from 1 to 0, node S1 transitions to the -Vdd voltage level (as it was previously at the ground voltage level). This negative voltage boost occurs due to the coupling effect across capacitor C1. When node S1 reaches the -Vdd voltage level, node Ng1 also reaches the -Vdd voltage level via transistor MN3, which is still in the on state. Since node Ng1 is at the -Vdd voltage level, it keeps transistor MN1 in the off state, and the charge at node S1 does not leak from node S1 to the input voltage VIN node. Thus, node S1 will switch between the ground voltage level and the -Vdd voltage level during different clock transitions. Similarly, due to the different transitions of clock phase signals ck3 and CK4, node S2b will switch between -Vdd voltage level and ground voltage level (but in the opposite phase of node S1).

[0041] 5) Also at time t4, node S1 is at the -Vdd voltage level, and node S1b is at the ground voltage level. This will cause transistor MN5 to switch to the on state, passing the -Vdd voltage level at node S1 to the output node VOUT. Since node S1 is at the -Vdd voltage level, it will cause transistor MN6 to be in the off state so that the charge stored at node VOUT will not leak to node S1b.

[0042] 6) Similarly, when node S1b is at the -Vdd voltage level, node S1 will be at the ground voltage level. This voltage level will cause transistor MN6 to turn on and keep transistor MN5 off. When transistor MN6 turns on, it will cause the -Vdd voltage level to be passed from node S1b to output node VOUT. See time t7.

[0043] 7) In this way, during half clock cycles (ck1 and ck2), the -Vdd voltage level will be passed to the output node VOUT through the turn-on transistor MN5. Similarly, during the second half clock cycle (ck3 and ck4), the -Vdd voltage level will be passed to the output node VOUT through the turn-on transistor MN6.

[0044] The above describes the operation of the left half of circuit 100. Due to the modularity of the architecture, the same explanation applies to the right half with respect to times t4, t5, t6, and t7.

[0045] To generate a higher amplitude negative voltage, multiple charge pump circuit stages 100(1)-100(3) can be coupled in series, such as Figure 7 As shown. Node B of a circuit stage 100 is coupled (preferably directly connected) to node A of a subsequent circuit stage 100. It should be noted that transistors MN3 and MN4 in the first circuit stage 100 (1) are driven by the gates of logic inverted clock signals ck1b and ck3b. However, in the second stage and subsequent stages 100 (2)-100 (3), transistors MN3 and MN4 are driven by the signal gates from the previous circuit stage 100 at nodes S1b and S1, respectively. This is because the sources of transistors MN3 and MN4 are connected to nodes S1 and S1b, respectively. In the first stage 100 (1), nodes S1 and S1b switch between ground voltage and -Vdd voltage. However, in subsequent stages 100 (2) and 100 (3), nodes S1 and S1b switch between -Vdd voltage and -2Vdd voltage and between -2Vdd voltage and -3Vdd voltage, respectively. For these subsequent stages 100(2) and 100(3), transistors MN3 and MN4 must be gate-driven to ensure they are cut off by voltages that depend on the voltage level at the source. The logic inverted clock signals ck1b and ck3b, which switch between logic 0 (ground) and logic 1 (Vdd) voltages, cannot be used. Instead, voltages from the S1 and S1b nodes of the previous stage are used, which are well-suited for turning on / off transistors MN3 / MN4 in the next stage. As an added benefit, this gate-driven connection for subsequent stages also helps to operate the transistors within the Safe Operating Area (SOA) constraints.

[0046] The output voltage VOUT of a charge pump circuit formed by N charge pump circuit stages 100(1)-100(N) connected in series is as follows: Figure 7 As shown, where N = 3, is given by the following formula:

[0047] VOUT=-(N*Vdd)+Vpar+(N / fc)Iload;

[0048] Where N is the cascade number, Vdd is the logic high voltage of the clock signal; Vpar is the voltage drop across the parasitic capacitance caused by the switch and routing load; fc is the frequency of the clock signal; and Iload is the load current driving the load circuit (not shown) connected to node B(N) of the Nth stage 100(N) in the charge pump circuit 100(N).

[0049] Now for reference Figure 8 It shows the generation used for driving Figure 5 The logic diagram of circuit 300 for the clock phase signals ck1, ck2, ck3, and ck4 of the negative voltage charge pump circuit is shown. The clock phase signals ck1, ck2, ck3, and ck4 are generated by circuit 300 from the master clock signal CK. Circuit 300 includes a first NAND latch circuit 302 (also called a set-reset latch), which is formed by a pair of cross-coupled NAND gates 304 and 306, wherein the output of gate 304, delayed by logic inverter 308, is applied to the input of gate 306, and the output of gate 306, delayed by logic inverter 310, is applied to the input of gate 304. The master clock CK is passed to gate 304 via transmission gate circuit 312 and logically inverted by inverter circuit 314 to be applied to gate 306. The transmission gate 312 is formed by parallel n-channel MOS transistors and p-channel MOS transistors, wherein the p-channel transistors have gates coupled (preferably directly connected) to ground Gnd, and the n-channel transistors have gates coupled (preferably directly connected) to the power supply voltage Vdd. The clock signals generated at the output nodes 316 and 318 of the first NAND latch circuit 302 have the same frequency but do not overlap and are logically inverted.

[0050] Circuit 300 includes a second NAND latch circuit 322 (also referred to as a set-reset latch) formed by a pair of cross-coupled NAND gates 324 and 326, wherein the output of gate 324, delayed by logic inverter 328, is applied to the input of gate 326, and the output of gate 326, delayed by logic inverter 330, is applied to the input of gate 324. The clock signal at node 316 is passed to gate 324 via transmission gate circuit 332 and logically inverted by inverter circuit 334 to be applied to gate 326. Transmission gate circuit 332 is formed by parallel n-channel MOS transistors and p-channel MOS transistors, wherein the p-channel transistors have gates coupled (preferably directly connected) to ground Gnd, and the n-channel transistors have gates coupled (preferably directly connected) to the power supply voltage Vdd. Transmission gate circuit 332 is used to match the clock path. Clock signals ck1 and ck4 are generated at the output nodes 336 and 338 of the second NAND latch circuit 322. They have the same frequency but do not overlap and are logically inverted.

[0051] Circuit 300 also includes a third NAND latch circuit 342 (also referred to as a set-reset latch), which is formed by a pair of cross-coupled NAND gates 344 and 346, wherein the output of gate 344, delayed by logic inverter 348, is applied to the input of gate 346, and the output of gate 346, delayed by logic inverter 350, is applied to the input of gate 344. The clock signal at node 318 is passed to gate 344 via transmission gate circuit 352 and logically inverted by inverter circuit 354 to be applied to gate 346. Transmission gate circuit 352 is formed by parallel n-channel MOS transistors and p-channel MOS transistors, wherein the p-channel transistors have gates coupled (preferably directly connected) to ground Gnd, and the n-channel transistors have gates coupled (preferably directly connected) to the power supply voltage Vdd. Transmission gate circuit 352 is used to match the clock path. Clock signals ck3 and ck2 are generated at output nodes 356 and 358 of the third NAND latch circuit 342. They have the same frequency but do not overlap and are logically inverted.

[0052] Transmission gates 312, 332, and 352 are used to match the clock path. Figure 6 The review notes that several very specific timing constraints must be met: a) clock phase signal ck2 should be precisely contained within clock phase signal ck1; b) clock phase signal ck4 should be precisely contained within clock phase signal ck3; and c) clock phase signals ck1 and ck3 should be completely out of phase. To satisfy these constraints, the timing path during clock signal generation must also be satisfied. (Reference) Figure 8In the generation of clock phase signals ck1 to ck4, for the circuits used to generate clock phase signals ck4 and ck2, there is an additional inverter in the signal generation path, which will provide additional delay. In order to meet and match the delay of this additional inverter, a transmission gate circuit 312 is set in the signal path of clock phase signals ck1 and ck3.

[0053] Figure 5 Circuit 100 in such Figure 7 Implemented in the cascading configuration shown, with Figure 1 , Figure 3 and Figure 4 The solutions shown have many advantages over known solutions. For example, circuits 100 and 200 do not undergo the same process as... Figure 1 The circuit 10 has known reliability issues. Furthermore, circuits 100 and 200 do not have the following characteristics: Figure 3 The threshold voltage drop experienced by circuit 20 that adversely affects conversion efficiency. Furthermore, with Figure 4 Compared to circuit 30, circuits 100 and 200 have lower output impedance, thus exhibiting better current drive capability. An additional advantage of circuits 110 and 200 compared to prior art solutions is that all n-channel MOS transistors MN1-MN6 can be implemented as "low-voltage" devices with better transconductance performance, since the clock signal is only in the Vdd voltage domain. Therefore, circuits 100 and 200 can use transistors that occupy a smaller surface area and consume less power. Furthermore, generating all clock signals in the Vdd voltage domain provides a simpler clock circuit than some prior art solutions that require clock signals in multiple different voltage domains. Therefore, circuits 100 and 200 provide the same negative voltage generation performance with better efficiency and a smaller circuit area.

[0054] Now for reference Figure 9 The diagram shows a circuit diagram of another embodiment of the negative voltage charge pump circuit 110. Figure 5 and Figure 9 Similar references in this context refer to identical or similar circuit elements. Figure 9 Circuit 110 and Figure 5The difference in circuit 100 lies in the addition of two diodes, 112 and 114, which are coupled (preferably directly connected) between the input node VIN and nodes S1 and S1b, respectively. More specifically, the anode terminals of diodes 112 and 114 are coupled (preferably directly connected) to the input node VIN, the cathode terminal of diode 112 is coupled (preferably directly connected) to node S1, and the cathode terminal of diode 114 is coupled (preferably directly connected) to node S1b. In a preferred configuration of circuit 110, the diodes are provided as diode-connected MOS transistors. Diodes 112 and 114 are used to mitigate the effect on the body current that will flow during different transitions of the clock phase signal.

[0055] The operation of circuit 110 is the same as the above regarding Figure 5 The operation described in circuit 100 is the same.

[0056] To generate a higher amplitude negative voltage, multiple charge pump circuit stages 110 can be configured similarly to... Figure 7 The circuit 100 is connected in series as shown in the diagram.

[0057] Now for reference Figure 10 The diagram shows a circuit diagram of another embodiment of the negative voltage charge pump circuit 120. Figure 5 and Figure 10 Similar references in this context refer to identical or similar circuit elements. Figure 10 Circuit 120 and Figure 5 The difference in circuit 100 is that each of the n-channel transistors MN1-MN6 used in circuit 120 is formed to share a common body 122. Another difference is that the source terminals of the n-channel MOS transistors MN1-MN6 are not connected to the common body 122. However, the common body 122 is not a floating node. Yet another difference is that circuit 120 also includes circuit 124 for biasing the common body 122.

[0058] The bias circuit 124 is formed by a pair of n-channel MOS transistors MN7 and MN8, whose source-drain paths are connected in series between nodes A and B. More specifically, the drain of transistor MN7 is connected to node A, and the drain of transistor MN8 is connected to node B. The sources of transistors MN7 and MN8 are connected to each other and output a body bias voltage Vbias applied to the common body 122. The gate of transistor MN7 is connected to the drain of transistor MN8 at node B, and the gate of transistor MN8 is connected to the drain of transistor MN7 at node A. Transistors MN7 and MN8 thus have a cross-coupled circuit structure.

[0059] The body bias voltage Vbias is the minimum voltage available in circuit 120 at any given time. This body bias voltage Vbias is used to bias the body 122 of all NMOS transistors, and we want it to be at its minimum voltage. This implementation helps reduce the area of ​​circuit 120 because the common body configuration makes it possible to fabricate NMOS transistors in a single PWELL.

[0060] Although not specifically shown, Figure 10 The circuit 120 may further include, for example, Figure 9 The diodes 112 and 114 are shown in circuit 110.

[0061] The foregoing description provides a complete and informative description of exemplary embodiments of the invention through exemplary and non-limiting examples. However, various modifications and adaptations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, taking into account the foregoing description. Nevertheless, all such modifications and similar alterations to the teachings of the invention will still fall within the scope of the invention as defined in the appended claims.

Claims

1. A circuit comprising: A first transistor has a source-drain path coupled between an input node and a first node, the input node being configured to receive a first voltage; The second transistor has a source-drain path coupled between the first node and the output node, the output node being configured to generate a second voltage that is negative than the first voltage; The third transistor has a source-drain path coupled between the first node and the first control terminal of the first transistor; The first boost capacitor has: a first plate coupled to the first node; And a second board, coupled to receive the first clock signal; The logic inversion of the first clock signal is applied to the third control terminal of the third transistor; A first bootstrap capacitor has: a first plate coupled to the first control terminal; And a second board, coupled to receive a second clock signal; and The first clock signal and the second clock signal have the same frequency but different duty cycles; The fourth transistor has a source-drain path coupled between the input node and the second node; The fifth transistor has a source-drain path coupled between the second node and the output node; The sixth transistor has a source-drain path coupled between the second node and the fourth control terminal of the fourth transistor; The second boost capacitor has: a first plate coupled to the second node; And the second board, which is coupled to receive the third clock signal; The logic inversion of the third clock signal is applied to the sixth control terminal of the sixth transistor; The second bootstrap capacitor has: a first plate coupled to the fourth control terminal; And the second board, which is coupled to receive the fourth clock signal; and The third clock signal and the fourth clock signal have the same frequency but different duty cycles; The second control terminal of the second transistor is coupled to the second node, and the fifth control terminal of the fifth transistor is coupled to the first node.

2. The circuit according to claim 1, wherein the duty cycle of the second clock signal is less than the duty cycle of the first clock signal.

3. The circuit according to claim 1, wherein the duty cycle of the fourth clock signal is less than the duty cycle of the third clock signal.

4. The circuit according to claim 1, wherein the third clock signal is 180 degrees out of phase with the first clock signal.

5. The circuit according to claim 1, wherein the first clock signal and the fourth clock signal do not overlap.

6. The circuit according to claim 1, wherein the second clock signal and the third clock signal do not overlap.

7. The circuit according to claim 1, further comprising: A first diode is coupled between the input node and the first node; as well as A second diode is coupled between the input node and the second node.

8. The circuit according to claim 7, wherein both the first diode and the second diode are formed by diode-connected transistors.

9. The circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor share a common body.

10. The circuit of claim 9, further comprising a bias circuit configured to generate a bias voltage applied to the common body of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

11. The circuit of claim 10, wherein the bias circuit comprises: The seventh transistor has a source-drain path coupled between the input node and the third node; The eighth transistor has a source-drain path coupled between the output node and the third node; The seventh control terminal of the seventh transistor is coupled to the output node; and The eighth control terminal of the eighth transistor is coupled to the input node.

12. The circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all n-channel MOS transistors.

13. The circuit of claim 1, further comprising: A diode is coupled between the input node and the first node.

14. The circuit of claim 13, wherein the diode is formed from a diode-connected transistor.

15. The circuit of claim 1, wherein the first transistor, the second transistor, and the third transistor share a common body.

16. The circuit of claim 15, further comprising a bias circuit configured to generate a bias voltage applied to the common body of the first transistor, the second transistor, and the third transistor.

17. The circuit of claim 16, wherein the bias circuit comprises: The seventh transistor has a source-drain path coupled between the input node and the third node; The eighth transistor has a source-drain path coupled between the output node and the third node; The seventh control terminal of the seventh transistor is coupled to the output node; and The eighth control terminal of the eighth transistor is coupled to the input node.

18. The circuit of claim 1, wherein the first transistor, the second transistor and the third transistor are all n-channel MOS transistors.

19. A circuit comprising: A first input transistor has a source-drain path coupled between an input node and a first node, the input node being configured to receive a first voltage; The second input transistor has a source-drain path coupled between the input node and the second node; The first boost capacitor has: a first plate coupled to the first node; And a second board, coupled to receive the first clock signal; A first bootstrap circuit is coupled between the first node and the first control terminal of the first input transistor. The first bootstrap circuit is controlled by the logic inversion of the first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles. The first bootstrap circuit includes: a first bootstrap transistor having a source-drain path coupled between the first node and a first control terminal of the first input transistor, wherein the control terminal of the first bootstrap transistor is coupled to receive a logic inversion of the first clock signal; The second boost capacitor has: a first plate coupled to the second node; and a second plate coupled to receive a third clock signal; and The second bootstrap circuit is coupled between the second node and the second control terminal of the second input transistor. The second bootstrap circuit is controlled by the logic inversion of the third clock signal and the fourth clock signal, wherein the third clock signal and the fourth clock signal have the same frequency but different duty cycles. A first output transistor has a source-drain path coupled between an output node and the first node, the output node being configured to generate a second voltage that is negative than the first voltage; and The second output transistor has a source-drain path coupled between the output node and the second node; The control terminal of the first output transistor is coupled to the second node, and the control terminal of the second output transistor is coupled to the first node.

20. The circuit of claim 19, wherein the first bootstrap circuit further comprises: A first bootstrap capacitor has: a first plate coupled to the first control terminal of the first input transistor; And a second board, which is coupled to receive the second clock signal.

21. The circuit of claim 19, wherein the second bootstrap circuit comprises: The second bootstrap transistor has a source-drain path coupled between the second node and the second control terminal of the second input transistor, wherein the control terminal of the second bootstrap transistor is coupled to receive a logic inversion of the third clock signal. as well as The second bootstrap capacitor has: a first plate coupled to the second control terminal of the second input transistor; And a second board, which is coupled to receive the fourth clock signal.

22. The circuit of claim 19, wherein the duty cycle of the second clock signal is less than the duty cycle of the first clock signal, and wherein the duty cycle of the fourth clock signal is less than the duty cycle of the third clock signal.

23. The circuit of claim 19, wherein the first clock signal and the fourth clock signal do not overlap, and wherein the second clock signal and the third clock signal do not overlap.

24. The circuit according to claim 19, wherein the third clock signal is 180 degrees out of phase with the first clock signal.

25. The circuit according to claim 19, further comprising: A first diode is coupled between the input node and the first node; as well as A second diode is coupled between the input node and the second node.

26. The circuit of claim 25, wherein both the first diode and the second diode are formed by diode-connected transistors.

27. The circuit of claim 19, wherein the first input transistor and the second input transistor share a common body.

28. The circuit of claim 27, further comprising a bias circuit configured to generate a bias voltage applied to the common body of the first input transistor and the second input transistor.

29. The circuit of claim 28, wherein the bias circuit comprises: The first bias transistor has a source-drain path coupled between the input node and the third node; The second bias transistor has a source-drain path coupled between the output node and the third node; The control terminal of the first bias transistor is coupled to the output node; and The control terminal of the second bias transistor is coupled to the input node.

30. A circuit comprising: The first boost capacitor is driven by the first clock signal and coupled to the first boost node; The first bootstrap capacitor is driven by the second clock signal and is coupled to the first intermediate node; The first clock signal and the second clock signal have different duty cycles, and the duty cycle of the second clock signal is smaller than that of the first clock signal. A first input transistor is coupled between an input node and a first boost node, wherein the control terminal of the first input transistor is coupled to the first intermediate node; A first bootstrap transistor is coupled between the first boost node and the control terminal of the first input transistor, wherein the control terminal of the first bootstrap transistor is driven by a logical inversion of the first clock signal; The second boost capacitor is driven by the third clock signal and is coupled to the second boost node; The second bootstrap capacitor is driven by the fourth clock signal and is coupled to the second intermediate node; The third clock signal and the fourth clock signal have different duty cycles, and the duty cycle of the fourth clock signal is smaller than that of the third clock signal. A second input transistor is coupled between the input node and the second boost node, wherein the control terminal of the second input transistor is coupled to the second intermediate node; A second bootstrap transistor is coupled between the second boost node and the control terminal of the second input transistor, wherein the control terminal of the second bootstrap transistor is driven by a logical inversion of the third clock signal; as well as A first output transistor is coupled between the first boost node and the output node, and the control terminal of the first output transistor is coupled to the second boost node; A second output transistor is coupled between the second boost node and the output node, and the control terminal of the second output transistor is coupled to the first boost node; The first output transistor and the second output transistor are configured to generate an output voltage that is more negative than the input voltage applied to the input node.

31. The circuit of claim 30 further includes a diode coupled between the input node and the boost node.

32. The circuit of claim 31, wherein the diode is formed from a diode-connected transistor.

33. The circuit of claim 30, wherein the input transistor and the bootstrap transistor share a common body.

34. The circuit of claim 33 further includes a bias circuit configured to generate a bias voltage applied to the common body of the input transistor and the bootstrap transistor.

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