Self-correcting voltage maintaining circuit, power-on reset circuit, zero-power voltage maintaining circuit

Abstract

The application provides a self-correcting voltage maintaining circuit, a power-on reset circuit and a zero-power-consumption voltage maintaining circuit. The self-correcting voltage maintaining circuit comprises a first LDO circuit, a second LDO circuit, a switch group, a first switch tube, a second switch tube, a comparator and a switch search logic circuit. The circuit can start self-correction after the chip is powered on or before entering an ultra-low power consumption state, thereby adapting to different power supply voltages and working environments. The power-on reset circuit and the self-correcting voltage maintaining circuit use the same resistance branch. The zero-power-consumption voltage maintaining circuit comprises the self-correcting voltage maintaining circuit and the power-on reset circuit. Since the self-correcting voltage maintaining circuit and the power-on reset circuit share the same resistance branch, the voltage maintaining circuit does not need to introduce new power consumption and resistance area when the power-on reset circuit is used, thereby reducing the power consumption of the chip and reducing the area of the chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, specifically to a self-calibrating voltage sustaining circuit, a power-on reset circuit, and a zero-power voltage sustaining circuit. Background Technology

[0002] In applications requiring ultra-long standby time and battery power, microcontrollers (MCUs) need to operate in an ultra-low-power sleep state to reduce system power demands. In these scenarios, an ultra-low-power voltage regulator circuit needs to be integrated within the chip to maintain power to the digital power supply and SRAM (Static Random Access Memory), preserving intermediate data and states generated during MCU operation so that the MCU can return to normal operating mode for continued use.

[0003] See Figure 1 A common practice is to directly connect one or two diodes or diode-connected MOSFETs from the chip's Vcc to reduce the voltage. The number of diodes is determined by the specific manufacturing process. However, because the diode's Vth changes with the manufacturing process and temperature, the actual output voltage fluctuates significantly, sometimes exceeding the voltage range that the low-voltage diode can withstand, leading to chip reliability issues.

[0004] See Figure 2 Another common approach is to set a low-power mode LDO (low dropout regulator), i.e., a voltage sustaining circuit, under the chip's VCC to maintain the chip's digital power supply. However, setting a low-power LDO usually requires consideration of LDO stability issues, because the on-chip digital filter capacitor value is generally between several hundred picofarads and several nanofarads, making compensation of the low-power LDO somewhat difficult. If the bias current is small, the output resistance of the first-stage op-amp of the low-power mode LDO is large, and the pole position is low. However, the large filter capacitor on the digital power supply and the extremely low load current will cause the output pole position of the second-stage op-amp of the low-power mode LDO to be too low. The two poles being too close together makes compensation of the low-power mode LDO difficult. In addition, using a low-power mode LDO requires an ultra-low-power bandgap reference as a reference voltage. Otherwise, an inaccurate reference voltage of the low-power mode LDO will lead to a large deviation in the output voltage. At the same time, setting an ultra-low-power bandgap reference also brings a series of problems to the chip design, such as bandgap stability, increased area, and long startup time. Summary of the Invention

[0005] The first objective of this invention is to provide a self-calibrating voltage sustaining circuit that can automatically correct the sustaining voltage before the chip operates in an ultra-low power sleep state, and switch the power supply to the corrected sustaining voltage when entering an ultra-low power state.

[0006] A second objective of this invention is to provide a power-on reset circuit that reuses the same resistor branch as the aforementioned self-calibrating voltage sustaining circuit.

[0007] A third objective of the present invention is to provide a zero-power voltage sustaining circuit that includes the above-described zero-power voltage sustaining circuit and power-on reset circuit.

[0008] To achieve the aforementioned first objective, the present invention provides a self-calibrating voltage sustaining circuit, comprising a first LDO circuit, further comprising: a second LDO circuit, the second LDO circuit comprising a resistor branch, a switch group, a first switching transistor, a second switching transistor, a comparator, and a switch search logic module; the resistor branch comprises multiple resistors connected in series, the first end of the resistor branch being connected to a power supply terminal, and the second end being grounded; the switch group comprises multiple switches, the switch group being connected to the control terminal of the resistor branch and the first switching transistor; the switch group is used to control the number of resistors in the resistor branch connected to the control terminal of the first switching transistor; each switch is used to control the number of resistors connected to the control terminal of the first switching transistor; the first end of the first switching transistor is connected to a power supply terminal, the first... The second terminal of the switching transistor is connected to a dummy load. The control terminal of the first switching transistor is used to control the connection between the first and second terminals of the switching transistor. The control terminal of the second switching transistor is connected to the first control signal output terminal. The first terminal of the second switching transistor is connected to the second terminal of the first switching transistor. The second terminal of the second switching transistor is connected to the output terminal of the first LDO circuit. The first input terminal of the comparator is connected to the second terminal of the first switching transistor. The second input terminal of the comparator is connected to the second terminal of the second switching transistor. The output terminal of the comparator is connected to the switch search logic module. The switch search logic module is connected to the start signal output terminal, the switch group, and the dummy load. The switch search logic module is used to control the opening and closing of the switch group and to control the connection state of the dummy load.

[0009] As can be seen from the above scheme, the present invention compares the voltage output of the first LDO circuit and the voltage output of the second LDO circuit through a comparator, and controls the number of resistors in the resistor branch connected to the first switching transistor through a switch search logic module. This makes the voltage output of the second LDO circuit close to the voltage output of the first LDO circuit, which can achieve self-correction of the maintenance voltage, adapt to different voltages and working environments, and solve the reliability problems caused by the voltage inaccuracy of commonly used diode buck circuits or the difficulties in low-power mode LDO compensation and the need to design an ultra-low power bandgap reference voltage.

[0010] A further solution is to have a first filter capacitor, with its first end connected to the control terminal of the first switching transistor and its second end grounded.

[0011] Therefore, it can be seen that interference signals connected to the first switching transistor can be filtered out.

[0012] A further proposed solution is that the dummy load includes a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor is connected to the reference current input terminal, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the second terminal of the first switching transistor, and the source of the second NMOS transistor is grounded.

[0013] This demonstrates that the power consumption required by the digital circuits and SARM can be simulated when the first LDO circuit is operating.

[0014] A further embodiment is that the first LDO circuit includes a first operational amplifier, a first PMOS transistor, a third NMOS transistor, a first voltage divider resistor, and a second voltage divider resistor; the inverting input of the first operational amplifier is connected to the output of the bandgap reference voltage, the non-inverting input of the first operational amplifier is connected to the second end of the first voltage divider resistor and the first end of the second voltage divider resistor, and the output of the first operational amplifier is connected to the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected to the first end of the first voltage divider resistor, and the drain of the first PMOS transistor is connected to the output of the first LDO circuit; the second end of the second voltage divider resistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is connected to the second control signal output terminal, and the source of the third NMOS transistor is grounded.

[0015] A further solution is to use a second filter capacitor, with its first end connected to the output of the first LDO circuit and its second end grounded.

[0016] Therefore, it can be seen that interference signals at the output of the self-calibrating voltage sustaining circuit can be filtered out.

[0017] A further approach is to make the first control signal output terminal an output terminal in the switch search logic module.

[0018] A further approach is to make the second control signal output terminal an output terminal in the switch search logic module.

[0019] To achieve the second objective mentioned above, the present invention provides a power-on reset circuit, comprising a resistor branch, which includes multiple resistors connected in series. The first end of the resistor branch is connected to a power supply terminal, and the second end is grounded. The circuit also includes: a third voltage divider resistor, a fourth voltage divider resistor, a second PMOS transistor, a fourth NMOS transistor, and an inverter. The third and fourth voltage divider resistors are connected in series. The first end of the third voltage divider resistor is connected to the power supply terminal, and the second end of the third voltage divider resistor is connected to the first end of the fourth voltage divider resistor. The second end of the fourth voltage divider resistor is connected to the drain of the fourth NMOS transistor and the input terminal of the inverter. The gate of the fourth NMOS transistor is connected to the resistor branch, the drain of the fourth NMOS transistor is connected to the input terminal of the inverter, and the source of the fourth NMOS transistor is grounded. The output terminal of the inverter is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is connected to the second end of the third voltage divider resistor.

[0020] As can be seen from the above scheme, the inverter is rapidly flipped by forming local positive feedback, achieving a rapid reset effect. Furthermore, by using the same resistor branch, the chip area can be reduced.

[0021] To achieve the third objective mentioned above, the present invention provides a zero-power voltage sustaining circuit, including the self-calibrating voltage sustaining circuit and the power-on reset circuit, wherein the resistor branch of the self-calibrating voltage sustaining circuit and the resistor branch of the power-on reset circuit share a common resistor branch.

[0022] As can be seen from the above scheme, since the self-calibrating voltage sustaining circuit and the power-on reset circuit reuse the same resistor branch, the voltage sustaining circuit does not need to introduce new power consumption and resistor area when using the above power-on reset circuit, thereby reducing the power consumption of the chip and reducing the chip area. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a voltage sustaining circuit that uses diodes to reduce voltage in existing technologies.

[0024] Figure 2 This is a circuit diagram of a voltage sustaining circuit using a low-power mode LDO in the prior art.

[0025] Figure 3 This is a circuit diagram of a portion of the second LDO circuit in an embodiment of the self-calibrating voltage sustaining circuit of the present invention.

[0026] Figure 4 This is a circuit diagram of an embodiment of the self-calibrating voltage maintenance circuit of the present invention.

[0027] Figure 5 This is a circuit diagram of an embodiment of the power-on reset circuit of the present invention.

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0029] The self-calibrating voltage sustaining circuit of the present invention can perform self-calibration according to actual needs during chip power-on and / or chip operation. The power-on reset circuit reuses the resistor branch of the self-calibrating voltage sustaining circuit. The zero-power voltage sustaining circuit includes the self-calibrating voltage sustaining circuit and the power-on reset circuit.

[0030] It should be noted that the terms "first," "second," "third," and "fourth" in this invention are used only to distinguish between similar things and do not have any meaning of order.

[0031] Example of a self-calibrating voltage sustaining circuit:

[0032] See Figure 3 and Figure 4 The self-calibrating voltage sustaining circuit includes a first LDO circuit M1 and a second LDO circuit M2. The second LDO circuit M2 includes a resistor branch 11, a switch group 12, a first switch MN1A, a second switch MN2A, a comparator CMP, a switch search logic module 13, and a dummy load 14. In this embodiment, the first switch is an NMOS transistor with its control terminal as the gate, its first terminal as the drain, and its second terminal as the source; the second switch is also an NMOS transistor with its control terminal as the gate, its first terminal as the drain, and its second terminal as the source.

[0033] Resistor branch 11 includes multiple resistors 111 connected in series. The first end of resistor branch 11 is connected to the power supply terminal Vcc, and the second end of resistor branch 11 is grounded. The first end and the second end of resistor branch 11 represent the two ends of resistor branch 11, and multiple resistors 111 are connected in series from the first end of resistor branch 11 to the second end.

[0034] The switch group 12 includes multiple switches (SW1, SW2, SW3, ..., SWN), which are connected to the resistor branch 11 and the gate of the first switching transistor MN1. The multiple switches on the switch group 12 are respectively connected to resistors in the resistor branch 11. By closing and opening the switches, the resistors in the resistor branch 11 are connected to the gate of the first switching transistor MN1A. Each switch can control the number of resistors connected to the gate of the first switching transistor MN1A. It should be noted that different switches can control the number of resistors connected to the first switching transistor MN1A. For example, when switch SW0 is closed and other switches are open, six resistors can be controlled to be connected to the first switching transistor MN1A. That is, the switch group 12 can be used to control the number of resistors connected to the first switching transistor MN1A. A first filter capacitor Cap1 is also connected between the switch group 12 and the first switch transistor MN1A. The first end of the first filter capacitor Cap1 is connected to the control terminal of the switch group 12 and the first switch transistor MN1A, and the second end of the first filter capacitor Cap1 is grounded. The first end of the first filter capacitor Cap1 is the end closer to node A, and the second end of the first filter capacitor Cap1 is the end farther away from node A.

[0035] The first terminal of the first switching transistor MN1A is connected to the power supply terminal Vcc, and the second terminal of the first switching transistor MN1A is connected to the dummy load 14. The control terminal of the first switching transistor is used to control the connection between the first terminal and the second terminal of the first switching transistor MN1A. The dummy load 14 includes a first NMOS transistor MN1 and a second NMOS transistor MN2. The drain of the first NMOS transistor MN1 is connected to the reference current input terminal (not shown in the figure), the source of the first NMOS transistor MN1 is grounded, and the gate of the first NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2. The drain of the second NMOS transistor MN2 is connected to the second terminal of the first switching transistor MN1A, and the source of the second NMOS transistor MN2 is grounded.

[0036] The control terminal of the second switching transistor MN2A is the first control signal output terminal (not shown in the figure). The first terminal of the second switching transistor MN2A is connected to the second terminal of the first switching transistor MN1A, and the second terminal of the second switching transistor MN2A is connected to the output terminal of the first LDO circuit, which is at node C. The first terminal of the second filter capacitor Cap2 is connected to node C, and the second terminal of capacitor Cap2 is grounded. The first terminal of capacitor Cap2 is the end closer to node C, and the second terminal is the end farther away from node C. The second filter capacitor Cap2 also serves a filtering function, preventing transient currents generated by digital circuit switching from causing glitches in the output of the first LDO circuit M1 or the second LDO circuit M2.

[0037] The first input terminal of comparator CMP is connected to the second terminal of the first switch MN1A, the second input terminal of comparator CMP is connected to the second terminal of the second switch, and the output terminal of comparator CMP is connected to the switch search logic module 13. The first terminal of comparator CMP is the terminal closer to node B, and the second terminal of comparator CMP is the terminal farther away from node B.

[0038] The switch search logic module 13 is connected to the start signal output terminal (not shown in the figure) and receives the start signal Cal start from the start signal output terminal. The switch search logic module 13 is connected to switch group 12 (connection relationship not shown in the figure). The switch search logic module 13 is used to control the closing and opening of the switches in switch group 12, and to control the connection state of the dummy load 14, that is, to control the connection and disconnection of the dummy load.

[0039] The first LDO circuit includes a first operational amplifier OA1, a first PMOS transistor MP1, a third NMOS transistor MN3, a first voltage divider resistor R1, and a second voltage divider resistor R2. The first end of the first voltage divider resistor R1 is closer to the first PMOS transistor MP1, and the second end is farther away from the first PMOS transistor MP1. The first end of the second voltage divider resistor R2 is closer to the first voltage divider resistor R1, and the second end is farther away from the first voltage divider resistor R1.

[0040] The inverting input of the first operational amplifier OA1 is connected to the output of the bandgap reference voltage (not shown in the figure), and receives the bandgap reference voltage VBGR from the output of the bandgap reference voltage. The non-inverting input is connected to the second end of the first voltage divider resistor R1 and the first end of the second voltage divider resistor R2. The output is connected to the gate of the first PMOS transistor MP1.

[0041] The source of the second PMOS transistor MP1 is connected to the power supply terminal Vcc, and the drain is connected to the first terminal of the voltage divider resistor R1. The drain is also connected to the output terminal of the first LDO circuit M2, i.e., node C.

[0042] The second end of the second voltage divider resistor R2 is connected to the drain of the third NMOS transistor MN3, the source of the third NMOS transistor MN3 is connected to the second control signal output terminal (not shown in the figure), and the source of the third NMOS transistor is grounded.

[0043] For ease of explanation, the self-calibrating voltage sustaining circuit of this embodiment is also connected to a digital circuit. This digital circuit is one that requires power to maintain operation even when the chip using the self-calibrating voltage sustaining circuit of this embodiment is operating in an ultra-low power state. Optionally, it is also connected to an SRAM (Static Random-Access Memory). When the chip is not operating in an ultra-low power state, the first LDO circuit M1 provides sustaining voltage to the digital circuit and the SRAM; at this time, the load current and power consumption are relatively high. When the chip is operating in an ultra-low power state, the second LDO circuit M2 provides sustaining voltage to the digital circuit and the SRAM; at this time, the load current and power consumption are relatively low.

[0044] The working principle of the above self-calibrating voltage sustaining circuit is further explained below:

[0045] See Figure 3 By controlling switch group 12, the switch to be turned on is selected, and the resistor of control resistor branch 11 is connected to node A. Since the power supply terminal Vcc is connected to resistor branch 11, the voltage at node A can be obtained by voltage division based on the resistor connected to resistor branch 11. This voltage value is filtered by the first filter capacitor Cap1 to remove glitches and fluctuations, and then the opening degree of the first switch transistor MN1A is controlled, thereby adjusting the voltage at node B. The first switch transistor MN1A is an NMOS transistor that maintains a stable voltage in low-power mode. In order not to limit the power supply terminal Vcc, a native NMOS transistor with a near-zero Vth, which is commonly available in CMOS technology, is further used. Since the voltage at point B can be adjusted by selecting different switches in switch group 12, the voltage at point B can be adjusted and accurately determined.

[0046] Refer to Figure 4 Before the chip is powered on or enters an ultra-low power state, the first LDO circuit M1 provides the sustaining voltage for the digital circuit and SRAM, which is provided from node C. Specifically, the source and drain of the third NMOS transistor are connected, and the voltage at node C is determined by VBGR and the first and second voltage divider resistors, and is independent of temperature.

[0047] Continue to refer to Figure 4The chip can enter an ultra-low power state after power-on reset or during chip operation. Before entering the ultra-low power state, the first LDO circuit M1 can stably provide a sustaining voltage to the digital circuits and SRAM. Before entering the ultra-low power state, the chip needs to complete the self-calibration process of the second LDO circuit M2. Specifically, the switch search logic module 13 starts self-calibration after receiving the start signal Cal start from the start signal output terminal. The self-calibration process can start after the chip is normally reset and / or during chip operation. When the self-calibration process is performed after the chip is normally reset, the start signal Cal start can be obtained from the delayed signal of the power-on reset circuit signal inside the chip. At this time, the start signal output terminal is set at the output terminal of the power-on reset circuit. That is, after the chip's power-on reset circuit is working, the first LDO circuit M1 is ensured to be stable during the delay period, and then the second LDO circuit M2 starts the self-calibration process. During the self-calibration process, the start signal Cal start can be generated by a preset program inside the chip (in this embodiment, the chip is an MCU and the preset program is an MCU program). That is, the second LDO circuit M2 can output the start signal Cal start to the switch search logic module 13 by the preset program as the working environment changes such as voltage and temperature. At this time, the start signal output terminal is the data bus. After receiving the start signal Cal start, the switch search logic module 13 performs a logic reset and the second LDO circuit M2 starts self-calibration.

[0048] When the second LDO circuit M2 starts self-calibration, the switch search logic module 13 receives the start signal Cal_start and performs a logic reset. That is, the switch search logic module 13 controls the switch SW0 at the lowest position to close while the other switches are open, and connects the resistor with the most power to the first switch MN1A. Simultaneously, the comparator CMP detects that the voltage value of node B is lower than the voltage value of node C, and outputs a low-level signal to the switch search logic module 13. Upon receiving the low-level signal from the comparator CMP, the switch search logic module 13 controls the active switches in switch group 12 to jump to the next higher level, i.e., closing switch SW1 and opening other switches. If the comparator CMP still detects that the voltage value of node B is lower than the voltage value of node C, it maintains the low-level output signal to the switch search logic module 13. The switch search logic module 13 continues to control the active switches in switch group 12 to jump to the next higher level until the comparator CMP detects that the voltage value of node B is greater than the voltage value of node C. At this point, the comparator CMP output signal jumps to a high level, and the switch search logic module 13 moves the currently active switch back one level and locks the current state. At this time, the voltage value of node B is closest to the sustaining voltage value provided by the second LDO circuit M2. The voltage value of node B can be used to power the chip's digital circuits and SRAM. After calibration, when the chip executes the instruction to enter the ultra-low power state, the second switch MN2A receives a signal from the first control signal output terminal connecting its first and second terminals, causing the voltage value at node B to power the chip's digital circuitry and SRAM. Simultaneously, the switch search logic module 13 controls the dummy load 14 to disconnect, and the third NMOS transistor receives a signal from the second control signal output terminal, disconnecting the drain and source of the third NMOS transistor MN3. In this embodiment, the first and second control signal output terminals are each an output terminal of the switch search logic module 13. When the MCU program enters the ultra-low power state, the switch search logic module 13 outputs corresponding signals through its output terminals to control the second switch MN2A to connect its first and second terminals and disconnect the drain and source of the third NMOS transistor MN3. Similarly, the disconnection of the dummy load 14 can also be achieved by connecting it to another output terminal of the switch search logic module 13, and a corresponding control signal is output to disconnect it when the comparator CMP signal is high.It is understandable that the first and second control signal output terminals may not be the output terminals on the switch search logic module 13. As long as the chip enters the ultra-low power state, both the first and second control signal output terminals will output signals to connect the first and second terminals of the second switch transistor MN2A and disconnect the drain and source of the third NMOS transistor MN3. When the MCU enters the ultra-low power state, the digital circuit on the MCU will provide corresponding indication signals to the analog circuit to shut down the first LDO circuit M1, BGR, clock, and other modules. Similarly, in the actual design of the self-calibrating voltage regulator circuit of this invention, specific indication signals can be designed to shut down the second switch transistor MN2A and disconnect the third NMOS transistor MN3. In this case, the first and second control signal output terminals are the digital circuits in the MCU capable of outputting these specific indication signals. It should be noted that the switch search logic module 13 is a digital circuit module and can be implemented by digital control logic circuits.

[0049] It should be noted that, optionally, when the chip is powered on and reset, and during normal operation of the chip, the second LDO circuit M2 needs to perform self-calibration. The output of the power-on reset circuit and the input of the data bus connected to the OR gate, and the output of the OR gate output a start signal Cal start to the switch search logic module 13. At this time, the chip can be powered on and reset, and after a certain delay, the second LDO circuit M2 performs a self-calibration. During the chip's operation, the MCU program written by the user according to actual needs is executed, and the start signal Cal start is output to the switch search logic module 13 through the data bus, so that the switch search logic module 13 performs a second self-calibration. The purpose of setting up a second self-calibration is to reduce the influence of the working environment and make the self-calibration results more accurate. Although the voltage output by the first LDO circuit M1 is a temperature-independent voltage obtained by resistor voltage division, in the second LDO circuit M2, resistor branch 11 divides the voltage of the power supply terminal Vcc. If the chip is powered on and does not lose power, and the voltage of the power supply terminal Vcc is powered by the battery and the battery works for a long time, the voltage of the power supply terminal Vcc will gradually decrease with the chip's working time, falling below the voltage of the power supply terminal Vcc at the beginning of power-on. This results in the actual voltage of node B being lower than the voltage of node B after the initial self-calibration. Secondly, since the first switching transistor MN1 is a MOSFET, the main voltage drop is the transistor's Vgs, which is closely related to the transistor's Vth. Since Vth has a negative temperature characteristic, if the ambient temperature changes during the chip's operation, the actual voltage at node B will also change, thus requiring a second self-calibration.

[0050] The dummy load 14 allows the self-calibrating voltage sustaining circuit to simulate the leakage current from the power supply Vcc to the digital circuits and SRAM when the chip is operating in an ultra-low power state during calibration. This is achieved through the current Iload and the voltage at node B, where Iref is the reference current. The value of Iload is typically determined based on the process technology used and the project's assessment of the leakage current level of the digital circuits under that process. Iload can be obtained through actual testing or parameters provided by the process manufacturer. The value of Iref, based on the magnitude of Iload, provides an on-chip leakage load simulation via current mirroring, aiming to closely approximate the actual low-power load conditions of the chip during automatic calibration. The first NMOS transistor obtains the reference current through the reference current input terminal, which can be provided by an internal current source within the chip. After calibration, the dummy load 14 can be disconnected, and the sustaining voltage for the digital circuits and SRAM operating in the ultra-low power state is then provided by the voltage at node B.

[0051] Because the self-calibrating voltage sustaining circuit adjusts the voltage through open-loop calibration, it does not require a bandgap reference voltage, and there are no low-power design requirements for the bandgap. The bandgap can be shut off when the chip is operating in ultra-low power mode. As long as the bandgap start-up speed is fast, it can quickly return to normal during the switch between ultra-low power and normal operating states. Furthermore, since the bandgap does not require low-power design, fast bandgap start-up is relatively easy to achieve. In addition, because the self-calibrating voltage sustaining circuit lacks closed-loop feedback, there are no stability design considerations, simplifying design requirements.

[0052] Example of a power-on reset circuit:

[0053] Reference Figure 5 This embodiment includes a resistor branch 11, a third voltage divider resistor R3, a fourth voltage divider resistor R4, a second PMOS transistor MP2, a fourth NMOS transistor MN4, and an inverter, which is a Schmitt inverter SMIT1.

[0054] The first end of the third voltage divider resistor R3 is the end closest to the power supply terminal Vcc, and the second end is the end furthest from the power supply terminal Vcc. The first end of the fourth voltage divider resistor R4 is the end closest to the third voltage divider resistor R3, and the second end is the end furthest from the third voltage divider resistor R3.

[0055] The third voltage divider resistor R3 and the fourth voltage divider resistor R4 are connected in series. The first end of the third voltage divider resistor R3 is connected to the power supply terminal Vcc, and the second end of the third voltage divider resistor R3 is connected to the first end of the fourth voltage divider resistor R4. The second end of the fourth voltage divider resistor R4 is connected to the drain of the fourth NMOS transistor MN4 and the input terminal of the Schmitt inverter SMIT1. The gate of the fourth NMOS transistor MN4 is connected to resistor branch 11, the drain of the fourth NMOS transistor is connected to the input terminal of the Schmitt inverter SMIT1, and the source of the fourth NMOS transistor MN4 is grounded. The output terminal of the Schmitt inverter SMIT1 is connected to the gate of the second PMOS transistor MP2, the source of the second PMOS transistor MP2 is connected to the power supply terminal Vcc, and the drain of the second PMOS transistor MP2 is connected to the second end of the third voltage divider resistor R3.

[0056] The working principle of the power-on reset circuit is as follows:

[0057] When the power supply voltage Vcc starts to rise, initially, because the fourth NMOS transistor MN4 is off, the voltage at V2 follows the power supply voltage Vcc, and the POR_B output is low. The second PMOS transistor is connected in parallel with the third voltage divider resistor R3, thereby reducing the voltage of the third voltage divider resistor R3. As the power supply voltage Vcc gradually rises, the voltage at the voltage divider point V1 rises proportionally, while the voltage at V2 slowly decreases. When the voltage at V1 rises to the Vth of the fourth NMOS transistor MN4, the fourth NMOS transistor MN4 is fully turned on, and the voltage at V2 begins to drop rapidly. When it falls below the switching voltage of the Schmitt inverter SMIT1, the output of the Schmitt inverter SMIT1 goes high, gradually turning off the second PMOS transistor. This causes the third voltage divider resistor R3 and the fourth voltage divider resistor R4 to form a larger resistance, further causing the voltage at V2 to drop. The POR_B output voltage rises further, forming local positive feedback, which causes the voltage at V2 to quickly move away from the switching threshold voltage of the Schmitt inverter SMIT1. The POR_B output reaches Vcc, and the power-on reset process ends.

[0058] Zero-power voltage sustaining circuit example:

[0059] The zero-power voltage sustaining circuit of this embodiment includes the self-calibrating sustaining circuit of the above-described self-calibrating voltage sustaining circuit embodiment and the power-on reset circuit of the above-described power-on reset circuit embodiment. The specific structure and working principle will not be described in detail here.

[0060] The resistor branch in the zero-power voltage sustaining circuit reuses the resistor branch in the power-on reset circuit. That is, the zero-power voltage sustaining circuit uses only one resistor branch, and the power-on reset circuit and the self-calibrating voltage sustaining circuit share the same resistor branch. If the chip uses the aforementioned power-on reset circuit, using the aforementioned self-calibrating voltage sustaining circuit will not introduce new power consumption or resistor area, thus saving the chip's final power consumption and area. In this sense, the self-calibrating voltage sustaining circuit in the zero-power voltage sustaining circuit is a zero-power voltage regulator circuit.

[0061] In summary, the self-calibrating voltage sustaining circuit of the present invention can initiate self-calibration immediately after the chip is powered on and / or before the chip operates in an ultra-low power state, thereby adapting to different power supply voltages and operating environments. The power-on reset circuit and the self-calibrating voltage sustaining circuit use the same resistor branch, which can reduce the chip area. The zero-power voltage sustaining circuit includes the aforementioned self-calibrating voltage sustaining circuit and the power-on reset circuit. Since the self-calibrating voltage sustaining circuit and the power-on reset circuit reuse the same resistor branch, when using the aforementioned power-on reset circuit, the voltage sustaining circuit does not need to introduce new power consumption and resistor area, thereby reducing the chip's power consumption and shrinking the chip area.

Claims

1. A self-calibrating voltage sustaining circuit, comprising a first LDO circuit, characterized in that, Also includes: The second LDO circuit includes a resistor branch, a switch group, a first switch transistor, a second switch transistor, a comparator, and a switch search logic module. The resistor branch includes multiple resistors connected in series. The first end of the resistor branch is connected to the power supply terminal, and the second end is grounded. The switch group includes multiple switches, and the switch group connects the resistor branch to the control terminal of the first switching transistor; the switch group is used to control the number of resistors in the resistor branch connected to the control terminal of the first switching transistor; each switch is used to control the number of resistors connected to the control terminal of the first switching transistor. The first end of the first switching transistor is connected to the power supply terminal, the second end of the first switching transistor is connected to the dummy load, and the control terminal of the first switching transistor is used to control the connection between the first end of the switching transistor and the second end of the switching transistor. The control terminal of the second switch is connected to the first control signal output terminal, the first terminal of the second switch is connected to the second terminal of the first switch, and the second terminal of the second switch is connected to the output terminal of the first LDO circuit. The first input terminal of the comparator is connected to the second terminal of the first switching transistor, the second input terminal of the comparator is connected to the second terminal of the second switching transistor, and the output terminal of the comparator is connected to the switch search logic module. The switch search logic module is connected to the start signal output terminal, the switch group, and the dummy load. The switch search logic module is used to control the closing and opening of the switches in the switch group and to control the connection state of the dummy load. The dummy load includes a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor is connected to the reference current input terminal, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the second terminal of the first switching transistor, and the source of the second NMOS transistor is grounded.

2. The self-calibrating voltage sustaining circuit as described in claim 1, characterized in that, Also includes: The first filter capacitor has its first end connected to the control terminal of the first switching transistor, and its second end grounded.

3. The self-calibrating voltage sustaining circuit as described in claim 1, characterized in that: The first LDO circuit includes a first operational amplifier, a first PMOS transistor, a third NMOS transistor, a first voltage divider resistor, and a second voltage divider resistor; The inverting input terminal of the first operational amplifier is connected to the output terminal of the bandgap reference voltage, the non-inverting input terminal of the first operational amplifier is connected to the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor, and the output terminal of the first operational amplifier is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected to the first terminal of the first voltage divider resistor, and the drain of the first PMOS transistor is connected to the output terminal of the first LDO circuit. The second end of the second voltage divider resistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is connected to the output terminal of the second control signal, and the source of the third NMOS transistor is grounded.

4. The self-calibrating voltage sustaining circuit as described in any one of claims 1 to 3, characterized in that, Also includes: The second filter capacitor has its first end connected to the output terminal of the first LDO circuit, and its second end grounded.

5. The self-calibrating voltage sustaining circuit as described in any one of claims 1 to 3, characterized in that: The first control signal output terminal is an output terminal of the switch search logic module.

6. The self-calibrating voltage sustaining circuit as described in claim 3, characterized in that: The second control signal output terminal is an output terminal of the switch search logic module.

7. A zero-power voltage sustaining circuit, characterized in that: Includes the self-calibrating voltage sustaining circuit and power-on reset circuit as described in any one of claims 1 to 6; The power-on reset circuit includes: Third voltage divider resistor, fourth voltage divider resistor, second PMOS transistor, fourth NMOS transistor, inverter; The third voltage divider resistor is connected in series with the fourth voltage divider resistor. The first end of the third voltage divider resistor is connected to the power supply terminal, and the second end of the third voltage divider resistor is connected to the first end of the fourth voltage divider resistor. The second end of the fourth voltage divider resistor is connected to the drain of the fourth NMOS transistor and the input terminal of the inverter. The gate of the fourth NMOS transistor is connected to the resistor branch, the drain of the fourth NMOS transistor is connected to the input terminal of the inverter, and the source of the fourth NMOS transistor is grounded. The output terminal of the inverter is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is connected to the second terminal of the third voltage divider resistor.

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