Data bus signal conditioner and level shifter

Abstract

A circuit (206) includes signal conditioner circuitry (208), level shifter circuitry (212), and state detector and controller circuitry (210) coupled between the signal conditioner circuitry (208) and the level shifter circuitry (212). The state detector and controller circuitry (210) includes receiver circuitry (228-238) and a finite state machine (222) coupled to the receiver circuitry (228-238). The finite state machine (222) is configured to detect a first data rate from a signal, control operation of the signal conditioner circuitry (208) in response to detecting the first data rate, and control operation of the level shifter circuitry (212) during a second data rate.

Description

Technical Field

[0001] This invention generally relates to data bus interfaces, and more specifically, to data bus signal conditioners and level shifters. Background Technology

[0002] Data buses that include buses conforming to one or more Universal Serial Bus (USB) industry standard specifications (generally referred to herein as USB) are widely used to facilitate communication between devices. The expansion of USB has resulted in a variety of USB-compatible devices with different communication and power requirements. For example, the embedded USB industry standard specification (generally referred to herein as eUSB2) enables reduced-power communication between devices (such as integrated circuits (ICs) or chips mounted on a circuit board or included in an assembly within a computer system). However, while eUSB2 allows serial communication between devices at reduced voltages, as device feature sizes decrease and the distance between devices on circuit boards or other assemblies increases, additional mechanisms are needed to support continuous communication between devices.

[0003] For example, some standards recommend implementing certain buses that are shorter than the specified maximum length. Buses longer than the specified maximum length can lead to data degradation on the bus. Additionally, power supply limitations (such as voltage sources and ground) can affect the specified maximum length of the bus. To facilitate longer bus lengths, some standards specify what types of repeaters can be used (e.g., hybrid repeaters specified by eUSB2). However, such repeaters require complex state machines and may degrade data passing through them. Furthermore, the specified repeaters require higher power. Summary of the Invention

[0004] In one example, a circuit includes a signal conditioner circuit system, a level shifter circuit system, and a state detector and controller circuit system coupled between the signal conditioner circuit system and the level shifter circuit system. The state detector and controller circuit system includes a receiver circuit system and a finite state machine coupled to the receiver circuit system. The finite state machine is configured to detect a first data rate from a signal, control the operation of the signal conditioner circuit system in response to detecting the first data rate, and control the operation of the level shifter circuit system during a second data rate.

[0005] In another example, an intermediate circuit is adapted to couple between first and second communication devices using first and second conductors and is operable to facilitate communication between the first and second communication devices. The intermediate circuit includes a state detector and controller circuit having first and second outputs adapted to be coupled to the first and second conductors. The intermediate circuit also includes a signal conditioning circuit coupled to the first output and adapted to be coupled to the first and second conductors, and a level shifter coupled to the second output and adapted to be coupled to the first and second conductors. The state detector and controller circuit is configured to: detect a communication state; enable the signal conditioning circuit in response to detecting a first communication state; and enable the level shifter during a second communication state. For example, the first communication state is a high-speed data rate, and the second communication state is a low-speed data rate or a full-speed data rate.

[0006] In another example, a system includes a first integrated circuit, a second integrated circuit, and intermediate circuitry coupled between the first and second integrated circuits. The intermediate circuitry includes a first switch, a signal conditioner circuitry configured to boost signal edges during a closed state of the first switch, a second switch, a level shifter circuitry operable during a closed state of the second switch, and a state detector and controller circuitry. The state detector and controller circuitry includes a receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from a signal received from the receiver circuitry, close the first switch in response to detecting the first data rate, and close the second switch during a second data rate.

[0007] In another example, a method includes receiving a signal and detecting a first data rate from the signal. The method further includes: operating a signal conditioner circuitry in response to detecting the first data rate to boost the signal edge; and operating a level shifter circuitry during a second data rate to shift the voltage level of the signal from a first voltage level to a second voltage level. Attached Figure Description

[0008] Figure 1 This is a block diagram depicting an example system with intermediate devices, which include a signal conditioner, a level shifter, and a state detector and controller circuit system.

[0009] Figure 2 This is a schematic diagram depicting an example eUSB2 system with an intermediate device, which includes a signal conditioner, a level shifter, and a state detector and controller circuitry.

[0010] Figure 3This is a schematic diagram depicting an example level shifter circuit system.

[0011] Figure 4 This is a schematic diagram depicting an example signal conditioner circuit system.

[0012] Figure 5 It is a description Figure 4 A schematic diagram illustrating some details of the high-speed signal booster described in the document.

[0013] Figure 6 This is a schematic diagram and state diagram depicting an example low-power mode detector circuit system.

[0014] Figure 7 It is a description of Figure 6 The circuitry in the diagram can detect a signaling diagram of a differential signal used to generate a clock signal for low-power mode detection.

[0015] Figure 8 It is a description and explanation by Figure 6 Signaling diagram of the simulation results of low-power mode detection performed by the circuit system in the diagram.

[0016] Figure 9 This is a flowchart of an example method for operating an intermediate device that includes a signal conditioner, a level shifter, and a state detector and controller circuit system.

[0017] Figure 10 This is a flowchart of another example method for operating an intermediate device that includes a signal conditioner, a level shifter, and a state detector and controller circuitry system.

[0018] The same reference numerals are used in the accompanying drawings to depict the same or similar (e.g., structural and / or functional) features. Features in the accompanying drawings are not necessarily drawn to scale. Detailed Implementation

[0019] In some of the described examples, an intermediate device is used between two devices and / or buses. In some examples, the intermediate device uses a simplified state machine that does not utilize protocol handshakes defined by certain bus standards (e.g., eUSB2). For example, the intermediate device includes a receiver circuitry that senses a voltage, and in response to said voltage, a state machine (e.g., a digital finite state machine) controls the operation of a signal conditioning circuitry and a level shifter circuitry. In some examples, signal conditioning involves edge boosting instead of repeated grouping. Furthermore, in some examples, the level shifter circuitry enables communication between devices operating at different voltage source levels and ground.

[0020] First refer to Figure 1This is a block diagram depicting a system 100 according to the described example. System 100 includes two devices 102 and 104 and an intermediate device 106. In one example, devices 102 to 106 are contained in or on the same physical arrangement or assembly 114. For example, physical arrangement 114 is a computer system, such as a laptop computer, desktop computer, mobile phone, tablet computer, wearable device, television, or monitor. In another example, physical arrangement 114 is a circuit board, such as a printed circuit board (PCB). Furthermore, although only two devices 102 and 104 and one intermediate device 106 are shown, additional such devices may be included in system 100.

[0021] Devices 102 and 104 can communicate on data bus 101 (also referred to herein as bus 101) using a communication protocol, and are therefore also referred to herein as communication devices. For example, bus 101 may include one or more conductors for transmitting signaling or communication between devices 102 and 104. Furthermore, the conductors may include one or more traces or other types of signal lines. In some instances, the conductors of bus 101 terminate at intermediate device 106, such as at level shifter circuitry 112, so that devices 102 and 104 do not have a direct electrical connection. In other instances, the conductors of bus 101 flow through intermediate device 106, such as at signal conditioner circuitry 108, so that devices 102 and 104 can maintain a direct electrical connection.

[0022] In another example, devices 102 and 104 include a circuitry (not shown) that implements serial communication on bus 101 using a communication protocol defined by eUSB2, consistent with and / or compatible with eUSB2 (e.g., the USB version 2.0 specification, version 1.1 or earlier or later eUSB2 specification, the embedded USB2 (eUSB2) physical layer supplement), the specifications of which are incorporated herein by reference. Devices that can communicate using protocols defined by eUSB2, consistent with and / or compatible with eUSB2, are referred to as eUSB2 devices, and the bus, cable or other electrical connection providing such communication between eUSB2 devices is referred to as an eUSB2 bus.

[0023] Examples of devices 102 and 104 include ICs or packaged systems, such as system-on-a-chip (SoC), data storage or memory devices, eUSB2 repeaters, etc. Furthermore, as eUSB2 devices, devices 102 and 104 may include circuitry (not shown) for native communication when neither device 102 nor 104 is an eUSB2 repeater, or for repeater communication when one of devices 102 or 104 is an eUSB2 repeater.

[0024] Intermediate device 106 facilitates communication between devices 102 and 104 on bus 101. Intermediate device 106 includes a signal conditioner (or regulation) circuit system 108, a status detector and controller circuit system 110, and a level shifter circuit system 112 (or simply level shifter 112). The components or elements 108 to 112 of intermediate device 106 may be contained on a single semiconductor substrate (and packaged in a single semiconductor package), on multiple semiconductor substrates (and packaged in a single semiconductor package as a single IC), or in multiple IC packages and included as a module, separate from devices 102 and 104.

[0025] The status detector and controller circuitry 110 monitors signaling on bus 101, for example, one or more signals or signal sequences contained in one or more eUSB2 packets and / or control commands or messages. The status detector and controller circuitry 110 then detects the communication status on bus 101 (also referred to herein as bus status or simply status) from the signaling. Furthermore, depending on the detected status, the status detector and controller circuitry 110 controls, for example, to enable or disable the operation of signal conditioner circuitry 108 and / or level shifter circuitry 112.

[0026] To monitor signaling on bus 101 and detect bus status, the status detector and controller circuitry 110 includes a receiver circuitry (not shown) coupled to bus 101 to receive signaling and one or more finite state machines (not shown) for detecting bus status from the received signaling. The detected status may include or indicate port configuration at startup, data (e.g., bit) rate or other data communication speed used for communication, pause or resumption of communication, entry or exit from low-power mode or other power management states, reset of devices on the bus, device connection or disconnection, etc.

[0027] In one example, upon detecting a first data rate (e.g., eUSB2 high-speed data rate), the state detector and controller circuitry 110 enables the signal conditioner circuitry 108 and disables the level shifter circuitry 112. Conversely, upon detecting a second data rate (e.g., eUSB2 low-speed or full-speed data rate), the state detector and controller circuitry 110 disables the signal conditioner circuitry 108 and enables the level shifter circuitry 112. In another example, upon detecting a low-power mode or state, such as the eUSB2 L1 power state (also referred to herein as L1 state), the state detector and controller circuitry 110 causes the intermediate device 106 to enter a low-power mode or state by disabling all or part of the signal conditioner circuitry 108. While in a low-power mode or state, the intermediate device 106 may also disable all or part of the level shifter circuitry 112. Entering a low-power mode achieves power savings.

[0028] Level shifter circuitry 112 translates signals on bus 101 from one logic level or voltage domain to another between devices 102 and 104. In this example, level shifter circuitry 112 translates signals at the bit level (e.g., one bit at a time) without using a retimer circuitry, and is therefore referred to herein as a “bit-level repeater.” This allows communication on bus 101 between devices 102 and 104 (comprising two eUSB2 devices) when the devices have different power and ground levels, offering the advantage of protocol independence, meaning it is independent of the communication protocol used between the devices. This contrasts with eUSB2 hybrid repeaters, which require: eUSB2-compliant ports, retimers and full clock and data recovery (CDR) circuitry, and the ability to perform a “packet-level repeater” by translating entire packets and control commands or messages between eUSB2 devices. Therefore, the bit-level repeater described herein can be advantageously implemented with less complexity and associated costs compared to an eUSB2 hybrid repeater.

[0029] A further advantage of the level shifter circuit system 112 is that it enables communication between devices 102 and 104 as the feature size of one or more components of the device (e.g., transistors) shrinks. For example, eUSB2 currently supports devices operating at 1.2 and 1.0 volts (V) (e.g., supporting 5 nanometer (nm) process nodes), where the level shifter circuit system 112 can directly translate signals at the bit level between two eUSB2 devices. As feature sizes shrink, for example, for 3nm and 2nm process nodes with associated lower voltage domains (e.g., 0.8V) and other process nodes, the level shifter circuit system 112 can translate signals between additional voltage domains. This advantageously allows the use of an intermediate device 106 to support bit-level translation from eUSB2 device to eUSB2 device, as eUSB2 expands to accommodate lower voltage domains.

[0030] The signal conditioner circuitry 108 includes a signal booster circuitry (not shown) that boosts signaling power on bus 101, without the complexity of acting as a packet repeater. In this example, during eUSB2 high-speed signaling, the signal conditioner circuitry 108 regulates the signal on bus 101 by detecting the edges of the differential signal on bus 101 and injecting differential current into bus 101. Injecting current into bus 101 increases the rate of edge transitions and correspondingly reduces the transition time of edges on bus 101, which improves the eye diagram of the signal and allows for an increase in the length of bus 101. Therefore, the signal conditioner circuitry 108 can advantageously overcome the 10-inch maximum trace length limitation between two eUSB2 devices to meet the eye diagram constraints defined in the eUSB2 specification. In some applications where larger board sizes or flexible cable connections are desired, using a longer bus is beneficial.

[0031] Figure 2 The eUSB2 system 200 is depicted according to the described example. System 200 is... Figure 1 An example implementation of system 100. System 200 includes two eUSB2 devices 202 and 204 and an intermediate device 206. eUSB2 devices 202 and 204 are example implementations of devices 102 and 104, and intermediate device 206 is an example implementation of intermediate device 106.

[0032] In one example, devices 202 to 206 are contained in or on the same physical arrangement or assembly 214. For example, physical arrangement 214 is a computer system, such as a laptop computer, desktop computer, mobile phone, tablet computer, wearable device, television, or monitor. In another example, physical arrangement 214 is a circuit board, such as a PCB. Furthermore, although only two eUSB2 devices 202 and 204 and one intermediate device 206 are shown, additional such devices may be included in system 200. Additionally, each of eUSB2 devices 202 and 204 may be contained on a single semiconductor substrate (and packaged in a single semiconductor package), on multiple semiconductor substrates (and packaged in a single semiconductor package as a single IC), or in multiple IC packages and contained as a module.

[0033] In this example, eUSB2 device 202 is a SoC operating as a host or controller device, and eUSB2 device 204 is a connected device that can be another SoC, a data storage or memory device, an eUSB2 repeater, etc. Other examples of eUSB2 devices 202 and 204 are contemplated within the scope of this description. eUSB2 devices 202 and 204 include circuitry (not shown) implementing serial communication on bus 201 using communication protocols defined by eUSB2, consistent with and / or compatible with eUSB2. Depending on the device type, devices 202 and 204 include circuitry (not shown) communicating in native mode and / or repeater mode.

[0034] Bus 201 includes conductors 203, 205, 207, and 209 for transmitting signaling between eUSB2 devices 202 and 204. The conductors may include one or more traces, conductors, or other types of signal lines. As shown, eUSB2 device 202 includes an eUSB2 data+ pin eDP0 (eDP0 pin) coupled to conductor 203 of data bus 201 and an eUSB2 data- pin eDM0 (eDM0 pin) coupled to conductor 205 of data bus 201. eUSB2 device 204 includes an eUSB2 data+ pin eDP1 (eDP1 pin) coupled to conductor 207 of data bus 201 and an eUSB2 data- pin eDM1 (eDM1 pin) coupled to conductor 209 of data bus 201.

[0035] exist Figure 2 In an example embodiment, the coupling between the eDP0, eDM0, eDP1, and eDM1 pins and bus 201 enables eUSB2 devices 202 and 204 to transmit signaling at a first data rate called "high-speed" data rate, a second data rate called "full-speed" data rate, and a third data rate called "low-speed" data rate. The "high-speed" data rate is the fastest data rate supported by eUSB2 and is currently defined in the standard as 480 megabits per second (Mb / s). The "full-speed" data rate is an intermediate data rate supported by eUSB2 and is currently defined in the standard as 12 Mb / s. The "low-speed" data rate is the slowest data rate supported by eUSB2 and is currently defined in the standard as 1.5 Mb / s.

[0036] Intermediate device 206 is coupled to bus 201 and facilitates communication between devices 202 and 204. In this example, intermediate device 206 (similar to...) Figure 1 The intermediate device 106 in the middle includes a signal conditioner circuit system 208 (similar to...). Figure 1 The signal conditioner circuit system 108 and the state detector and controller circuit system 210 (similar to) Figure 1The state detector and controller circuit system 110 and the level shifter circuit system 212 (similar to) Figure 1 The level shifter circuitry 112, L1 mode or state detector circuitry 216 (also referred to herein as L1 circuitry 216), and eSE1 mode or state detector circuitry 218 (also referred to herein as eSE1 circuitry 218) are included in the intermediate device 206. Components or elements 208 to 212, 216, and 218 of the intermediate device 206 may be contained on a single semiconductor substrate (and packaged in a single semiconductor package), on multiple semiconductor substrates (and packaged in a single semiconductor package as a single IC), or in multiple IC packages and included as a module, separate from the eUSB2 devices 202 and 204.

[0037] The state detector and controller circuitry 210 monitors signaling on bus 201, for example, one or more signals or signal sequences contained in one or more packets and / or control messages. The state detector and controller circuitry 210 then detects the communication state (i.e., bus state or status) on bus 201 from the signaling. Depending on the detected state, the state detector and controller circuitry 210 controls (e.g., enables or disables) the operation of signal conditioner circuitry 208, level shifter circuitry 212, L1 circuitry 216, and / or eSE1 circuitry 218. Furthermore, once enabled, L1 circuitry 216 and / or eSE1 circuitry 218 can provide input to the state detector and controller circuitry 210 to further control the operation of signal conditioner circuitry 208 and / or level shifter circuitry 212.

[0038] To monitor signaling on bus 201 and detect bus status, the state detector and controller circuitry 210 includes a receiver circuitry coupled to bus 201 to receive signaling and a digital finite state machine (FSM) 222 to detect bus status from the received signaling. The digital FSM 222 includes an FSM 224 implemented by a digital circuitry and one or more oscillators 226 coupled to the FSM 224. The digital circuitry of the FSM 224 may include one or more of logic gates, combinational logic, flip-flops, repeaters, registers, programmable logic devices, and / or programmable logic controllers, or combinations thereof. The FSM 224 is implemented as a simplified state machine that passively detects bus status rather than actively participating in protocol handshakes like a packet repeater. The oscillators 226 provide one or more clock signals to sample the signals used by the FSM 224 to detect bus status at the receiver output. The oscillators 226 may be implemented using crystal oscillators, microelectromechanical systems (MEMS) devices, bulk acoustic wave devices, or other electronic oscillators.

[0039] The receiver circuitry of the state detector and controller circuitry 210 includes single-ended or single-input receivers 228, 230, 232, and 234, and dual-input receivers 236 and 238. For example, receivers 228 to 234 are voltage buffers (e.g., single-ended complementary metal-oxide-semiconductor (CMOS) buffers) that act as analog comparators, comparing a single signal at an input to a function of the supply voltage provided to the comparator to determine the signal at the output. For example, when the signal input to the single-ended receiver exceeds half the voltage source, the output signal is logic level 1; otherwise, the output signal is logic level 0. Receivers 236 and 238 are differential receivers that compare signals at two inputs to generate a signal at the output. For example, when the signal at the eDP0 pin exceeds the signal at the eDM0 pin, the output signal is logic level 1; otherwise, the output is logic level 0. Similarly, when the signal at the eDP1 pin exceeds the signal at the eDM1 pin, the output signal is logic level 1; otherwise, the output is logic level 0. In other instances, differential receivers 236 and 238 are not included in the state detector and controller circuitry 210.

[0040] As explained, the input of receiver 228 is coupled to conductor 203 to receive signaling from the eDP0 pin of eUSB2 device 202, and the input of receiver 230 is coupled to conductor 205 to receive signaling from the eDM0 pin of eUSB2 device 202. The input of receiver 236 is coupled to conductors 203 and 205, respectively, to receive signaling from both the eDP0 and eDM0 pins. As further explained, the input of receiver 232 is coupled to conductor 207 to receive signaling from the eDP1 pin of eUSB2 device 204, and the input of receiver 234 is coupled to conductor 209 to receive signaling from the eDM1 pin of eUSB2 device 204. The input of receiver 238 is coupled to conductors 207 and 209, respectively, to receive signaling from the eDP1 and eDM1 pins. The outputs of receivers 228 to 238 are coupled to FSM 224.

[0041] During operation, FSM 224 samples signaling from receivers 228 to 238 via its digital circuitry to determine the bus state. For example, when eUSB2 device 202 is used as a SoC controller or host, eUSB2 device 202 can detect the startup or connection of eUSB2 device 204 on bus 201. Alternatively, during communication on bus 201, where eUSB2 device 204 supports low-speed, full-speed, and high-speed signaling, the data rate can be changed from one data rate to another, for example, from low-speed or full-speed to high-speed signaling. In response or therefore, eUSB2 device 202 and / or eUSB2 device 204 send signaling on bus 201 indicating the data rate of communication on bus 201. In this example, the signaling includes a specific voltage level sequence recognizable by FSM 224. The signaling may include control signaling, such as control commands or messages indicating L0 state and the data rate of L0 state.

[0042] In this example, FSM 224 receives one or more voltage output signal sequences from receivers 228 and 230, which FSM 224 identifies as low-speed or full-speed signaling on bus 201. According to eUSB2, to distinguish between low-speed and full-speed signaling, all low-speed signaling is the opposite of full-speed; for example, except for control message signaling, eD+ and eD- are swapped. Alternatively, FSM 224 receives one or more voltage output signal sequences from receivers 228 and 230 and / or from differential receiver 236, which FSM 224 identifies as high-speed signaling on bus 201.

[0043] In one example, upon detecting a high-speed eUSB2 data rate, FSM 224 sends one or more signals on conductor 211, which couples signal conditioner circuitry 208 to state detector and controller circuitry 210. FSM 224 also sends one or more signals on conductor 213, which couples level shifter circuitry 212 to state detector and controller circuitry 210. One or more signals on conductor 211 (e.g., enable signals) enable operation of signal conditioner circuitry 208. One or more signals on conductor 213 (e.g., disable signals) disable operation of level shifter circuitry 212. Conversely, upon detecting a low-speed or full-speed eUSB2 data rate, or by default when signal conditioner circuitry 208 is not operating, FSM 224 sends one or more signals on conductors 211 and 213 to disable operation of signal conditioner circuitry 208 and enable operation of level shifter circuitry 212. In this example, the enable signal is a logic level 1 or a "high" signal or state, and the disable signal is a logic level 0 or a "low" signal or state. However, in another example, the opposite can be implemented.

[0044] Furthermore, upon detecting an eUSB2 high-speed data rate, the FSM 224 sends one or more signals on conductor 215, which couples the L1 circuit system 216 to the state detector and controller circuit system 210. The one or more signals on conductor 215 enable the operation of the L1 circuit system 216 during operation of the signal conditioner circuit system 208.

[0045] When L1 circuitry 216 detects an eUSB2 L1 state, it signals FSM 224 via conductor 215, which couples L1 circuitry 216 to the state detector and controller circuitry 210. In response, for example, FSM 224 may send one or more signals on conductors 211 and 215 to disable the operation of signal conditioner circuitry 208 and L1 circuitry 216 until FSM 224 detects an eUSB2 L1 recovery state. In response to the L1 recovery state, and in some instances, upon detection of an eUSB2 high-speed data rate, FSM 224 may send one or more signals on conductors 211 and 215 to re-enable the operation of signal conditioner circuitry 208 and L1 circuitry 216. According to eUSB2, the L1 state is part of link power management. See later. Figures 6 to 8 Describe an example implementation scheme and operation of the L1 circuit system 216.

[0046] The eSE1 circuitry 218 detects the eUSB2 Single-Ended 1 (eSE1) state or the XeSE1 state. For example, typical eSE1 states include Extended Single-Ended 1 (ESE1), SOWake, SOResume, and SOReset. In a particular instance, the ESE1 state notifies a device disconnection event or port reset event during power-on of the eUSB2 device 202 and / or 204. The eSE1 circuitry 218, which detects port resets during power-on, precedes and in this instance enables the FSM 224 to detect the data rate used on bus 201. The ESE1 state is detected when signaling on conductors 203 and 205 is at logic level 1 or high, or when signaling on conductors 207 and 209 is high for a period defined by the eUSB2 standard.

[0047] During operation, and in response to the FSM 224 detecting a high state from the output signals of receivers 228 and 230 or receivers 232 and 234, the FSM 224 sends one or more signals on conductor 217 that couples the eSE1 circuitry 218 to the state detector and controller circuitry 210. The one or more signals on conductor 217 reset the operation of the eSE1 circuitry 218. When the eSE1 circuitry 218 detects the ESE1 state, it signals the FSM 224 via conductor 217 that couples the eSE1 circuitry 218 to the state detector and controller circuitry 210. The FSM 224 can then continue to monitor the data rate on bus 201.

[0048] In this example, the eSE1 circuit system 218 includes four single-ended receivers (not shown), such as CMOS buffers and counter functions (not shown), including an oscillator for generating a clock signal and a digital counter coupled to the receiver. Two of the receivers are coupled to conductors 203 and 205, respectively, to detect signaling from the eUSB2 device 202. The other two receivers are coupled to conductors 207 and 209, respectively, to detect signaling from the eUSB2 device 204. The eSE1 circuit system 218 may also include switches that couple the receivers to bus 201.

[0049] When one or more signals are received on conductor 217, both switches close to couple both receivers to bus 201. The closed switches couple the receivers to conductors 203 and 205, or to conductors 207 and 209, respectively. When the high state of the counter indicator signal has been maintained at the receiver output for the amount of time required to indicate the ESE1 state, the eSE1 circuitry 218 signals the FSM 224 via conductor 217. Upon receiving the signal indicating the ESE1 state, the FSM 224 may responsively send one or more signals on conductor 217 to open the switches and reset the counter of the eSE1 circuitry.

[0050] The level shifter circuit system 212 is implemented as a bit-level repeater that translates signals on bus 201 from one logic level or voltage domain to another between eUSB2 devices 202 and 204. In the illustrated example, the voltage domain in which eUSB2 devices 202 and 204 operate or are compatible with eUSB2 devices 202 and 204 is one of 0.8V, 1.0V, or 1.2V, which determines the high logic level, such as 1, in the binary configuration. The low logic level, such as 0, is determined by the ground reference of the level shifter circuit system 212.

[0051] The level shifter circuit system 212 includes receivers 240, 242, 244, and 246, and translation circuit systems 248, 250, 252, and 254, which implement bidirectional voltage level translation between eUSB2 devices 202 and 204. In this example, receivers 240 to 246 are single-ended CMOS buffers, and translation circuit systems 248 to 254 include switches.

[0052] As shown, the input of receiver 240 is coupled to conductor 203, and the input of receiver 242 is coupled to conductor 205 to receive signaling at a voltage level supported by eUSB2 device 202. The output of receiver 240 is coupled to the input of translation circuitry system 248, and the output of receiver 242 is coupled to the input of translation circuitry system 250. Furthermore, the output of translation circuitry system 248 is coupled to conductor 207, and the output of translation circuitry system 250 is coupled to conductor 209, so that signaling from receivers 240 and 242 can be translated to a voltage and ground reference level supported by eUSB2 device 204.

[0053] In the opposite direction, the input of receiver 244 is coupled to conductor 207, and the input of receiver 246 is coupled to conductor 209 to receive signaling at a voltage level supported by eUSB2 device 204. The output of receiver 244 is coupled to the input of translation circuit system 252, and the output of receiver 246 is coupled to the input of translation circuit system 254. Furthermore, the output of translation circuit system 252 is coupled to conductor 203, and the output of translation circuit system 254 is coupled to conductor 205, so that signaling from receivers 244 and 246 can be translated to the voltage and ground reference level supported by eUSB2 device 202.

[0054] In this implementation, the level shifter circuit system 212 is active in only one direction at a time, for example, for communication from eUSB2 device 202 to eUSB2 device 204 or from eUSB2 device 204 to eUSB2 device 202. For example, a signal on conductor 213 that enables the operation of the level shifter circuit system 212 is also configured to indicate the direction in which it performs voltage translation. See later. Figure 3 An example implementation of the level shifter circuit system 212 is described.

[0055] The signal conditioner circuit system 208 includes switches SW1 and SW2, and a high-speed (HS) signal booster circuit system 220 (also referred to herein as signal booster circuit system 220). Switches SW1 and SW2 may contain one or more transistors of suitable types, such as field-effect transistors (FETs) and / or bipolar junction transistors (BJTs). A first terminal or end of switch SW1 is coupled to conductor 203, and a second terminal of switch SW1 is coupled to conductor 207 and signal booster circuit system 220. A first terminal of switch SW2 is coupled to conductor 205, and a second terminal of switch SW2 is coupled to conductor 209.

[0056] In response to one or more signals on conductor 211, switches SW1 and SW2 transition from an open state (on) to a closed state (closed) to couple signal booster circuitry 220 to bus 201. Once coupled, signal booster circuitry 220 boosts the signaling power on bus 201. See later. Figure 4 and 5 Describe an example implementation of the signal conditioner circuit system 208.

[0057] Figure 3 A level shifter circuit system 312 is depicted according to the described example. The level shifter circuit system 312 is... Figure 1 The level shifter circuit system 112 and Figure 2 An example implementation of the level shifter circuit system 212. Specifically, Figure 3 The components described herein implement voltage translation for low-speed and full-speed signaling from eUSB2 device 202 to eUSB2 device 204. The same or similar circuitry can be used to implement voltage translation for low-speed and full-speed signaling from eUSB2 device 204 to eUSB2 device 202.

[0058] The level shifter circuit system 312 includes receivers 240 and 242 coupled to the eDP0 and eDM0 pins via conductors 203 and 205, respectively; programmable voltage sources 300 and 302; a translation circuit system 348 including switches SW3 and SW4; a translation circuit system 350 including switches SW5 and SW6; and switches SW7 and SW8. Switches SW3 and SW4 operate alternately, meaning that when one switch is open, the other is closed, and vice versa. Similarly, switches SW5 and SW6 operate alternately. Furthermore, switches SW3 through SW8 may include one or more transistors of a suitable type, such as FETs and / or BJTs. Additionally, each of the programmable voltage sources 300 and 302 can be programmed to 0.8V, 1.0V, or 1.2V. However, other voltage levels are contemplated within the scope of this description.

[0059] Programmable voltage source 300 is coupled to the corresponding inputs of receivers 240 and 242 and programmed to a voltage level V supported by eUSB2 device 202. SUPPLY1 The programmable voltage source 302 is coupled to the corresponding first terminals of switches SW3 and SW5 and programmed to a voltage level V supported by the eUSB2 device 204. SUPPLY2 The second terminal of switch SW3 is coupled to the output of receiver 240 and the first terminal of switch SW4. The third terminal of switch SW3 is coupled to the second terminal of switch SW4 and the first terminal of switch SW7. The third terminal of switch SW4 is coupled to ground reference 304 of eUSB2 device 204 (also referred to herein as ground 304). Conductor 213 is coupled to the corresponding second terminals of switches SW7 and SW8, and the third terminal of switch SW7 is coupled to conductor 207.

[0060] The second terminal of switch SW5 is coupled to the output of receiver 242 and the first terminal of switch SW6. The third terminal of switch SW5 is coupled to the second terminal of switch SW6 and the first terminal of switch SW8. The third terminal of switch SW6 is coupled to ground 304, and the third terminal of switch SW8 is coupled to conductor 209.

[0061] In response to an enable signal (e.g., logic 1) on conductor 213, switches SW7 and SW8 transition from an open state to a closed state, coupling translation circuit systems 348 and 350 to conductors 207 and 209, respectively. In an example, when the signaling at the input of receiver 240 exceeds V... SUPPLY1 When / 2, the output of receiver 240 is at logic level 1, which represents logic level 1 of eUSB2 device 202. Logic level 1 at the output of receiver 240 closes switch SW3 to provide V on conductor 207. SUPPLY2 This indicates a logic level of 1 at the output of the eUSB2 device 204. A logic level of 1 at the output of the receiver 240 causes the switch SW4 to be in the open state.

[0062] Conversely, when the signaling at the input of receiver 240 is less than V SUPPLY1 When / 2, the output of receiver 240 is at logic level 0, which represents logic level 0 of eUSB2 device 202. The logic level 0 at the output of receiver 240 closes switch SW4 to provide a ground reference 304 on conductor 207, which represents logic level 0 of eUSB2 device 204. The logic level 0 at the output of receiver 240 causes switch SW3 to be in the open state.

[0063] Similarly, when the signaling at the input of receiver 242 exceeds V SUPPLY1When / 2, the output of receiver 242 is at logic level 1, which represents logic level 1 of eUSB2 device 202. The logic level 1 at the output of receiver 242 closes switch SW5 to provide V on conductor 209. SUPPLY2 This indicates a logic level of 1 at the output of the eUSB2 device 204. A logic level of 1 at the output of the receiver 242 causes the switch SW6 to be in the open state.

[0064] Conversely, when the signaling at the input of receiver 242 is less than V SUPPLY1 When / 2, the output of receiver 242 is at logic level 0, which represents logic level 0 of eUSB2 device 202. Logic level 0 at the output of receiver 242 closes switch SW6 to provide ground reference 304 on conductor 209, which represents logic level 0 of eUSB2 device 204. Logic level 0 at the output of receiver 242 causes switch SW5 to open. Furthermore, in response to receiving a disable signal (e.g., logic 0) on conductor 213, switches SW7 and SW8 transition from closed to open to decouple translation circuit systems 348 and 350 from conductors 207 and 209, respectively.

[0065] Figure 4 A signal conditioner circuit system 408 is depicted according to the described example. The signal conditioner circuit system 408 is... Figure 1 Signal conditioner circuit system 108 and Figure 2 An example implementation of the signal conditioner circuit system 208. The signal conditioner circuit system 408 includes switches SW1 and SW2, switches SW9 and SW10, and a signal booster circuit system 220.

[0066] Signal line 401 of conductor 211 is coupled to the corresponding first terminals of switches SW1 and SW2, and signal line 403 of conductor 211 is coupled to the corresponding first terminals of switches SW9 and SW10. The second terminal of switch SW1 is coupled to conductor 203, and the third terminal of switch SW1 is coupled to conductor 207 and the second terminal of switch SW9. The third terminal of switch SW9 is coupled to signal booster circuit system 220. The second terminal of switch SW2 is coupled to conductor 205, and the third terminal of switch SW2 is coupled to conductor 209 and the second terminal of switch SW10. The third terminal of switch SW10 is coupled to signal booster circuit system 220.

[0067] In response to an enable signal, such as logic 1, on signal lines 401 and 403 of conductor 211, switches SW1, SW2, SW9, and SW10 change from an open state to a closed state. Closed switches SW1 and SW9 couple conductors 203 and 207 to the signal booster circuit system 220, and closed switches SW2 and SW10 couple conductors 205 and 209 to the signal booster circuit system 220. This enables the operation of the signal booster circuit system 220.

[0068] Figure 5 A schematic diagram depicts a signal booster circuit system 520 according to the described example. The signal booster circuit system 520 is... Figure 2 and 4 An example implementation of the signal booster circuit system 220 is provided. The signal booster circuit system 520 includes transition detector circuits 500 and 502, current sources 504 and 506, and switches SW11 and SW12. In this example, the transition detector circuit 500 is a differential comparator having first and second inputs coupled to bus 201 to receive data+ and data- differential signals (e.g., from eDP0 and eDM0 pins or from eDP1 and eDM1 pins), and thereby detects the rising edge of the differential signal. Similarly, the transition detector circuit 502 is a differential comparator having first and second inputs coupled to bus 201 to receive data+ and data- differential signals, and thereby detects the falling edge of the differential signal.

[0069] The output of transition detector circuit 500 is coupled to the first terminal of switch SW11. The second terminal of switch SW11 is coupled to the output of current source 504, and the third terminal of switch SW11 is coupled to bus 201 to receive signaling from the eDP0 and eDP1 pins during operation of signal booster circuit system 220. Similarly, the output of transition detector circuit 502 is coupled to the first terminal of switch SW12. The second terminal of switch SW12 is coupled to the output of current source 506, and the third terminal of switch SW12 is coupled to bus 201 to receive signaling from the eDM0 and eDM1 pins during operation of signal booster circuit system 220.

[0070] When a rising edge of the differential signal on bus 201 is detected, the transition detector circuit 500 outputs a signal to close switch SW11. In response, current source 504 supplies current to conductor 203 or 207 (depending on the direction of the high-speed signaling) to raise the rising edge on the conductor. When no rising edge is detected, the transition detector circuit 500 outputs a signal to open switch SW11 to disconnect current source 504 from bus 201.

[0071] When a falling edge of the differential signal on bus 201 is detected, the transition detector circuit 502 outputs a signal to close switch SW12. In response, current source 506 draws current from conductor 205 or 209 (depending on the direction of the high-speed signaling) to raise the falling edge on the conductor. When no falling edge is detected, the transition detector circuit 502 outputs a signal to open switch SW12 to disconnect current source 506 from bus 201.

[0072] In another example, current sources 504 and 506 are adjustable current sources. For instance, the status detector and controller circuitry 210 (or 110) may include circuitry (not shown) that senses the impedance on bus 201 to determine the boost current provided via current sources 504 and 506. Furthermore, in some examples, the signal booster circuitry 520 is triggered only when a high-speed packet is transmitted on bus 202. Otherwise, the signal booster circuitry is idle.

[0073] The injected current improves the rise and fall times of signals traveling in either direction on bus 201, allowing for increased signal transmission distance. Packet repeaters introduce jitter and skew, potentially truncating the start of a packet bit and possibly adding a dribble bit at the end of a packet. However, the signal booster circuitry 520 can be implemented without one or more of these limitations.

[0074] Figure 6 The L1 circuit system 616 is depicted according to the described example. The L1 circuit system 616 is... Figure 2 An example implementation of the L1 circuit system 216 is provided. The L1 circuit system 616 includes a clock and data recovery (CDR) circuit 600 and an FSM 602. The CDR circuit 600 derives a clock, such as a 480 MHz clock, from one or more packets on the bus 201, which is provided by the CDR circuit to the FSM 602 for detecting the L1 state.

[0075] The CDR circuit 600 includes a receiver 604, current sources 606 and 608, a differential amplifier 610, comparators 612 and 614, a delay circuit 618, switches SW13 to SW15, capacitors C1 and C2, and resistors R1 and R2. In this example, the delay circuit 618 is a delay line, capacitors C1 and C2 have the same capacitance value, resistors R1 and R2 have the same resistance value, and the receiver 604 is a differential receiver that compares the signals at its two inputs to generate a signal at its output. For example, when the signal at the eDP0 pin exceeds the signal at the eDM0 pin, the output signal is logic level 1; otherwise, the output signal is logic level 0. Similarly, when the signal at the eDP1 pin exceeds the signal at the eDM1 pin, the output signal is logic level 1; otherwise, the output signal is logic level 0. Furthermore, switches SW13 to SW15 can be FETs, BJTs, or combinations thereof.

[0076] The FSM 602 includes digital logic 622 and a counter 624. Logic 622 is used to detect packet identifiers (PIDs) used to indicate the L1 state. Additional logic (not shown) for performing other functions (such as detecting one or more additional PIDs) may be included in the FSM 602. Counter 624 is coupled to the output of receiver 604 and assists in detecting PIDs from one or more packets on data bus 201. The FSM 602 may include one or more or a combination of logic gates, combinational logic, flip-flops, repeaters, registers, programmable logic devices, and / or programmable logic controllers. The FSM 602 also passively detects information from communications on bus 201 but does not actively participate in communication protocol exchange.

[0077] As described, the output of receiver 604 is coupled to the respective first terminals of switches SW13 and SW14 and the input of FSM 602. The second terminal of switch SW13 is coupled to the output of current source 606, and the third terminal of switch SW13 is coupled to the first terminal of capacitor C1, the non-inverting input of differential amplifier 610, and the non-inverting input of comparator 614. The second terminal of capacitor C1 is coupled to ground reference 620 (also referred to herein as ground 620).

[0078] Resistors R1 and R2 are coupled together with differential amplifier 610 to form a voltage multiplier, in this case, a voltage doubler. Specifically, the inverting input of differential amplifier 610 is coupled to the corresponding first terminals of resistors R1 and R2. The second terminal of resistor R1 is coupled to ground 620, and the second terminal of resistor R2 is coupled to the output of differential amplifier 610.

[0079] The inverting input of comparator 612 is also coupled to the output of differential amplifier 610. The non-inverting input of comparator 612 is coupled to: the non-inverting input of comparator 614; the corresponding first terminal of switch SW15 and capacitor C2; and the output of current source 608 via switch SW14. The corresponding second terminal of capacitor C2 and switch SW15 is coupled to ground 620. The output of comparator 612 is coupled to the input of delay circuit 618, and the output of delay circuit 618 is coupled to the third terminal of switch SW15. Finally, the output of comparator 614 is coupled to another input of FSM 602 and assists in detecting PID from one or more packets on data bus 201.

[0080] Reference Figure 7 The operation of the CDR circuit 600 is described using the example signaling diagram 700 illustrated herein. Signaling diagram 700 shows differential signals 702 and 704 provided at the inputs of receiver 604. In one example, signal 702 is provided from the eDP0 pin to conductor 203, and signal 704 is provided from the eDM0 pin to conductor 205. Alternatively, signal 702 is provided from the eDP1 pin to conductor 207, and signal 704 is provided from the eDM1 pin to conductor 209. For simplicity, the operation of the L1 circuit system 616 is described by referring to the eUSB2 device 202 sending high-speed signaling to the eUSB2 device 204, where the signaling contains eUSB2 packets. Therefore, signal 702 is referred to as eDP0 signal 702, and signal 704 is referred to as eDM0 signal 704.

[0081] At position 706, the end of packet (EOP) of the first packet is indicated. Following EOP is the SE0 (single-ended 0) state indicated at position 708. The SE0 state is indicated by the eDP0 signal 702 and the eDM0 signal 704, which in this example are at logic level 0 or low. The SE0 state immediately precedes the start of the next packet, where the start of SYNC mode 710 indicates the start of the next packet. The CDR circuit 600 uses SYNC mode 710 to generate a 480MHz clock.

[0082] During the SE0 state, the L1 circuit system 616 is reset. For example, the FSM 224 detects the SE0 state and sends an enable / reset signal to the L1 circuit system 616 on conductor 215. In response to the enable / reset signal, the FSM 602 resets logic 622 to the start state and resets counter 624, thereby resetting the clock of the FSM 602. Furthermore, in the example implementation, current sources 606 and 608 are in the off state (OFF) at the start of SYNC mode. In a further example, the FSM 224 enables / resets the L1 circuit system 616 only when it first enables the signal conditioner circuit system 210, allowing circuit systems 210 and 616 to operate simultaneously. Subsequent SE0 states are detected by logic (not shown) contained in the FSM 602, which causes the L1 circuit system 616 to reset.

[0083] At 712, the start of the first SYNC bit of SYNC mode 710 is indicated. Thereafter, whenever the eDP0 signal 702 transitions to a value greater than the eDM0 signal 704 (thereby causing the output of receiver 604 to transition to logic 1), counter 624 increments to count the number of SYNC bits. Switches SW13 and SW14 close in response to the logic 1 at the output of receiver 604. However, whether current sources 606 and 608 are in an ON state to charge the corresponding capacitors C1 and C2 coupled thereto depends on the counter value.

[0084] That is, at 716, current source 606 is turned on after counter 624 counts the first SYNC bit and / or in response to counter 624 counting the first SYNC bit. This allows current source 606 to charge capacitor C1 when switch SW13 is closed. At 718, current source 606 is turned off after counter 624 counts the third SYNC bit and / or in response to counter 624 counting the third SYNC bit. At this time, capacitor C1 has been charged for a sufficient amount of time to generate voltage V1 across capacitor C1.

[0085] A voltage V1 is provided as a reference voltage at the inverting input of comparator 614. Voltage V1 is also provided to the non-inverting input of differential amplifier 610, which produces a voltage of 2*V1 at the output of differential amplifier 610. A voltage of 2*V1 is provided as a reference voltage at the inverting input of comparator 612. The accuracy of the reference voltage V1 and 2*V1 is limited by leakage in capacitor C1.

[0086] At 720, current source 608 is turned on after and / or in response to counter 624 counting the seventh SYNC bit. The current ratio Ix to I (Ix / I) between current sources 608 and 606 is used to tune the clock frequency to compensate for the delay between turning off current source 606 and turning on current source 608. When switch SW14 is closed, turning on current source 608 enables charging of capacitor C2, and further enables the operation of comparators 612 and 614 and switch SW15 to generate a 480 MHz clock signal (CLK) at the output of comparator 614. Generally, timing information from signals 702 and 704 is represented as voltage V across capacitor C2 RAMP .

[0087] More specifically, as capacitor C2 charges, ramp voltage V RAMP increases and is supplied to respective non-inverting inputs of comparators 612 and 614. When V RAMP < V1, CLK is low and a reset signal (RESET) from comparator 612 is low. The low RESET keeps switch SW15 open. When V RAMP exceeds V1, CLK goes high. When V RAMP exceeds 2*V1, RESET goes high.

[0088] After a delay generated by delay circuitry 618, the high RESET closes switch SW15. In response, capacitor C2 starts to discharge and pulls V RAMP down. When V RAMP goes below 2*V1, RESET goes low. However, the low RESET is delayed for a sufficient time to allow V RAMP to drop below V1 and pull CLK low. Once low RESET is supplied to switch SW15, SW15 transitions to an open state to allow capacitor C2 to start recharging to generate the next CLK pulse.

[0089] Although in Figure 7Not shown, but the PID for the current packet begins after SYNC mode 710 ends. FSM 602 receives both the output signal from receiver 604 and CLK. CLK is used to sample the output signal from receiver 604 so that logic 622 can detect the PID indicating entry into a low-power state. For example, entering the L1 state is indicated by EXT PID 1010. When logic 622 fails to detect the EXT PID, it exits. In response, L1 circuitry 616 is reset and waits for the next packet. However, if logic 622 detects the EXT PID, then L1 circuitry 616 resets and attempts to detect the SUB PID and ACK PID using additional logic (not shown) of FSM 602. If FSM 602 fails to detect either the SUB PID or the ACK PID, then L1 circuitry 616 resets and waits for the next packet. When EXT PID, SUB PID, and ACK PID are detected, FSM 602, for example, uses logic 1 to signal FSM 224 on conductor 215 to indicate a valid entry in L1 state.

[0090] Figure 8 Signaling diagram 800 illustrates the simulation results from L1 circuitry 616, which detects L1 states. Signaling diagram 800 illustrates eDP and eDM signals 802 carrying multiple packets, CLK signals 804 generated from packets conveyed by eDP and eDM signals 802, and signals 806 on conductor 215. Decomposition segment 808 of eDP and eDM signals 802 and CLK signals 804 shows a generated CLK signal 810 for detecting an EXT PID 812 of a first packet, a generated CLK signal 814 for detecting a SUB PID 816 of a second packet, and a generated CLK signal 818 for detecting an ACK PID 820 of a third packet. After detecting an ACK PID, FSM 602 sends a logic 1 (indicated at 824) on conductor 215 to FSM 624 to enter L1 state. In this example, as indicated at 822, the FSM 602 waits 10 microseconds after detecting the ACK PID before signaling the L1 detection. However, in other examples, the waiting period differs, or there is no waiting period at all.

[0091] Figure 9 This is a flowchart of an example method 900 for operating an intermediate device comprising a signal conditioner circuit system, a level shifter circuit system, and a state detector and controller circuit system. In one example, method 900 is derived from a reference... Figure 1 The described intermediate device 106 is executed. In another instance, method 900 is executed by reference. Figure 2The described intermediate device 206 is executed. Furthermore, in yet another instance, method 900 implements only a portion or some of the functionality or operability of the intermediate device according to the described instance, and method 900 describes an instance operation method. For simplicity, refer to the above... Figures 2 to 8 The method 900 is described by referring to the intermediate device 206 in the example.

[0092] According to method 900, the state detector and controller circuitry 210 receives signals from bus 201 using one or more of receivers 228 to 238 and operates digital FSM 222 at block 902 to detect bus status or communication status from the signals. At block 904, detecting the bus status involves detecting a first data rate or a second data rate from the signals received at the receiver circuitry. In this example, at block 904, FSM 224 determines whether a high-speed (HS) data rate is detected. If FSM 224 does not detect a high-speed data rate, but instead detects a low-speed or full-speed data rate, then at block 906, FSM 224 enables the operation of level shifter circuitry 212. Level shifter circuitry 212 is used to shift the voltage level of a signal from a first voltage level to a second voltage level. In this example, level shifter circuitry 312 is implemented and operated according to example level shifter circuitry 312. While operating the level shifter circuit system 212, method 900 also continues to operate the digital FSM 222 at block 902 to detect other bus states as needed, including detecting data rates.

[0093] If FSM 224 detects a high data rate, then FSM 224 enables the operation of signal conditioner circuitry 208 at block 908 and the operation of L1 circuitry 216 at block 910. In this example, the signal conditioner circuitry is implemented and operates according to example signal conditioner circuitry 408 and HS signal booster 520, and the L1 circuitry is implemented and operates according to example L1 circuitry 616. For example, operating signal conditioner circuitry 208 is used to boost signal edges. Furthermore, in this example, at block 912, operating L1 circuitry 216 is used to detect L1 state. For example, operating L1 circuitry 216 includes generating a clock signal, for example, by CDR circuitry 600 using a corresponding synchronization (SYNC) mode within a packet conveyed in the signal. Furthermore, detecting L1 state includes providing a clock signal to a finite state machine (e.g., FSM 622), and the finite state machine using the clock signal to detect indications of EXT PID, SUB PID, and ACK PID in consecutive packets.

[0094] At block 912, if no L1 state is detected, method 900 continues operation of signal conditioner circuitry 208 at block 908 and L1 circuitry 216 at block 910. If an L1 state is detected, intermediate device 206 operates in a low-power state at block 914. The low-power state includes at least disabling signal conditioner circuitry 208. At block 916, the low-power state continues until an L1 recovery state is detected. When an L1 recovery state is detected, method 900 continues operation of digital FSM 222 at block 902 to detect other bus states as needed, including data rate detection.

[0095] At block 918, while operating signal conditioner circuitry 208 or level shifter circuitry 212, digital FSM 222 also enables operation of eSE1 circuitry 218. At block 920, operation of eSE1 circuitry 218 is used to detect one or more eSE1 states from a signal. In this example, at block 920, eSE1 circuitry 218 may continue to operate until an eSE1 state is detected. Once detected, digital FSM 222 may disable one or both of level shifter circuitry 212 or signal conditioner circuitry 208 at blocks 922 and 924. At block 902, method 900 may continue operation of digital FSM 222 to detect other bus states as needed, including detecting data rates.

[0096] Figure 10 This is a flowchart of an example method 1000 for operating an intermediate device comprising a signal conditioner circuit system, a level shifter circuit system, and a state detector and controller circuit system. In one example, method 1000 is derived from a reference... Figure 1 The described intermediate device 106 is executed. In another instance, method 1000 is executed by reference. Figure 2 The described intermediate device 206 is executed. Furthermore, in yet another instance, method 1000 implements only a portion or some of the functionality or operability of the intermediate device according to the described instance, and method 1000 describes an instance operation method. For simplicity, refer to the above... Figures 2 to 8 The method 1000 is described by referring to the intermediate device 206 of the example.

[0097] According to method 1000, the state detector and controller circuitry 210 receives signals from bus 201 using one or more receivers 228 to 234 and operates the digital FSM 222 at block 1000 to detect bus status or communication status from the signals. In this example, the digital FSM 222 does not actively detect low-speed or full-speed data rates. Therefore, at block 1004, when no high-speed data rate is detected, the FSM 222 enables the level shifter circuitry 212.

[0098] However, at block 1006, detecting the bus status includes detecting the high-speed (HS) data rate from the signal received at the receiver circuitry. If the FSM 224 does not detect the high-speed data rate, then at block 1004, operation of the level shifter circuitry 212 continues. In this example, the level shifter circuitry 312 is implemented and operates according to the example level shifter circuitry 312.

[0099] If FSM 224 detects a high data rate, then FSM 224 enables operation of signal conditioner circuitry 208 at block 1008, L1 circuitry 216 at block 1010, and eSE1 circuitry at block 1018. In this example, the signal conditioner circuitry is implemented and operates according to example signal conditioner circuitry 408 and HS signal booster 520, the L1 circuitry is implemented and operates according to example L1 circuitry 616, and the eSE1 circuitry is implemented and operates according to example eSE1 circuitry 218. For example, at block 1012, L1 circuitry 216 is operated to detect L1 states, and at block 1020, eSE1 circuitry 218 is operated to detect one or more eSE1 states. For example, operating L1 circuitry 216 includes generating a clock signal, for example, by CDR circuitry 600 using a corresponding synchronization (SYNC) mode within a packet conveyed in the signal. In addition, detecting the L1 state involves providing a clock signal to a finite state machine (e.g., FSM 622), and the finite state machine uses the clock signal to detect indications of the EXT PID, SUB PID, and ACK PID in consecutive packets.

[0100] At block 1012, if an L1 state is detected, the intermediate device 206 operates in a low-power state. At block 1026, the low-power state at least includes disabling the signal conditioner circuitry 208. However, in this example, at block 1014, the low-power state includes enabling the operation of the digital FSM 222 level shifter circuitry 212. At block 1016, the low-power state continues until an L1 recovery state is detected. When an L1 recovery state is detected, method 1000 enables the operation of the signal conditioner circuitry 208 at block 1010 and also disables the level shifter circuitry 212. Furthermore, in some examples, the eSE1 circuitry 218 is also disabled when an L1 state is detected.

[0101] At block 1020, the eSE1 circuitry 218 is operated to detect one or more eSE1 states from the signal. In this example, the eSE1 circuitry 218 may continue to operate until the start of an eSE1 state is detected at block 1020 and until the end of a high-speed data rate is detected at block 1024. Once detected, the digital FSM 222 disables the operation of the signal conditioner circuitry 208 at block 1022 and enables the operation of the level shifter circuitry 212 at block 1004. At block 1006, method 1000 may continue the operation of the digital FSM 222 to enable the detection of the high-speed data rate. At blocks 1020 and 1024, the digital FSM 222 may also disable the L1 circuitry 216 and the eSE1 circuitry 218 upon detection of both the eSE1 state and the end of the high-speed data rate.

[0102] In this specification and claims, unless otherwise stated, the terms "comprising" and "having," and variations thereof, are included in a manner similar to the term "comprising." Additionally, the term "coupled" (coupled, coupled, or couples) refers to an indirect or direct electrical or mechanical connection. The term may encompass connection, communication, or signaling paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B; or in a second instance, if intermediate component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via a control signal generated by device A, then device A is coupled to device B through intermediate component C.

[0103] A device “configured to” perform a task or function may be configured by the manufacturer at the time of manufacture (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof.

[0104] The circuits or devices described herein as containing certain components may be alternatively adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled, for example, by an end user and / or a third party during or after manufacturing to at least some of the passive elements and / or sources to form the described structure.

[0105] The circuits described herein can be reconfigured to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors respectively coupled in series between the same two nodes as the single resistor or capacitor.

[0106] While a specific transistor structure has been mentioned above, other transistor or device structures can be used instead. For example, a p-type MOSFET can be used instead of an n-type MOSFET with little or no change. Alternatively, other types of transistors (e.g., bipolar transistors – NPN or PNP) can be used instead of the transistors shown. Capacitors can be implemented using different device structures (e.g., metal structures formed by stacking parallel plates to form capacitors), or they can be formed on layers (metal or doped semiconductor) closer to or farther from the surface of the semiconductor substrate.

[0107] As used herein, the terms “terminal,” “node,” “interconnect,” and “pin” are used interchangeably. Unless otherwise expressly stated, these terms are generally used to mean interconnections or terminals between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0108] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0109] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. A circuit comprising: Signal conditioner circuit system; Level shifter circuit system; and A state detector and controller circuit system, coupled between the signal conditioner circuit system and the level shifter circuit system, includes: Receiver circuitry; and A finite state machine, coupled to the receiver circuitry and configured to: First data rate is detected from the signal; The operation of the signal conditioner circuit system is controlled in response to the detection of the first data rate; and The operation of the level shifter circuit system is controlled during the second data rate.

2. The circuit according to claim 1, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

3. The circuit according to claim 2, wherein: The high-speed data rate is 480 megabits per second (Mb / s); The full-speed data rate is 12 Mb / s; and The low-speed data rate is 1.5 Mb / s.

4. The circuit of claim 1, wherein the finite state machine is a first finite state machine, and the circuit further includes a low-power state detection circuit system comprising: Differential receiver; Clock and data recovery (CDR) circuitry, coupled to the differential receiver; and A second finite state machine is coupled to the differential receiver and the CDR circuit, and is configured to detect low-power states from the signal using a clock signal generated by the CDR circuit.

5. The circuit according to claim 4, wherein: The CDR circuit is configured to generate the clock signal using a synchronization pattern of packets conveyed in the signal; and The second finite state machine is configured to detect the link power management LPM-L1 state using the packet identifier of the packet.

6. The circuit of claim 1, wherein the signal conditioner circuit system is configured to boost the edge of the signal.

7. A system comprising: First integrated circuit; Second integrated circuit; and An intermediate circuit, coupled between the first and second integrated circuits, includes: First switch; A signal conditioner circuit system configured to boost the edge of the signal during the state of the first switch being closed; Second switch; A level shifter circuit system that is capable of operating during the closed state of the second switch; and The state detector and controller circuit system includes: Receiver circuitry; and A finite state machine, coupled to the receiver circuitry and configured to: The first data rate is detected from the signal received from the receiver circuitry. The first switch is closed in response to the detection of the first data rate; and The second switch is closed during the second data rate period.

8. The system of claim 7, wherein the first integrated circuit is a first embedded universal serial bus (eUSB2) device, and the second integrated circuit is a second eUSB2 device.

9. The system of claim 7, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

10. The system of claim 7, wherein the finite state machine is a first finite state machine, and the circuit further includes a low-power state detection circuit system comprising: Differential receiver; Clock and data recovery (CDR) circuitry, coupled to the differential receiver; and A second finite state machine is coupled to the differential receiver and the CDR circuit, and is configured to use a clock signal generated by the CDR circuit to detect the link power management LPM-L1 (L1) state from the signal detection link.

11. The system according to claim 10, wherein: The CDR circuit is configured to generate the clock signal using a synchronization pattern of packets conveyed in the signal; and The second finite state machine is configured to detect the L1 state using the packet identifier of the packet.

12. A method comprising: Receive signal; Detect the first data rate from the signal; The signal conditioner circuitry operates in response to the detection of the first data rate to boost the edge of the signal; and The level shifter circuitry operates during the second data rate to shift the voltage level of the signal from a first voltage level to a second voltage level.

13. The method of claim 12, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

14. The method of claim 12, further comprising operating a low-power mode detection circuitry system in response to detecting the second data rate for detecting a link power management LPM-L1 (L1) state from the signal.

15. The method of claim 14, wherein operating the low-power mode detection circuit system comprises generating a clock signal using a corresponding synchronization (SYNC) mode within a packet conveyed in the signal.

16. The method of claim 15, wherein detecting the L1 state comprises: The clock signal is provided to the finite state machine; and The finite state machine uses the clock signal to detect the EXT packet identifier (PID), SUB PID, and ACK PID in consecutive packets.

17. The method of claim 12, further comprising detecting the state of an embedded universal serial bus single-ended 1 (ESE1) from the signal.

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