Semiconductor circuit

Abstract

This disclosure relates to a semiconductor circuit comprising: a first inductor unit connected in series with the source electrode of a first semiconductor element; and a second inductor unit connected in series with the source electrode of a second semiconductor element, the second semiconductor element being connected in parallel with the first semiconductor element, the first inductor unit and the second inductor unit being configured such that an induced electromotive force is induced in the first inductor unit and the second inductor unit due to magnetic interaction, and the currents flowing through the first inductor unit and the second inductor unit reinforce each other in the same direction.

Description

Technical Field

[0001] This invention relates to semiconductor circuits. Background Technology

[0002] Semiconductor devices consisting of multiple semiconductor elements connected in parallel have been disclosed (e.g., Patent Documents 1-2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 3421544

[0006] Patent Document 2: Japanese Patent Application Publication No. 2017-175602 Summary of the Invention

[0007] The technical problem that the invention aims to solve

[0008] When switching each semiconductor element by applying a gate voltage to each of multiple semiconductor elements, it is assumed that the magnitude of the drain current flowing through each semiconductor element deviates. Therefore, for example, in Patent Document 1, a common source inductor is provided between the gate circuit and the main circuit in which the individual semiconductor elements are arranged. In such a common source inductor, an electromotive force (EMF) is generated in the opposite direction to the drain current, depending on the magnitude of the drain current flowing through the semiconductor element. The gate voltage of the semiconductor element is then adjusted by the generated EMF to suppress the deviation in the magnitude of the drain current.

[0009] Furthermore, for example, in Patent Document 2, the inductance of the gate node of one semiconductor element is coupled to the inductance of the drain node of another semiconductor element. In this structure, an electromotive force is generated that directs the current in the opposite direction to the drain current, based on the magnitude of the drain current flowing through the semiconductor elements at the coupling point. Therefore, for example, when the magnitude of the drain current in one semiconductor element is greater than the magnitude of the drain current in another semiconductor element, the gate voltage of the other semiconductor element can be adjusted to increase the magnitude of the drain current flowing through it. In this way, deviations in the magnitude of the drain current flowing through each semiconductor element are suppressed.

[0010] In the methods for suppressing drain current deviations described above, large impedances are considered in the gate and main circuits to cope with rapid drain currents. However, if large impedances are used, it must be considered that the rapid drain current flowing through the main circuit will generate sharp noise in the gate circuit. Therefore, malfunctions due to the switching action of the semiconductor device must be taken into account. Furthermore, if the semiconductor device malfunctions, it must be considered that current exceeding the semiconductor device's withstand voltage will flow into the circuitry included in the semiconductor device, potentially damaging the device. In addition, it must be considered that malfunctions in switching will lead to significant deviations in the power loss of the semiconductor device during switching, which may greatly affect the semiconductor device's heat generation and lifespan.

[0011] The present invention was made in view of the above circumstances, and the object of the present invention is to provide a technique for minimizing the impact on a semiconductor device while suppressing deviations in the magnitude of the current flowing through each of the semiconductor elements in a semiconductor device comprising semiconductor elements connected in parallel.

[0012] Technical solution for solving this problem

[0013] To solve the above problems, the present invention employs the following structure.

[0014] That is, a semiconductor circuit according to one aspect of the present invention includes: a first inductor unit connected in series with the source electrode of a first semiconductor element; and a second inductor unit connected in series with the source electrode of a second semiconductor element, the second semiconductor element being connected in parallel with the first semiconductor element, the first inductor unit and the second inductor unit being configured such that an induced electromotive force is induced in the first inductor unit and the second inductor unit due to magnetic interaction, and the currents flowing through the first inductor unit and the second inductor unit reinforce each other in the same direction.

[0015] According to this structure, even if the current flowing through the first and second semiconductor elements deviates, the current is adjusted to suppress the deviation in the current flowing through each semiconductor element through the mutual inductance electromotive force induced between the first and second inductors. Furthermore, according to this structure, the deviation in current flow can be suppressed without requiring a large impedance in the gate circuit. Therefore, according to this structure, the impact on the semiconductor device can be minimized.

[0016] Alternatively, according to the semiconductor circuit described above, the semiconductor circuit further comprises: a third inductor unit connected in series with the first inductor unit; and a fourth inductor unit connected in series with the second inductor unit. The third inductor unit is configured to generate a voltage in the direction opposite to the voltage applied to itself, by means of a first induced electromotive force induced by magnetic interaction from the first inductor unit, and to cause the first inductor unit to generate a voltage in the direction opposite to the voltage applied to it, by means of the first induced electromotive force induced by its own magnetic interaction. The fourth inductor unit is configured to generate a voltage in the direction opposite to the voltage applied to it, by means of a second induced electromotive force induced by magnetic interaction from the second inductor unit, and to cause the second inductor unit to generate a voltage in the direction opposite to the voltage applied to it, by means of the second induced electromotive force induced by its own magnetic interaction.

[0017] According to this structure, when a surge voltage is generated in a circuit equipped with a first inductor unit and a third inductor unit, a voltage is generated in the circuit in the opposite direction to the direction in which the surge voltage is applied due to the first mutual inductance electromotive force induced between the first and third inductor units. Therefore, the surge voltage can be reduced. Similarly, when a surge voltage is generated in a circuit equipped with a second inductor unit and a fourth inductor unit, a voltage is generated in the circuit in the opposite direction to the direction in which the surge voltage is applied due to the second mutual inductance electromotive force induced between the second and fourth inductor units. Therefore, the surge voltage can be reduced. Thus, the impact on semiconductor devices can be minimized as much as possible.

[0018] Alternatively, in the semiconductor circuit according to the above aspects, at least one of the first inductor unit, the second inductor unit, the third inductor unit, and the fourth inductor unit includes parasitic inductance.

[0019] This structure eliminates the need for components designed to suppress current deviations or reduce surge voltage, thus eliminating the need for mutual inductance electromotive force. This reduces the number of components required to form the circuit. Consequently, it simplifies the circuit manufacturing process, reduces component management costs, and lowers component costs.

[0020] Alternatively, according to the semiconductor circuit described above, the semiconductor circuit includes a plurality of stacked metal layers and insulating portions disposed between the plurality of metal layers, wherein a pair of predetermined metal layers opposite each other in the plurality of stacked metal layers are electrically connected in parallel, and the pair of predetermined metal layers are the first inductor unit and the second inductor unit.

[0021] According to this structure, a mutual induced electromotive force is induced in each of the pair of predetermined metal layers to suppress deviations in the amount of current flowing through the pair of predetermined metal layers. In other words, the problem can be solved without the need for components that generate mutual induced electromotive force to suppress current deviations. Therefore, the number of components forming the circuit is reduced. This simplifies the circuit manufacturing process, reduces component management costs, and lowers component costs, among other things.

[0022] Alternatively, in the semiconductor circuit according to the above aspects, the pair of predetermined metal layers are formed by a first metal layer and a second metal layer, a third metal layer opposite to the first metal layer is divided into a first part and a second part by the insulating portion, the first part, the first metal layer and the second part are electrically connected in series, a fourth metal layer opposite to the second metal layer is divided into a third part and a fourth part by the insulating portion, the third part, the second metal layer and the fourth part are electrically connected in series, the first metal layer is the first inductor unit, the second metal layer is the second inductor unit, the second part of the third metal layer is the third inductor unit, and the fourth part of the fourth metal layer is the fourth inductor unit.

[0023] According to this structure, when a surge voltage is generated in the first portion of the third metal layer, the first metal layer, and the second portion of the third metal layer connected in series, a mutual inductance electromotive force is induced in the first metal layer and the second portion of the third metal layer in the direction opposite to the direction in which the surge voltage is applied. Therefore, the surge voltage can be reduced. Similarly, when a surge voltage is generated in the third portion of the fourth metal layer, the second metal layer, and the fourth portion of the fourth metal layer connected in series, a mutual inductance electromotive force is induced in the second metal layer and the fourth portion of the fourth metal layer in the direction opposite to the direction in which the surge voltage is applied. Therefore, the surge voltage can be reduced. In other words, when a semiconductor element is mounted on the first portion of the third metal layer and the third portion of the fourth metal layer, and current flows through the semiconductor element, it is not necessary to have components that generate mutual inductance electromotive force to reduce surge voltage. Therefore, the number of components required to form the circuit is reduced. Therefore, the circuit manufacturing process can be simplified, component management costs can be reduced, or component costs can be reduced, etc.

[0024] Furthermore, the solutions used in this invention to solve the above problems can be combined in as many ways as possible.

[0025] Invention Effects

[0026] According to the present invention, the impact on the semiconductor device can be minimized as much as possible while suppressing deviations in the magnitude of the current flowing through each of the semiconductor elements in the semiconductor device, which includes semiconductor elements connected in parallel. Attached Figure Description

[0027] Figure 1 An outline of the current balance adjustment circuit according to an embodiment is shown.

[0028] Figure 2 An example of the electromotive force generated in a coil is shown.

[0029] Figure 3 The simulation results show the current and voltage variations over time when a voltage is applied to each gate of the switching element.

[0030] Figure 4 An outline of a current balancing circuit without a coil is shown.

[0031] Figure 5 An example of the first use case of the current balance adjustment circuit is shown.

[0032] Figure 6 An example of a second use case of the current balance adjustment circuit is shown.

[0033] Figure 7 A summary of the current balance adjustment circuit according to the second variation is shown. Detailed Implementation

[0034] §1 Application Examples

[0035] In the following description, examples of applications of the present invention will be illustrated with reference to the accompanying drawings. Figure 1 A summary of the current balance adjustment circuit 20 according to this embodiment is shown. The current balance adjustment circuit 20 includes coil 3A and coil 3B. Coils 3A and 3B are connected in series to switching elements 22A and 22B, respectively, and switching elements 22A and 22B are connected in parallel to the input power supply 21. Furthermore, coils 3A and 3B are configured such that the source (S) pole of coil 3A and the north (N) pole of coil 3B are close to each other, and the north (N) pole of coil 3A and the source (S) pole of coil 3B are close to each other.

[0036] Furthermore, the current balance adjustment circuit 20 includes coil 4A and coil 4B. Coil 4A is connected in series with coil 3A. Coil 4A and coil 3A are configured such that their respective source poles (S) are close to each other, and their respective north poles (N) are close to each other. Similarly, coil 4B is connected in series with coil 3B. Furthermore, coil 4B and coil 3B are configured such that their respective source poles (S) are close to each other, and their respective north poles (N) are close to each other.

[0037] According to the current balance adjustment circuit 20 described above, even if the current id1 and current id2 flowing through each switching element 22A and 22B deviate, the deviation is suppressed by the induced electromotive force between coils 3A and 3B. Therefore, according to the current balance adjustment circuit 20 described above, the impact on semiconductor devices can be minimized.

[0038] Furthermore, according to the current balance adjustment circuit 20 described above, when a surge voltage is generated in the circuit where coils 3A and 4A are provided, a voltage is generated in the circuit in the opposite direction to the direction in which the surge voltage is applied due to the induced electromotive force induced between coils 3A and 4A. Therefore, the surge voltage can be reduced. Similarly, when a surge voltage is generated in the circuit where coils 3B and 4B are provided, a voltage is generated in the circuit in the opposite direction to the direction in which the surge voltage is applied due to the induced electromotive force induced between coils 3B and 4B. Therefore, the surge voltage can be reduced. Thus, the impact on semiconductor devices can be minimized as much as possible.

[0039] §2 Configuration Example

[0040] [Hardware Configuration]

[0041] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0042] Figure 1A summary of a current balancing circuit 20 (an example of the "circuit" of this disclosure) according to this embodiment is shown. The current balancing circuit 20 includes a coil 3A (an example of the "first inductor unit" of this disclosure) and a coil 3B (an example of the "second inductor unit" of this disclosure). Coils 3A and 3B are connected in series to switching elements 22A (an example of the "first semiconductor element" of this disclosure) and 22B (an example of the "second semiconductor element" of this disclosure), respectively, and switching elements 22A and 22B are connected in parallel to an input power supply 21. Here, switching elements 22A and 22B are, for example, MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Furthermore, an input voltage Vin is applied from the input power supply 21 between the source and drain of each switching element 22A and 22B. Such switching elements 22A and 22B control the current flow between their source and drain by controlling their respective gate signal voltages, and adjust the power supplied from the input power supply 21 to the load 23. Furthermore, when current flows through coils 3A and 3B, magnetic fields are generated in coils 3A and 3B. Then, coils 3A and 3B are configured such that the S pole of the magnetic field formed by coil 3A is close to the N pole of the magnetic field formed by coil 3B, and the N pole of the magnetic field formed by coil 3A is close to the S pole of the magnetic field formed by coil 3B (hereinafter referred to as anti-polarity coupling). By configuring coils 3A and 3B in this way, magnetic interaction is generated between coils 3A and 3B.

[0043] Furthermore, the current balancing circuit 20 includes coil 4A (an example of the "third inductor unit" of this disclosure) and coil 4B (an example of the "fourth inductor unit" of this disclosure). Coil 4A is connected in series with coil 3A. Here, when current flows through coil 4A, a magnetic field is generated in coil 4A. Coil 4A and coil 3A are configured such that the S poles of their respective magnetic fields are close to each other, and the N poles of their respective magnetic fields are close to each other (hereinafter referred to as same-polarity coupling). By configuring coils 3A and 4A in this way, magnetic interaction is generated between coils 3A and 4A. Similarly, coil 4B is connected in series with coil 3B. Here, when current flows through coil 4B, a magnetic field is generated in coil 4B. Coil 3B and coil 4B are configured such that the S poles of their respective magnetic fields are close to each other, and the N poles of their respective magnetic fields are close to each other (hereinafter referred to as same-polarity coupling). By configuring coils 3B and 4B in this way, magnetic interaction is generated between coils 3B and 4B.

[0044] [Operation example]

[0045] When voltages are applied to the gates of the switching elements 22A and 22B, respectively, current id1 flows from switching element 22A to coil 3A. An electromotive force (EMF) is generated in coil 3A, causing a current to flow in the opposite direction to the current id1 flowing through coil 3A itself. Similarly, current id2 flows from switching element 22B to coil 3B. An EMF is generated in coil 3B, causing a current to flow in the opposite direction to the current id2 flowing through coil 3B itself.

[0046] Furthermore, in coil 3A, an induced electromotive force (EMF) corresponding to the current id2 flowing through coil 3B is induced through coil 3B, which is coupled with coil 3B with opposite polarity. This induced EMF causes the current to flow in the same direction as the current id2. Similarly, in coil 3B, an induced EMF corresponding to the current id1 flowing through coil 3A, which is coupled with coil 3A with opposite polarity, is induced. This induced EMF causes the current to flow in the same direction as the current id1.

[0047] Furthermore, the current id1 flowing through coil 3A flows into coil 4A. This generates an electromotive force (EMF) in coil 4A, which causes a current to flow in the opposite direction to the current id1 flowing through coil 4A itself. The magnitude of this EMF corresponds to the magnitude of the current id1 flowing through it. Similarly, the current id2 flowing through coil 3B flows into coil 4B. This generates an EMF in coil 4B, which causes a current to flow in the opposite direction to the current id2 flowing through coil 4B itself. The magnitude of this EMF corresponds to the magnitude of the current id2 flowing through it.

[0048] Furthermore, in coil 4A, an induced electromotive force (EMF) corresponding to the current id1 flowing through coil 3A is induced through coil 3A, which is coupled with coil 3A to the same polarity as itself (an example of the "first induced EMF" of this disclosure). This induced EMF causes the current to flow in the opposite direction to the current id1 flowing through coil 4A. Similarly, in coil 4B, an induced EMF corresponding to the current id2 flowing through coil 3B is induced through coil 3B, which is coupled with coil 3B to the same polarity as itself (an example of the "second induced EMF" of this disclosure). This induced EMF causes the current to flow in the opposite direction to the current id2 flowing through coil 4B. Figure 2 The diagram summarizes the electromotive forces V1 to V4 generated in coils 3A, 3B, 4A, and 4B. The directions of electromotive forces V1 and V3 are positive if they are opposite to the direction of current id1. Similarly, the directions of electromotive forces V2 and V4 are positive if they are opposite to the direction of current id2.

[0049] Here, L1 to L4 are the self-inductances of coils 3A and 3B, and coils 4A and 4B, respectively. Furthermore, ω is the angular frequency. Additionally, k1 is the magnetic coupling coefficient between coils 3A and 3B. Furthermore, k2 is the magnetic coupling coefficient between coils 3A and 4A, and between coils 3B and 4B.

[0050] Figure 3 The simulation results show the time-varying currents id1 and id2, and the voltage Vds2 applied to the load 23, when voltages are applied to the gates of switching elements 22A and 22B (hereinafter referred to as switch ON). Figure 3 In the case where switching elements 22A and 22B are each connected to the current balance adjustment circuit 20 of this embodiment ( Figure 3 (C) ) The case where switching elements 22A and 22B are not connected to the current balance adjustment circuit 20 ( Figure 3 (A) and the current balance adjustment circuit 20A with coils 3A and 3B but without coils 4A and 4B are respectively connected to switching elements 22A and 22B. Figure 3 The current balance adjustment circuit 20A is compared with (B). For example, the outline of the current balance adjustment circuit 20A is as follows: Figure 4 As shown.

[0051] like Figure 3 As shown in (A), when the current balancing circuit 20 is not connected and the switching elements 22A and 22B are turned on, the current id1, current id2, and voltage Vds2 fluctuate and gradually converge to a stable value. Furthermore, the current id1 and current id2 deviate at the initial stage of switch conduction, and their convergence values ​​are also different. In addition, Vds2 fluctuates greatly at the initial stage of switch conduction, generating a surge voltage.

[0052] On the other hand, such as Figure 3 As shown in (B), when connected to a current balancing circuit 20A that has coils 3A and 3B but not coils 4A and 4B, it is similar to... Figure 3 Compared to (A), the deviations of current id1 and current id2 are suppressed. Furthermore, the difference between the convergence values ​​of current id1 and current id2 is also reduced. Therefore, when coils 3A and 3B are coupled in opposite polarities, the deviations of current id1 and current id2 are suppressed. That is, it can be said that… Figure 2 The second term on the right side of each of the equations (1) and (2) shown is effective in suppressing the deviation between the current id1 and the current id2.

[0053] In addition, such as Figure 3 As shown in (C), when connected to the current balance adjustment circuit 20, with Figure 3Similar to (B), the deviation between current id1 and current id2 is suppressed. Furthermore, the difference between the convergence values ​​of current id1 and current id2 also decreases. Additionally, in Figure 3 In equation (C), the fluctuation of voltage Vds2 begins to decrease when the switch is turned on, and voltage Vds2 converges to a stable value earlier. Therefore, it can be said that when coils 3A and 4A, as well as coils 3B and 4B, are coupled with the same polarity, they have the effect of suppressing the fluctuation of Vds2 (surge voltage). That is, it can be said that the third term on the right side of equations (1) and (2) and the second term on the right side of equations (3) and (4) are effective in suppressing surge voltage.

[0054] [Usage Example]

[0055] Next, we will explain an example of using the current balance adjustment circuit 20. Figure 5 A summary of a synchronous rectification boost chopper circuit 30 is shown. The synchronous rectification boost chopper circuit 30 includes switching elements (22C, 22D) and switching elements (22E, 22F). Furthermore, the synchronous rectification boost chopper circuit 30 includes an input power supply 21 with an input voltage Vin, a reactor, a diode, a capacitor, and a load 23. Here, the switching elements (22C, 22D) and switching elements (22E, 22F) are connected in parallel. In the synchronous rectification boost chopper circuit 30, when an input voltage Vin is input from the input power supply 21, the output Vout, boosted by Vin, is generated by executing the switching control of each of the switching elements 22C to 22F. Here, the current balancing circuit 20 is connected to the switching elements (22C, 22D) and switching elements (22E, 22F), respectively. By configuring the current balance adjustment circuit 20 in this way, when the output is boosted to Vout, the current deviation and surge voltage generated in each switching element (22C, 22D) and switching element (22E, 22F) are suppressed, and the fault of the synchronous rectification type boost chopper circuit 30 is suppressed.

[0056] also, Figure 6 Another example of the use of the current balance adjustment circuit 20 is shown. Figure 6 This is an example of using the current balancing circuit 20 in an inverter circuit 40. An input power supply 21 with an input DC voltage Vin is provided in the inverter circuit 40. Furthermore, switching elements (22G, 22H), (22I, 22J), (22K, 22L), and (22M, 22N) are connected in parallel with the inverter circuit 40. When a DC voltage Vin is applied to such an inverter circuit 40 from the input power supply 21, an AC voltage Vout is output by executing the switching control of each of the switching elements 22G to 22N.

[0057] Furthermore, the current balance adjustment circuit 20 is connected to the switching elements (22G, 22H), (22I, 22J), (22K, 22L), and (22M, 22N), respectively. By configuring the current balance adjustment circuit 20 in this way, when outputting AC voltage, the current deviation and surge voltage generated in each of the switching elements (22G, 22H), (22I, 22J), (22K, 22L), and (22M, 22N) are suppressed, and the faults in the inverter circuit 40 are also suppressed.

[0058] In addition, Figure 5 , Figure 6 In addition to its applications, the current balance adjustment circuit 20 is also used in DC / DC converters and inverter topologies to suppress malfunctions in these devices.

[0059] [Function / Effect]

[0060] According to the current balance adjustment circuit 20 described above, coils 3A and 3B are connected in parallel. Through reverse polarity coupling, an induced electromotive force is induced in coil 3A from coil 3B. The induced electromotive force induced in coil 3A from coil 3B causes the current corresponding to current id2 to flow in the direction of current id2 flowing through switching element 22B (the second term of equation (1)). Similarly, an induced electromotive force is induced in coil 3B from coil 3A. The induced electromotive force induced in coil 3B from coil 3A causes the current corresponding to current id1 to flow in the direction of current id1 flowing through switching element 22A (the second term of equation (2)). Therefore, even if the current amounts id1 and id2 flowing in each switching element 22A, 22B deviate, such as Figure 3 (B) and Figure 3 As shown in (C), this deviation is suppressed. Furthermore, according to the current balance adjustment circuit 20 described above, the deviation between current id1 and current id2 can be suppressed without setting a large impedance in the gate circuit. Therefore, according to the current balance adjustment circuit 20 described above, the impact on the semiconductor device can be minimized.

[0061] Furthermore, according to the current balance adjustment circuit 20 described above, coils 3A and 4A are connected in series, and through same-polarity coupling, an induced electromotive force is induced in coil 3A from coil 4A. The induced electromotive force induced in coil 3A from coil 4A is generated in the direction opposite to the direction of the current id1 flowing through the switching element 22A (the third term of equation (1)), and is a value corresponding to the current id1. Similarly, an induced electromotive force is induced in coil 4A from coil 3A. The induced electromotive force induced in coil 4A from coil 3A is generated in the direction opposite to the direction of the current id1 flowing through the switching element 22A (the second term of equation (3)), and is a value corresponding to the current id1. That is, in the circuit connected to the switching element 22A, compared to the case where coil 3A is set alone, when the current id1 flows, a larger induced electromotive force is generated in the direction opposite to the flow direction of the current id1. That is, even if a surge voltage is generated in this circuit, compared to the case where coil 3A is set alone, it can be said that the effect of reducing the surge voltage is improved. Furthermore, this effect is confirmed by the following, relative to Figure 3 (B) Figure 3 The fluctuation of voltage Vds2 in (C) begins to decrease after the switch is turned on, and voltage Vds2 converges to a stable value relatively early. Therefore, the impact on semiconductor devices can be minimized.

[0062] Furthermore, similarly, coils 3B and 4B are connected in series, and through same-polarity coupling, an induced electromotive force is induced in coil 3B from coil 4B. The induced electromotive force induced in coil 3B from coil 4B is generated in the direction opposite to the direction of the current id2 flowing through switching element 22B (the third term of equation (2)), and is a value corresponding to the current id2. Similarly, an induced electromotive force is induced in coil 4B from coil 3B. The induced electromotive force induced in coil 4B from coil 3B is generated in the direction opposite to the direction of the current id2 flowing through switching element 22B (the second term of equation (4)), and is a value corresponding to the current id2. That is, in the circuit connected to switching element 22B, compared to the case where coil 3B is set alone, when the current id2 flows, a larger induced electromotive force is generated in the direction opposite to the flow direction of the current id2. That is, even if a surge voltage is generated in this circuit, it can be said that the effect of reducing the surge voltage is improved compared to the case where coil 3B is set alone. Furthermore, this effect is confirmed by the following, relative to Figure 3 (B) Figure 3 The fluctuation of voltage Vds2 in (C) decreases from the moment the switch is turned on, and voltage Vds2 converges to a stable value relatively early. Therefore, the impact on semiconductor devices can be minimized.

[0063] In this embodiment, the current balance adjustment circuit 20 is described as an example of a "semiconductor circuit" of this disclosure, but the current balance adjustment circuit 20A can also be an example of a "semiconductor circuit" of this disclosure. Figure 3 As shown in (B), such a current balance adjustment circuit 20A also has the effect of suppressing the deviation between current id1 and current id2.

[0064] §3 Variations

[0065] Although embodiments of the present invention have been described in detail above, the above description is merely illustrative in all respects. Various modifications and variations can be made without departing from the scope of the invention. For example, the following changes can be made. Hereinafter, the same reference numerals will be used to denote the same constituent elements as in the above embodiments, and descriptions of parts identical to those in the above embodiments will be appropriately omitted. The following variations can be appropriately combined.

[0066] <3.1>

[0067] The current balance adjustment circuit 20B according to the first modification includes a MIM (metal-insulator-metal) substrate 5. Furthermore, in the current balance adjustment circuit 20B, the parasitic inductance contained in the MIM substrate 5 is used instead of coils 3A, 3B and coils 4A, 4B. More specifically, the parasitic inductance contained in the MIM substrate 5 is used to achieve the current deviation suppression function and surge voltage suppression function achieved by coils 3A, 3B and coils 4A, 4B. Such a current balance adjustment circuit 20B has the same effects as the current balance adjustment circuit 20. In addition, since coils 3A, 3B and coils 4A, 4B are not provided in the current balance adjustment circuit 20B, the manufacturing process can be simplified by reducing the number of parts, thereby reducing part management costs or part costs.

[0068] <3.2>

[0069] Figure 7 An outline of the current balance adjustment circuit 20C according to the second variation is shown. Figure 7 (A) is a summary of the cross-sectional view of the current balance adjustment circuit 20C. Figure 7 (B) is a top view summary of the current balance adjustment circuit 20C. (See diagram below.) Figure 7As shown, the current balance adjustment circuit 20C has a MIM substrate 5A. The MIM substrate 5A is formed of four metal layers (M1 to M4), and an insulator is disposed between the metal layers. The M1 layer of the MIM substrate 5A is formed on the surface of the MIM substrate 5A (an example of the "third metal layer" of this disclosure). The M1 layer is divided into two regions (M1A and M1B, where M1A is an example of the "first part" of this disclosure and M1B is an example of the "second part" of this disclosure) by the insulator, and the switching element 22A is mounted on one region M1A. In addition, the M2 layer is disposed opposite to the M1 layer through the insulator (an example of the "first metal layer" of this disclosure). The M2 layer is connected in series with M1A of the M1 layer. In addition, the M2 layer is also connected in series with M1B.

[0070] Furthermore, layers M3 and M4 have the same structure as layers M1 and M2. That is, layer M3 is formed on the back side of the MIM substrate 5A (an example of the "fourth metal layer" of this disclosure). Layer M3 is divided into two regions (M3A and M3B, where M3A is an example of the "third part" of this disclosure and M3B is an example of the "fourth part") by an insulator, and the switching element 22B is mounted on one region M3A. Furthermore, layer M4 is configured to face layer M3 across an insulator (an example of the "second metal layer" of this disclosure). Layer M4 is connected in series with M3A of layer M3. Furthermore, layer M4 is connected in series with M3B of layer M3. Layer M4 is configured to face layer M2 across an insulator, although not shown, layer M4 and layer M2 are electrically connected. Here, layers M2 and M4 are an example of the "pair of predetermined metal layers" of this disclosure.

[0071] In this current balancing circuit 20C, since layers M2 and M4 are positioned opposite each other with an insulator in between, magnetic coupling is formed between layers M2 and M4. That is, layer M2 is a substitute for coil 3A, and layer M4 is a substitute for coil 3B. Furthermore, since layers M1 and M2 are positioned opposite each other with an insulator in between, magnetic coupling is formed between M1B of layer M1 and layer M2. That is, M1B is a substitute for coil 4A. Furthermore, since layers M3 and M4 are positioned opposite each other with an insulator in between, magnetic coupling is formed between M3B of layer M3 and layer M4. That is, M3B is a substitute for coil 4B.

[0072] The same effect as the current balance adjustment circuit 20 can be achieved by using the current balance adjustment circuit 20C as described above. Furthermore, since coils 3A, 3B and 4A, 4B are not included in the current balance adjustment circuit 20C, the manufacturing process can be simplified by reducing the number of parts, thereby reducing parts management costs or parts costs.

[0073] The above-disclosed implementation methods and variations can be combined with each other.

[0074] In order to compare the constituent elements of the present invention with the configuration of the embodiments, the constituent elements of the present invention will be described below by referring to the reference numerals in the accompanying drawings.

[0075] <Postscript 1>

[0076] A semiconductor circuit (20, 20A, 20B, 20C) comprising:

[0077] The first inductor unit (3A, M2) is connected in series with the source electrode of the first semiconductor element (22A); and

[0078] A second inductor unit (3B, M4) is connected in series with the source electrode of the second semiconductor element (22B), and the second semiconductor element (22B) is connected in parallel with the first semiconductor element (22A), wherein...

[0079] The first inductor unit (3A, M2) and the second inductor unit (3B, M4) are configured to induce an electromotive force in the first inductor unit (3A, M2) and the second inductor unit (3B, M4) through magnetic interaction, and the currents flowing through the first inductor unit (3A, M2) and the second inductor unit (3B, M4) reinforce each other in the same direction.

[0080] <Appendix 2>

[0081] The semiconductor circuits (20, 20B, 20C) according to Appendix 1 also include:

[0082] A third inductor unit (4A, M1B) connected in series with the first inductor unit (3A, M2); and

[0083] The fourth inductor unit (4B, M3B) is connected in series with the second inductor unit (3B, M4), wherein

[0084] The third inductor unit (4A, M1B) is configured to generate a voltage in the direction opposite to the voltage applied to itself, through a first induced electromotive force induced by the magnetic interaction from the first inductor unit (3A, M2), and to cause the first inductor unit (3A, M2) to generate a voltage in the direction opposite to the voltage applied to it, through the first induced electromotive force induced by its own magnetic interaction.

[0085] The fourth inductor unit (4B, M3B) is configured to generate a voltage in the direction opposite to the voltage applied to itself, by means of a second induced electromotive force induced by the magnetic interaction from the second inductor unit (3B, M4), and to cause the second inductor unit (3B, M4) to generate a voltage in the direction opposite to the voltage applied to the second inductor unit (3B, M4), by means of the second induced electromotive force induced by its own magnetic interaction.

[0086] <Appendix 3>

[0087] According to the semiconductor circuits (20, 20A, 20B, 20C) described in Appendix 1 or 2,

[0088] At least one of the first inductor unit (3A, M2), the second inductor unit (3B, M4), the third inductor unit (4A, M1B), and the fourth inductor unit (4B, M3B) includes a parasitic inductance.

[0089] <Appendix 4>

[0090] According to the semiconductor circuit (20C) in Appendix 3, it also has:

[0091] Multiple stacked metal layers and insulating portions disposed between the multiple metal layers, wherein

[0092] A pair of predetermined metal layers (M2, M4) opposite each other in the stacked plurality of metal layers are electrically connected in parallel.

[0093] The pair of predetermined metal layers (M2, M4) are the first inductor unit (M2) and the second inductor unit (M4).

[0094] <Appendix 5>

[0095] According to the semiconductor circuit (20C) described in Appendix 4, wherein,

[0096] The pair of predetermined metal layers (M2, M4) are formed by a first metal layer (M2) and a second metal layer (M4).

[0097] The third metal layer (M1), opposite to the first metal layer (M2), is divided into a first part (M1A) and a second part (M1B) by the insulating portion.

[0098] The first part (M1A), the first metal layer (M2), and the second part (M1B) are electrically connected in series.

[0099] The fourth metal layer (M3), opposite to the second metal layer (M4), is divided into a third part (M3A) and a fourth part (M3B) by the insulating portion.

[0100] The third part (M3A), the second metal layer (M4), and the fourth part (M3B) are electrically connected in series.

[0101] The first metal layer (M2) is the first inductor unit (M2).

[0102] The second metal layer (M4) is the second inductor unit (M4).

[0103] The second portion (M1B) of the third metal layer (M1) is the third inductor unit (M1B).

[0104] The fourth portion (M3B) of the fourth metal layer (M3) is the fourth inductor unit (M3B).

[0105] Explanation of reference numerals in the attached figures

[0106] 3A, 3B: Coils; 4A, 4B: Coils; 5, 5A: Baseboard; 20, 20A, 20B, 20C: Current balance adjustment circuit; 21: Input power supply; 22A~22N: Switching element; 23: Load; 30: Synchronous rectification type boost chopper circuit; 40: Inverter circuit.

Claims

1. A semiconductor circuit comprising: The first inductor unit is connected in series with the source electrode of the first semiconductor element; The second inductor unit is connected in series with the source electrode of the second semiconductor element, and the second semiconductor element is connected in parallel with the first semiconductor element; The third inductor unit is connected in series with the first inductor unit; as well as The fourth inductor unit is connected in series with the second inductor unit. The first inductor and the second inductor are configured such that an induced electromotive force is generated in the first inductor and the second inductor due to magnetic interaction, and the currents flowing through the first inductor and the second inductor reinforce each other in the same direction. The third inductor unit is configured to generate a voltage in the direction opposite to the voltage applied to it, through a first induced electromotive force induced by the magnetic interaction from the first inductor unit, and to cause the first inductor unit to generate a voltage in the direction opposite to the voltage applied to it, through the first induced electromotive force induced by its own magnetic interaction. The fourth inductor is configured to generate a voltage in the direction opposite to the voltage applied to itself, by means of a second induced electromotive force induced by the magnetic interaction from the second inductor, and to cause the second inductor to generate a voltage in the direction opposite to the voltage applied to the second inductor, by means of the second induced electromotive force induced by its own magnetic interaction.

2. The semiconductor circuit according to claim 1, wherein, At least one of the first inductor unit, the second inductor unit, the third inductor unit, and the fourth inductor unit includes parasitic inductance.

3. The semiconductor circuit according to claim 2, wherein, The semiconductor circuit includes multiple stacked metal layers and insulating portions disposed between the multiple metal layers. A pair of predetermined metal layers that are opposite each other in the stacked plurality of metal layers are electrically connected in parallel. The pair of predetermined metal layers are the first inductor unit and the second inductor unit.

4. The semiconductor circuit according to claim 3, wherein, The pair of predetermined metal layers are formed by a first metal layer and a second metal layer. The third metal layer, opposite the first metal layer, is divided into a first part and a second part by the insulating portion. The first part, the first metal layer, and the second part are electrically connected in series. The fourth metal layer, opposite the second metal layer, is divided into a third part and a fourth part by the insulating portion. The third part, the second metal layer, and the fourth part are electrically connected in series. The first metal layer is the first inductor unit. The second metal layer is the second inductor unit. The second portion of the third metal layer is the third inductor unit. The fourth portion of the fourth metal layer is the fourth inductor unit.

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