Storage space mapping method for SGL and apparatus thereof

Abstract

Provided are a storage space mapping method for an SGL and a device thereof. A method for processing a cache includes obtaining an IO command; allocating one or more entries from a first memory according to the IO command, each of the one or more entries of the first memory corresponding to an entry of a second memory; obtaining data to be accessed by the IO command, and caching the one or more entries of the second memory corresponding to the one or more entries of the first memory.

Description

Technical Field

[0001] This application relates to memory space mapping, and more particularly to a memory space mapping method for SGL and an apparatus for implementing and using the method. Background Technology

[0002] Figure 1 A block diagram of the storage device is shown. Storage device 102 is coupled to a host to provide storage capabilities to the host. The host and solid-state storage device 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), UFS (Universal Flash Storage), eMMC (embedded MMC (MultiMediaCard)), Ethernet, Fibre Channel, and wireless communication networks. The host can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and optionally DRAM (Dynamic Random Access Memory) 110. Some storage devices omit DRAM to reduce costs; instead, the control unit 104 integrates memory such as SRAM.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] ScatterGatherList (SGL) describes a discrete data cache and is used for data description between the host and information processing devices. For example, according to NVMe protocol I / O commands, SGL can be used to describe the host's data cache and the logical address of the corresponding storage device.

[0008] SGL consists of one or more SGL segments. Figure 2A This diagram illustrates the SGL segmentation in the NVMe protocol. An SGL segment comprises one or more SGL descriptors, each with a fixed size (e.g., 16 bytes).

[0009] Figure 2B A schematic diagram of an SGL descriptor is shown. An SGL descriptor consists of an SGL identifier and a content portion that varies depending on the descriptor type. Figure 2B(This is displayed as a "descriptor type specific" field).

[0010] Figure 2C This diagram illustrates the SGL descriptor types. SGL descriptors include various types, each with a specific type.

[0011] Typically, the SGL descriptor describes the address and length of the data cache. In the NVMe protocol, the data cache described by the SGL descriptor resides in the memory of the device issuing the I / O command (e.g., the host).

[0012] Figure 3 A schematic diagram illustrating existing technology for transmitting data based on SGL is shown.

[0013] Host 310 is coupled to storage device 102. The host includes CPU 320 and memory 340. Host 310 prepares an SGL and one or more data caches for providing I / O commands to storage device 102. Figure 3 The diagram illustrates data cache A, data cache B, and data cache C. The data cache is used to hold data associated with I / O commands. If the I / O command is a write command, the data to be written to storage device 102 is stored in the data cache; if the I / O command is a read command, the data read from storage device 102 is moved to the data cache.

[0014] The data cache is discrete, comprising one or more data cache blocks, each of the same or different sizes, and located at any location in memory 340. The SGL describes one or more data cache blocks used by the same I / O command, so that the storage device obtains the SGL based on the I / O command to know the data cache of that I / O command.

[0015] IO commands also describe the logical address and length of the storage device. For example, an IO command indicates the starting logical address (X) and the data length (n) to be accessed.

[0016] exist Figure 3 In the example, SGL includes 4 segments, which describe the 3KB of data starting from logical address X as associated with data cache block A, the next 4KB of data at the logical address as associated with data cache block C, the next 2KB of data at the logical address as belonging to the bit bucket (not associated with any data cache block), and the next 4KB of data at the logical address as associated with data cache block B.

[0017] To process I / O commands, the control unit of storage device 102 obtains SGL from host 310 and moves data between the data cache in host memory and storage device according to SGL.

[0018] If the IO command is a write command, storage device 102 writes data cache block A of host memory 340 to the 3KB storage space starting at logical address X according to SGL; writes data cache block B to the 4KB storage space starting at logical address X+9KB; and writes data cache block C to the 4KB storage space starting at logical address X+3KB.

[0019] If the IO command is a read command, storage device 102 will move 3KB of data starting from logical address X to data cache block A of host memory 340 according to SGL; move 4KB of data starting from logical address X+3KB to data cache block C; and move 4KB of data starting from logical address X+9KB to data cache block B.

[0020] Optionally, storage device 102 also provides a cache unit to receive data retrieved from the data cache of host 310 or data read from the NVM chip. The logical address accessed by the IO command may be different from the address of the cache unit and also different from the address of the NVM chip.

[0021] Figure 4 A detailed schematic diagram of SGL based on existing technology is shown.

[0022] For example, an IO command is a read command. The SGL indicated by the IO command includes SGL segment 0, SGL segment 1, and SGL segment 2. SGL segment 0 includes two descriptors: one indicating the address and length (3KB) of data block A in host memory, and the other indicating the address of SGL segment 1. Thus, the storage device obtains SGL segment 1 based on SGL segment 0. SGL segment 1 includes three descriptors: one indicating the address and length (4KB) of data block B in host memory, the second indicating the bit bucket (BB) and its length (2KB), and the third indicating the address of SGL segment 2.

[0023] The SGL segments and descriptors within each segment are linked sequentially. These descriptors, in addition to indicating the host address (data block address or SGL segment address), also imply their position in the logical address space accessed by the I / O command. Each SGL segment and its descriptor correspond to a sequentially arranged logical address range in the logical address space accessed by the I / O command. For example, let the logical address range accessed by the IO command be from logical address x to logical address X+n (length n = 13KB) (excluding point X+n). The first descriptor of SGL segment 0 corresponds to a logical address range from x to x+3KB, where the size of this range "3KB" is also the length indicated by the descriptor. The first descriptor of SGL segment 1 corresponds to a logical address range from x+3KB to X+7KB, where the size of this range "4KB (=7KB-3KB)" is also the length indicated by the descriptor. The second descriptor of SGL segment 1 (of type bit bucket) corresponds to a logical address range from x+7KB to X+9KB. Since the second descriptor is a bit bucket, the data in its corresponding logical address range is not transmitted to the host.

[0024] Continue reading Figure 4 SGL segment 2 includes one descriptor that indicates the address and length (4KB) of the data block C in the host memory, and the corresponding logical address range is from x+9KB to x+13KB, where the size of the range is "4KB (=13KB-9KB)".

[0025] The storage device retrieves SGL segment 0 from the host based on the I / O command (read command) and extracts the descriptors from SGL segment 0. Based on the first descriptor, it moves 3KB of data starting at logical address X to data block A in host memory. Based on the second descriptor, it retrieves SGL segment 1. The storage device then moves 4KB of data starting at logical address X+3KB to data block B in host memory based on the first descriptor of SGL segment 1. Based on the second descriptor (bit bucket) of SGL segment 1, it skips 2KB of data starting at logical address X+7KB (this 2KB of data is not moved to host memory). Based on the third descriptor, it retrieves SGL segment 2. The storage device then moves the 4KB of data starting from logical address X+9KB to data block C in host memory according to the first descriptor of SGL segment 2. SGL segment 1 also indicates that SGL segment 2 is the last segment of its SGL. Thus, the storage device knows that the processing of its SGL is complete and the data movement of the IO command to which the SGL belongs is complete, based on the fact that all descriptors of SGL segment 2 have been processed.

[0026] In addition to writing the contents of the host data blocks described by the SGL (referred to as user data) to the storage medium, the control unit also attaches metadata to the user data written to the storage medium and writes the metadata to the storage medium as well. The metadata describes the user data associated with it; for example, the metadata records the logical address of the storage device carrying the user data. Summary of the Invention

[0027] SGL has a relatively complex structure (a variable number of segments and descriptors organized in the form of linked lists), and the data blocks described by SGL are discretely distributed. Each SGL descriptor corresponds to a data block of variable size (destination address), and also allows for non-contiguous logical addresses (source address) (through bit buckets). This gives SGL strong data representation capabilities, but also introduces complexity to its parsing. The control unit of the storage device must parse the SGL when using it for data transfer. When transferring a data block associated with a specific logical address, it is necessary to traverse the SGL to find the corresponding SGL descriptor before initiating the data transfer, reducing data transfer efficiency. The traversal complexity of the SGL is approximately O(N) (where N is the length of the linked list or the number of descriptors in the SGL). When the SGL is long, traversing the SGL also introduces significant processing latency, affecting the performance of the storage device in processing I / O commands.

[0028] It is also necessary to obtain metadata associated with the user data, or at least a portion thereof, such as the logical address of the storage device carrying the user data, and write the user data along with the metadata to the storage medium. Generating metadata for user data and writing the metadata along with the user data to the storage medium incurs additional access to the memory that caches the metadata and increases the overhead of the I / O command processing.

[0029] According to a first aspect of this application, a method for a first processing cache according to the first aspect of this application is provided, comprising: obtaining an I / O command; allocating one or more entries from a first memory according to the I / O command, wherein each of the one or more entries in the first memory corresponds to an entry in a second memory; obtaining data to be accessed by the I / O command and caching it in one or more entries in the second memory corresponding to the one or more entries in the first memory.

[0030] According to a first method of using a cache according to a first aspect of this application, a second method of processing a cache according to a first aspect of this application is provided, wherein the first memory is a TCM, the second memory is an SRAM; the first memory is directly coupled to a processor; the second memory is coupled to the processor via a bus; and the processor executes the method.

[0031] According to the first or second method of using a cache according to the first aspect of this application, a third method of using a cache according to the first aspect of this application is provided, further comprising: recording an index indicating an entry of the first memory in one or more entries allocated from the first memory, such that the one or more entries of the first memory constitute a linked list.

[0032] According to one of the first to third methods of using a cache according to the first aspect of this application, a fourth method of using a cache according to the first aspect of this application is provided, which further includes: recording data to be accessed by an I / O command in one or more entries of a second memory; and recording metadata corresponding to the data in the corresponding entries of the second memory in the one or more entries of the first memory.

[0033] According to the fourth method of using a cache according to the first aspect of this application, a fifth method of using a cache according to the first aspect of this application is provided, which further includes: obtaining metadata from a first entry in a first memory, obtaining data from a second entry in a second memory corresponding to the first entry; combining the metadata obtained from the first entry and the data obtained from the second entry and writing it into the NVM.

[0034] According to the fourth or fifth method of using cache according to the first aspect of this application, a sixth method of using cache according to the first aspect of this application is provided, which further includes: reading the combined first metadata and first data from the NVM; storing the first metadata in a first entry; and storing the first data in a second entry.

[0035] According to the fifth or sixth method of using a cache according to the first aspect of this application, a seventh method of using a cache according to the first aspect of this application is provided, further comprising: obtaining an index indicating a third entry of the first memory from the first entry in the process of obtaining metadata from the first entry of the first memory; obtaining metadata from the third entry of the first memory and obtaining data from a fourth entry of the second memory corresponding to the third entry; combining the metadata obtained from the third entry and the data obtained from the fourth entry and writing it into the NVM; and repeating the above process until all the data accessed by the IO command is written into the NVM.

[0036] According to one of the fifth to seventh methods of using a cache according to the first aspect of this application, an eighth method of using a cache according to the first aspect of this application is provided, further comprising: in the step of obtaining metadata from a first entry of a first memory, obtaining an index indicating a fifth entry of the first memory from the first entry; and reading a combination of second metadata and second data from the NVM; storing the second metadata in the fifth entry, and storing the second data in a sixth entry of the second memory corresponding to the fifth entry; and repeating the above process until all the data accessed by the IO command is read from the NVM.

[0037] According to one of the first to eighth methods of using a cache according to the first aspect of this application, a ninth method of using a cache according to the first aspect of this application is provided, wherein the number of entries allocated from the first memory is determined based on the size of the address space to be accessed by the IO command.

[0038] According to the ninth method of using a cache according to the first aspect of this application, a tenth method of using a cache according to the first aspect of this application is provided, wherein the one or more entries allocated from the first memory are ordered, and their sequence numbers indicate the address space range accessed by the I / O command.

[0039] According to the ninth or tenth method of using a cache according to the first aspect of this application, an eleventh method of using a cache according to the first aspect of this application is provided, wherein each of the one or more entries allocated from the first memory includes one or more descriptors; the descriptors record the cache address and length of the data to be accessed by the provider of the IO command; and the one or more entries in the second memory have the same size.

[0040] According to one of the first to eleventh methods of using a cache according to the first aspect of this application, a twelfth method of using a cache according to the first aspect of this application is provided, wherein the one or more entries of the first memory have the same size.

[0041] According to one of the first to twelfth methods of using a cache according to the first aspect of this application, a thirteenth method of using a cache according to the first aspect of this application is provided, further comprising: in response to allocating one or more entries from a first memory according to an IO command, if the IO command is a write command, indicating to the provider of the IO command that data to be written by the write command can be received.

[0042] According to the thirteenth method of using a cache according to the first aspect of this application, a fourteenth method of using a cache according to the first aspect of this application is provided, wherein in response to allocating one or more entries from a first memory according to an IO command, if the IO command is a write command, data of a specified length to be written by the write command is obtained from the cache address of the provider of the IO command according to the descriptor recorded in the entry of the first memory, and stored in an entry of a second memory corresponding to the entry of the first memory.

[0043] According to one of the first to fourteenth methods of using cache according to the first aspect of this application, a fifteenth method of using cache according to the first aspect of this application is provided, further comprising: if the IO command is a read command, in response to one or more entries in the second memory caching the data to be accessed by the IO command, sending the data to be read by the read command to the provider of the IO command.

[0044] According to the fifteenth method of using a cache according to the first aspect of this application, a sixteenth method of using a cache according to the first aspect of this application is provided, wherein: if the IO command is a read command, in response to one or more entries in the second memory caching the data to be accessed by the IO command, one or more entries in the first memory corresponding to the one or more entries in the second memory are determined, and the data to be read by the read command is sent to the cache of the provider of the IO command according to the cache address and length of the data to be accessed by the IO command recorded in the data descriptor of the one or more entries in the first memory.

[0045] According to a second aspect of this application, a first storage device according to the second aspect of this application is provided, including a control unit and a non-volatile memory chip, the control unit including a processor, the processor performing a method of using a cache according to one of the first to sixteenth methods of the first aspect of this application.

[0046] According to the first storage device of the second aspect of this application, a second storage device according to the second aspect of this application is provided, wherein the control component further includes a first memory and a second memory; the first memory is directly coupled to the processor; and the second memory is coupled to the processor via a bus.

[0047] According to the second storage device of the second aspect of this application, a third storage device according to the second aspect of this application is provided, wherein the first memory is a TCM; and the second memory is an SRAM. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0049] Figure 1 This is a block diagram of a storage device in the prior art;

[0050] Figure 2A A schematic diagram of SGL segmentation is shown;

[0051] Figure 2B A schematic diagram of the SGL descriptor is shown;

[0052] Figure 2C A diagram illustrating SGL descriptor types is shown;

[0053] Figure 3 This diagram illustrates the existing technology of transmitting data according to SGL.

[0054] Figure 4 A detailed schematic diagram of SGL based on existing technology is shown;

[0055] Figure 5 A schematic diagram illustrating a list of data descriptors according to an embodiment of this application is provided;

[0056] Figure 6 A schematic diagram illustrating a data descriptor list according to yet another embodiment of this application is provided;

[0057] Figure 7 A schematic diagram illustrating data organization according to yet another embodiment of this application is shown;

[0058] Figure 8 A schematic diagram illustrating the processing of a write command according to yet another embodiment of this application is shown;

[0059] Figure 9 A schematic diagram illustrating the processing of a read command according to yet another embodiment of this application is shown;

[0060] Figure 10 A diagram illustrating yet another type of I / O command for storage devices; and

[0061] Figure 11 A schematic diagram illustrating a list of data descriptors according to another embodiment of this application is shown. Detailed Implementation

[0062] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0063] Figure 5 A schematic diagram illustrating a list of data descriptors according to an embodiment of this application is shown.

[0064] SGL 510 is the SGL obtained based on the I / O command to be processed. The SGL includes linked segments and SGL descriptors. Descriptors indicating SGL data blocks are sequentially associated with the contiguous logical address space accessed by the I / O command. Figure 5 The LBA space is represented by LBAX to LBAX+5, which are five storage units. SGL 510 describes a 20KB data block, so each storage unit in each LBA space is 4KB in size. The associated LBA space is determined by the position of the SGL data block descriptor in the SGL, and the SGL data block descriptor records the address (not shown) and length of the data block in the host memory.

[0065] The data descriptor list 580 includes multiple data transmission unit nodes (530, 535, 540, 545, and 550). Each data transmission unit node includes one or more data descriptors (532, 534, 537, 542, 547, 548, 549, and 552).

[0066] The data descriptor list 580 includes multiple data transfer unit nodes, which are also linked sequentially. Each data transfer unit node records the index or address of the next data transfer unit node it is linked to. Each data transfer unit node indicates a storage space of the same size (e.g., 4KB). A 4KB data size is referred to as a data transfer unit. When the storage device processes I / O commands, its control unit initiates data transfer in units of data transfer units. The data transfer unit nodes in the data descriptor list 580 correspond to one of the data transfer units. Data transfer unit node 530 corresponds to data transfer unit 510, data transfer unit node 535 corresponds to data transfer unit 512, and so on.

[0067] See Figure 5 The SRAM stores multiple data transfer units (511, 512, 514, and 516), which store user data provided by the host to the storage device, or user data read from the storage medium and to be provided to the host. The SRAM also stores metadata (520, 522, 524, and 526) associated with the user data of the data transfer units. Metadata 520 is associated with data transfer unit 510, metadata 522 is associated with data transfer unit 512, and so on. Thus, based on the data transfer unit node, the corresponding data transfer unit and its metadata can be accessed.

[0068] In SRAM, data transfer units and their metadata are stored separately from each other, while in storage media such as NVM chips, data transfer units and their metadata are stored in the same page, allowing access to the data transfer units and their metadata through a single read or write command to access the NVM chip.

[0069] The data descriptor of the data transfer unit node records the address and length of the data block in the host memory. There is a many-to-one relationship between the data descriptor and the SGL descriptor; one or more data descriptors are generated based on the SGL descriptor.

[0070] Data descriptors (532 and 534) are grouped together and belong to data transmission unit node 530; data descriptor (537) is grouped separately and belongs to data transmission unit node 535; data descriptor (542) is grouped separately and belongs to data transmission unit node 540; data descriptors (547, 548, and 549) are grouped together and belong to data transmission unit node 545; and data descriptor (552) is grouped separately and belongs to data transmission unit node 550. The size of the host memory space described by each group of multiple data descriptors has a specified length. In the example according to this application, the specified length is, for example, 4KB.

[0071] The data descriptor (552) corresponds to the last SGL descriptor of SGL 810 and also belongs to the last data transfer unit node in the data descriptor list 528. The size of the host memory space described by the last data transfer unit node may be less than the length of a data transfer unit.

[0072] Optionally, the data transfer unit nodes in the data descriptor list 580 are ordered, so that the position of the data transfer unit node in the data descriptor list 580 indicates the position of the data of its corresponding data transfer unit within the logical address range accessed by the IO command. The data transfer unit nodes in the data descriptor list 580 are sequentially associated with the contiguous logical address space accessed by the IO command. Figure 5 The LBA space is represented by LBAX to LBAX+5 (excluding point X+5). Based on the position of the data transfer unit node in the data descriptor list 580, its associated LBA space is determined. Furthermore, the position of the corresponding data transfer unit node in the data descriptor list 580 is directly determined based on the LBA space to be accessed. Optionally, the data transfer unit nodes in the data descriptor list 580 do not need to be sorted, and the data transfer unit node also records the position of its corresponding data within the logical address range accessed by the IO command.

[0073] SGL 510 and data descriptor list 580 each describe the data transfer required by the same IO command.

[0074] Therefore, in order to process I / O commands, such as read commands, one or more data transfer units belonging to that command must be transferred to the data cache block of host memory described by the SGL of the read command. The control unit of the storage device controls the data transfer process according to the data descriptor list 580. For example, one of the data transfer unit nodes is obtained from the data descriptor list 580, which indicates the storage location of the data transfer unit and its metadata in the SRAM of the storage device. According to the logical address corresponding to the obtained data transfer unit node, the control unit reads user data and metadata from the NVM chip, stores the read user data in the data transfer unit indicated by the data transfer unit node, and stores the read metadata in the corresponding metadata storage location in the SRAM.

[0075] The control unit also acquires a set of data descriptors included in the data transfer unit node, which collectively describe a data cache block in host memory equal to the size of the data transfer unit node. Based on each of these data descriptors, the control unit initiates a DMA transfer from the data transfer unit in the SRAM of the storage device to the host memory address and length indicated by the data descriptor. The control unit repeats the above data transfer process for all data transfer unit nodes in the data descriptor list 580 to complete the processing of the read command.

[0076] If the I / O command is a write command, the control unit obtains a corresponding set of data descriptors for each data transfer unit node in the data descriptor list 580, and initiates data transfer from host memory to SRAM based on each data descriptor in that set. It also writes metadata corresponding to the data transfer unit to the SRAM, and writes the data transfer unit along with its corresponding metadata to the NVM chip.

[0077] Therefore, according to the embodiments of this application, a data descriptor list 580 is first generated based on the IO command and SGL 510, and then the data descriptors are obtained based on the data descriptor list 580, and DMA transfer is initiated. Initiating DMA transfer based on the data descriptors in the data descriptor list 580 eliminates the need to traverse the SGL. Furthermore, when the control unit concurrently processes multiple IO commands using multiple processing units, the process of generating a data descriptor list for each IO command based on its SGL occurs during the data transfer with the host for other IO commands, thus hiding the process of generating the data descriptor list and further improving the efficiency of IO command processing.

[0078] To generate the data descriptor list 580, optionally, also refer to Figure 5The 3KB host memory space indicated by the first SGL descriptor in SGL 510, plus the first 1KB host memory space indicated by the second SGL descriptor in SGL 510, forms a 4KB host memory space equal to the data transfer unit size. Therefore, a data transfer unit node comprising two data descriptors is generated and added to the data descriptor list 580. Data transfer units are also allocated in SRAM, and the address or index of the corresponding data transfer unit in SRAM is recorded in the generated data transfer unit node. Furthermore, a cache storing the corresponding metadata is allocated in SRAM, and the logical address corresponding to the generated data transfer unit node is recorded in the metadata cache as part or all of the metadata.

[0079] Similarly, all remaining SGL descriptors are split into data descriptor groups representing 4K of host memory space and stored in data descriptor list 580.

[0080] According to embodiments of this application, a data descriptor list describes data transfer between the host and the storage device. During I / O command processing, the data descriptor list is accessed multiple times. It is necessary to optimize access to the data descriptor list and reduce the number of memory accesses to speed up I / O command processing.

[0081] Figure 6 A schematic diagram illustrating a list of data descriptors according to yet another embodiment of this application is shown.

[0082] Compared to Figure 5 The illustrated embodiments are based on Figure 6 In this embodiment, the data descriptor list 680 includes multiple data transfer unit nodes (630, 635, 640, 645, and 650). Each data transfer unit node includes one or more data descriptors (632, 634, 637, 642, 647, 648, 649, and 652). Each data transfer unit node also includes metadata corresponding to the data transfer unit (620, 622, 624, and 626). Thus, the corresponding metadata can be obtained while accessing the data transfer unit node, and the SRAM only stores the data transfer units (511, 512, 514, and 516) and no longer stores the metadata. Accessing the data descriptor list 680 is essential during the process of writing data to the NVM chip, but according to... Figure 6 In this embodiment, the corresponding metadata is obtained while accessing the data transfer unit node of the data descriptor list 680, which saves at least one memory access operation to read metadata from SRAM and speeds up the processing of IO commands.

[0083] Optionally or further, a list of data descriptors 680 is stored in the TCM (Tight-Coupled Memory) 670 of the control unit of the storage device. The TCM 670 is directly coupled to the processor of the control unit via a dedicated bus, while the SRAM is coupled to the processor of the control unit via a bus shared with other components. This allows the processor to access the TCM 670 faster than accessing the SRAM, further accelerating the processing of I / O commands.

[0084] according to Figure 6 In this embodiment, to process a write command, the SGL 510 for obtaining the write command is used. Based on the SGL 510, a data descriptor list 680 is generated using the TCM 670, and a data transmission unit is allocated to each data transmission unit node in the data descriptor list 680. When generating each data transmission unit node in the data descriptor list 680, corresponding metadata is also generated and recorded in the data transmission unit node. For example, the metadata 620 records the logical address corresponding to the data transmission unit node 630. Optionally, the control unit may also generate the metadata for each data transmission unit node in other ways.

[0085] Next, the control unit moves the user data to be written to the storage device by the write command from the host to the data transfer units (511, 512, 514, 516) in the SRAM according to the data descriptors of each data transfer unit node (630, 635, 640, 645) in the data descriptor list 680.

[0086] The control unit also traverses the data descriptor list 680, accessing each data transmission unit node (630, 635, 640, 645), obtaining the index and metadata (620, 622, 624, 626) of the associated data transmission units (511, 512, 514, 516), and writes the user data and corresponding metadata of the data transmission units to the NVM. By obtaining the data transmission unit node and its corresponding index and metadata in a single TCM access, the operation of writing each data transmission unit and its metadata to the NVM is significantly faster than... Figure 5 The illustrated embodiment eliminates at least one memory access operation. In yet another example, the data transfer from the host to the data transfer unit also occurs during this traversal of the data descriptor list 680, thereby obtaining the data transfer unit node and its corresponding host address, data transfer unit index, and metadata in a single TCM access.

[0087] according to Figure 6In one embodiment, for example, to process a read command, the SGL of the read command is obtained. A data descriptor list is generated using the TCM670 based on the SGL, and a data transmission unit is allocated to each data transmission unit node in the data descriptor list. Storage space for storing metadata is also reserved in each data transmission unit node of the data descriptor list 680. Optionally, during the generation of each data transmission unit node of the data descriptor list 680, the logical address corresponding to the data transmission unit node is also recorded in the reserved metadata storage space.

[0088] Next, the control unit reads data from the NVM chip according to the logical addresses corresponding to each data transmission unit node in the data descriptor list. The data read from the NVM chip includes user data and metadata. The read user data is stored in the data transmission unit corresponding to the data transmission unit node in the same data descriptor list, and the read metadata is stored in the storage space reserved for metadata within the data transmission unit node.

[0089] The control unit also traverses the list of data descriptors, accesses each of its data transmission unit nodes, obtains the index and optional metadata (620, 622, 624, 626) of the associated data transmission unit, and moves the user data of the data transmission unit and the corresponding optional metadata together to the host memory space indicated by the data descriptor of the data transmission unit node.

[0090] Figure 7 A schematic diagram illustrating data organization according to yet another embodiment of this application is shown.

[0091] The CPU of the control unit is coupled to the TCM and SRAM. The TCM is coupled to the CPU via a dedicated high-speed bus, while the SRAM is coupled to the CPU via a bus shared with other components.

[0092] Both the TCM and SRAM contain multiple entries (entry 0 through entry 5). The entry number is used to index the entry and determine its storage location in the TCM and SRAM. Entries with the same number in the TCM and SRAM are associated with each other. Therefore, based on the same entry number, it is possible to access both the TCM entry and the corresponding SRAM entry.

[0093] TCM entries are used to store data transfer unit nodes for metadata and data descriptor lists. SRAM entries are used to store data transfer units. All TCM entries and SRAM entries are the same size. The data transfer unit node of a TCM entry records the index of the next TCM entry belonging to the same data descriptor list as that data transfer unit node. The index of a TCM entry can have a smaller size compared to the storage space address of the TCM or SRAM.

[0094] The control unit of the storage device generates a list of data descriptors based on the SGL of the IO command. Figure 7 The example demonstrates the data descriptor lists (710 and 720) generated for two IO commands. Data descriptor list 710 indicates the index of its first data transfer unit node in the TCM (index of entry 0), and data descriptor list 720 indicates the index of its first data transfer unit node in the TCM (index of entry 1). The data transfer unit node of entry 0 in the TCM indexes entry 2, and then entry 2 indexes entry 5, thus entries 0, 2, and 5 in the TCM constitute the data transfer unit nodes of data descriptor list 710.

[0095] During the process of generating a data descriptor list based on the SGL according to the IO command, an entry of TCM is assigned to each generated data transfer unit node, and the generated data transfer unit node is recorded in the assigned entry. In addition, the entry index of the generated data transfer unit node is also recorded in the data descriptor list relative to the previous data transfer unit node.

[0096] According to embodiments of this application, the entries allocated to the TCM also represent the allocated SRAM entries. TCM entries and SRAM entries with the same entry number are allocated and released simultaneously or in association. Thus, based on the number of the TCM entry containing the data transfer unit, the corresponding SRAM entry and the data transfer unit therein used to store user data can be indexed.

[0097] Optionally, metadata is also written to the TCM entry.

[0098] Optionally, the data transmission unit nodes of each entry in the TCM have the same size.

[0099] Optionally, the metadata of a TCM entry shares a portion of the TCM entry's storage space with the data transfer unit node. For example, for a write command, after the data to be written is moved from the host to the SRAM entry based on the data descriptor of the data transfer unit, that data descriptor is no longer used; the generated metadata overwrites the data descriptor, thereby further reducing the size of the TCM entry. Again, as an example, some metadata read from the NVM chip does not need to be provided to the host; the storage space in the TCM entry used for metadata is used to store the data descriptor.

[0100] During the process of writing data to the NVM according to the data descriptor list, the data descriptor list is traversed, and an entry is read from the TCM. The metadata recorded in the TCM entry and the corresponding data transfer unit in SRAM are written to the NVM together. The index of the TCM entry recording the next data transfer unit node is also obtained from the read entries in the TCM. This process only requires accessing the TCM once, eliminating the memory access operations required to obtain the metadata. Based on the obtained index of the TCM entry, the TCM entry recording the next data transfer unit node and its metadata is retrieved.

[0101] During the process of reading data from the NVM according to the data descriptor list, the data transfer unit read from the NVM and the corresponding metadata are written to the SRAM and the corresponding TCM.

[0102] Figure 8 A schematic diagram illustrating the processing of a write command according to yet another embodiment of this application is shown.

[0103] The control unit of the storage device includes a command processing unit (e.g., CPU), and a TCM, SRAM, and media interface controller coupled to the command processing unit. The TCM stores a list of data descriptors and metadata, while the SRAM stores data transfer units (user data). Optionally, DRAM, independent of the control unit, can replace SRAM as a user data cache. The storage device also includes an NVM chip coupled to the control unit.

[0104] In response to receiving a write command from the host, the command processing unit obtains the SGL from the write command, generates a list of data descriptors based on the SGL, and records it in one or more entries allocated from the TCM. Figure 8 In the figure (1), each allocated entry of the TCM records the data transfer unit node of the data descriptor list and the index pointing to the TCM entry that records the next data transfer unit node. For example, if a write command is to write 16KB of data, and each data transfer unit node describes a data transfer unit size of 4KB, then the data descriptor list corresponding to the write command includes 4 data transfer unit nodes, occupying 4 entries of the TCM. Optionally, metadata or partial metadata is also generated and recorded in the TCM entries.

[0105] Next, based on the data transfer unit node recorded in the TCM entry, the data to be written by the write command is moved from the host memory space to the SRAM entry corresponding to that TCM entry. Figure 8 (as indicated by reference numeral (2) in the figure). Optionally or further, in response to writing data to an SRAM entry, corresponding metadata is also generated, and the generated metadata is recorded in the corresponding TCM entry.

[0106] Subsequently, in response to the user data and its metadata corresponding to the data transmission unit being stored in SRAM and TCM respectively, the command processing unit instructs the media interface controller to write the user data and its metadata corresponding to the data transmission unit together into the NVM (Network Virtual Machine). Figure 8 (As indicated by reference numeral (3) in the figure). For example, the instruction provided by the command processing unit to the media interface controller includes an index of a TCM entry or an SRAM entry. The media interface controller uses this index to retrieve user data from both the SRAM and metadata from the TCM. Figure 8 In the figure, indicated by reference numerals (4) and (5). The media interface controller writes the acquired user data and metadata together into the NVM ( Figure 8 (Indicated by reference numeral (6) in the figure). Optionally, the media interface controller also obtains the index of the next TCM entry recorded in the same memory access to obtain metadata from the TCM entry, and obtains metadata from the next TCM entry and corresponding user data from SRAM according to the obtained index and writes it to the NVM, until all entries of the data transfer unit nodes of the record data descriptor list are obtained and the data writing to the NVM is completed.

[0107] In another example, in response to the user data and its metadata corresponding to the data transfer unit being stored in SRAM and TCM respectively, the command processing unit retrieves the metadata from the TCM entry based on the TCM entry index and sends the TCM entry index and metadata together to the media interface controller. The media interface controller accesses the SRAM based on the received TCM entry index to retrieve the corresponding data transfer unit (user data) from the SRAM and writes the metadata and corresponding user data together to the NVM. The command processing unit also retrieves the index of the next TCM entry from the TCM entries, retrieves the metadata from the next TCM entry based on the retrieved index, and sends the metadata and the next TCM entry index to the media interface controller, until all data transfer unit nodes in the record data descriptor list have been retrieved and the data writing to the NVM is completed.

[0108] Figure 9 A schematic diagram illustrating the processing of a read command according to yet another embodiment of this application is shown.

[0109] In response to receiving a read command from the host, the command processing unit obtains the SGL from the read command, generates a list of data descriptors based on the SGL, and records it in one or more entries allocated from the TCM. Figure 9 (As indicated by reference numeral (1) in the figure). For example, if a read command reads 16KB of data, and each data transfer unit node describes a data transfer unit size of 4KB, then the data descriptor list corresponding to the read command includes 4 data transfer unit nodes, occupying 4 entries in the TCM.

[0110] Next, the command processing unit traverses the data descriptor list. Based on the data transfer unit node recorded in the TCM entry, the command processing unit instructs the media interface controller to read the user data and optional metadata corresponding to the data transfer unit node from the NVM. For example, the command processing unit instructs the media interface controller to match the physical address corresponding to the logical address associated with the data transfer unit node with the TCM entry index or SRAM entry index. Figure 9 (as indicated by reference numeral (2) in the attached figure).

[0111] The media interface controller reads data from the NVM. Figure 9 In the figure, indicated by reference numeral (3), the media interface controller moves the user data read from the NVM to the SRAM entry indicated by the received TCM entry index or SRAM entry index. Figure 9 In the figure, indicated by reference numeral (4), and optionally, the corresponding metadata read from the NVM is moved to the TCM entry indicated by the index. Figure 9 (Indicated by reference numeral (5) in the figure). Optionally, the media interface controller also obtains the index of the next TCM entry recorded in the TCM entry based on the index, and obtains the physical address corresponding to the logical address of the data transmission unit node recorded in the next TCM entry based on the obtained index, and accesses the NVM until all entries of the data transmission unit nodes in the record data descriptor list have been obtained and the data reading from the NVM has been completed.

[0112] In response to the entry where user data is moved to SRAM from the corresponding data transfer unit node, the command processing unit also moves the user data to host memory based on the data descriptor recorded in that data transfer unit node. Figure 9 (Indicated by reference numeral (6) in the attached figure). Optionally, the command processing unit also moves metadata to host memory based on the data descriptor recorded by the data transfer unit node. Figure 9 (In the figure, indicated by reference numeral (7)).

[0113] In another example, in response to recording the generated list of data descriptors in one or more entries of the TCM, the command processing unit also traverses the list of data transmission unit nodes by accessing the TCM, obtains the physical address corresponding to the logical address associated with the data transmission unit node from the read TCM entries, and provides the physical address and the TCM entry index (also as the SRAM entry index) to the media interface controller. The command processing unit also obtains the index of the next TCM entry from the read TCM entries, and based on the obtained index, obtains the physical address corresponding to the logical address associated with the data transmission unit node from the next TCM entry, and sends the physical address and the next TCM entry index to the media interface controller, until all entries of the data transmission unit nodes recording the data descriptor list have been obtained and data reading from the NVM is completed.

[0114] Figure 10 This diagram illustrates yet another type of I / O command used for storage devices.

[0115] Figure 10 In the diagram, right-angled rectangles represent data packets containing I / O commands sent from the host to the storage device, while rounded rectangles represent data packets containing I / O commands sent from the storage device to the host. When the host sends data packets to the device, packets closer to the right (i.e., closer to the device) are sent earlier, and packets closer to the left (i.e., closer to the host) are sent later. The opposite is true when the device sends data packets to the host.

[0116] Write command 1010 is an I / O command sent by the host to the storage device. A write command consists of multiple data packets. The host first sends a data packet representing the command type to the storage device. In response to recognizing the write command type, the storage device internally allocates a buffer for the data to be written by the write command and sends a response data packet to the host, indicating the amount and size of the data that can be received. In response, the host sends a data packet carrying the data to be written to the storage device. These two stages—the storage device sending a response data packet to the host, and the host sending a data packet carrying the data to be written to the storage device—can be repeated once or multiple times until all the data to be written by the write command has been transmitted to the storage device. Optionally, the storage device may also send a data packet (not shown) indicating the processing result of the write command to the host.

[0117] Read command 1020 is an I / O command sent by the host to the storage device. A read command consists of multiple data packets. The host first sends a data packet representing the command type to the storage device. In response to recognizing the read command type, the storage device internally prepares the data to be read for processing the read command and sends one or more data packets carrying the data to be read to the host. Optionally, the storage device also sends a data packet (not shown) representing the processing result of the read command to the host.

[0118] exist Figure 10 In the illustrated I / O command example, the read / write command indicates a logical address to the storage device. This logical address represents the storage space provided by the storage device to the host. Furthermore, the read / write command does not reveal the host's memory address or data cache to the storage device. Therefore, in response to write command 1010, the storage device receives the data to be written from the host, but is unaware of the data's storage address on the host. Similarly, in response to read command 1020, the storage device provides read data to the host without needing to know where the host stores this read data. Thus, Figure 10 The demonstrated I / O commands do not need to carry an SGL to describe the storage location of the data associated with the I / O command on the host. Instead, the logical address of the storage device to be accessed and the length of the data to be accessed are indicated in the I / O command (e.g., in a data packet representing the command type). The storage device allocates an appropriate cache for the I / O command to hold the data to be accessed. However, the allocated cache may still be non-contiguous. According to embodiments of this application, a list of data descriptors is used to describe the cache allocated to the I / O command.

[0119] Figure 11 A schematic diagram illustrating a list of data descriptors according to another embodiment of this application is shown.

[0120] Compared to Figure 6 The illustrated embodiments are based on Figure 11 In this embodiment, SGL is not required to describe the relationship between the logical address accessed by the IO command and the host memory address.

[0121] See Figure 11 The data descriptor list 1180 includes multiple data transfer unit nodes (1130, 1135, 1140, 1145, and 1150). Each data transfer unit node in the data descriptor list 1180 explicitly or implicitly indicates the corresponding logical address to be accessed by the IO command. For example, the logical address is recorded in the data transfer unit node, or the sequence number of the data transfer unit node in the data descriptor list 1180 implies the logical address.

[0122] Each data transfer unit node includes only one data descriptor (1132, 1135, 1142, 1147, and 1152). Each data descriptor indicates a data transfer unit (1111, 1112, 1114, 1116, or 1118) of a specified size in SRAM. Figure 11 In this example, each data descriptor indicates a specified size of 4KB. Thus, the data transfer unit node associates a logical address range with the data transfer unit.

[0123] Optionally, the data transmission unit node implies a logical address, while the data descriptor implies (e.g., by the sequence number of its data transmission unit node in the data descriptor list 1180) the data transmission unit. Thus, the data descriptor only needs to record the address or index indicating the next data transmission unit node, without recording other information, thereby reducing the storage space occupied by the data descriptor itself. Understandably, there is a one-to-one correspondence between the data transmission unit node and the data descriptor, so the information recorded by the data descriptor can be recorded in the data transmission unit node, eliminating the need for a separate data descriptor.

[0124] Each data transfer unit node also includes metadata corresponding to the data transfer unit (1120, 1122, 1124, and 1126). Thus, the corresponding metadata can be obtained while accessing the data transfer unit node, and the SRAM only stores the data transfer units (1111, 1112, 1114, 1116, and 1118) that carry user data and no longer stores metadata.

[0125] Optionally or further, a list of data descriptors 1180 is stored in the TCM (Tight-Coupled Memory) 1170 of the control unit of the storage device. The TCM 1170 is directly coupled to the processor of the control unit via a dedicated bus, while the SRAM is coupled to the processor of the control unit via a bus shared with other components. Therefore, the processor accesses the TCM 1170 faster than accessing the SRAM, further accelerating the processing of I / O commands.

[0126] Data descriptor list 1180 corresponds to one of the I / O commands. In response to receiving an I / O command, data descriptor list 1180 is generated based on the logical address range accessed by the I / O command and (optionally) the length of the data to be accessed.

[0127] See Figure 11 For example, an I / O command accesses a logical address space ranging from logical address LBAX to logical address LBAX+5, representing a 20KB range, where X is a natural number. Each 4KB logical address space starting from logical address LBAX corresponds to one of the data transfer unit nodes in data descriptor list 1180.

[0128] according to Figure 11In one embodiment, to process a write command, a data descriptor list 1180 (including 5 data transfer unit nodes) is generated in the TCM1170 according to the logical address range accessed by the write command (its length is, for example, 20KB), and a data transfer unit is allocated in SRAM for each data transfer unit node in the data descriptor list 1180. Optionally, in generating each data transfer unit node in the data descriptor list 1180, corresponding metadata is also generated and recorded in the data transfer unit node. As an example, the metadata 1120 records the logical address corresponding to the data transfer unit node 1130. Optionally, the control unit may also generate the metadata of each data transfer unit node in other ways.

[0129] Optionally, based on the logical address range accessed by the write command, the generated data descriptor list 1180 requires 5 data transfer unit nodes. Then, 5 data transfer units are allocated from SRAM. For each allocated data transfer unit, a corresponding data transfer unit node is generated. Alternatively, the TCM1170 includes multiple data transfer unit nodes, and 5 unused data transfer unit nodes are selected to construct the data descriptor list 1180.

[0130] Next, the control unit requests the host to provide the data to be written using a write command. In response to receiving the data to be written, the data to be written received from the host is stored in the data transfer units (1111, 1112, 1114, 1116, and 1118) in SRAM according to the data transfer unit nodes (1130, 1135, 1140, 1145, and 1150) of the data descriptor list 1180. Optionally, metadata is also generated based on the data to be written received from the host and written to the data transfer unit nodes.

[0131] The control unit also traverses the data descriptor list 1180, accessing each data transmission unit node (1130, 1135, 1140, 1145, and 1150), obtaining the index and metadata (1120, 1122, 1124, 1126, and 1128) of the associated data transmission units (1111, 1112, 1114, 1116, and 1118), and writes the user data of the data transmission unit along with the corresponding metadata to the NVM. The data transmission unit node is obtained in a single TCM access, along with the corresponding index and metadata.

[0132] according to Figure 11In one embodiment, as an example, to process a read command, a data descriptor list 1180 is generated based on the logical address range accessed by the read command. Each data transmission unit node in the data descriptor list 1180 indicates a data transmission unit. Storage space for storing metadata is also reserved in each data transmission unit node in the data descriptor list 1180.

[0133] Next, the control unit reads data from the NVM chip according to the logical addresses corresponding to each data transmission unit node in the data descriptor list. The data read from the NVM chip includes user data and metadata. The read user data is stored in the data transmission unit corresponding to the data transmission unit node in the same data descriptor list, and the read metadata is stored in the storage space reserved for metadata within the data transmission unit node.

[0134] The control unit also traverses the list of data descriptors, accesses each data transmission unit node, obtains the index and optional metadata of the associated data transmission unit, and provides the user data and optional corresponding metadata of the data transmission unit to the host.

[0135] Return to view Figure 8 For example, the control unit receives according to Figure 10 IO commands.

[0136] In one example, in response to receiving a write command from the host, the command processing unit obtains the logical address range to be accessed from the write command and allocates one or more entries from the TCM. Figure 8 In the TCM, each data transfer unit node (as indicated by reference numeral (1)) is recorded in one of the TCM entries, and the index of the TCM entry storing the next data transfer unit node is also recorded. Optionally, metadata or partial metadata is also generated and recorded in the TCM entries.

[0137] For example, if a write command needs to write 20KB of data, and each data transfer unit node describes a data transfer unit size of 4KB, then the data descriptor list corresponding to this write command includes 5 data transfer unit nodes, occupying 5 entries in the TCM.

[0138] The allocated TCM entries correspond to available data transfer units in SRAM. The control unit sends a data packet representing a response to the host, indicating to the host the amount of data that can be received and its size. In response, the host sends a data packet carrying the data to be written to the storage device. The control unit retrieves the data from the received data packet carrying the data to be written and records it in the data transfer unit (TMU) in SRAM. Figure 8(As indicated by reference numeral (2) in the figure). For one or more data packets carrying data to be written, the data carried is sequentially recorded in the SRAM entries corresponding to the data transfer unit nodes in the data descriptor list. Optionally or further, in response to writing data to the SRAM entries, corresponding metadata is also generated, and the generated metadata is recorded in the corresponding TCM entries.

[0139] Subsequently, in response to the user data and its metadata corresponding to the data transmission unit being stored in SRAM and TCM respectively, the command processing unit instructs the media interface controller to write the user data and its metadata corresponding to the data transmission unit together into the NVM (Network Virtual Machine). Figure 8 (As indicated by reference numeral (3) in the figure). For example, the instruction provided by the command processing unit to the media interface controller includes an index of a TCM entry or an SRAM entry. The media interface controller uses this index to retrieve user data from both the SRAM and metadata from the TCM. Figure 8 In the figure, indicated by reference numerals (4) and (5). The media interface controller writes the acquired user data and metadata together into the NVM ( Figure 8 (as indicated by reference numeral (6) in the attached figure).

[0140] Go back and see Figure 9 In response to receiving data from the host according to Figure 10 The command processing unit obtains the logical address range to be accessed from the read command and allocates one or more entries from the TCM. Figure 9 In the TCM, each data transfer unit node (as indicated by reference numeral (1)) is recorded in one of the TCM entries, and the index of the TCM entry storing the next data transfer unit node is also recorded. Optionally, metadata or partial metadata is also generated and recorded in the TCM entries.

[0141] Next, the command processing unit traverses the data descriptor list and, based on the data transmission unit node recorded in the TCM entry, instructs the media interface controller to read the user data corresponding to the data transmission unit node and optional metadata from the NVM. Figure 9 (as indicated by reference numeral (2) in the attached figure).

[0142] The media interface controller reads data from the NVM. Figure 9 In the figure, indicated by reference numeral (3), the media interface controller moves the user data read from the NVM to the SRAM entry indicated by the received TCM entry index or SRAM entry index. Figure 9In the figure, indicated by reference numeral (4), and optionally, the corresponding metadata read from the NVM is moved to the TCM entry indicated by the index. Figure 9 (Indicated by reference numeral (5) in the figure). Optionally, the media interface controller also obtains the index of the next TCM entry recorded in the TCM entry based on the index, and obtains the physical address corresponding to the logical address of the data transmission unit node recorded in the next TCM entry based on the obtained index, and accesses the NVM until all entries of the data transmission unit nodes in the record data descriptor list have been obtained and the data reading from the NVM has been completed.

[0143] In response to the user data being moved to the entry in SRAM from the corresponding data transmission unit node, the control unit also provides the data in the SRAM entry to the host via a data packet carrying the data to be read. Figure 9 In the figure, indicated by reference numeral (6). Optionally, the logical address range corresponding to the data carried is also indicated in the data packet. And optionally, the control unit also provides metadata from the corresponding entry in the TCM to the host through the data packet carrying the data to be read, based on the entry recording the SRAM. Figure 9 (In the figure, indicated by reference numeral (7)).

[0144] According to an embodiment of this application, a storage device is also provided, including a controller and a non-volatile memory chip, wherein the controller executes any of the processing methods provided in the embodiments of this application.

[0145] According to embodiments of this application, a program stored on a readable medium is also provided, which, when the controller of the storage device is run, causes the storage device to execute any of the processing methods provided according to embodiments of this application.

[0146] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for using caching, comprising: Obtain IO commands; The SGL descriptor list is obtained according to the IO command, and a data descriptor list is generated according to the SGL descriptor list; wherein, the data descriptor list includes one or more data descriptors; One or more entries are allocated from the first memory according to the data descriptor list, each of the one or more entries in the first memory corresponding to an entry in the second memory; Obtain the data to be accessed by the IO command, initiate a DMA transfer based on the data descriptor, and cache the data to be accessed by the IO command into one or more entries in the second memory corresponding to the one or more entries in the first memory.

2. The method according to claim 1, wherein The first memory is TCM, and the second memory is SRAM; The first memory is directly coupled to the processor; The second memory is coupled to the processor via a bus; and The processor executes the method.

3. The method according to any one of claims 1-2, further comprising: Record the data to be accessed by the I / O command in one or more entries in the second memory; Metadata corresponding to data in the corresponding entries of the second memory is recorded in one or more entries of the first memory.

4. The method according to claim 3, further comprising: Metadata is retrieved from the first entry in the first memory, and data is retrieved from the second entry in the second memory corresponding to the first entry; Combine the metadata obtained from the first entry with the data obtained from the second entry and write it to the NVM.

5. The method according to claim 4, further comprising: In the process of obtaining metadata from the first entry in the first memory, an index indicating a third entry in the first memory is also obtained from the first entry; as well as Metadata is retrieved from the third entry in the first memory, and data is retrieved from the fourth entry in the second memory corresponding to the third entry; Combine the metadata obtained from the third entry with the data obtained from the fourth entry and write it to the NVM; And repeat the above process until all the data accessed by the IO command is written to the NVM.

6. The method according to any one of claims 1-5, further comprising: In response to allocating one or more entries from a first memory according to an IO command, if the IO command is a write command, the provider of the IO command is indicated to receive the data to be written by the write command.

7. The method of claim 6, wherein In response to allocating one or more entries from the first memory according to an IO command, if the IO command is a write command, the data to be written by the write command of a specified length is obtained from the cache address of the provider of the IO command according to the descriptor recorded in the entry of the first memory, and stored in the entry of the second memory corresponding to the entry of the first memory.

8. The method according to any one of claims 1-7, further comprising: If the I / O command is a read command, in response to one or more entries in the second memory caching the data to be accessed by the I / O command, the data to be read by the read command is sent to the provider of the I / O command.

9. The method according to claim 8, wherein: If the IO command is a read command, in response to one or more entries in the second memory caching the data to be accessed by the IO command, one or more entries in the first memory corresponding to the one or more entries in the second memory are determined, and the data to be read by the read command is sent to the cache of the provider of the IO command according to the cache address and length of the data to be accessed by the IO command recorded in the data descriptor of one or more entries in the first memory.

10. A storage device, comprising a control unit and a non-volatile memory chip, The control unit includes a processor that performs the method according to any one of claims 1-9.

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