Display device and driving method thereof

Abstract

The present application relates to a display device and a driving method thereof, the display device including: an LDO regulator providing a second power voltage to a first power line during a first period of a frame; a step-down converter providing a first power voltage to the first power line during a third period of the frame; and a pixel commonly connected to the LDO regulator and the step-down converter through the first power line, a voltage level of the second power voltage being the same as a voltage level of the first power voltage.

Description

Technical Field

[0001] This invention relates to a display device and its driving method. Background Technology

[0002] With the development of information technology, the importance of display devices as the connection medium between users and information has become prominent. Correspondingly, the use of display devices such as liquid crystal display devices (LCDs) and organic light-emitting display devices (OLEDs) is increasing.

[0003] Organic light-emitting display devices utilize self-emissive organic light-emitting diodes (OLEDs), thus possessing advantages such as fast response speed, high luminous efficiency, and high brightness. However, as the driving time increases, degradation may occur in the circuit components such as OLEDs and transistors contained in each pixel. Furthermore, with degradation, the inherent characteristic values ​​of the circuit components such as OLEDs and transistors may change.

[0004] Therefore, organic light-emitting display devices may also include circuitry for sensing and compensating for the characteristic values ​​or changes in characteristics of each pixel. However, noise is generated during the sensing of pixel characteristic values, which may reduce the accuracy of the characteristic value sensing. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a display device and its driving method that simultaneously connects the ELVDD power supply of the pixel sensing circuit used for external compensation to a buck converter and an LDO (low drop-out) regulator.

[0006] In addition, the technical problem to be solved by the present invention is to provide a display device and its driving method in which the output of the buck converter supplies the ELVDD power supply when the display screen is driven, and the output of the LDO regulator supplies the ELVDD power supply when the display is turned on / off.

[0007] Furthermore, the technical issues to be addressed in the embodiments are not limited to those mentioned above. Those skilled in the art can clearly understand other unmentioned technical issues from the description of the embodiments.

[0008] According to an embodiment of the present invention, a display device includes: an LDO regulator that provides a second power supply voltage to a first power line during a first time period of a frame; a buck converter that provides a first power supply voltage to the first power line during a third time period of the frame; and a pixel that is connected to the LDO regulator and the buck converter via the first power line, wherein the voltage level of the second power supply voltage is the same as the voltage level of the first power supply voltage.

[0009] According to one embodiment of the present invention, the LDO regulator is connected to the first power line via a second switch, and the buck converter is connected to the first power line via a first switch.

[0010] According to an embodiment of the present invention, the display device further includes: a timing control unit, which supplies a second control signal to turn on the second switch during the first time period and supplies a first control signal to turn on the first switch during the third time period.

[0011] According to an embodiment of the present invention, during a second time period between the first time period and the third time period of the frame, the first switch and the second switch are turned off, and the timing control unit does not supply the first control signal and the second control signal during the second time period.

[0012] According to an embodiment of the present invention, the third time period corresponds to the display time period within the frame, and the first time period corresponds to the sensing time period within the frame excluding the display time period.

[0013] According to one embodiment of the present invention, the LDO regulator is connected to the timing control unit via a second line, and the buck converter is connected to the timing control unit via a first line.

[0014] According to an embodiment of the present invention, the timing control unit supplies a fourth control signal to the LDO regulator via the second line during the first time period, and supplies a third control signal to the buck converter via the first line during the third time period.

[0015] According to one embodiment of the present invention, when the LDO regulator receives the supply of the fourth control signal, it provides the second power supply voltage during the first time period, and when the buck converter receives the supply of the third control signal, it provides the first power supply voltage during the third time period.

[0016] According to an embodiment of the present invention, the timing control unit does not supply the third control signal and the fourth control signal during the second time period of the frame, wherein the second time period is the time period between the first time period and the third time period.

[0017] According to an embodiment of the present invention, the third time period corresponds to the display time period within the frame, and the first time period corresponds to the sensing time period within the frame excluding the display time period.

[0018] According to an embodiment of the present invention, a driving method for a display device including an LDO regulator, a buck converter, and pixels includes: the LDO regulator supplying a second power supply voltage to a first power line during a first time period of a frame; the buck converter supplying a first power supply voltage to the first power line during a third time period of the frame; and the pixel receiving the supply of the first power supply voltage or the second power supply voltage through the first power line, wherein the voltage level of the second power supply voltage is the same as the voltage level of the first power supply voltage.

[0019] According to one embodiment of the present invention, the LDO regulator is connected to the first power line via a second switch, and the buck converter is connected to the first power line via a first switch.

[0020] According to an embodiment of the present invention, the display device further includes a timing control unit, wherein the step of supplying a second power supply voltage to the first power line during the first time period includes the step of the timing control unit supplying a second control signal to turn on the second switch during the first time period.

[0021] According to an embodiment of the present invention, the step of supplying a first power supply voltage to the first power line during the third time period includes the step of the timing control unit supplying a first control signal to turn on the first switch during the third time period.

[0022] According to an embodiment of the present invention, during a second time period between the first time period and the third time period of the frame, the first switch and the second switch are turned off, and the driving method of the display device further includes the step of the timing control unit not supplying the first control signal and the second control signal during the second time period.

[0023] According to one embodiment of the present invention, the LDO regulator is connected to the timing control unit via a second line, and the buck converter is connected to the timing control unit via a first line.

[0024] According to an embodiment of the present invention, the step of supplying a second power supply voltage to a first power supply line during the first time period includes the step of the timing control unit supplying a fourth control signal to the LDO regulator during the first time period.

[0025] According to an embodiment of the present invention, the step of supplying a first power supply voltage to the first power supply line during the third time period includes the step of the timing control unit supplying a third control signal to the buck converter during the third time period.

[0026] According to an embodiment of the present invention, the step of supplying a second power supply voltage to a first power supply line during the first time period includes: supplying the second power supply voltage during the first time period when the LDO regulator receives the supply of the fourth control signal.

[0027] According to an embodiment of the present invention, the step of supplying a first power supply voltage to the first power line during the third time period includes: supplying the first power supply voltage during the third time period when the buck converter receives the supply of the third control signal.

[0028] (Invention Effects)

[0029] According to the display device and driving method of the present invention, the ELVDD power supply of the pixel sensing circuit used for external compensation can be simultaneously connected to both the buck converter and the LDO regulator.

[0030] Furthermore, according to the display device and driving method of the present invention, when the display screen is driven, the output of the buck converter supplies the ELVDD power supply, and when the display is turned on / off, the output of the LDO regulator supplies the ELVDD power supply, thereby minimizing the influence of noise and increasing the characteristic sensing accuracy of the pixels. Attached Figure Description

[0031] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0032] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention.

[0033] Figure 3 This is a diagram illustrating a pixel driving method according to an embodiment of the present invention.

[0034] Figure 4 This is a diagram illustrating a first power supply and a timing control unit according to an embodiment of the present invention.

[0035] Figure 5 This is a diagram illustrating the driving method of the buck converter and LDO regulator in the first to third time periods according to an embodiment of the present invention.

[0036] Figure 6This is a diagram illustrating a first power supply and a timing control unit according to another embodiment of the present invention.

[0037] Figure 7 This is a diagram illustrating the driving method of the buck converter and LDO regulator in the fourth to sixth time periods according to another embodiment of the present invention. Detailed Implementation

[0038] The preferred embodiments will now be described in detail with reference to the accompanying drawings. (Refer to the accompanying drawings...) Figure 1 The advantages and features of the embodiments, as well as the methods of implementing them, will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in various forms that differ from each other. These embodiments are provided merely to make the disclosure of the invention complete and to fully convey the scope of the invention to those skilled in the art to which these embodiments pertain. The embodiments are defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same constituent elements.

[0039] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be understood in the sense that are commonly understood by one of ordinary skill in the art to which these embodiments pertain. Furthermore, terms as defined in commonly used dictionaries are not to be idealized or over-interpreted unless explicitly defined. The terminology used in this specification is for illustrative purposes and is not intended to limit the scope of the embodiments. In this specification, singular forms include plural forms unless specifically stated in the context.

[0040] The following is for reference Figure 1 A display device according to an embodiment of the present invention is described.

[0041] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0042] Reference Figure 1 According to an embodiment of the present invention, the display device 10 may include a timing control unit 11, a data driving unit 12, a scanning driving unit 13, a pixel unit 14, a sensing unit 15, and a power supply unit 16.

[0043] The timing control unit 11 can receive grayscale values ​​and control signals for each image frame from an external processor. The timing control unit 11 can render grayscale values ​​to correspond to the specifications of the display device 10.

[0044] For example, an external processor can provide red, green, and blue grayscale values ​​for each unit dot. However, when the pixel unit 14 has a pentile structure, adjacent unit dots can share pixels, so pixels may not correspond one-to-one with individual grayscale values. In this case, grayscale rendering is required. When pixels correspond one-to-one with individual grayscale values, grayscale rendering may not be necessary.

[0045] The rendered or unrendered grayscale values ​​can be provided to the data driving unit 12. In addition, the timing control unit 11 can provide control signals suitable for their respective specifications to the data driving unit 12, the scan driving unit 13, the sensing unit 15, and the power supply unit 16 for displaying frames.

[0046] The data driving unit 12 can generate data voltages to be provided to the data lines D1, D2, D3, ... Dm using grayscale values ​​and control signals. For example, the data driving unit 12 can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines D1, D2, D3, ... Dm in pixel row units. m can be an integer greater than 0. A pixel row can refer to pixels connected to the same scan line.

[0047] The scan drive unit 13 can receive clock signals, scan start signals, etc. from the timing control unit 11, and generate first scan signals to be provided to the first scan lines S11, S12, ... S1n and second scan signals to be provided to the second scan lines S21, S22, ... S2n. n can be an integer greater than 0.

[0048] The scan drive unit 13 can sequentially supply a first scan signal with a pulse having a conduction level to the first scan lines S11, S12, ... S1n. Additionally, the scan drive unit 13 can sequentially supply a second scan signal with a pulse having a conduction level to the second scan lines S21, S22, ... S2n.

[0049] For example, the scan driver unit 13 may also include a first scan driver unit connected to the first scan lines S11, S12, ... S1n and a second scan driver unit connected to the second scan lines S21, S22, ... S2n. Each of the first and second scan driver units may include a scan stage configured as a shift register. Each of the first and second scan driver units can generate a scan signal by sequentially transmitting a scan start signal in the form of a pulse with a conduction level to the next scan stage under the control of a clock signal.

[0050] According to the embodiment, the first scan signal and the second scan signal can be the same. In this case, the first scan lines S11, S12, ... S1n and the second scan lines S21, S22, ... S2n connected to each pixel PXij can be connected to the same node. In this case, the scan driving unit 13 can be configured as a single scan driving unit instead of being divided into a first scan driving unit and a second scan driving unit.

[0051] The sensing unit 15 may include sensing channels connected to the sensing lines I1, I2, I3, ... Ip. For example, the sensing lines I1, I2, I3, ... Ip and the sensing channels may correspond one-to-one.

[0052] The power supply unit 16 may include a first power supply 16a and a second power supply 16b. The first power supply 16a and the second power supply 16b may be composed of different integrated circuits (ICs) or integrated into a single IC. The first power supply 16a is connected to the pixel PXij via a first power line ELVDD. The second power supply 16b is connected to the pixel PXij via a second power line ELVSS. The first power supply 16a is supplied with power voltage via the first power line ELVDD. The second power supply 16b is supplied with power voltage via the second power line ELVSS. During the display period of the pixel unit 14, the power voltage supplied via the first power line ELVDD may be greater than the power voltage supplied via the second power line ELVSS. During the display period of the pixel unit 14, a current path can be formed via the first power supply 16a, the first power line ELVDD, the pixel unit 14, the second power line ELVSS, and the second power supply 16b.

[0053] The following is for reference Figure 2 The pixels are described according to an embodiment of the present invention.

[0054] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention.

[0055] Reference Figure 2 Pixel PXij may include transistors T1, T2, T3, storage capacitor Cst, and light-emitting diode LD.

[0056] Transistors T1, T2, and T3 can be constructed from N-type transistors. In another embodiment, transistors T1, T2, and T3 can be constructed from P-type transistors. In yet another embodiment, transistors T1, T2, and T3 can be constructed from a combination of N-type and P-type transistors. P-type transistors are generally referred to as transistors whose current increases when the voltage difference between the gate and source electrodes increases in the negative direction. N-type transistors are generally referred to as transistors whose current increases when the voltage difference between the gate and source electrodes increases in the positive direction. Transistors can be constructed in various forms, such as TFT (thin film transistor), FET (field effect transistor), BJT (bipolar junction transistor), and MOS (metal oxide semiconductor transistor).

[0057] Alternatively, the gate electrode of the first transistor T1 can be connected to the first node N1, the first electrode can be connected to the first power line ELVDD, and the second electrode can be connected to the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0058] Alternatively, the gate electrode of the second transistor T2 can be connected to the first scan line S1i, the first electrode to the data line Dj, and the second electrode to the first node N1. The second transistor T2 can be called a scan transistor.

[0059] Alternatively, the gate electrode of the third transistor T3 can be connected to the second scan line S2i, the first electrode to the second node N2, and the second electrode to the sensing line Ik. The third transistor T3 can be called a sensing transistor.

[0060] It is possible that the first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode is connected to the second node N2.

[0061] Alternatively, the anode of the light-emitting diode (LD) can be connected to the second node N2, and the cathode can be connected to the second power line ELVSS. The LD can be composed of organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (OLEDs), quantum dot / well light-emitting diodes (QD / QWLEDs), etc. Furthermore, the LD can be composed of multiple OLEDs connected in series, parallel, or series-parallel connections.

[0062] During the display period, the voltage level of the power supply supplied through the first power line ELVDD can be greater than the voltage level of the power supply supplied through the second power line ELVSS. However, in special cases such as preventing the light-emitting diode (LD) from emitting light, the voltage level of the power supply supplied through the second power line ELVSS can also be set to be greater than the voltage level of the power supply supplied through the first power line ELVDD.

[0063] The following is for reference Figure 3 A pixel driving method according to an embodiment of the present invention is described.

[0064] Figure 3 This is a diagram illustrating a pixel driving method according to an embodiment of the present invention.

[0065] Reference Figure 3 This diagram illustrates exemplary waveforms of signals applied to scan lines S1i and S2i, data line Dj, and sensing line Ik connected to pixel PXij during a horizontal period corresponding to scan lines S1i and S2i. K can be an integer greater than 0. A frame period may include multiple horizontal periods corresponding to pixel rows.

[0066] An initialization voltage VINT can be applied to the sensing line Ik.

[0067] Data voltages DS(i-1)j, DSij, and DS(i+1)j can be sequentially applied to data line Dj in horizontal time intervals. During the corresponding horizontal time interval, a first scan signal with a conduction level (logic high level) can be applied to the first scan line S1i. Additionally, a second scan signal with a conduction level can be applied to the second scan line S2i synchronously with the first scan line S1i.

[0068] For example, if a scan signal with a conduction level is applied to the first scan line S1i and the second scan line S2i, the second transistor T2 and the third transistor T3 can be in the conducting state. Therefore, a voltage equivalent to the difference between the data voltage DSij and the initialization voltage VINT is input to the storage capacitor Cst of pixel PXij.

[0069] In pixel PXij, the amount of drive current flowing through the drive path connecting the first power line ELVDD, the first transistor T1, the light-emitting diode LD, and the second power line ELVSS is determined based on the voltage difference between the gate electrode and the source electrode of the first transistor T1. The luminous intensity of the light-emitting diode LD can be determined based on the amount of drive current.

[0070] Subsequently, if a cutoff level (logic low level) scan signal is applied to the first scan line S1i and the second scan line S2i, the second transistor T2 and the third transistor T3 can be in the cutoff state. Therefore, regardless of the voltage change of the data line Dj, the voltage difference between the gate electrode and the source electrode of the first transistor T1 can be maintained by the storage capacitor Cst, thus maintaining the brightness of the light-emitting diode LD.

[0071] The following is for reference Figure 4 The first power supply and timing control unit according to an embodiment of the present invention will be described.

[0072] Figure 4 This is a diagram illustrating a first power supply and a timing control unit according to an embodiment of the present invention.

[0073] Reference Figure 4 According to an embodiment of the present invention, the first power supply 16a may include a buck converter 160, an LDO (low drop-out) regulator 161, a first switch SW1, and a second switch SW2.

[0074] The step-down converter 160 can be connected to the first power line ELVDD via the first switch SW1.

[0075] Specifically, when the first switch SW1 is turned on by the first control signal from the timing control unit 11, the buck converter 160 can apply a first-level voltage to the first power supply line ELVDD. The first-level voltage can be the first power supply voltage required by the pixel PXij during the display period.

[0076] The LDO regulator 161 can be connected to the first power line ELVDD via the second switch SW2.

[0077] Specifically, when the second switch SW2 is turned on by the second control signal from the timing control unit 11, the LDO regulator 161 can apply a second-level voltage to the first power supply line ELVDD. The second-level voltage can be the second power supply voltage required by the pixel PXij during the sensing period other than the display period.

[0078] At this time, the sensing period other than the display period refers to the period during which the inherent characteristic values ​​of the circuit elements included in the pixel PXij are sensed by external compensation at the instant when the display device 10 is turned on or off.

[0079] Specifically, at the instant the display device 10 is turned on or off, the second power supply voltage output by the LDO regulator 161 is supplied to the pixel PXij through the first power supply line ELVDD, and the sensing unit 15 uses it to sense the inherent characteristic values ​​of the circuit elements included in the pixel PXij.

[0080] The voltage level required by pixel PXij during the display period is the same as the voltage level required by pixel PXij during the sensing period other than the display period. Therefore, the voltage level of the first power supply voltage is the same as the voltage level of the second power supply voltage.

[0081] In one embodiment of the present invention, the first switch SW1 and the second switch SW2 cannot be in the on state at the same time. Either the first switch SW1 or the second switch SW2 can be converted into the on state by the control signal (first control signal or second control signal) of the timing control unit 11.

[0082] Specifically, in order to supply the first power supply voltage required by pixel PXij to pixel PXij via the first power line ELVDD during the display period, the timing control unit 11 can supply a first control signal to the first switch SW1 to switch on. Furthermore, in order to supply the second power supply voltage required by pixel PXij to pixel PXij via the first power line ELVDD during the sensing period other than the display period, the timing control unit 11 can supply a second control signal to the second switch SW2 to switch on.

[0083] The following is for reference Figure 5 This invention describes a method for driving a buck converter and an LDO regulator during the first to third time periods according to an embodiment of the present invention.

[0084] Figure 5 This is a diagram illustrating the driving method of the buck converter and LDO regulator in the first to third time periods according to an embodiment of the present invention.

[0085] The first time period is from time t1a to time t2a, referring to the sensing period excluding the display period. The third time period is from time t3a onwards, referring to the display period. The second time period is from time t2a to time t3a, referring to the period between the sensing period and the display period excluding the display period.

[0086] During the first time period, the timing control unit 11 applies a second control signal to the second switch SW2 to switch SW2 to switch it to the on state. At this time, from time t1a to time t2a, the second switch SW2 remains in the on state. Meanwhile, no control signal for switching the first switch SW1 to the on state is applied from the timing control unit 11, so from time t1a to time t2a, the first switch SW1 remains in the off state.

[0087] During the first time period, the LDO regulator 161 can be connected to the first power supply line ELVDD via the second switch SW2. At this time, the LDO regulator 161 can apply a second-level voltage to the first power supply line ELVDD. This second-level voltage can be the second power supply voltage.

[0088] The time period from time t2a to time t3a, also known as the second time period, is equivalent to the dead time, which is the time between the sensing period (excluding the display period) and the start of the display period. During the dead time, it refers to the state where the display device 10 is turned off.

[0089] At this time, since the timing control unit 11 does not apply a control signal (first control signal or second control signal) to the first switch SW1 and the second switch SW2 for switching to the conduction state, the first switch SW1 and the second switch SW2 remain in the off state from time t2a to time t3a.

[0090] During the third time period, the timing control unit 11 applies a first control signal to the first switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW1 to switch SW2 ....

[0091] During the third time period, the buck converter 160 can be connected to the first power supply line ELVDD via the first switch SW1. At this time, the buck converter 160 can apply a first-level voltage to the first power supply line ELVDD. This first-level voltage can be the first power supply voltage.

[0092] Equivalent to Figure 5The third period of the display phase can be longer than the first period corresponding to the sensing phase. Furthermore, during the third period corresponding to the display phase, the first switch SW1 is in the on state, allowing a first power supply voltage with the same voltage level as the second power supply voltage to be output from the buck converter 160 to the first power line ELVDD and applied to the pixel PXij. During the first period corresponding to the sensing phase other than the display phase, the second switch SW2 is in the on state, allowing the LDO regulator 161 to output a second power supply voltage with the same voltage level as the first power supply voltage to the first power line ELVDD and apply it to the pixel PXij.

[0093] According to one embodiment of the present invention, during sensing periods that are not display periods, an LDO regulator 161 can be used to provide a second power supply voltage to the first power line ELVDD and use it to drive the pixel PXij. At this time, the second power supply voltage output by the LDO regulator 161 has less noise compared to the first power supply voltage applied to the first power line ELVDD by the buck converter 160. Therefore, during sensing periods that are not display periods, the pixel PXij can be stably driven by the first power line ELVDD.

[0094] More specifically, the buck converter 160 generates power using a switching action, thereby producing ripple in the power supply. That is, noise may be generated in the power supply voltage output by the buck converter 160. Therefore, the voltage applied to the first power line ELVDD of the pixel PXij can be set differently depending on the moment when the voltage (or current) is sensed during the sensing period, thereby reducing the accuracy of the sensing.

[0095] Conversely, the LDO regulator 161 has higher power loss and lower power generation efficiency compared to the buck converter 160, but it generates power without the need for switching operations. Therefore, power ripple can be minimized, and the voltage applied to the first power line ELVDD of pixel PXij is set to a constant according to the moment when voltage (or current) is sensed during the sensing period, thereby increasing the accuracy of sensing.

[0096] The following is for reference Figure 6 The first power supply and timing control unit according to another embodiment of the present invention will be described.

[0097] Figure 6 This is a diagram illustrating a first power supply and a timing control unit according to another embodiment of the present invention.

[0098] The step-down converter 160' may have one end connected to the timing control unit 11 via the first line ELVDD_EN1, and the other end connected to the first power line ELVDD.

[0099] Specifically, when the timing control unit 11 applies the third control signal to the buck converter 160' via the first line ELVDD_EN1, the buck converter 160' can apply a first-level voltage to the first power supply line ELVDD. At this time, with... Figure 4 Similarly, the voltage of the first level can be the first power supply voltage required by pixel PXij during the display period.

[0100] The LDO regulator 161' may have one end connected to the timing control unit 11 via the second line ELVDD_EN2, and the other end connected to the first power line ELVDD.

[0101] Specifically, when the timing control unit 11 applies the fourth control signal to the LDO regulator 161' via the second line ELVDD_EN2, the LDO regulator 161' can apply a second-level voltage to the first power supply line ELVDD. At this time, with... Figure 4 Similarly, the voltage at the second level can be the second power supply voltage required by pixel PXij during the sensing period other than the display period.

[0102] At this time, the voltage level required by pixel PXij during the display period is the same as the voltage level required by pixel PXij during the sensing period other than the display period. Therefore, the voltage level of the first power supply voltage can be the same as the voltage level of the second power supply voltage.

[0103] In one embodiment of the present invention, the third control signal supplied to the buck converter 160' and the fourth control signal supplied to the LDO regulator 161' cannot be simultaneously output from the timing control unit 11.

[0104] Specifically, either a first power supply voltage or a second power supply voltage can be applied to the first power line ELVDD by the buck converter 160' or the LDO regulator 161' through the third or fourth control signal output from the timing control unit 11.

[0105] Specifically, in order to supply the first power supply voltage required by pixel PXij during the display period, timing control unit 11 can supply a third control signal to buck converter 160'. In addition, in order to supply the second power supply voltage required by pixel PXij during the sensing period other than the display period, timing control unit 11 can supply a fourth control signal to LDO regulator 161'.

[0106] The following is for reference Figure 7 This invention describes a method for driving a buck converter and an LDO regulator during the fourth to sixth time periods according to another embodiment of the present invention.

[0107] Figure 7This is a diagram illustrating the driving method of the buck converter and LDO regulator in the fourth to sixth time periods according to another embodiment of the present invention.

[0108] The fourth time period is from time t1a' to time t2a', referring to the sensing period excluding the display period. The sixth time period is from time t3a' onwards, referring to the display period. The fifth time period is from time t2a' to time t3a', referring to the period between the sensing period and the display period excluding the display period.

[0109] During the fourth time period, the timing control unit 11 applies the fourth control signal to the LDO regulator 161' via the second line ELVDD_EN2. At this time, from time t1a' to time t2a', the timing control unit 11 continuously supplies the fourth control signal via the second line ELVDD_EN2. Furthermore, the timing control unit 11 does not apply the third control signal to the buck converter 160' via the first line ELVDD_EN1.

[0110] During the fourth time period, the LDO regulator 161', to which the fourth control signal is applied, can apply a second-level voltage to the first power supply line ELVDD. At this time, the second-level voltage can be the second power supply voltage.

[0111] The period from time t2a' to time t3a', also known as the fifth period, is equivalent to the dead time, which is the time between the sensing period (excluding the display period) and the start of the display period. During the fifth period, the third control signal and the fourth control signal are not applied from the timing control unit 11 to the buck converter 160' and the LDO regulator 161', therefore the buck converter 160' and the LDO regulator 161' do not apply the first power supply voltage and the second power supply voltage to the first power line ELVDD.

[0112] During the sixth time period, the timing control unit 11 applies the third control signal to the buck converter 160' via the first line ELVDD_EN1. At this time, after time t3a', the timing control unit 11 continuously supplies the third control signal via the first line ELVDD_EN1. Furthermore, the timing control unit 11 does not apply the fourth control signal to the LDO regulator 161' via the second line ELVDD_EN2.

[0113] During the sixth time period, the buck converter 160', which is subject to the third control signal, can apply a first-level voltage to the first power supply line ELVDD. At this time, the first-level voltage can be the first power supply voltage.

[0114] Equivalent to Figure 7The sixth period of the display phase can be longer than the fourth period corresponding to the sensing phase. During the sixth period, which corresponds to the display phase, a third control signal can be supplied to the buck converter 160' via the first line ELVDD_EN1. The buck converter 160' outputs a first power supply voltage with the same voltage level as the second power supply voltage to the first power supply line ELVDD and applies it to the pixel PXij. Alternatively, during the fourth period, which corresponds to the sensing phase other than the display phase, a fourth control signal can be supplied to the LDO regulator 161' via the second line ELVDD_EN2. The LDO regulator 161' outputs a second power supply voltage with the same voltage level as the first power supply voltage to the first power supply line ELVDD and applies it to the pixel PXij.

[0115] According to an embodiment of the present invention Figure 6 as well as Figure 7 ,and Figure 4 as well as Figure 5 In comparison, since the first switch SW1 and the second switch SW2 are not included, power consumption can be reduced. Furthermore, during sensing periods that are not display periods, a second power supply voltage with lower noise than the first power supply voltage is applied to pixel PXij via the first power supply line ELVDD, enabling stable driving of pixel PXij.

[0116] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art to which the embodiments pertain should understand that they may be implemented in other specific ways without altering the technical concept or essential features of the embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not limiting.

Claims

1. A display device, wherein, The display device includes: The LDO regulator provides a second power supply voltage to the first power line during the first time period of a frame; A buck converter, during the third time period of the frame, provides a first power supply voltage to the first power line; and The pixels are connected to both the LDO regulator and the buck converter via the first power line. The voltage level of the second power supply voltage is the same as the voltage level of the first power supply voltage. The third time period is equivalent to the display time period within the frame. The first time period is equivalent to the sensing time period within the frame excluding the display time period.

2. The display device according to claim 1, wherein, The LDO regulator is connected to the first power line via a second switch. The step-down converter is connected to the first power line via a first switch.

3. The display device according to claim 2, wherein, The display device further includes: The timing control unit supplies a second control signal to turn on the second switch during the first time period and a first control signal to turn on the first switch during the third time period.

4. The display device according to claim 3, wherein, During the second time period between the first time period and the third time period of the frame, both the first switch and the second switch are turned off. The timing control unit does not supply the first control signal and the second control signal during the second time period.

5. The display device according to claim 1, wherein, The LDO regulator is connected to the timing control unit via a second line. The buck converter is connected to the timing control unit via a first line.

6. The display device according to claim 5, wherein, The timing control unit supplies a fourth control signal to the LDO regulator via the second line during the first time period, and supplies a third control signal to the buck converter via the first line during the third time period.

7. The display device according to claim 6, wherein, When the LDO regulator receives the fourth control signal, it provides the second power supply voltage during the first time period. When the buck converter receives the supply of the third control signal, it provides the first power supply voltage during the third time period.

8. The display device according to claim 7, wherein, The timing control unit does not supply the third control signal and the fourth control signal during the second time period of the frame. The second time period is the period between the first time period and the third time period.

9. The display device according to claim 8, wherein, The third time period is equivalent to the display time period within the frame. The first time period is equivalent to the sensing time period within the frame excluding the display time period.

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