Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures and methods of manufacturing the same are provided. A method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source / drain structure adjacent to the gate structure over the substrate and forming a contact over the source / drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices capable of performing increasingly complex and sophisticated functions is constantly growing. Consequently, there is a sustained trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). However, the fabrication and integration of multi-gate devices can be challenging. Summary of the Invention

[0004] Some embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a gate structure over a substrate; forming a mask layer covering the gate structure; forming a source / drain structure adjacent to the gate structure over the substrate; forming a contact over the source / drain structure; forming a dielectric layer over the contact and the mask layer; forming a first trench over the gate structure through the dielectric layer and the mask layer; forming a first conductive structure in the first trench; removing an upper portion of the first conductive structure; and forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

[0005] Other embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a nanostructure over a substrate; forming a gate structure surrounding the nanostructure; forming a source / drain structure attached to the nanostructure adjacent to the gate structure; forming contacts bonded to the source / drain structure; forming a dielectric layer over the contacts and the gate structure; forming a first conductive structure through the dielectric layer and covering the gate structure; etching an upper portion of the first conductive structure such that the top surface of the first conductive structure is lower than the top surface of the dielectric layer; and forming a second conductive structure through the dielectric layer to cover the contacts and the first conductive structure.

[0006] Further embodiments of this application provide a semiconductor structure including: a substrate; a gate structure formed over the substrate; a mask layer formed over the gate structure; a source / drain structure formed adjacent to the gate structure over the substrate; a contact formed over the source / drain structure; a first conductive structure formed through the mask layer and bonded to the gate structure; and a second conductive structure covering the first conductive structure and the contact, wherein the second conductive structure includes an extension sandwiched between an upper portion of the first conductive structure and an upper portion of the contact. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1E A perspective view showing an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0009] Figures 2A-1 to 2P-1 The manufacturing process according to some embodiments is shown along Figure 1E The line A-A' in the diagram shows cross-sectional views of various stages of the semiconductor structure.

[0010] Figures 2A-2 to 2P-2 The manufacturing process according to some embodiments is shown along Figure 1E The line B-B' in the diagram shows a cross-sectional view of the various stages of the semiconductor structure.

[0011] Figure 3 A cross-sectional view is shown, illustrating another intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0012] Figure 4 A cross-sectional view is shown, illustrating another intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0013] Figure 5 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0014] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 A cross-sectional view of a semiconductor structure fabricated according to some embodiments is shown.

[0015] Figure 7 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0016] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0017] Figure 9 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0018] Figure 10 A cross-sectional view of a semiconductor structure 100e according to some embodiments is shown.

[0019] Figure 11A and Figure 11B A cross-sectional view of a semiconductor structure fabricated according to some embodiments is shown.

[0020] Figure 12A and Figure 12B A cross-sectional view of a semiconductor structure fabricated according to some embodiments is shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Some variations of the embodiments are described. Similar reference numerals are used throughout the various views and illustrative embodiments to indicate similar elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be substituted or eliminated for other embodiments of the method.

[0023] The gate-all-around (GAA) transistor structure described below can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns, for example, with spacing smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0024] The fins described below can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins. Typically, dual-patterning or multi-patterning processes combine photolithography with a self-aligned process, thereby allowing the creation of patterns with, for example, spacing smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins.

[0025] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a gate structure formed above a substrate and a source / drain structure formed adjacent to the gate structure. Contacts may be formed above the source / drain structures, and conductive structures may be formed to connect the contacts to the gate structure. Since the contacts and gate structure may have different heights, forming the conductive structure may include first forming a first portion above the gate structure, and then forming a second portion above the first portion and the contacts. The height difference between the first portion of the conductive structure formed above the gate structure and the contacts may be relatively small, thereby preventing the gate structure and contacts from disconnecting due to a large height difference.

[0026] Figures 1A to 1E A perspective view is shown of an intermediate stage in the fabrication of a semiconductor structure 100 according to some embodiments. Figure 1A As shown, according to some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed above a substrate 102.

[0027] Substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0028] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked over a substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the material of the first semiconductor material layer 106 is SiGe, while the material of the second semiconductor material layer 108 is silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and second semiconductor material layers.

[0029] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, other suitable methods, or combinations thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0030] According to some embodiments, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor material stack above the substrate 102, the semiconductor material stack is patterned to form a fin structure 104, such as... Figure 1B As shown. In some embodiments, the fin structure 104 includes a base fin structure 104B and a semiconductor material stack of a first semiconductor material layer 106 and a second semiconductor material layer 108.

[0031] In some embodiments, the patterning process includes forming a mask structure 110 over a semiconductor material stack and etching through the mask structure 110 to the semiconductor material stack and the underlying substrate 102. In some embodiments, the mask structure 110 is a multilayer structure including a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 may be made of silicon oxide, which is formed by thermal oxidation or CVD, while the nitride layer 114 may be made of silicon nitride, which is formed by CVD such as LPCVD or plasma-enhanced CVD (PECVD).

[0032] According to some embodiments, after the fin structure 104 is formed, an isolation structure 116 is formed around the fin structure 104, and the mask structure 110 is removed, such as... Figure 1C As shown. According to some embodiments, the isolation structure 116 is configured as an active region (e.g., fin structure 104) of the electrically isolated semiconductor structure 100, and is also referred to as a shallow trench isolation (STI) component.

[0033] The isolation structure 116 can be formed by depositing an insulating layer over the substrate 102 and recessing the insulating layer so that the fin structure 104 protrudes from the isolation structure 116. In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric pad (not shown) is formed prior to the formation of the isolation structure 116, and the dielectric pad is made of silicon nitride, and the isolation structure formed over the dielectric pad is made of silicon oxide.

[0034] According to some embodiments, after the isolation structure 116 is formed, a dummy gate structure 118 and a transfin structure 104 are formed and extend over the isolation structure 116, such as Figure 1D As shown. The pseudo-gate structure 118 can be used to define the source / drain region and channel region of the resulting semiconductor structure 100.

[0035] In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0036] In some embodiments, the conductive material includes polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metals, or combinations thereof. In some embodiments, CVD, PVD, or combinations thereof are used to form the dummy gate electrode layer 122.

[0037] In some embodiments, a hard mask layer 124 is formed over the dummy gate structure 118. In some embodiments, the hard mask layer 124 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride.

[0038] Forming the dummy gate structure 118 may include conformally forming a dielectric material as a dummy gate dielectric layer 120. Then, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 122, and a hard mask layer 124 may be formed over the conductive material. Next, the dielectric and conductive materials may be patterned using the hard mask layer 124 to form the dummy gate structure 118.

[0039] According to some embodiments, after forming the dummy gate structure 118, a gate spacer 126 is formed along and covering the opposite sidewalls of the dummy gate structure 118, and a fin spacer 128 is formed along and covering the opposite sidewalls of the source / drain regions of the fin structure 104, such as... Figure 1E As shown.

[0040] The gate spacer 126 can be configured to separate the source / drain structure from the dummy gate structure 118 and support the dummy gate structure 118, while the fin spacer 128 can be configured to constrain the lateral growth of the subsequently formed source / drain structure and support the dummy fin structure 104.

[0041] In some embodiments, the gate spacer 126 and the fin spacer 128 are made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbonitride (SiOCN), and / or combinations thereof. Forming the gate spacer 126 and the fin spacer 128 may include conformally depositing a dielectric material covering the dummy gate structure 118, the fin structure 104, and the isolation structure 116 over a substrate 102, and performing an anisotropic etching process such as dry plasma etching to remove the dielectric layer covering the top surface of the dummy gate structure 118, the fin structure 104, and a portion of the isolation structure 116.

[0042] Figures 2A-1 to 2P-1 The manufacturing process according to some embodiments is shown along Figure 1E The cross-sectional view of each stage of the semiconductor structure 100 shown by line A-A' in the figure. Figures 2A-2 to 2P-2 The manufacturing process according to some embodiments is shown along Figure 1E The line B-B' in the diagram shows a cross-sectional view of various stages of the semiconductor structure 100. More specifically, according to some embodiments, Figure 2A-1 The cross-sectional view shown along line A-A' is given, while Figure 2A-2 Show along Figure 1E The cross-sectional view is shown by line B-B' in the diagram.

[0043] According to some embodiments, after forming the gate spacer 126 and the fin spacer 128, the source / drain regions of the fin structure 104 are recessed to form a source / drain groove 130, such as Figure 2B-1 and Figure 2B-2 As shown. More specifically, according to some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 not covered by the dummy gate structure 118 and the gate spacer 126 are removed. Furthermore, according to some embodiments, such as Figure 2B-1 As shown, some portions of the basal fin structure 104B are also recessed to form a curved top surface.

[0044] In some embodiments, the fin structure 104 is recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and a dummy gate structure 118 and gate spacer 126 are used as an etching mask during the etching process. In some embodiments, the fin spacer 128 is also recessed to form a lowered fin spacer 128'.

[0045] According to some embodiments, after the source / drain trench 130 is formed, the first semiconductor material layer 106 exposed by the source / drain trench 130 is laterally recessed to form a notch 132, such as Figure 2C-1 and Figure 2C-2 As shown.

[0046] In some embodiments, an etching process is performed on the semiconductor structure 100 to laterally recess the first semiconductor material layer 106 of the fin structure 104 from the source / drain groove 130. In some embodiments, during the etching process, the etching rate (or etching amount) of the first semiconductor material layer 106 is greater than that of the second semiconductor material layer 108, thereby forming a notch 132 between adjacent second semiconductor material layers 108. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0047] Next, according to some embodiments, such as Figure 2D-1 and Figure 2D-2 As shown, an inner spacer 134 is formed in a recess 132 between the second semiconductor material layers 108. According to some embodiments, the inner spacer 134 is configured to separate the source / drain structure from the gate structure formed in subsequent manufacturing processes. In some embodiments, the inner spacer 134 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbonitride (SiOCN), or combinations thereof.

[0048] According to some embodiments, after forming the inner spacer 134, a source / drain structure 136 is formed in the source / drain groove 130, such as... Figure 2E-1 and Figure 2E-2 As shown. In some embodiments, the source / drain structure 136 is formed using an epitaxial growth process such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structure 136 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof.

[0049] In some embodiments, the source / drain structure 136 is in-situ doped during the epitaxial growth process. For example, the source / drain structure 136 may be boron (B)-doped epitaxially grown SiGe. Alternatively, the source / drain structure 136 may be carbon-doped to form a silicon:carbon (Si:C) source / drain device, phosphorus-doped to form a silicon:phosphorus (Si:P) source / drain device, or carbon and phosphorus-doped to form a silicon-carbon-phosphorus (SiCP) source / drain device. In some embodiments, the source / drain structure 136 is doped in one or more implantation processes after the epitaxial growth process.

[0050] According to some embodiments, after forming the source / drain structure 136, a contact etch stop layer (CESL) 138 is conformally formed to cover the source / drain structure 136, and an interlayer dielectric (ILD) layer 140 is formed above the contact etch stop layer 138, such as... Figure 2F-1 and Figure 2F-2 As shown.

[0051] In some embodiments, the contact etch stop layer 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layer 138 may be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

[0052] The interlayer dielectric layer 140 may comprise a multilayer made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The interlayer dielectric layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0053] According to some embodiments, after the contact etch stop layer 138 and the interlayer dielectric layer 140 are deposited, a planarization process such as CMP or an etch-back process can be performed until the gate electrode layer 120 of the dummy gate structure 118 is exposed. Figure 2F-1 As shown.

[0054] Next, according to some embodiments, the pseudo-gate structure 118 is replaced with the gate structure 142, such as... Figure 2G-1 and Figure 2G-2As shown. More specifically, according to some embodiments, the dummy gate structure 118 and the first semiconductor material layer 106 are removed to form a nanostructure 108' with the second semiconductor material layer 108. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 122 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 122. Subsequently, plasma dry etching, dry chemical etching, and / or wet etching may be used to remove the dummy gate dielectric layer 120. The first semiconductor material layer 106 may be removed by performing a selective wet etching process, such as an APM (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine catechol (EDP), and / or potassium hydroxide (KOH) solution. In some embodiments, the upper portion of the gate spacer 126 is also removed.

[0055] According to some embodiments, after forming the nanostructure 108', a gate structure 142 is formed surrounding the nanostructure 108', such as... Figure 2G-1 and Figure 2G-2 As shown. According to some embodiments, the gate structure 142 surrounds the nanostructure 108' to form an all-around gate transistor structure. In some embodiments, the gate structure 142 includes an interface layer 144, a gate dielectric layer 146, and a gate electrode layer 148.

[0056] In some embodiments, the interface layer 144 is an oxide layer formed around the nanostructure 108' and on top of the base fin structure 104B. In some embodiments, the interface layer 144 is formed by performing a thermal process.

[0057] In some embodiments, a gate dielectric layer 146 is formed over an interface layer 144 such that the nanostructure 108' is surrounded (e.g., encircled) by the gate dielectric layer 146. Furthermore, according to some embodiments, the gate dielectric layer 146 also covers the sidewalls of the gate spacer 126 and the inner spacer 134. In some embodiments, the gate dielectric layer 146 is made of one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or combinations thereof. In some embodiments, CVD, ALD, another suitable method, or a combination thereof is used to form the gate dielectric layer 146.

[0058] In some embodiments, the gate electrode layer 148 is formed on the gate dielectric layer 146. In some embodiments, the gate electrode layer 148 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layer 148 is formed using CVD, ALD, electroplating, another suitable method, or a combination thereof. Other conductive layers, such as a work function metal layer, may also be formed in the gate structure 142, although they are not shown in the figures. After the interface layer 144, the gate dielectric layer 146, and the gate electrode layer 148 are formed, a planarization process, such as CMP or an etch-back process, may be performed until the interlayer dielectric layer 140 is exposed.

[0059] Subsequently, according to the embodiment, a row etch-back process is performed to remove the upper portion of the gate structure 142, and a capping layer 150 and a mask layer 152 are formed over the gate structure 142, as follows. Figure 2G-1 and Figure 2G-2 As shown. More specifically, according to some embodiments, the upper portion of the gate structure 142 is removed to form a groove in the interlayer dielectric layer 140, and a capping layer 150 and a mask layer 152 are formed in the groove.

[0060] In some embodiments, the capping layer 150 is made of W, Ti, Co, Ru, Ni, etc. The capping layer 150 can be formed using CVD, ALD, electroplating, another suitable method, or a combination thereof. In some embodiments, the capping layer 150 is selectively formed over the gate structure 142. In some embodiments, the mask layer 152 is made of SiO2, Si3N4, SiON, SiOCN, SiOCH, etc. The mask layer 152 can be formed using CVD, ALD, electroplating, another suitable method, or a combination thereof.

[0061] According to some embodiments, after forming the mask layer 152, a contact opening is formed through the contact etch stop layer 138 and the interlayer dielectric layer 140, and a silicide layer 154 and a contact 156 are formed over the source / drain structure 136, such as... Figure 2H-1 and Figure 2H-2 As shown. In some embodiments, a pad 158 and a barrier layer 160 are formed around the contact 156.

[0062] More specifically, contact openings can be formed through the contact etch stop layer 138 and the interlayer dielectric layer 140 to expose the top surface of the source / drain structure 136, and a silicide layer 154 and contact 156 can be formed in the contact openings. Photolithography and etching processes can be used to form the contact openings. Furthermore, during the etching process, some portions of the source / drain structure 136 exposed by the contact openings can also be etched.

[0063] After the contact opening is formed, the silicide layer 154 can be formed by forming a metal layer above the top surface of the source / drain structure 136 and annealing the metal layer to react with the source / drain structure 136 to form a silicide layer 154. Unreacted metal layers can be removed after the silicide layer 154 is formed.

[0064] Subsequently, according to some embodiments, a pad 158, a barrier layer 160, and a contact 156 are formed over the silicide layer 154 in the contact opening, and a polishing process is performed, such as... Figure 2H-1 and Figure 2H-2 As shown. Figure 2H-1 As shown, according to some embodiments, the top surface of the contact 156 is substantially flush with the top surface of the mask layer 152.

[0065] In some embodiments, the contact 156 is made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. In some embodiments, the pad 158 is made of silicon nitride, but any other suitable dielectric may be used as an alternative. In some embodiments, the barrier layer 160 is made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used. The pad 158, barrier layer 160, and contact 156 may be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0066] In some embodiments, the top surface of the contact 156 is higher than the top surface of the gate structure 142 and substantially flush with the mask layer 152. In some embodiments, the height difference between the contact 156 and the gate structure 142 is substantially flush with the height of the mask layer 152.

[0067] According to some embodiments, after the contact 156 is formed, an etch stop layer 162 is formed over the contact 156 and the mask layer 152, and a dielectric layer 164 is formed over the etch stop layer 162, such as... Figure 2I-1 and Figure 2I-2 As shown.

[0068] In some embodiments, the etch stop layer 162 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used to contact the etch stop layer 162 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

[0069] The dielectric layer 164 may comprise a multilayer made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The dielectric layer 164 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0070] According to some embodiments, after the dielectric layer 164 is formed, a first trench 166 is formed through the mask layer 152, the etch stop layer 162, and the dielectric layer 164, such as... Figure 2J-1 and Figure 2J-2 As shown. In some embodiments, the upper portion of the overlay layer 150 is also etched when forming the first trench 166. The first trench 166 can be formed by performing one or more etching processes, including dry etching and / or wet etching processes.

[0071] Next, according to some embodiments, such as Figure 2K-1 and Figure 2K-2 As shown, a conductive material 168 is formed in the first trench 166. In some embodiments, the conductive material 168 is W, Ru, Mo, etc. In some embodiments, the conductive material 168 is formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0072] In some embodiments, the conductive material 168 is formed by performing a bottom-up deposition process. A bottom-up deposition process generally refers to a deposition process that fills openings from bottom to top. By using a bottom-up deposition process, the first trench 166 can be filled without creating air gaps therein. In some embodiments, the bottom-up deposition process is a selective CVD process, wherein the conductive material 168 is selectively deposited over the capping layer 150.

[0073] In some embodiments, the conductive material 168 is Ru, and the precursor gas used in the bottom-up deposition process includes Ru(CO)5 and Ru3(CO). 12 The conductive material 168 includes RuCl3, Ru(od)3, bis(cyclopentadienyl)ruthenium(II), Ru(CO)3C6H8, Ru(CO)2(tmhd)2, Ru(EtCp)2, Ru(CO)2(acac)2, Ru(C6H6)(C6H8), Ru(DMBD)(CO)3, and combinations thereof. In some embodiments, the conductive material 168 is W, and the precursor gas used in the bottom-up deposition process includes W(CO)6, W(F)6, etc. In some embodiments, the conductive material 168 is Mo, and the precursor gas used in the bottom-up deposition process includes MoF6, Mo(CO)6, MoCl5, MoO x Cl y wait.

[0074] Subsequently, according to some embodiments, a polishing process is performed to form a conductive structure 170 in the first trench 166 above the gate structure 142, such as... Figure 2L-1 and Figure 2L-2 As shown. In some embodiments, a CMP process is performed to polish the conductive material 168 such that the top surface of the conductive structure 170 is substantially flush with the top surface of the dielectric layer 164.

[0075] Next, according to some embodiments, the conductive structure 170 is shortened to form a shortened conductive structure 171, such as... Figure 2M-1 and Figure 2M-2 As shown. More specifically, according to some embodiments, the upper portion of the conductive structure 170 is etched back such that the top surface of the shortened conductive structure 171 is substantially flush with the top surface of the etch stop layer 162.

[0076] In some embodiments, the height H1 of the shortened conductive structure 171 is in the range of about 10 nm to about 50 nm. In some embodiments, the depth D1 of the trench 167 (e.g., the height of the upper portion of the conductive structure 170 removed) is in the range of about 30 nm to about 70 nm. In some embodiments, the ratio of height H1 to depth D1 is in the range of about 0.6 to about 7.

[0077] According to some embodiments, after shortening the conductive structure 170, a second trench 172 is formed through the dielectric layer 164 and the etch stop layer 162 to expose the top surface of the contact 156 and the top surface of the shortened conductive structure 171, such as... Figure 2N-1 and Figure 2N-2As shown. The second trench 172 can be formed by performing an etching process. According to some embodiments, during the etching process, both the corners of the contact 156 and the corners of the shortened conductive structure 171 are etched, such that the contact 156 and the shortened conductive structure 171 have rounded corners facing each other.

[0078] In some embodiments, a portion of the mask layer 152 is also removed, such that the second trench 172 has an extension 173 extending into the mask layer 142. In some embodiments, the lowest portion of the extension 173 of the second trench 172 is below the top surface of the contact 156. Furthermore, according to some embodiments, the upper portion of the sidewall of the shortened conductive structure 171 is exposed by the extension 173 of the second trench 172.

[0079] Next, according to some embodiments, such as Figure 2O-1 and Figure 2O-2 As shown, conductive material 174 is formed in the second trench 172. According to some embodiments, the shortened conductive structure 171 and conductive material 174 have a curved interface because the corners of the shortened conductive structure 171 are etched.

[0080] In some embodiments, the conductive material 174 is W, Ru, Mo, Cu, etc. In some embodiments, the conductive material 174 and the conductive material 168 are the same metal. In some embodiments, the conductive material 174 and the conductive material 168 are different metals.

[0081] In some embodiments, the conductive material 174 is formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the conductive material 174 is formed by performing a bottom-up deposition process. The bottom-up deposition process used to form the conductive material 174 may be the same as or similar to the process used to form the conductive material 168, and will not be described further herein. In some embodiments, the deposition processes (e.g., precursor gases) used for the conductive material 174 and the conductive material 168 are the same.

[0082] Since the shortened conductive structure 171 is formed first, the height difference between different regions of the second trench 172 (e.g., the region above the contact 156 and the region above the gate structure 142) can be relatively small. Therefore, the conductive material 174 can be formed by performing a bottom-up deposition process, wherein the connection between the contact 156 and the gate structure 142 is improved.

[0083] In some embodiments, a void 176 is formed in the conductive material 174 at the extension 173 of the second trench 173. In some embodiments, the void 176 is sandwiched between the contact 156 and the shortened conductive structure 171 and is located directly above the mask layer 152.

[0084] Subsequently, according to some embodiments, a polishing process is performed to form a conductive structure 176 in the semiconductor structure 100, such as... Figure 2P-1 and Figure 2P-2 As shown. In some embodiments, a CMP process is performed to polish the conductive material 174 so that the top surface of the conductive structure 176 is substantially flush with the top surface of the dielectric layer 164.

[0085] In some embodiments, the height difference H2 between the shortened conductive structure 171 and the contact 156 is less than 10 nm. Because the height difference H2 between the shortened conductive structure 171 and the contact 156 is relatively small, the conductive structure 178 can be formed more effectively. That is, the risk of disconnection between the gate structure 142 and the contact 156 due to the height difference between them can be reduced. In some embodiments, the ratio of the height difference H2 between the shortened conductive structure 171 and the contact 156 to the height difference H3 between the contact 156 and the gate structure 142 is in the range of about 0.2 to about 0.5.

[0086] like Figure 2P-1 As shown, different portions of the conductive structure 178 may have different thicknesses. In some embodiments, the conductive structure 178 has a first portion above the contact 156, and the thickness T1 of the first portion is in the range of about 35 nm to about 90 nm. In some embodiments, the conductive structure 178 has a second portion above the shortened conductive structure 171, and the thickness T2 of the second portion is in the range of about 30 nm to about 70 nm. In some embodiments, the ratio of thickness T2 to thickness T1 is in the range of about 0.5 to about 3.

[0087] In some embodiments, the conductive structure 178 has a third portion between the first portion and the second portion, and the thickness T3 of the third portion is in the range of about 38 nm to about 100 nm. More specifically, the conductive structure 178 has an extension portion between the shortened conductive structure 171 and the contact 156, and the thickness T4 of the extension portion is in the range of about 3 nm to about 10 nm.

[0088] In some embodiments, the bottommost portion of the conductive structure 178 (e.g., the bottommost portion of the extension of the conductive structure 178) is lower than the topmost portion (e.g., the top surface) of the shortened conductive structure 171, the contact 156, the mask layer 152, and the etch stop layer 162. Furthermore, the bottommost portion of the conductive structure 178 is higher than the bottommost surface of the shortened conductive structure 171, the contact 156, and the mask layer 152.

[0089] It should be understood that, despite Figure 2P-1 and Figure 2P-2The cross-sectional view shown is described by the reference method, but the structure is not limited to this method and can exist independently of this method.

[0090] Figure 3 A cross-sectional view is shown of another intermediate stage in the fabrication of semiconductor structure 100 according to some embodiments. According to some embodiments, the above-described process for fabricating semiconductor structure 100 can be performed, the difference being that the conductive material 168-1 formed in the first trench is comparable. Figure 2K-1 The conductive material shown is 168 thin.

[0091] More specifically, according to some embodiments, the following is performed: Figures 1A to 1E , Figures 2A-1 to 2J-1 and Figures 2A-2 to 2J-2 The process shown involves forming a first trench (e.g., first trench 166) through a mask layer 152, an etch stop layer 162, and a dielectric layer 164. Subsequently, according to some embodiments, a conductive material 168-1 is formed in the first trench, such as... Figure 3 As shown. Conductive material 168-1 may be similar to conductive material 168, except that conductive material 168-1 does not cover the top surface of dielectric layer 164. The process and materials used to form conductive material 168-1 may be similar to or the same as those used to form conductive material 168, and will not be described further here.

[0092] In some embodiments, the top surface of the conductive material 168-1 is lower than the top surface of the dielectric layer 164, such that the first trench is not completely filled with the conductive material 168-1. According to some embodiments, after forming the conductive material 168-1, a polishing process is performed to form a conductive structure over the gate structure 142. According to some embodiments, during the polishing process, the upper portion of the conductive material 168-1 and the upper portion of the dielectric layer 164 are removed, such that the resulting conductive structure and dielectric layer 164 can still have a substantially flat top surface (similar to...). Figure 2L-1 and Figure 2L-2 (As shown). After that, execution is possible. Figures 2M-1 to 2P-1 and Figures 2M-2 to 2P-2 The process shown is used to form semiconductor structure 100.

[0093] Figure 4 A cross-sectional view is shown of another intermediate stage in the fabrication of semiconductor structure 100 according to some embodiments. According to some embodiments, the above-described process for fabricating semiconductor structure 100 can be performed, differing in the formation of conductive material 168-2 and additional conductive material 169.

[0094] More specifically, according to some embodiments, the following is performed: Figures 1A to 1E , Figures 2A-1 to 2J-1 and Figures 2A-2 to 2J-2The process shown involves forming a first trench (e.g., first trench 166) through a mask layer 152, an etch stop layer 162, and a dielectric layer 164. Subsequently, according to some embodiments, a conductive material 168-2 is formed in the first trench, and a conductive material 169 is formed above the conductive material 168-2, such as... Figure 4 As shown. The process and materials used to form conductive material 168-2 may be similar to or the same as those used to form conductive material 168, and will not be described again here.

[0095] According to some embodiments, similar to conductive material 168-1, the top surface of conductive material 168-2 is lower than the top surface of dielectric layer 164, such that the first trench is not completely filled with conductive material 168-2. Furthermore, according to some embodiments, the upper portion of the first trench is filled with conductive material 169, and the top surface of dielectric layer 164 is covered by conductive material 169.

[0096] In some embodiments, conductive material 168-2 and conductive material 169 are made of the same material but formed by different processes. In some embodiments, conductive material 169 is formed by performing a CVD process.

[0097] According to some embodiments, after forming the conductive material 169, a polishing process is performed to form a conductive structure over the gate structure 142. In some embodiments, the conductive material 169 is completely removed during the polishing process, such that the resulting conductive structure is entirely made of the conductive material 168-2. In some embodiments, the upper portion of the conductive material 168-2 and the upper portion of the dielectric layer 164 are also removed during the polishing process. Since the upper portion of the first trench is filled with the conductive material 169 and the top surface of the dielectric layer 164 is covered by the conductive material 169, the uniformity of the polishing process can be improved. Afterwards, [further steps can be performed]. Figures 2M-1 to 2P-1 and Figures 2M-2 to 2P-2 The process shown is used to form semiconductor structure 100.

[0098] Figure 5 A cross-sectional view of a semiconductor structure 200 according to some embodiments is shown. According to some embodiments, the semiconductor structure 200 may be similar to... Figure 2P-1 and Figure 2P-2 The semiconductor structure 100 shown differs in that the semiconductor structure 200 is a FinFET structure. The materials and processes used to manufacture the semiconductor structure 200 may be similar to or the same as those used to manufacture the semiconductor structure 100, and will not be described again here.

[0099] More specifically, according to some embodiments, such as Figure 5As shown, the fin structure 204 is formed to protrude from the substrate 102, and the gate structure 242 is formed to span the fin structure 204. According to some embodiments, the gate structure 242 includes an interface layer 244, a gate dielectric layer 246, and a gate electrode layer 248. The processes and materials used to form the interface layer 244, the gate dielectric layer 246, and the gate electrode layer 248 are the same as those used to form the interface layer 144, the gate dielectric layer 146, and the gate electrode layer 148, and will not be described again here. According to some embodiments, similar to... Figure 2P-1 and Figure 2P-2 As shown, shortened conductive structures 171 are formed above the gate structure 242, and conductive structures 178 cover the contact 156 and the shortened conductive structures 171 above the gate structure 242, such as Figure 5 As shown.

[0100] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 A cross-sectional view of a semiconductor structure 100a manufactured according to some embodiments is shown. According to some embodiments, semiconductor structure 100a may be identical to semiconductor structure 100, differing only in the shape of the contacts and shortened conductive structures. The materials and processes used to manufacture semiconductor structure 100a may be similar to or identical to those described above for manufacturing semiconductor structure 100, and will not be repeated here.

[0101] More specifically, Figure 6A-1 and Figure 6B-1 It is a cross-sectional view showing only the fin direction, while Figure 6A-2 and Figure 6B-2 This is a cross-sectional view showing only the gate direction. According to some embodiments, similar to those used to form semiconductor structure 100, the following is performed: Figures 1A to 1E , Figures 2A-1 to 2M-1 and Figures 2A-2 to 2M-2 The process shown forms a shortened conductive structure 171a. Subsequently, according to some embodiments, an etching process is performed to form a second trench 172a through the dielectric layer 164 and the etch stop layer 162, as shown. Figure 6A-1 and Figure 6B-1 As shown. During the etching process, an etchant can be selected to have good etching selectivity between conductive and dielectric materials, so that the shape of the contact 156a and the shortened conductive structure 171a can be substantially preserved.

[0102] According to some embodiments, the following steps are performed: Figure 2O-1 , Figure 2O-2 , Figure 2P-1 and Figure 2P-2 The process shown and previously described is used to form a conductive structure 178a in the semiconductor structure 100a, such as Figure 6B-1 and Figure 6B-2As shown. Furthermore, according to some embodiments, a gap 176a is formed in the conductive structure 178a and is also sandwiched between the shortened conductive structure 171a and the contact 156a. The processes and materials used to form the contact 156a, the shortened conductive structure 171a, and the conductive structure 178a are the same as those used to form the contact 156, the shortened conductive structure 171, and the conductive structure 178, and will not be described again here.

[0103] Figure 7 A cross-sectional view of a semiconductor structure 100b according to some embodiments is shown. According to some embodiments, the semiconductor structure 100b may be... Figure 2P-1 and Figure 2P-2 The semiconductor structure 100 shown is the same as that shown, except that its capping layer 150b extends over the gate spacer 126. The materials and processes used to manufacture the semiconductor structure 100b may be similar to or the same as those used to manufacture the semiconductor structure 100 described above, and will not be repeated here.

[0104] More specifically, according to some embodiments, a capping layer 150b is sandwiched between the shortened conductive structure 171b and the gate structure 142, and also between the mask layer 152 and the gate spacer 126. In some embodiments, the capping layer 150b is in direct contact with the pad 158 surrounding the contact 156. In some embodiments, the capping layer 150b vertically overlaps with the gap 176b in the conductive structure 178b.

[0105] In some embodiments, the capping layer 150b is made of W, Ti, Co, Ru, Ni, etc. The capping layer 150b can be formed using CVD, ALD, electroplating, another suitable method, or a combination thereof. The processes and materials used to form the shortened conductive structures 171b and 178b are the same as those used to form the shortened conductive structures 171 and 178 described above, and will not be repeated here.

[0106] Figure 8 A cross-sectional view of a semiconductor structure 100c according to some embodiments is shown. According to some embodiments, the semiconductor structure 100c can be coupled with… Figure 2P-1 and Figure 2P-2 The semiconductor structure 100 shown is the same as that of semiconductor structure 100, except that a barrier layer 179 is formed around the conductive structure 178c. The materials and processes used to manufacture semiconductor structure 100c may be similar to or the same as those used to manufacture semiconductor structure 100, and will not be described again here.

[0107] According to some embodiments, more specifically, in forming the second trench (e.g., as... Figure 2N-1 and Figure 2N-2Following the second trench 172 shown, a barrier layer 179 is formed to line the second trench, and a conductive structure 178c is formed above the barrier layer 179, as shown. Figure 8 As shown. In some embodiments, the barrier layer 179 is made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used. The barrier layer 179 may be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0108] In some embodiments, a portion of the barrier layer 179 is sandwiched between the shortened conductive structure 171c and the contact 156. In some embodiments, the barrier layer 179 is in direct contact with the contact 156, the mask layer 152, and the shortened conductive structure 171c. In some embodiments, the bottom portion of the barrier layer 179 is lower than the top portion of the mask layer 152, the top portion of the contact 156, and the top portion of the shortened conductive structure 171c. The processes and materials used to form the shortened conductive structure 171c and the conductive structure 178c are the same as those used to form the shortened conductive structure 171 and the conductive structure 178 described above, and will not be repeated here.

[0109] Figure 9 A cross-sectional view of a semiconductor structure 100d according to some embodiments is shown. According to some embodiments, the semiconductor structure 100d can be... Figure 2P-1 and Figure 2P-2 The semiconductor structure 100 shown is the same as that shown, except that no voids are formed in the conductive structure 178d. The materials and processes used to manufacture the semiconductor structure 100d may be similar to or the same as those used to manufacture the semiconductor structure 100, and will not be described again here.

[0110] More specifically, according to some embodiments, in forming the second trench (e.g., Figure 2N-1 and Figure 2N-2 Following the second trench 171 shown, the second trench is completely filled with the conductive structure 178d, as shown. Figure 9 As shown. The processes and materials used to form the shortened conductive structures 171d and 178d are the same as those used to form the shortened conductive structures 171 and 178, and will not be described again here.

[0111] Figure 10 A cross-sectional view of a semiconductor structure 100e according to some embodiments is shown. According to some embodiments, the semiconductor structure 100e may be... Figure 2P-1 and Figure 2P-2The semiconductor structure 100 shown is the same as that shown, except that a gap 176e is formed between the conductive structure 178e and the mask layer 152. The materials and processes used to manufacture the semiconductor structure 100e may be similar to or the same as those used to manufacture the semiconductor structure 100 described above, and will not be repeated here.

[0112] According to some embodiments, more specifically, after the second trench is formed, the extension portion of the second trench (e.g.) Figure 2N-1 The bottom portion of the extended portion 173) shown is not filled with the conductive structure 178e, thus forming a void 176e, as... Figure 10 As shown. In some embodiments, the sidewalls of the shortened conductive structure 171e and the top surface of the mask layer 152 are exposed by a void 176e. In some embodiments, the bottom region of the void 176e is lower than the bottom portion of the conductive structure 178e. The processes and materials used to form the shortened conductive structure 171e and the conductive structure 178e may be the same as those used to form the shortened conductive structure 171 and the conductive structure 178 described above, and will not be repeated here.

[0113] Figure 11A and Figure 11B A cross-sectional view of a semiconductor structure 100f manufactured according to some embodiments is shown. According to some embodiments, the semiconductor structure 100f may be identical to the semiconductor structure 100, except that its shortened conductive structure 171f is longer than the shortened conductive structure 171. The materials and processes used to manufacture the semiconductor structure 100f may be similar to or identical to those used to manufacture the semiconductor structure 100, and will not be described again here.

[0114] More specifically, executable Figures 1A to 1E , Figures 2A-1 to 2L-1 as well as Figures 2A-2 to 2L-2 The process shown is used to form a conductive structure (e.g., Figure 2L-1 The conductive structure 170 is shown. Next, according to some embodiments, the conductive structure is shortened to form a shortened conductive structure 171f, and the top surface of the shortened conductive structure 171f is higher than the top surface of the etch stop layer 162, as shown. Figure 11A As shown.

[0115] Next, according to some embodiments, the following will be performed. Figures 2N-1 to 2P-1 and Figures 2N-2 to 2P-2 The process shown and previously described is used to form a conductive structure 178f in the semiconductor structure 100f, as... Figure 11BAs shown. Furthermore, according to some embodiments, a gap 176f is formed in the conductive structure 178f and sandwiched between the shortened conductive structure 171f and the contact 156. Since the sidewalls of the etch stop layer 162 are completely covered by the shortened conductive structure 171f, the etch stop layer 162 is protected during the etching process used to form the second trench, and thus the friction between the conductive structure 178f and the adjacent contact 156 (e.g., ...) is reduced. Figure 11B The risk of short circuits between the contacts shown on the right side of the diagram.

[0116] The processes and materials used to form the shortened conductive structures 171f and 178f are the same as those used to form the shortened conductive structures 171 and 178, and will not be described again here.

[0117] Figure 12A and Figure 12B A cross-sectional view of a semiconductor structure 100g manufactured according to some embodiments is shown. According to some embodiments, the semiconductor structure 100g may be identical to the semiconductor structure 100, except that its shortened conductive structure 171g is shorter than the shortened conductive structure 171. The materials and processes used to manufacture the semiconductor structure 100g may be similar to or identical to those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0118] More specifically, executable Figures 1A to 1E , Figures 2A-1 to 2L-1 as well as Figures 2A-2 to 2L-2 The process shown is used to form a conductive structure (e.g., Figure 2L-1 The conductive structure 170 is shown. Next, according to some embodiments, the conductive structure is shortened to form a shortened conductive structure 171g, and the top surface of the shortened conductive structure 171g is lower than the top surface of the etch stop layer 162, as shown. Figure 12A As shown.

[0119] Next, according to some embodiments, the following will be performed. Figures 2N-1 to 2P-1 and Figures 2N-2 to 2P-2 The process shown and previously described is used to form a conductive structure 178g in a semiconductor structure 100g, as... Figure 12B As shown. Furthermore, according to some embodiments, a void 176g is formed within the conductive structure 178g and is also sandwiched between the shortened conductive structure 171g and the contact 156. Since the sidewalls of the etch stop layer 162 are partially covered by the shortened conductive structure 171g, the etch stop layer 162 is still protected during the etching process, and lateral etching of the etch stop layer 162 can be reduced.

[0120] The processes and materials used to form the shortened conductive structures 171g and 178g are the same as those used to form the shortened conductive structures 171 and 178, and will not be described again here.

[0121] It should be understood that, similar to Figure 5 As shown, the aforementioned semiconductor structures 100a to 100g, having shortened conductive structures 171a to 171g and conductive structures 178a to 178g, can also be applied to FinFET structures, although they are not shown in the figure.

[0122] Typically, conductive structures are formed to connect the gate structure to the contacts above the S / D structure. However, as device dimensions shrink, it may be necessary to form conductive structures in relatively small trenches. In some cases, bottom-up deposition can be performed to fill the conductive material in the small trenches, resulting in fewer air gaps within the trenches. However, since the contacts may be much higher than the gate structure, the conductive material formed above the contacts may initially block the trench opening as the conductive material is formed in the trench, meaning the conductive material above the gate structure (i.e., in the deeper parts of the trench) may not be fully filled. In other words, the contacts and gate structure may not be well connected.

[0123] Therefore, according to some embodiments, a first conductive structure (e.g., conductive structure 170) is first formed above the gate structure 142, and the upper portion of the conductive structure is removed to form a shortened conductive structure (e.g., shortened conductive structures 171 and 171a to 171g). By forming the shortened conductive structure, the subsequently formed second conductive structure (e.g., conductive structures 178 and 178a to 178g) can be formed by bottom-up deposition without worrying about the aforementioned blockage problem due to the relatively large height difference. Furthermore, since both the shortened conductive structure and the subsequently formed second conductive structure can be formed by bottom-up deposition, trench filling can be improved, and thus the performance of the resulting semiconductor structure (e.g., semiconductor structures 100, 100a to 100g and 200) can also be improved.

[0124] It should be noted that Figures 1A to 12B The same components may use the same designation, may include similar or identical materials, and may be formed using similar or identical processes; therefore, for the sake of brevity, such redundant details are omitted. Furthermore, although... Figures 1A to 12B It's about the method description, but it should be understood that... Figures 1A to 12B The structure disclosed herein is not limited to this method, but can exist independently of this method. Similarly, although Figures 1A to 12B The methods shown are not limited to the disclosed structures, but can exist independently of such structures. Furthermore, according to some embodiments, the aforementioned nanostructures may include nanowires, nanosheets, or other suitable nanostructures.

[0125] Furthermore, although the disclosed methods are shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown may be altered in some other embodiments. For example, in addition to those steps or events shown and / or described above, certain steps may occur in a different order and / or simultaneously with other steps or events. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described above. Moreover, one or more actions depicted above may be performed in one or more separate actions and / or phases.

[0126] Furthermore, the terms “about,” “approximately,” “basically,” and “about” described above have minor variations and can vary across different technologies and fall within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, these terms can refer to a situation where the event or situation occurred precisely or a situation where the event or situation occurred very approximately.

[0127] Embodiments for forming semiconductor structures are available. The semiconductor structure may include a gate structure, a source / drain structure adjacent to the gate structure, and contacts above the source / drain structures. A first conductive structure may be formed above the gate structure, and then the upper portion of the first conductive structure may be removed. A second conductive structure may be formed above the contacts and the first conductive structure. Because the height difference between the shortened first conductive structure and the contacts is smaller, the second conductive structure can be formed more effectively, and the performance of the semiconductor structure can be improved.

[0128] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes: forming a gate structure over a substrate; and forming a mask layer covering the gate structure. The method for manufacturing the semiconductor structure further includes: forming a source / drain structure adjacent to the gate structure over the substrate; and forming a contact over the source / drain structure. The method for manufacturing the semiconductor structure further includes: forming a dielectric layer over the contact and the mask layer; and forming a first trench over the gate structure through the dielectric layer and the mask layer. The method for manufacturing the semiconductor structure further includes: forming a first conductive structure in the first trench; and removing an upper portion of the first conductive structure. The method for manufacturing the semiconductor structure further includes: forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

[0129] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes: forming a nanostructure over a substrate; and forming a gate structure surrounding the nanostructure. The method for manufacturing the semiconductor structure further includes: forming a source / drain structure attached to the nanostructure adjacent to the gate structure; and forming contacts bonded to the source / drain structure. The method for manufacturing the semiconductor structure further includes: forming a dielectric layer over the contacts and the gate structure; and forming a first conductive structure through the dielectric layer and covering the gate structure. The method for manufacturing the semiconductor structure further includes: etching an upper portion of the first conductive structure such that the top surface of the first conductive structure becomes lower than the top surface of the dielectric layer; and forming a second conductive structure through the dielectric layer to cover the contacts and the first conductive structure.

[0130] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate; and a gate structure formed over the substrate. The semiconductor structure further includes: a mask layer formed over the gate structure; and a source / drain structure formed adjacent to the gate structure over the substrate. The semiconductor structure further includes: a contact formed over the source / drain structure; and a first conductive structure formed through the mask layer and bonded to the gate structure. The semiconductor structure further includes: a second conductive structure covering the first conductive structure and the contact. Additionally, the second conductive structure includes an extension sandwiched between an upper portion of the first conductive structure and an upper portion of the contact.

[0131] Some embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a gate structure over a substrate; forming a mask layer covering the gate structure; forming a source / drain structure adjacent to the gate structure over the substrate; forming a contact over the source / drain structure; forming a dielectric layer over the contact and the mask layer; forming a first trench over the gate structure through the dielectric layer and the mask layer; forming a first conductive structure in the first trench; removing an upper portion of the first conductive structure; and forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

[0132] In some embodiments, after the upper portion of the first conductive structure is removed, the top surface of the first conductive structure is lower than the top surface of the dielectric layer. In some embodiments, the method of manufacturing the semiconductor structure further includes: forming a second trench through the dielectric layer, wherein the contact and the first conductive structure are exposed by the second trench. In some embodiments, the method of manufacturing the semiconductor structure further includes: partially removing the mask layer such that the second trench extends into the mask layer. In some embodiments, the method of manufacturing the semiconductor structure includes: forming a third conductive structure above the first conductive structure in the upper portion of the first trench; and removing the third conductive structure before forming the second conductive structure. In some embodiments, the method of manufacturing the semiconductor structure includes: the bottom portion of the second conductive structure is lower than the top surface of the mask layer.

[0133] Other embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a nanostructure over a substrate; forming a gate structure surrounding the nanostructure; forming a source / drain structure attached to the nanostructure adjacent to the gate structure; forming contacts bonded to the source / drain structure; forming a dielectric layer over the contacts and the gate structure; forming a first conductive structure through the dielectric layer and covering the gate structure; etching an upper portion of the first conductive structure such that the top surface of the first conductive structure is lower than the top surface of the dielectric layer; and forming a second conductive structure through the dielectric layer to cover the contacts and the first conductive structure. In some embodiments, the method for manufacturing the semiconductor structure includes forming voids in the second conductive structure. In some embodiments, the method for manufacturing the semiconductor structure further includes: forming a mask layer over the gate structure, wherein the top surface of the mask layer is substantially flush with the top surface of the contacts. In some embodiments, the method of manufacturing the semiconductor structure further includes: forming an etch stop layer covering the top surface of the contact and the top surface of the mask layer; and forming a first trench through the dielectric layer, the etch stop layer, and the mask layer, wherein the first conductive structure is formed in the first trench. In some embodiments, the method of manufacturing the semiconductor structure further includes: etching the dielectric layer and the etch stop layer after etching the upper portion of the first conductive structure to form a second trench exposing the contact; forming a conductive material in the second trench; and polishing the conductive material to form the second conductive structure in the second trench. In some embodiments, the method of manufacturing the semiconductor structure further includes: removing corner portions of the first conductive structure before forming the conductive material in the second trench. In some embodiments, the method of manufacturing the semiconductor structure includes, after etching the upper portion of the first conductive structure, the top surface of the first conductive structure is lower than the top surface of the etch stop layer.

[0134] Further embodiments of this application provide a semiconductor structure including: a substrate; a gate structure formed over the substrate; a mask layer formed over the gate structure; a source / drain structure formed adjacent to the gate structure over the substrate; a contact formed over the source / drain structure; a first conductive structure formed through the mask layer and bonded to the gate structure; and a second conductive structure covering the first conductive structure and the contact, wherein the second conductive structure includes an extension sandwiched between an upper portion of the first conductive structure and an upper portion of the contact.

[0135] In some embodiments, a semiconductor structure is provided, wherein the lowest portion of the second conductive structure is lower than the top surface of the first conductive structure. In some embodiments, a semiconductor structure is provided, wherein a void is embedded in the second conductive structure. In some embodiments, a semiconductor structure is provided, wherein the void is sandwiched between the upper portion of the first conductive structure and the upper portion of the contact. In some embodiments, a semiconductor structure is provided, further comprising: a dielectric layer formed over the mask layer and the contact, wherein the second conductive structure penetrates the dielectric layer, and the extended portion of the second conductive structure extends into the mask layer. In some embodiments, a semiconductor structure is provided, further comprising: a barrier layer surrounding the extended portion of the second conductive structure, wherein the barrier layer is in direct contact with the first conductive structure, the contact, and the mask layer.

[0136] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A pseudo-gate structure is formed above the substrate; Form a mask layer covering the pseudo-gate structure; A source / drain structure adjacent to the dummy gate structure is formed above the substrate; Replace the pseudo-gate structure with a gate structure; A contact is formed above the source / drain structure; A dielectric layer is formed over the contact and the mask layer; A first trench is formed above the gate structure, passing through the dielectric layer and the mask layer; A first conductive structure is formed in the first trench; Remove the upper portion of the first conductive structure; as well as A second conductive structure is formed that penetrates the dielectric layer and covers the contact and the first conductive structure. Wherein, the top surface of the first conductive structure is higher than the top surface of the contact, and the height difference between the first conductive structure and the contact is less than 10 nm.

2. The method for manufacturing the semiconductor structure according to claim 1, wherein, After the upper portion of the first conductive structure is removed, the top surface of the first conductive structure is lower than the top surface of the dielectric layer.

3. The method for manufacturing the semiconductor structure according to claim 1, further comprising: A second trench is formed through the dielectric layer, wherein the contact and the first conductive structure are exposed by the second trench.

4. The method for manufacturing the semiconductor structure according to claim 3, further comprising: The mask layer is partially removed so that the second trench extends into the mask layer.

5. The method for manufacturing the semiconductor structure according to claim 4, wherein, The second conductive structure is formed in the second trench.

6. The method for manufacturing the semiconductor structure according to claim 1, further comprising: A third conductive structure is formed above the first conductive structure in the upper portion of the first trench; as well as The third conductive structure is removed before the second conductive structure is formed.

7. The method for manufacturing the semiconductor structure according to claim 1, wherein, The bottom portion of the second conductive structure is lower than the top surface of the mask layer.

8. A method for manufacturing a semiconductor structure, comprising: Nanostructures are formed on the substrate; A pseudo-gate structure is formed around the nanostructure; A source / drain structure is formed adjacent to the pseudo-gate structure and attached to the nanostructure; Replace the pseudo-gate structure with a gate structure; Forming contacts that are bonded to the source / drain structure; A dielectric layer is formed over the contact and the gate structure; A first conductive structure is formed that passes through the dielectric layer and covers the gate structure; The upper portion of the first conductive structure is etched so that the top surface of the first conductive structure is lower than the top surface of the dielectric layer; as well as A second conductive structure is formed through the dielectric layer to cover the contact and the first conductive structure. Wherein, the top surface of the first conductive structure is higher than the top surface of the contact, and the height difference between the first conductive structure and the contact is less than 10 nm.

9. The method for manufacturing the semiconductor structure according to claim 8, wherein, A void is formed in the second conductive structure.

10. The method for manufacturing the semiconductor structure according to claim 8, further comprising: A mask layer is formed above the gate structure, wherein the top surface of the mask layer is substantially flush with the top surface of the contact.

11. The method for manufacturing the semiconductor structure according to claim 10, further comprising: An etch stop layer is formed, the etch stop layer covering the top surface of the contact and the top surface of the mask layer; as well as A first trench is formed through the dielectric layer, the etch stop layer, and the mask layer. The first conductive structure is formed in the first trench.

12. The method for manufacturing the semiconductor structure according to claim 11, further comprising: After etching the upper portion of the first conductive structure, the dielectric layer and the etch stop layer are etched to form a second trench exposing the contact. A conductive material is formed in the second trench; as well as The conductive material is polished to form the second conductive structure in the second trench.

13. The method for manufacturing the semiconductor structure according to claim 12, further comprising: The corners of the first conductive structure are removed before the conductive material is formed in the second trench.

14. The method for manufacturing the semiconductor structure according to claim 11, wherein, After etching the upper portion of the first conductive structure, the top surface of the first conductive structure is lower than the top surface of the etch stop layer.

15. A semiconductor structure comprising: Substrate; A gate structure is formed above the substrate; A mask layer is formed above the gate structure; A source / drain structure is formed adjacent to the gate structure above the substrate; Contacts are formed above the source / drain structure; A first conductive structure is formed through the mask layer and bonded to the gate structure; as well as A second conductive structure covers the first conductive structure and the contact, wherein the second conductive structure includes an extension sandwiched between the upper portion of the first conductive structure and the upper portion of the contact. Wherein, the top surface of the first conductive structure is higher than the top surface of the contact, and the height difference between the first conductive structure and the contact is less than 10 nm.

16. The semiconductor structure according to claim 15, wherein, The bottom part of the second conductive structure is lower than the top surface of the first conductive structure.

17. The semiconductor structure according to claim 15, wherein, The gap is embedded in the second conductive structure.

18. The semiconductor structure according to claim 17, wherein, The gap is sandwiched between the upper portion of the first conductive structure and the upper portion of the contact.

19. The semiconductor structure according to claim 15, further comprising: A dielectric layer is formed above the mask layer and the contact. The second conductive structure penetrates the dielectric layer, and the extended portion of the second conductive structure extends into the mask layer.

20. The semiconductor structure according to claim 15, further comprising: A barrier layer surrounds the extension of the second conductive structure, wherein the barrier layer is in direct contact with the first conductive structure, the contact element, and the mask layer.

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