Method for manufacturing semiconductor device, semiconductor manufacturing system, and semiconductor device

Abstract

According to one embodiment, a method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes a step of inspecting each of a plurality of chip regions on a substrate, and determining the inspected chip regions as either a pass chip region or a fail chip region. The plurality of chip regions on the substrate are arranged in a planar direction. The plurality of chip regions are configured as one system. The method of manufacturing a semiconductor device includes a step of forming a re-wiring layer including a wire connected to an electrode of the pass chip region of the plurality of chip regions and not connected to an electrode of the fail chip region.

Description

[0001] Related applications

[0002] This application enjoys the benefit of priority to Japanese Patent Application No. 2021-037778, filed on March 9, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a method for manufacturing a semiconductor device, a semiconductor manufacturing system, and a semiconductor device. Background Technology

[0004] In the manufacturing process of semiconductor devices, multiple chip regions are formed on a substrate to manufacture the semiconductor device. At this point, it is desirable to improve the yield rate of the semiconductor device. Summary of the Invention

[0005] One embodiment provides a method for manufacturing a semiconductor device, a semiconductor manufacturing system, and a semiconductor device that can easily improve the manufacturing yield of a semiconductor device.

[0006] According to this embodiment, a method for manufacturing a semiconductor device is provided. The method includes the step of inspecting each of a plurality of chip regions on a substrate and determining the inspected chip regions as either qualified chip regions or unqualified chip regions. The plurality of chip regions on the substrate are arranged in a planar direction. The plurality of chip regions are configured into a system. The method also includes the step of forming a redistribution layer, the redistribution layer comprising lines connected to electrodes of qualified chip regions among the plurality of chip regions but not connected to electrodes of unqualified chip regions.

[0007] Based on the above configuration, a semiconductor device manufacturing method, a semiconductor manufacturing system, and a semiconductor device can be provided that can easily improve the manufacturing yield of semiconductor devices. Attached Figure Description

[0008] Figures 1A to 1D These are plan views and cross-sectional views illustrating an outline of a method for manufacturing a semiconductor device according to the first embodiment.

[0009] Figure 2 This is a diagram illustrating the configuration of a semiconductor manufacturing system in which the semiconductor device manufacturing method according to the first embodiment is applied.

[0010] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figures 4A to 4C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 5A and Figure 5B This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figures 6A to 6C These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figures 7A to 7C These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0015] Figures 8A to 8C These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figures 9A to 9C These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figures 10A to 10C These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 11 This is a plan view showing the system wafer in a first variation of the first embodiment.

[0019] Figure 12 This is a plan view showing the system chip in a second variation of the first embodiment.

[0020] Figures 13A to 13D These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0022] Figure 15A and 15B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0023] Figure 16A and 16B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0024] Figure 17A and Figure 17B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0025] Figure 18A and Figure 18BThese are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0026] Figure 19 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0027] Figure 20A and Figure 20B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0028] Figure 21A and 21B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0029] Figure 22A and Figure 22B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to a variation of the third embodiment.

[0030] Figure 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment.

[0031] Figure 24 This is a plan view illustrating a method for manufacturing a semiconductor device according to another embodiment.

[0032] Figures 25A-25E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment.

[0033] Figures 26A-26C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment. Detailed Implementation

[0034] Hereinafter, a method for manufacturing a semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0035] (First Implementation)

[0036] In the semiconductor device manufacturing method according to the first embodiment, a plurality of chip regions are formed on a substrate to manufacture a semiconductor device. Sometimes, a semiconductor device is manufactured that forms wiring connecting the plurality of chip regions and functions as a large system. When manufacturing a semiconductor device in which multiple chip regions are connected as a system, if the entire system is defective due to the defect of one chip region, the manufacturing yield of the semiconductor device is likely to decrease.

[0037] For example, if the power lines connecting multiple chip areas experience leakage and / or short circuits, it is difficult to avoid overall system failure.

[0038] Therefore, in this embodiment, the objective is to: inspect each chip region of a substrate arranged in a planar direction, determine whether it is a qualified chip region or a defective chip region, and form wiring that is connected to the electrodes of the qualified chip regions but not to the electrodes of the defective chip regions, thereby improving the manufacturing yield of semiconductor devices.

[0039] Specifically, semiconductor device 1 can be like Figures 1A to 1D It was manufactured as shown. Figures 1A to 1D These are plan views and cross-sectional views illustrating a general method for manufacturing semiconductor device 1. Hereinafter, the direction perpendicular to the surface of substrate 2 will be designated as the Z direction, and the two directions orthogonal to each other in the plane perpendicular to the Z direction will be designated as the X direction and the Y direction. Figure 1A , Figure 1C This is an XY plan view showing an outline of the manufacturing method of semiconductor device 1. Figure 1B , Figure 1D This is a YZ cross-sectional view showing an outline of the manufacturing method of semiconductor device 1, showing the... Figure 1A , Figure 1C The cross-section obtained by cutting with lines AA and BB.

[0040] like Figure 1A As shown, in semiconductor device 1, multiple chip regions CR1 to CR3 are connected to function as a system. Semiconductor device 1 can be, for example, a system wafer incorporating multiple chip regions as a system, or a system chip incorporating multiple chip regions as a system. Each chip region CR1 to CR3 can have the same function.

[0041] In the manufacture of semiconductor device 1, a device structure 3 is formed on a substrate 2, and an electrode 4 is formed on the device structure 3. Then, as... Figure 1A , Figure 1B As shown, motion tests and other checks are performed. Then, each chip area is determined by CR as a qualified or unqualified chip area, and an inspection result containing the determination is generated. Figure 1A , Figure 1B The example illustrates the case where chip region CR2 is determined to be a defective chip region, while chip regions CR1 and CR3 are determined to be qualified chip regions.

[0042] After forming the through-hole conductor 5, as Figure 1C , Figure 1D As shown, the inspection results are fed forward, altering the routing method of the subsequent redistribution layer (RDL). For example, a redistribution layer RDL is formed comprising lines connecting to electrodes in acceptable chip regions but not to electrodes in unacceptable chip regions. Figure 1C , Figure 1D The diagram illustrates lines 7 and 8 connected to the electrodes 4 of the qualified chip regions CR1 and CR3, but not to the electrodes 4 of the unqualified chip region CR2. Viewed from the Z-direction, lines 7 and 8 are formed in patterns that pass through the electrodes 4 and through-hole conductors 5 of the qualified chip regions CR1 and CR3, respectively, and bypass the electrodes 4 and through-hole conductors 5 of the unqualified chip region CR2. Line 7 is, for example, a power line, and line 8 is, for example, a ground line.

[0043] More specifically, as a semiconductor device 1, it can be used Figure 2 The semiconductor manufacturing system 100 shown is as follows Figure 3 It was manufactured as shown. Figure 2 This is a diagram showing the configuration of a semiconductor manufacturing system 100. Figure 3 This is a flowchart illustrating a method for manufacturing semiconductor device 1.

[0044] The semiconductor manufacturing system 100 includes a transport system 101, a coating apparatus 102, an exposure apparatus 103, a developing apparatus 104, an etching apparatus 105, a film forming apparatus 106, an inspection apparatus 107, and a main controller 109. The transport system 101, coating apparatus 102, exposure apparatus 103, developing apparatus 104, exposure apparatus 105, etching apparatus 106, film forming apparatus 107, and inspection apparatus 108 are configured to transport substrates to each other via the transport system 101.

[0045] The main controller 109 is communicatively connected to the transport system 101, coating device 102, exposure device 103, developing device 104, exposure device 105, etching device 106, film forming device 107, and inspection device 108 via a communication line (not shown). The main controller 109 controls the transport system 101, coating device 102, exposure device 103, developing device 104, exposure device 105, etching device 106, film forming device 107, and inspection device 108 respectively.

[0046] Furthermore, exposure apparatus 103 is an exposure apparatus that uses a mask, while exposure apparatus 105 is a direct-drawing type exposure apparatus that does not use a mask. Exposure apparatus 103 illuminates the substrate with exposure light obtained by illuminating the mask, transferring the original pattern onto the substrate. Exposure apparatus 105 illuminates the substrate with exposure light according to the pattern data, drawing a pattern on the photosensitive material.

[0047] In the manufacturing method of semiconductor device 1, the following processes are repeatedly performed: film formation on substrate 2 using film forming apparatus 107, coating of photosensitive material using coating apparatus 102, formation of latent image pattern on photosensitive material using exposure apparatus 103 and 105, development of latent image pattern using developing apparatus 104, and film processing with respect to the developed photosensitive material pattern.

[0048] Therefore, as Figure 4A As shown, device structure 3 is formed in multiple chip regions CR1 to CR3. Figures 4A to 4C This is a cross-sectional view illustrating a method for manufacturing semiconductor device 1. The device structures 3 of each chip region CR1 to CR3 are, for example, those of a memory device, and may have identical structures. In each chip region CR1 to CR3, the device structure 3 includes a conductive pattern, and an electrode 4 is formed on its +Z side surface. The electrode 4 is electrically connected to the conductive pattern of the device structure 3. Additionally, a test electrode 4' (not shown) may be further formed. The test electrode 4' is electrically connected to the conductive pattern of the device structure 3.

[0049] The transport system 101 transports the substrate 2 to the inspection apparatus 108. The inspection apparatus 108 places the substrate 2 on its stage and inspects each chip region CR1 to CR3 (S1) on the substrate 2. When test electrodes 4' are formed, the inspection apparatus 108 contacts the detector with the electrodes 4' of each chip region CR1 to CR3, and supplies test signals to the device structure 3 via the detector and electrodes 4' to perform operational tests on the device structure 3. When test electrodes 4' are not formed, electrodes 4 can also be used as test electrodes. That is, the inspection apparatus 108 contacts the detector with the electrodes 4 of each chip region CR1 to CR3, and supplies test signals to the device structure 3 via the detector and electrodes 4 to perform operational tests on the device structure 3.

[0050] The main controller 109 obtains the inspection results from the inspection device 108. For example... Figure 4A As shown, the main controller 109, based on the inspection results, determines each chip region CR as a qualified or unqualified chip region, and generates and maintains inspection result information containing its determination. Figure 4A The example illustrates a scenario where the main controller 109 determines chip region CR2 as a defective chip region and chip regions CR1 and CR3 as acceptable chip regions. The main controller 109 has a storage unit that stores inspection result information in association with identifiers on the substrate 2. The inspection result information is obtained by associating the identification information of the chip region CR with information indicating whether it is a acceptable or unacceptable chip region. The inspection result information can be in tabular form. Alternatively, the inspection result information can be two-dimensional information such as a wafer map, obtained by associating information about the position of the chip region CR within the wafer with information indicating whether it is an acceptable or unacceptable chip region.

[0051] After inspection (S1) is completed, an interlayer insulating film 6i is formed (S2). The transport system 101 transports the substrate 2 from the inspection apparatus 108 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it applies an insulating material to the substrate 2. The insulating material is a solution to form the interlayer insulating film 6i, and can be formed from a positively photosensitive material or a negatively photosensitive material. Positively photosensitive materials include phenolic varnish resins, polyimide (PI) resins, rubber resins, acrylic resins, etc. Negatively photosensitive materials include phenolic varnish resins, polyimide (PI) resins, rubber resins, acrylic resins, etc. Thus, as... Figure 4B As shown, an interlayer insulating film 6i is formed covering the device structure 3 and electrodes 4 of each chip region CR1 to CR3.

[0052] Next, a pattern for the through-hole conductor 5 is formed (S3). The transport system 101 transports the substrate 2 from the coating apparatus 102 to the exposure apparatus 103.

[0053] In the exposure apparatus 103, the transported substrate 2 is placed on the substrate stage. The exposure apparatus 103 exposes the interlayer insulating film 6i above the substrate 2 through a mask MK0 for through-hole opening patterns. As a result, a latent image pattern corresponding to the mask data is formed on the interlayer insulating film 6i. The transport system 101 transports the exposed substrate 2 to the developing apparatus 104.

[0054] The developing apparatus 104 develops the latent pattern formed on the interlayer insulating film 6i, and then develops it onto the substrate 2 as shown in the image. Figure 4C The opening pattern 6i1 shown is formed on the interlayer insulating film 6. The opening pattern 6i1 is formed in each chip region CR1 to CR3, exposing the +Z side of the electrode 4 of the plurality of electrodes 4 in each chip region CR1 to CR3 that corresponds to the lines 7 and 8 to be formed. The transport system 101 transports the substrate 2 with the opening pattern 6i1 formed from the developing apparatus 104 to the film forming apparatus 107.

[0055] The film-forming apparatus 107 embeds a conductive material into the opening pattern 6i1 using methods such as CVD or deposition. The conductive material can be a material primarily composed of metals such as tungsten or copper. Thus, as... Figure 5A As shown, in each chip region CR1 to CR3, a through-hole conductor 5 is formed on the +Z side of electrode 4.

[0056] Next, a wiring pattern is formed (S4). Specifically, processes S41 to S47 are performed.

[0057] The transport system 101 transports the substrate 2 from the film forming apparatus 107 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it applies a photoresist 9i onto the substrate 2 (S41). The photoresist 9i forms in areas where wiring is not formed and is removed after wiring is formed. The photoresist 9i can be formed from a positively or negatively photosensitive material. Positively photosensitive materials include phenolic varnish resins, polyimide (PI) resins, rubber resins, acrylic resins, etc. Negatively photosensitive materials include phenolic varnish resins, polyimide (PI) resins, rubber resins, acrylic resins, etc.

[0058] In the exposure apparatus 103, the delivered substrate 2 is placed on the substrate stage. The exposure apparatus 103 acquires inspection result information of the substrate 2. The inspection result information can be obtained from the main controller 109 via a communication line, or it can be obtained by directly inputting it into the exposure apparatus 103. After identifying the chip area to be exposed among the multiple chip areas on the substrate 2, the exposure apparatus 103 refers to the inspection result information and determines whether the chip area to be exposed is a defective chip area (S42).

[0059] If the chip area to be exposed is a qualified chip area (S42 is "No"), the exposure apparatus 103 performs the following operations. If no mask is set on the mask stage, the exposure apparatus 103 sets the mask MK1 for the qualified chip area on the mask stage. If the mask MK1 is set on the mask stage, the exposure apparatus 103 maintains this state. If the mask MK2 is set on the mask stage, the exposure apparatus 103 retracts the mask MK2 from the mask stage and sets the mask MK1 on the mask stage. The exposure apparatus 103 exposes the resist 9i above the substrate 2 using the mask MK1 (S43). The exposure apparatus 103 illuminates the mask MK1 on the mask stage using an illumination optical system and projects the illumination light onto the substrate 2 on the substrate stage using a projection optical system, thus exposing the substrate 2. As a result, a latent image pattern corresponding to the mask data for the qualified chip area is formed on the resist 9i.

[0060] If the chip area to be exposed is a defective chip area (S42 is "Yes"), the exposure apparatus 103 performs the following operations. If no mask is set on the mask stage, the exposure apparatus 103 sets a mask MK2 for the defective chip area on the mask stage. If mask MK2 is set on the mask stage, the exposure apparatus 103 maintains this state. If mask MK1 is set on the mask stage, the exposure apparatus 103 retracts mask MK1 from the mask stage and sets mask MK2 on the mask stage. The exposure apparatus 103 exposes the resist 9i above the substrate 2 using mask MK2 (S44). The exposure apparatus 103 illuminates mask MK2 on the mask stage using an illumination optical system and projects the illumination light onto the substrate 2 on the substrate stage using a projection optical system, thus exposing the substrate 2. As a result, a latent image pattern corresponding to the mask data for the defective chip area is formed on the resist 9i.

[0061] After the exposure process in S43 or S44 is completed, the exposure apparatus 103 determines whether there are other chip areas to be exposed (S45). If there are other chip areas to be exposed (S45 is "yes"), the exposure apparatus 103 returns to S42. The exposure apparatus 103 then determines again whether the chip area to be exposed is a defective chip area (S42). That is, for each chip area, the exposure apparatus 103 performs exposure processing while switching between the mask MK1 for qualified chip areas and the mask MK2 for defective chip areas, based on the inspection result information.

[0062] For example, when the exposure target is the chip area CR1, a mask MK1 for a qualified chip area is used to form a photoresist 9i. Figures 6A to 6C The latent shadow patterns shown are LI71 and LI81. Figures 6A to 6C These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating the case where the chip region CR1 of the exposed object is a qualified chip region. Figure 6A This is an XY plan view, illustrating the latent image patterns LI71 and LI81 of the via conductor 5 passing through the chip region CR1 when viewed from the Z direction. Figure 6B Cut with CC line Figure 6A The YZ cross-sectional view obtained from the XY plan view shows the case where no latent pattern is formed in the region between multiple through-hole conductors 5. Figure 6C Cut using DD line Figure 6A The YZ cross-sectional view obtained from the XY plan view shows the case where a latent pattern LI81 is formed in the vicinity of the through-hole conductor 5.

[0063] When the exposure target is chip region CR2, a mask MK2 for defective chip regions is used to form a layer on resist 9i. Figures 7A to 7CThe latent patterns shown are LI72 and LI82. Figures 7A to 7C These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating a case where the chip region CR2 of the exposed object is a defective chip region. Figure 7A This is an XY plan view, illustrating the latent patterns LI72 and LI82 of the via conductor 5 that bypasses the chip region CR2 when viewed from the Z direction. Figure 7B Cut with EE line Figure 7A The YZ cross-sectional view obtained from the XY plane diagram shows the formation of a latent pattern LI82 in the region between multiple through-hole conductors 5. Figure 7C Sectioning with FF lines Figure 7A The YZ cross-sectional view obtained from the XY plane diagram shows the case where a latent pattern LI82 is formed in the vicinity of the via conductor 5.

[0064] When the exposed object is the chip area CR3, such as Figure 8C As shown, it forms on resist 9i Figure 8A The latent shadow patterns shown are LI71 and LI81. Figures 8A to 8C These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating the case where the chip region CR3 of the exposed object is a qualified chip region. Figure 8A This is an XY plan view, illustrating the latent image patterns LI71 and LI81 of the via conductor 5 passing through the chip region CR3 when viewed from the Z direction. Figure 8B Cut with GG line Figure 8A The YZ cross-sectional view obtained from the XY plan view shows the case where no latent pattern is formed in the region between multiple through-hole conductors 5. Figure 8C Cut with HH line Figure 8A The YZ cross-sectional view obtained from the XY plan view shows the case where a latent pattern LI81 is formed in the vicinity of the through-hole conductor 5.

[0065] If the exposure apparatus 103 determines that there are no other chip areas to be exposed (S45 is "No"), the transport system 101 transports the exposed substrate 2 to the developing apparatus 104. After the substrate 2 is transported, the developing apparatus 104 develops the substrate 2 (S46). The developing apparatus 104 develops the latent pattern formed in the resist 9i on the substrate 2. Thus, a substrate 2 with a groove pattern formed on the resist 9 is obtained.

[0066] For example, on substrate 2, a photoresist 9 is formed. Figures 9A to 9C The groove patterns shown are 9i71, 9i72, 9i81, and 9i82. Figures 9A to 9CThese are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating cases where chip region CR2 is a defective chip region and chip regions CR1 and CR3 are acceptable chip regions. Figure 9A This is an XY planar view showing the formation of groove patterns 9i72 and 9i82 on chip region CR2, and groove patterns 9i71 and 9i81 on chip regions CR1 and CR3. Groove patterns 9i72 and 9i82 are for defective chip regions; when viewed from the Z direction, they bypass the via conductor 5 of chip region CR2. Groove patterns 9i72 and 9i82 do not expose the +Z side of the via conductor 5 of chip region CR2. Groove patterns 9i71 and 9i81 are for acceptable chip regions; when viewed from the Z direction, they pass through the via conductor 5 of chip regions CR1 and CR3. Groove patterns 9i71 and 9i81 expose the +Z side of the via conductor 5 of chip regions CR1 and CR3. Figure 9B Sectioning with line II Figure 9A The YZ cross-sectional view obtained from the XY plan view shows the case where no groove pattern is formed in the region between multiple through-hole conductors 5. Figure 9C Cut with JJ line Figure 9A The YZ cross-sectional view obtained from the XY plan view shows the case where, for example, a groove pattern 9i81 is formed in the region near the through-hole conductor 5.

[0067] If development (S46) is completed, the transport system 101 will transport the substrate 2 with the grooved pattern from the developing apparatus 104 to the film forming apparatus 107.

[0068] The film-forming apparatus 107 performs a film-forming process (S47) by embedding a conductive material in the trench pattern using methods such as CVD or plating. The conductive material can also be a material whose main component is metal such as tungsten or copper. This allows the formation of a line that is positioned at a height corresponding to the upper end of the via conductor 5, passes through the via conductor 5 of the qualified chip regions CR among the multiple chip regions CR, and bypasses the via conductor 5 of the unqualified chip regions. In other words, wiring can be formed that connects to the electrodes 4 of the qualified chip regions CR among the multiple chip regions CR but not to the electrodes 4 of the unqualified chip regions CR. Therefore, in a semiconductor device 1 comprising multiple chip regions CR as a system, if a portion of the chip regions CR are unqualified chip regions, the semiconductor device 1 can be salvaged into a qualified product.

[0069] For example, forming on substrate 2 Figures 10A to 10C Lines 7 and 8 are shown. Figures 10A to 10C These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, with lines 7 and 8 illustrating cases where chip region CR2 is a defective chip region and chip regions CR1 and CR3 are acceptable chip regions. Figure 10AThis is an XY planar diagram illustrating lines 7 and 8 that bypass the via conductor 5 of chip region CR2 and pass through the via conductors 5 of chip regions CR1 and CR3 when viewed from the Z direction. Lines 7 and 8 do not contact the +Z side surface of the via conductor 5 of chip region CR2, but do contact the +Z side surface of the via conductors 5 of chip regions CR1 and CR3. Figure 10B Cut using KK line Figure 10A The YZ cross-sectional view obtained from the XY plan view shows the pattern of line 8 formed in the area between multiple via conductors 5 in the chip region CR2. Figure 10C Cut with LL line Figure 10A The YZ cross-sectional view obtained from the XY plan view shows the formation of line 8 in the vicinity of the via conductor 5 in the chip regions CR1 and CR3.

[0070] As described above, in the first embodiment, for a substrate 2 in which multiple chip regions CR are arranged in a planar direction, each chip region CR is inspected and determined to be a qualified chip region or a defective chip region. Wiring is then formed that connects to the electrodes 4 of the qualified chip regions CR but not to the electrodes 4 of the defective chip regions CR. For example, lines 7 and 8 are formed, positioned at a height corresponding to the upper end of the via conductor 5, extending through the via conductor 5 of the qualified chip regions and around the via conductor 5 of the defective chip regions. Therefore, in a semiconductor device 1 comprising multiple chip regions CR as a system, if a portion of the chip regions among the multiple chip regions CR are defective chip regions, the semiconductor device 1 can be salvaged into a qualified product. As a result, the manufacturing yield of the semiconductor device 1 can be improved.

[0071] Alternatively, the semiconductor device 1 manufactured by the manufacturing method of the first embodiment may also be... Figure 11 The system wafer WF is shown. Figure 11 This is a plan view showing the system wafer in a first variation of the first embodiment.

[0072] On the system wafer WF, multiple chip regions CR1 to CRn (n is any integer greater than 5) are arranged in the XY plane. Figure 11 The diagram illustrates a configuration where multiple chip regions CR1 to CRn are arranged in a matrix-like two-dimensional configuration. Each chip region CR can also be a chip region of a non-volatile memory such as NAND flash memory. In this case, the system wafer WF can be a wafer-level SSD where the entire wafer functions as an SSD (Solid State Drive) or its memory portion.

[0073] exist Figure 11The example illustrates the case where chip region CRk (where k is any integer greater than or equal to 3 and less than n) among multiple chip regions CR1 to CRn is determined to be a defective chip region, while chip regions CR1 to CR(k-1) and CR(k+1) to CRn are determined to be acceptable chip regions. The multiple chip regions CR1 to CRn are connected by a common line 7. Line 7 is a power line that extends through the power supply electrodes 4 of the acceptable chip regions CR1 to CR(k-1) and CR(k+1) to CRn and bypasses the power supply electrode 4 of the defective chip region CRk. Furthermore, the multiple chip regions CR1 to CRn are connected by a common line 8. Line 8 is a ground line that extends through the power supply electrodes 4 of the acceptable chip regions CR1 to CR(k-1) and CR(k+1) to CRn and bypasses the power supply electrode 4 of the defective chip region CRk. Therefore, in a semiconductor device 1 that includes multiple chip regions CR1 to CRn as a system, if a portion of the chip regions CR1 to CRn is a defective chip region, the semiconductor device 1 can be salvaged into a qualified product.

[0074] Alternatively, the semiconductor device 1 manufactured by the manufacturing method of the first embodiment may also be... Figure 12 The system chip CH shown is shown. Figure 12 This is a plan view showing the system chip CH in a second variation of the first embodiment.

[0075] In the system-on-a-chip (CH), multiple chip regions CR1 to CRn (where n is any integer greater than 5) are arranged in the XY plane. Figure 12 The diagram illustrates a configuration where multiple chip regions CR1 to CRn are arranged in the Y direction. Each chip region CR can also be a chip region of non-volatile memory such as NAND flash memory. In this case, the system chip CH can be an entire chip functioning as an SSD (Solid State Drive) or its memory portion as an on-chip SSD.

[0076] exist Figure 12The example illustrates a scenario where, among multiple chip regions CR1 to CRn, chip region CRk (where k is any integer greater than or equal to 3 and less than n) is determined to be a defective chip region, while chip regions CR1 to CR(k-1) and CR(k+1) to CRn are determined to be acceptable chip regions. The multiple chip regions CR1 to CRn are connected by a common line 7. Line 7 is a power line that extends through the power supply electrodes 4 of the acceptable chip regions CR1 to CR(k-1) and CR(k+1) to CRn, and bypasses the power supply electrode 4 of the defective chip region CRk. Furthermore, the multiple chip regions CR1 to CRn are connected by a common line 8. Line 8 is a ground line that extends through the power supply electrodes 4 of the acceptable chip regions CR1 to CR(k-1) and CR(k+1) to CRn, and bypasses the power supply electrode 4 of the defective chip region CRk. Therefore, in a semiconductor device 1 that includes multiple chip regions CR1 to CRn as a system, if a portion of the chip regions CR1 to CRn is a defective chip region, the semiconductor device 1 can be salvaged into a qualified product.

[0077] (Second Implementation)

[0078] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first embodiment.

[0079] In the first embodiment, a method is illustrated in which wiring is formed that is not connected to the electrodes of the defective chip region by forming lines that bypass the electrodes of the defective chip. In the second embodiment, a method is illustrated in which wiring is formed that is not connected to the electrodes of the defective chip region by not forming via conductors on the electrodes of the defective chip.

[0080] Specifically, semiconductor device 1 can be like Figures 13A to 13D It was manufactured as shown. Figures 13A to 13D These are plan views and cross-sectional views illustrating an outline of the manufacturing method of the semiconductor device 1 according to the second embodiment. Figure 13A , Figure 13C This is an XY plan view showing an outline of the manufacturing method of semiconductor device 1. Figure 13B , Figure 13D This is a YZ cross-sectional view showing an outline of the manufacturing method of semiconductor device 1, with sections cut using MM and NN lines respectively. Figure 13A , Figure 13C The resulting cross-section.

[0081] In the manufacture of semiconductor device 1, a device structure 3 is formed on a substrate 2, and an electrode 4 is formed on the device structure 3. Then, as... Figure 13A , Figure 13BAs shown, checks such as motion testing are performed, which is the same as in the first embodiment. Figure 13A , Figure 13B The example illustrates the case where chip region CR2 is determined to be a defective chip region, while chip regions CR1 and CR3 are determined to be acceptable chip regions.

[0082] like Figure 13C , Figure 13D As shown, the inspection results are fed forward, altering the layout of the via conductor 5 to be formed subsequently. For example, via conductor 5 is formed on the electrodes of qualified chip regions among multiple chip regions, but not on the electrodes of unqualified chip regions. Figure 13C , Figure 13D The illustration shows a layout where through-hole conductors 5 are formed on the electrodes 4 of the acceptable chip regions CR1 and CR3, but not on the electrodes 4 of the unacceptable chip region CR2. Consequently, lines 7 and 8 are then formed that pass through the electrodes 4 of each chip region CR1, CR2, and CR3 when viewed from the Z-direction, thus forming wiring where lines 7 and 8 are connected to the electrodes 4 of the acceptable chip regions CR1 and CR3 but not to the electrodes 4 of the unacceptable chip region CR2. Line 7 is, for example, a power line, and line 8 is, for example, a ground line.

[0083] More specifically, as a semiconductor device 1, it can be used Figure 2 The semiconductor manufacturing system 100 shown is as follows Figure 14 It was manufactured as shown. Figure 14 This is a flowchart illustrating a method for manufacturing semiconductor device 1.

[0084] The inspection is performed in the same manner as in the first embodiment (S1). After the inspection is completed, an interlayer insulating film 16i is formed using a positive photosensitive material (S12). The transport system 101 transports the substrate 2 from the inspection apparatus 108 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it applies the insulating material to the substrate 2. The insulating material is a solution to be formed into the interlayer insulating film 6i and can be formed from a positive photosensitive material. Positive photosensitive materials include phenolic varnish resins, polyimide (PI) resins, etc.

[0085] Therefore, as Figures 15A-15B As shown, an interlayer insulating film 16i is formed covering the device structure 3 and electrodes 4 of each chip region CR1 to CR3. Figures 15A-15B These are plan and cross-sectional views illustrating the manufacturing process of a semiconductor device. Figure 15A This is an XY plan view showing the formation of an interlayer insulating film 16i covering the device structure 3 and the electrode 4 in each chip region CR. Figure 15B Cut using OO line Figure 15AThe YZ cross-sectional view obtained from the XY plan view shows the case where the interlayer insulating film 16i covering the device structure 3 and the electrode 4 is formed in each chip region CR.

[0086] After the interlayer insulating film 16i is formed, the transport system 101 transports the substrate 2 from the coating apparatus 102 to the exposure apparatus 103.

[0087] Next, the pattern of the through-hole conductor 5 is formed (S13). Specifically, the processes S131 to S135 are performed.

[0088] The main controller 109 obtains layout data for the qualified chip area as layout data for the layer (i.e., interlayer insulating film 16i) of the processing target. The layout data for the qualified chip area includes the pattern of the via conductor 5 at the position corresponding to the electrode 4 of the qualified chip area, and does not include the pattern of the via conductor 5 at the position corresponding to the electrode 4 of the unqualified chip area.

[0089] In the exposure apparatus 103, the delivered substrate 2 is placed on the substrate stage. The exposure apparatus 103 acquires inspection result information of the substrate 2. The inspection result information can be obtained from the main controller 109 via a communication line, or it can be obtained by directly inputting it into the exposure apparatus 103. After identifying the chip area to be exposed among the multiple chip areas on the substrate 2, the exposure apparatus 103 refers to the inspection result information and determines whether the chip area to be exposed is a defective chip area (S131).

[0090] If the chip area to be exposed is a qualified chip area (S131 is "No"), the exposure apparatus 103 performs the following operations. If no mask is set on the mask stage, the exposure apparatus 103 sets a mask MK3 for the qualified chip area on the mask stage. If the mask MK3 is set on the mask stage, the exposure apparatus 103 maintains this state. The exposure apparatus 103 exposes the interlayer insulating film 16i above the substrate 2 using the mask MK3 (S132). The exposure apparatus 103 illuminates the mask MK3 on the mask stage using an illumination optical system, and projects the illumination light onto the substrate 2 on the substrate stage using a projection optical system, thus exposing the substrate 2. As a result, a latent image pattern corresponding to the mask data for the qualified chip area is formed on the interlayer insulating film 16i.

[0091] If the chip area to be exposed is a defective chip area (S131 is "Yes"), the exposure device 103 does not expose the chip area.

[0092] For example, when the exposure target is the chip region CR1, a mask MK3 for a qualified chip region is used to form a portion of the chip region CR1 in the interlayer insulating film 16i. Figure 16A , Figure 16BThe latent shadow patterns shown are LI171 and LI181. Figure 16A , Figure 16B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating the case where the chip region CR1 of the exposed object is a qualified chip region. Figure 16A This is an XY planar diagram illustrating the latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR1 when viewed from the Z direction. Figure 16B Cut with PP thread Figure 16A The YZ cross-sectional view obtained from the XY plan view shows the formation of the latent pattern LI181 on electrode 4 in chip region CR1.

[0093] When the exposure target is the chip area CR2, the exposure process is skipped, and no latent image pattern is formed.

[0094] When the exposure target is chip region CR3, an interlayer insulating film 16i is formed. Figure 16A The latent shadow patterns shown are LI171 and LI181. Figure 16A Examples of latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR3 when viewed from the Z direction are shown. Figure 16B The case of forming a latent pattern LI181 on electrode 4 in chip region CR3 is shown.

[0095] If the exposure apparatus 103 determines that there are other chip areas to be exposed (S133 is "Yes"), the process returns to S131. If the exposure apparatus 103 determines that there are no other chip areas to be exposed (S133 is "No"), the transport system 101 transports the exposed substrate 2 to the developing apparatus 104. After the substrate 2 is transported, the developing apparatus 104 develops the substrate 2 (S134). The developing apparatus 104 develops the latent pattern formed on the interlayer insulating film 16i of the substrate 2. Thus, a substrate 2 in which the hole pattern 161 is selectively formed in a portion of the qualified chip areas in the interlayer insulating film 16 is obtained.

[0096] For example, forming such in the interlayer insulating film 16 Figure 17A and 17B The hole pattern 161 shown is as shown. Figure 17A and Figure 17B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating cases where chip region CR2 is a defective chip region and chip regions CR1 and CR3 are acceptable chip regions. Figure 17A This is an XY plan view showing the case where a hole pattern 161 is formed that overlaps with the electrodes 4 of the chip regions CR1 and CR3, but not with the electrode 4 of the chip region CR2. Figure 17B Cut with QQ thread Figure 17A The YZ cross-sectional view obtained from the XY plan view shows the case where the hole pattern 161 is formed on the electrode 4 of the chip regions CR1 and CR3, but not on the electrode 4 of the chip region CR2.

[0097] After development (S134) is completed, the transport system 101 transports the substrate 2 with the hole pattern formed from the developing apparatus 104 to the film forming apparatus 107.

[0098] The film-forming apparatus 107 performs a film-forming process (S135) by embedding a conductive material into the hole pattern using methods such as CVD or deposition. The conductive material can also be a material whose main component is metal such as tungsten or copper. As a result, a through-hole conductor 5 can be formed that is positioned at a height corresponding to the upper end of the electrode 4 and overlaps with the electrode 4 of the qualified chip region CR among the multiple chip regions CR, without forming a through-hole conductor 5 that overlaps with the electrode 4 of the unqualified chip region.

[0099] For example, forming such on substrate 2 Figure 18A and 18B The through-hole conductor 5 is shown in the figure. Figure 18A and Figure 18B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating the via conductor 5 in cases where chip region CR2 is a defective chip region and chip regions CR1 and CR3 are acceptable chip regions. Figure 18A This is an XY plan view showing the case where a via conductor 5 is formed that does not overlap with the electrode 4 of the chip region CR2, but overlaps with the electrode 4 of the chip regions CR1 and CR3. Figure 18B Cut using RR lines Figure 18A The YZ cross-sectional view obtained from the XY plan view shows the case where a via conductor is not formed on the electrode 4 in chip region CR2, but a via conductor 5 is formed on the electrode 4 in chip regions CR1 and CR3.

[0100] Next, a wiring pattern is formed (S14). The transport system 101 transports the substrate 2 from the film forming apparatus 107 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it coats the substrate 2 with an insulating material containing a positively or negatively photosensitive material. After coating, the transport system 101 transports the substrate 2 from the coating apparatus 102 to the exposure apparatus 103. In the exposure apparatus 103, the transported substrate 2 is placed on the substrate stage, and the resist 9i above the substrate 2 is exposed using a mask MK1. As a result, a latent pattern corresponding to the mask data is formed on the resist 9i. After the exposure process is completed, the transport system 101 transports the exposed substrate 2 to the developing apparatus 104. After the substrate 2 is transported, the developing apparatus 104 develops the substrate 2. The developing apparatus 104 develops the latent pattern formed on the resist 9i on the substrate 2. As a result, a substrate 2 with a groove pattern formed on the resist 9i is obtained. When development is complete, the transport system 101 transports the substrate 2 with the grooved pattern formed from the developing apparatus 104 to the film forming apparatus 107. The film forming apparatus 107 performs a film forming process by embedding conductive material in the grooved pattern using CVD or plating methods.

[0101] Therefore, as Figure 13C , Figure 13D As shown, lines 7 and 8 can be formed at a height corresponding to the upper end of the via conductor 5 and passing above the electrodes 4 of each chip region CR. These lines 7 and 8 are connected to the electrodes 4 via the via conductor 5 in the qualified chip regions and insulated from the electrodes 4 via the interlayer insulating film 6 in the unqualified chip regions. That is, wiring can be formed that connects to the electrodes 4 of the qualified chip regions CR among the multiple chip regions CR but not to the electrodes 4 of the unqualified chip regions CR. Therefore, in a semiconductor device 1 containing multiple chip regions CR as a system, if some of the chip regions CR are unqualified chip regions, the semiconductor device 1 can be salvaged into a qualified product.

[0102] As described above, in the second embodiment, through-hole conductors 5 are formed on the electrodes 4 of the qualified chip region, but not on the electrodes 4 of the unqualified chip region. Furthermore, lines 7 and 8 are formed, positioned at a height corresponding to the upper end of the through-hole conductor 5 and extending through the through-hole conductor 5 of the qualified chip region. This allows for wiring that connects to the electrodes 4 of the qualified chip region CR but not to the electrodes 4 of the unqualified chip region CR.

[0103] (Third Implementation)

[0104] Next, a method for manufacturing a semiconductor device according to the third embodiment will be described. The following description will focus on the parts that differ from the first and second embodiments.

[0105] In the second embodiment, a method is illustrated in which a via conductor is not formed on the electrode of a defective chip when the interlayer insulating film is a positive photosensitive material. In the third embodiment, a method is illustrated in which a via conductor is not formed on the electrode of a defective chip when the interlayer insulating film is a negative photosensitive material.

[0106] Specifically, as a semiconductor device 1, it can be used Figure 2 The semiconductor manufacturing system 100 shown is as follows Figure 19 It was manufactured as shown. Figure 19 This is a flowchart illustrating a method for manufacturing semiconductor device 1.

[0107] The inspection is performed in the same manner as in the first embodiment (S1). After completion, an interlayer insulating film 16i is formed using a negative photosensitive material (S22). The transport system 101 transports the substrate 2 from the inspection apparatus 108 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it applies the insulating material onto the substrate 2. The insulating material is a solution to be formed into the interlayer insulating film 16i and can be formed from a negative photosensitive material. Negative photosensitive materials include rubber-based materials, acrylic resins, etc. Thus, an interlayer insulating film 16i covering the device structure 3 and the electrode 4 of each chip region CR1 to CR3 is formed.

[0108] When the interlayer insulating film 16i is formed, the transport system 101 transports the substrate 2 from the coating apparatus 102 to the exposure apparatus 103.

[0109] Next, the pattern of the through-hole conductor 5 is formed (S23). Specifically, the processes S231 to S236 are performed.

[0110] The main controller 109 obtains layout data for the qualified chip area as layout data for the layer (i.e., interlayer insulating film 16i) of the processing target. The layout data for the qualified chip area includes the pattern of the via conductor 5 at the position corresponding to the electrode 4 of the qualified chip area, and does not include the pattern of the via conductor 5 at the position corresponding to the electrode 4 of the unqualified chip area.

[0111] In the exposure apparatus 103, the delivered substrate 2 is placed on a substrate stage. If no mask is placed on the mask stage, the exposure apparatus 103 places a mask MK3 for the qualified chip area on the mask stage. If the mask MK3 is placed on the mask stage, the exposure apparatus 103 maintains this state. The exposure apparatus 103 exposes the interlayer insulating film 16i above the substrate 2 using the mask MK3 (S231). The exposure apparatus 103 illuminates the mask MK3 on the mask stage using an illumination optical system, and projects the illumination light onto the substrate 2 on the substrate stage using a projection optical system, thus exposing the substrate 2. As a result, a latent image pattern corresponding to the mask data for the qualified chip area is formed on the interlayer insulating film 16i.

[0112] The exposure apparatus 103 acquires the inspection result information of the substrate 2. The inspection result information can be obtained from the main controller 109 via a communication line, or it can be obtained by directly inputting it into the exposure apparatus 103. After determining the chip area to be exposed among the multiple chip areas of the substrate 2, the exposure apparatus 103 refers to the inspection result information to determine whether the chip area to be exposed is a defective chip area (S232).

[0113] If the chip area to be exposed is a defective chip area (S232 is "Yes"), the exposure apparatus 103 performs additional exposure on the chip area (S233). The exposure apparatus 103 places a mask blank on the mask stage. The exposure apparatus 103 exposes the interlayer insulating film 16i above the substrate 2 using the mask blank. The exposure apparatus 103 illuminates the mask MK3 on the mask stage using an illumination optical system, and projects the illumination light onto the substrate 2 on the substrate stage using a projection optical system, thus exposing the substrate 2. As a result, the defective chip area in the interlayer insulating film 16i is fully exposed, and the latent image pattern is eliminated.

[0114] If the chip area to be exposed is a qualified chip area (S232 is "No"), the exposure device 103 does not perform additional exposure on the chip area.

[0115] For example, when the exposure target is the chip region CR1, a mask MK3 for a qualified chip region is used to form a portion of the chip region CR1 in the interlayer insulating film 16i. Figure 20A , Figure 20B The latent shadow patterns shown are LI171 and LI181. Figure 20A , Figure 20B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device, illustrating the case where the chip region CR1 of the exposed object is a qualified chip region. Figure 20A This is an XY planar diagram illustrating the latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR1 when viewed from the Z direction. Figure 20B Sectioning with SS lines Figure 20A The YZ cross-sectional view obtained from the XY plan view shows the formation of the latent pattern LI181 on electrode 4 in chip region CR1.

[0116] And, as Figure 21A , Figure 21B As shown, no additional exposure will be applied. Figure 21A This is an XY planar diagram showing the maintenance of latent patterns LI171 and LI181 in chip region CR1. Figure 21B Cut with TT line Figure 21A The YZ cross-sectional view obtained from the XY plan view shows the case of the latent pattern LI181 on the electrode 4 that maintains the chip region CR1.

[0117] When the exposure target is chip region CR2, a qualified chip region mask MK3 is used to form a portion of chip region CR2 in the interlayer insulating film 16i. Figure 20A , Figure 20B The latent shadow patterns shown are LI171 and LI181. Figure 20A Examples of latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR2 when viewed from the Z direction are shown. Figure 20B The case of forming a latent pattern LI181 on electrode 4 in chip region CR2 is shown.

[0118] Then, as Figure 21A , Figure 21B As shown, additional exposure is performed. Figure 21A This shows the case where the chip region CR2 is fully exposed as an additional exposure, and the latent patterns LI171 and LI181 are eliminated. Figure 21B The image shows the case where the latent pattern LI181 on electrode 4 of chip region CR2 is eliminated.

[0119] When the exposure target is chip region CR3, a mask MK3 for qualified chip regions is used to form a portion of chip region CR1 in the interlayer insulating film 16i. Figure 20A , Figure 20B The latent shadow patterns shown are LI171 and LI181. Figure 20A Examples of latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR1 when viewed from the Z direction are shown. Figure 20B The case of forming a latent pattern LI181 on electrode 4 in chip region CR3 is shown.

[0120] Then, as Figure 21A , Figure 21B As shown, no additional exposure will be applied. Figure 21AThe case of maintaining latent patterns LI171 and LI181 in chip region CR3 is shown. Figure 21B The latent pattern LI181 on electrode 4 of chip region CR3 is shown to be maintained.

[0121] If the exposure apparatus 103 determines that there are other chip areas to be exposed (S234 is "Yes"), the process returns to S231. If the exposure apparatus 103 determines that there are no other chip areas to be exposed (S234 is "No"), the transport system 101 transports the exposed substrate 2 to the developing apparatus 104. After the substrate 2 is transported, the developing apparatus 104 develops the substrate 2 (S235). The developing apparatus 104 develops the latent pattern formed on the interlayer insulating film 16i of the substrate 2. Thus, a substrate 2 in which the hole pattern 161 is selectively formed in a portion of the qualified chip area of ​​the interlayer insulating film 16 is obtained.

[0122] When development (S235) is completed, the transport system 101 transports the substrate 2 with the hole pattern formed from the developing apparatus 104 to the film forming apparatus 107.

[0123] The film-forming apparatus 107 performs a film-forming process (S236) by embedding a conductive material into the hole pattern using methods such as CVD or deposition. The conductive material can also be a material whose main component is metal such as tungsten or copper. As a result, a through-hole conductor 5 can be formed that is positioned at a height corresponding to the upper end of the electrode 4 and overlaps with the electrode 4 of the qualified chip region CR among the multiple chip regions CR, without forming a through-hole conductor 5 that overlaps with the electrode 4 of the unqualified chip region.

[0124] Next, a wiring pattern is formed (S24). The transport system 101 transports the substrate 2 from the film forming apparatus 107 to the coating apparatus 102. After the coating apparatus 102 places the substrate 2 on its stage, it coats the substrate 2 with an insulating material containing a positively or negatively photosensitive material. After coating, the transport system 101 transports the substrate 2 from the coating apparatus 102 to the exposure apparatus 103. In the exposure apparatus 103, the transported substrate 2 is placed on the substrate stage, and the resist 9i above the substrate 2 is exposed using a mask MK1. As a result, a latent pattern corresponding to the mask data is formed on the resist 9i. After the exposure process is completed, the transport system 101 transports the exposed substrate 2 to the developing apparatus 104. After the substrate 2 is transported, the developing apparatus 104 develops the substrate 2. The developing apparatus 104 develops the latent pattern formed on the resist 9i of the substrate 2. As a result, a substrate 2 with a groove pattern formed on the resist 9i is obtained. After development is complete, the transport system 101 transports the substrate 2 with the grooved pattern formed from the developing apparatus 104 to the film forming apparatus 107. The film forming apparatus 107 performs a film forming process by embedding conductive material in the grooved pattern using CVD or plating methods.

[0125] Therefore, as Figure 13C , Figure 13D As shown, lines 7 and 8 can be formed at a height corresponding to the upper end of the via conductor 5 and passing above the electrodes 4 of each chip region CR. These lines 7 and 8 are connected to the electrodes 4 via the via conductor 5 in the qualified chip regions and insulated from the electrodes 4 via the interlayer insulating film 6 in the unqualified chip regions. That is, wiring can be formed that connects to the electrodes 4 of the qualified chip regions CR among the multiple chip regions CR but not to the electrodes 4 of the unqualified chip regions CR. Therefore, in a semiconductor device 1 containing multiple chip regions CR as a system, if some of the chip regions CR are unqualified chip regions, the semiconductor device 1 can be salvaged into a qualified product.

[0126] As described above, in the third embodiment, an interlayer insulating film is formed using a negative photosensitive material. Each chip region is exposed using a mask of a qualified chip region to form a latent pattern of a via pattern. Subsequently, unqualified chip regions are selectively additionally exposed to eliminate the latent pattern. Therefore, via conductors 5 can be formed on the electrodes 4 of qualified chip regions, while via conductors 5 are not formed on the electrodes 4 of unqualified chip regions.

[0127] in addition, Figure 19 The additional exposure (S233) shown can also be performed by partial exposure. In partial exposure, the latent image pattern to be eliminated is exposed locally. For example, partial exposure can be easily performed by using an exposure device (electron beam drawing device) 105 instead of an exposure device 103.

[0128] For example, when the object to be exposed is the chip region CR2, a mask MK3 for a qualified chip region is used to form a portion of the chip region CR2 in the interlayer insulating film 16i. Figure 20A , Figure 20B The latent shadow patterns shown are LI171 and LI181. Figure 20A Examples of latent image patterns LI171 and LI181 that overlap with electrode 4 of chip region CR2 when viewed from the Z direction are shown. Figure 20B The case of forming a latent pattern LI181 on electrode 4 in chip region CR2 is shown.

[0129] Then, as Figure 22A , Figure 22B As shown, additional exposure is achieved through partial exposure. Figure 22AThe diagram shows the case where, as additional exposure to the chip region CR2, the area corresponding to the latent patterns LI171 and LI181 (i.e., the portion of the chip region CR2 not exposed by the mask MK3) is partially exposed, and the latent patterns LI171 and LI181 are eliminated. Figure 22B The image shows the case where the latent pattern LI181 on electrode 4 of chip region CR2 is eliminated.

[0130] Therefore, through-hole conductors 5 can be formed on electrodes 4 in qualified chip areas, but not on electrodes 4 in unqualified chip areas.

[0131] (Other implementation methods)

[0132] (a) In the above embodiment, during the exposure of the interlayer insulating film 6i and the resist 9i, a pre-formed mask for a qualified chip area and a mask for forming a defective chip area are used. However, instead of these masks, an exposure apparatus 105 that can perform exposure even without a mask can be used to expose the interlayer insulating film 6i and the resist 9i.

[0133] For example, the exposure of the resist 9i of the first embodiment will be described.

[0134] Based on the inspection results, the main controller 109 controls the exposure device 105 so that pattern data above the via opening is used in the defective chip area CR2 of the chip areas CR1 to CR3, and pattern data above the via opening is used in the qualified chip areas CR1 and CR3.

[0135] When exposing the interlayer insulating film 6i of the second embodiment, the main controller 109 controls the exposure device 105 according to the inspection results, so that pattern data without opening vias is used in the defective chip area CR2 of the chip areas CR1 to CR3, and pattern data with opening vias is used in the qualified chip areas CR1 and CR3.

[0136] Thus, similar to the above-described embodiments, lines 7 and 8 can be formed that pass through pads in the qualified chip area but bypass pads in the unqualified chip area.

[0137] (b) In the first embodiment, resist 9 remains between lines 7 and 8, but this can also be substituted, such as... Figure 23 As shown, after the resist 9 is peeled off, an interlayer insulating film 10 is formed. At this point, it can also be done as follows: Figure 24As shown, an opening 10A is appropriately provided on the interlayer insulating film 10 to allow electrical contact with an external device. Furthermore, for line A, except for power line 7 and ground line 8, the defective chip can be bypassed. Line A is designated as a signal transmission line. In this case, since power line 7 and ground line 8 bypass the defective chip, the defective chip will not operate. Therefore, even if line A passes through the pads of the defective chip, the signal transmitted by line A will be minimally affected by the defective chip. However, signal line A can, of course, bypass the pads of the defective chip. For example, in the case of a short circuit between the pads connected to line A, if line A is connected to the pads of the defective chip, it will be affected. In this case, it is best to completely bypass the pads of the defective chip.

[0138] (c) Other electrode forming methods in the above embodiments will be described.

[0139] like Figure 25A As shown, for example in the first embodiment, after forming an opening in the interlayer insulating film 6i, a metal film 5A is formed on the interlayer insulating film 6i and the opening using a film forming apparatus 107. The metal film 5A is, for example, a Ti / Cu laminate. The metal film 5A has a thickness that does not completely cover the opening. Next, as... Figure 25B As shown, apply resist 9i. Then, as... Figure 25C As shown, similar to the first embodiment, the groove pattern is formed by exposure and development of areas for qualified chips and areas for unqualified chips. Next, as... Figure 25D As shown, for example, by Cu plating, plated wiring is formed in the tank. At this time, the opening is also buried by plating, forming a through-hole conductor 5. Next, as... Figure 25E As shown, after stripping the resist 9i, etching is performed to remove the metal film 5A from the portion where the plated wiring has not been formed. The etching can be wet or dry. Thus, similar to the first embodiment, lines 7 and 8 can be formed that pass through the pads in the qualified chip area but bypass the pads in the unqualified chip area.

[0140] (d) Other electrode forming methods in the above embodiments will be described.

[0141] In the above embodiments, such as Figure 26A As shown, a thick-film metal film 5A is formed. At this time, the opening of the insulating film 6i is also completely buried by the metal film 5A, becoming a through-hole conductor 5. Next, as... Figure 26B As shown, similar to the first embodiment, exposure and development are performed in areas of qualified chips and areas of unqualified chips to form a resist pattern 9 that passes through the pads of the qualified chip areas but avoids the pads of the unqualified chip areas (see reference). Figures 9A to 9C Next, as... Figure 26CAs shown, metal 5A is etched to remove resist 9. Thus, similar to the first embodiment, lines 7 and 8 can be formed that pass through pads in the qualified chip area but bypass pads in the unqualified chip area.

[0142] (e) In the above embodiments, the masks for the qualified chip area and the masks for the unqualified chip area are formed in advance outside the system 100. However, the masks for the qualified chip area and the masks for the unqualified chip area may also be formed online in the system 100, and the exposure of the first to third embodiments may be performed using the masks.

[0143] For example, if we take the first embodiment as an example for explanation, it will be described as follows.

[0144] In step S4, the main controller 109 acquires layout data for the qualified chip area and layout data for the unqualified chip area, as layout data for the layer (i.e., resist 9i) to be processed. The layout data for the qualified chip area includes a pattern of lines passing through the via conductor 5 of the qualified chip area. The layout data for the unqualified chip area includes a pattern of lines bypassing the via conductor 5 of the unqualified chip area.

[0145] The main controller 109 generates first mask data based on the layout data for the qualified chip area. The main controller 109 supplies the first mask data to the exposure apparatus 105.

[0146] Upon receiving the first mask data, the exposure apparatus 105 fabricates a mask MK1 based on the first mask data. The exposure apparatus 105 draws a pattern corresponding to the first mask data on a mask blank to fabricate the mask MK1. The fabricated mask MK1 can be set on the mask stage of the exposure apparatus 103 as a mask that can be used as a qualified chip area.

[0147] The main controller 109 generates second mask data based on the layout data for the defective chip area. The main controller 109 supplies the second mask data to the exposure apparatus 105.

[0148] Upon receiving the second mask data, the exposure apparatus 105 fabricates a mask MK2 based on the second mask data. The exposure apparatus 105 traces a pattern corresponding to the second mask data on a mask blank to fabricate the mask MK2. The fabricated mask MK2 can be placed on the mask stage of the exposure apparatus 103 in a state where it can be used as a mask for defective chip areas.

[0149] The wiring pattern of the first embodiment can also be processed using the masks MK1 and MK2 formed in this way.

[0150] While some embodiments of the invention have been described, these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: The step of inspecting each of the plurality of chip regions on a substrate arranged in a planar direction as a system, and determining the inspected chip region as a qualified chip region or a unqualified chip region. as well as The step of forming wiring that connects to the electrodes of qualified chip regions among the plurality of chip regions but not to the electrodes of unqualified chip regions. The steps for forming the wiring include: The steps of forming multiple via openings on the electrodes of the multiple chip regions; and The step of forming a line above the via opening, connecting the electrode through the via opening in the qualified chip area, and extending around the via opening in the unqualified chip area. The steps for forming the line include: The step of forming a resist covering the multiple through-hole openings; The step of exposing a qualified chip area with a first mask to form a first latent image pattern on the resist that passes over the via opening; The step of exposing the defective chip area with a second mask to form a second latent image pattern on the resist that bypasses the via opening; The steps of developing the first latent pattern and the second latent pattern to form a first groove pattern and a second groove pattern on the resist; and The step of embedding conductive material into the first groove pattern and the second groove pattern to form the line.

2. A method for manufacturing a semiconductor device, comprising: The step of inspecting each of the plurality of chip regions on a substrate arranged in a planar direction as a system, and determining the inspected chip region as a qualified chip region or a unqualified chip region. as well as The step of forming wiring that connects to the electrodes of qualified chip regions among the plurality of chip regions but not to the electrodes of unqualified chip regions. The steps for forming the wiring include: The steps of forming via conductors on electrodes in qualified chip regions among the plurality of chip regions, and not forming via conductors on electrodes in unqualified chip regions; and The step of forming a line that is positioned at a height corresponding to the upper end of the through-hole conductor and extends through the through-hole conductor. The steps of forming via conductors on electrodes in acceptable chip regions and not forming via conductors on electrodes in unacceptable chip regions include: The step of forming an insulating film covering the electrodes of the plurality of chip regions; The step of exposing a qualified chip area with a third mask to form a third latent image pattern that selectively covers the surface of the electrode; The step of not exposing areas of defective chips; The steps of developing the third latent pattern in the qualified chip area to form a hole pattern on the insulating film; and The step of embedding conductive material in the hole pattern to form a through-hole conductor on the electrode in the qualified chip area.

3. The method for manufacturing a semiconductor device according to claim 2, wherein, It also includes the step of forming a positive resist covering the insulating film. The step of forming the third latent pattern includes the step of forming the third latent pattern on the resist.

4. A method for manufacturing a semiconductor device, comprising: The step of inspecting each of the plurality of chip regions on a substrate arranged in a planar direction as a system, and determining the inspected chip region as a qualified chip region or a unqualified chip region. as well as The step of forming wiring that connects to the electrodes of qualified chip regions among the plurality of chip regions but not to the electrodes of unqualified chip regions. The steps for forming the wiring include: The steps of forming via conductors on electrodes in qualified chip regions among the plurality of chip regions, and not forming via conductors on electrodes in unqualified chip regions; and The step of forming a line that is positioned at a height corresponding to the upper end of the through-hole conductor and extends through the through-hole conductor. The steps of forming via conductors on electrodes in acceptable chip regions and not forming via conductors on electrodes in unacceptable chip regions include: The step of forming an insulating film covering the electrodes of the plurality of chip regions; The step of exposing each chip region with a third mask to form a third latent shadow pattern that selectively covers the area around the electrode; The step of exposing the defective chip area to eliminate the third latent image pattern; The steps of developing the third latent pattern in the qualified chip area to form vias on the insulating film; and The step of embedding a conductive material in the via and selectively forming via conductors on the electrodes in the qualified chip area.

5. The method for manufacturing a semiconductor device according to claim 4, wherein, It also includes the step of forming a negative resist covering the insulating film. The step of forming the third latent pattern includes the step of forming the third latent pattern on the resist.

6. The method for manufacturing a semiconductor device according to claim 4, wherein, The step of eliminating the third latent image pattern includes the step of fully exposing the defective chip area.

7. The method for manufacturing a semiconductor device according to claim 4, wherein, The step of eliminating the third latent image pattern includes a step of partially exposing the portion of the defective chip area that was not exposed by the third mask.

8. A semiconductor manufacturing system, comprising: An inspection device that inspects the function of each of the multiple chip regions on a substrate arranged in a planar direction as a system. An exposure device that exposes each of the plurality of chip regions with a mask corresponding to the inspection result of the inspection device; as well as The controller determines whether the chip area inspected by the inspection device is a qualified chip area or a defective chip area. When multiple via conductors are formed on the electrodes of the multiple chip regions, the exposure apparatus exposes the chip regions to be exposed using a first mask containing a pattern corresponding to a line extending through the via conductors of the qualified chip regions among the multiple chip regions, and a second mask containing a pattern corresponding to a line extending around the via conductors of the unqualified chip regions among the multiple chip regions.

9. A semiconductor manufacturing system, comprising: An inspection device that inspects the function of each of the multiple chip regions on a substrate arranged in a planar direction as a system. An exposure device that exposes each of the plurality of chip regions with a mask corresponding to the inspection result of the inspection device; as well as The controller determines whether the chip area inspected by the inspection device is a qualified chip area or a defective chip area. The exposure apparatus exposes the chip area to be exposed using a mask containing a pattern corresponding to a layout in which via conductors are formed on the electrodes of the qualified chip areas among the plurality of chip areas, but not on the electrodes of the unqualified chip areas. Then, it exposes the chip area to be exposed using a mask containing a pattern corresponding to lines extending through the via conductors of the qualified chip areas among the plurality of chip areas. The exposure apparatus performs exposure using the mask, forms the via conductor on each of the plurality of chip regions, fully exposes the defective chip regions in the plurality of chip regions, and eliminates the latent image pattern of the via conductor on the electrode of the defective chip region in the plurality of chip regions.

10. A semiconductor manufacturing system, comprising: An inspection device that inspects the function of each of the multiple chip regions on a substrate arranged in a planar direction as a system. An exposure device that exposes each of the plurality of chip regions with a mask corresponding to the inspection result of the inspection device; as well as The controller determines whether the chip area inspected by the inspection device is a qualified chip area or a defective chip area. The exposure apparatus exposes the chip area to be exposed using a mask containing a pattern corresponding to a layout in which via conductors are formed on the electrodes of the qualified chip areas among the plurality of chip areas, but not on the electrodes of the unqualified chip areas. Then, it exposes the chip area to be exposed using a mask containing a pattern corresponding to lines extending through the via conductors of the qualified chip areas among the plurality of chip areas. It also features a second exposure device that allows for exposure without the use of a mask. The exposure apparatus performs exposure using the mask to form the via conductor on each of the plurality of chip regions. The second exposure apparatus performs local exposure without using the mask to eliminate the latent pattern of the via conductor on the electrode of the defective chip region in the plurality of chip regions.

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