形成半导体装置的方法
By using atomic layer deposition (ALD) processes and pre-fabrication methods to purify the gas pipeline of the deposition system, the problem of reducing the width of adjacent features in lithography technology has been solved, achieving high feature density and precision in semiconductor devices and improving integrated circuit performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2022-03-30
- Publication Date
- 2026-07-17
AI Technical Summary
Existing lithography techniques have difficulty effectively reducing the width between adjacent features when forming semiconductor devices, thus limiting the improvement of feature density in integrated circuits.
The atomic layer deposition (ALD) process is employed, which involves multiple cycles of precursor and inert gas treatment, combined with pre-manufacturing methods to purify the gas pipelines of the deposition system, ensuring uniform deposition of the material layer, reducing defects, and improving the control precision of the material layer thickness.
This achieves higher feature density, improves the manufacturing precision and reliability of semiconductor devices, reduces variations in material layer thickness, and enhances the performance of integrated circuits.
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Figure CN115050693B_ABST