Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a preparation method. The preparation method comprises: providing a substrate; forming a bit line contact structure and a bit line on the substrate; the bit line contact structure is located between the bit line and the substrate; performing ion doping treatment on the sidewall of the lower part of the bit line contact structure to form a doped region; performing nitriding treatment on the doped region to convert the doped region into a nitrided structure. For the problem of easy occurrence of the inclination angle of the lower part of the bit line contact structure, ion doping treatment is adopted to form a doped region on the sidewall of the lower part of the bit line contact structure. In the subsequent nitriding treatment, the bit line contact structure of the doped region is easy to be nitrided, and the bit line contact structure outside the doped region is not easy to be nitrided. In this way, the bit line contact structure can be selectively trimmed, the lower inclination angle of the bit line contact structure can be eliminated, the consistency of the bit line width can be improved, and thus a basis for the reduction of the bit line width can be provided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, reducing linewidth is crucial for minimizing the size of semiconductor devices. For example, in Dynamic Random Access Memory (DRAM), reducing bitline width provides a richer design foundation and reduces the DRAM's design size. In traditional bitline fabrication, the lower sidewalls of the bitline contact structure tend to have a certain tilt angle, leading to an increase in the width of the lower part of the bitline contact structure, which in turn restricts the reduction of bitline width. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems mentioned above in the background art, so as to eliminate the tilt angle of the lower sidewall of the bit line contact structure and provide a basis for reducing the bit line width.

[0004] To address the aforementioned technical problems, a first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0005] Provide substrate;

[0006] A bit line contact structure and a bit line are formed on the substrate; the bit line contact structure is located between the bit line and the substrate.

[0007] The lower sidewall of the bit line contact structure is subjected to ion doping treatment to form a doped region;

[0008] The doped region is subjected to nitriding treatment to transform the doped region into a nitrided structure.

[0009] In one embodiment, the ion dose of the ion doping treatment is 10. 4 cm -2 ~10 5 cm -2 .

[0010] In one embodiment, the ions used in the ion doping treatment include ions of Group V main elements.

[0011] In one embodiment, the ions used in the ion doping treatment include at least one of arsenic ions and phosphorus ions.

[0012] In one embodiment, after nitriding the doped region, the process further includes:

[0013] The semiconductor structure obtained after nitriding is then subjected to annealing.

[0014] In one embodiment, the annealing temperature is 550°C to 650°C.

[0015] In one embodiment, the annealing process takes 50 to 70 minutes.

[0016] In one embodiment, prior to nitriding the doped region, the method further includes:

[0017] The doped region is subjected to rapid thermal treatment.

[0018] In one embodiment, the nitriding treatment of the doped region includes:

[0019] The doped region is nitrided using a nitrogen reaction; or,

[0020] A silicon nitride layer is formed on the surface of the doped region to nitride the doped region.

[0021] In one embodiment, forming the bit line contact structure and bit line on the substrate includes:

[0022] Bit line contact holes are formed within the substrate;

[0023] A bit line contact material layer is formed inside the bit line contact hole;

[0024] A bit line material layer is formed on the upper surface of the bit line contact material layer;

[0025] The bit line contact material layer and the bit line material layer are etched to obtain the bit line contact structure and the bit line.

[0026] In one embodiment, after nitriding the doped region, the process further includes:

[0027] A first dielectric layer is formed on the nitrided bit line contact structure and the surface of the bit line;

[0028] A second dielectric layer is formed on the surface of the first dielectric layer; wherein the first dielectric layer and the second dielectric layer fill the bit line contact hole.

[0029] In one embodiment, before forming the bit line contact structure and bit line on the substrate, the method further includes:

[0030] A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolating a plurality of spaced active regions in the substrate; the bit line extends along a first direction, the active regions extend along a second direction, and the first direction and the second direction intersect.

[0031] In one embodiment, the bit line includes a first bit line conductive layer, a second bit line conductive layer, and a bit line protective layer stacked sequentially from bottom to top.

[0032] In one embodiment, the material of the first bit line conductive layer includes titanium nitride.

[0033] In one embodiment, the material of the second bit line conductive layer includes tungsten.

[0034] In one embodiment, the bit line protection layer is made of silicon nitride.

[0035] A semiconductor structure is prepared according to the semiconductor structure preparation method described in any of the above embodiments; the semiconductor structure comprises:

[0036] Substrate;

[0037] Bit line contact structure, located on the surface of the substrate and in contact with the substrate;

[0038] A nitrided structure is located on the sidewall of the lower part of the bit line contact structure and is in contact with the substrate;

[0039] Bit lines are located on the bit line contact structure.

[0040] In one embodiment, the semiconductor structure includes:

[0041] A first dielectric layer covers the surface of the bit line contact structure, the nitrided structure, and the bit line;

[0042] A second dielectric layer covers the surface of the first dielectric layer.

[0043] This disclosure provides a method for fabricating a semiconductor structure, primarily by performing ion doping and nitriding treatments on the lower sidewalls of the bit line contact structure to refine them. Specifically, to address the issue of tilt angles easily occurring on the lower sidewalls of the bit line contact structure, ion doping is employed to form a doped region on the lower sidewalls. During subsequent nitriding, the bit line contact structure within the doped region is easily nitrided, while the bit line contact structure outside the doped region is less likely to be nitrided. This allows for selective refining of the bit line contact structure, eliminating the lower tilt angle, improving the consistency of the bit line width, and thus providing a basis for reducing the bit line width. Attached Figure Description

[0044] To better describe and illustrate the disclosed embodiments and / or examples herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosures, the currently described embodiments and / or examples, or the best mode of these disclosures as currently understood.

[0045] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figures 2-9 A schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0047] Figure 10 This is a flowchart of a method for fabricating a semiconductor structure provided in another embodiment of this disclosure.

[0048] Explanation of markings in the diagram:

[0049] 100, Substrate; 101, Bit line contact hole; 102, Active region; 103, Shallow trench isolation structure; 200, Bit line contact structure; 201, Doped region; 202, Nitride structure; 300, Bit line; 301, First bit line conductive layer; 302, Second bit line conductive layer; 303, Bit line protection layer; 400, First dielectric layer; 500, Second dielectric layer; 600, Third dielectric layer. Detailed Implementation

[0050] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this disclosure. Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0056] In one embodiment of this disclosure, such as Figure 1 As shown, a method for fabricating a semiconductor structure is provided, comprising:

[0057] Step S10: Provide a substrate.

[0058] Step S20: Form a bit line contact structure and a bit line on the substrate; the bit line contact structure is located between the bit line and the substrate.

[0059] Step S30: Perform ion doping on the lower sidewall of the position line contact structure to form a doped region.

[0060] Step S40: Nitride the doped region to convert it into a nitrided structure.

[0061] In the semiconductor structure fabrication method of this embodiment, the lower sidewalls of the bit line contact structure are mainly trimmed by performing ion doping and nitriding treatments. Specifically, during the fabrication of the bit line contact structure, when using traditional methods such as etching, a certain tilt angle easily appears on the lower sidewalls of the bit line contact structure. The presence of this tilt angle leads to an increase in the width of the lower part of the bit line contact structure, which in turn restricts further reduction of the bit line width and affects the conductivity of the bit line. In the embodiments of this disclosure, to address the problem of the tilt angle easily appearing on the lower sidewalls of the bit line contact structure, ion doping treatment is used to form a doped region on the lower sidewalls of the bit line contact structure. During the subsequent nitriding treatment, the bit line contact structure in the doped region is easily nitrided, while the bit line contact structure outside the doped region is not easily nitrided. This allows for selective trimming of the bit line contact structure, eliminating the lower tilt angle of the bit line contact structure, improving the consistency of the bit line width, and thus providing a basis for reducing the bit line width.

[0062] Please see Figure 1 In some embodiments of this disclosure, the substrate provided in step S10 may be formed from a semiconductor substrate such as a silicon wafer. The substrate material includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate includes, but is not limited to, monocrystalline silicon substrates, polycrystalline silicon substrates, or amorphous silicon substrates.

[0063] Please see Figure 1 and Figure 2 In some embodiments of this disclosure, step S20, as an example of forming a bit line contact structure 200 and a bit line 300 on a substrate 100, includes: forming a bit line contact hole 101 in the substrate 100, forming a bit line contact material layer in the bit line contact hole 101, forming a bit line material layer on the upper surface of the bit line contact material layer; etching the bit line contact material layer and the bit line material layer to obtain the bit line contact structure 200 and the bit line 300, such as... Figure 2 As shown. It is understood that the bit line contact material layer may include, but is not limited to, a doped polysilicon layer. Optionally, when forming the bit line contact material layer within the bit line contact hole 101, a deposition process can be used. For example, bit line contact material is deposited within the bit line contact hole 101 using a deposition process to form the bit line contact material layer. When performing the bit line contact material deposition process, the deposition process may include, but is not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Optionally, when forming the bit line material layer on the upper surface of the bit line contact material layer, a deposition process can be used. For example, bit line 300 material is deposited on the upper surface of the bit line contact material layer using a deposition process to form the bit line material layer. When performing the bit line 300 material deposition process, the deposition process may include, but is not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Alternatively, the etching of the bit line contact material layer and the bit line material layer can be performed using either a dry etching process or a wet etching process. When using dry etching, ion milling, plasma etching, or reactive ion etching can be employed. In one specific embodiment, gas plasma is used for dry etching. For example, a reactive etching gas is selected for etching during dry etching; the reactive etching gas could be Cl2, CF4, etc. When using wet etching, the etching solution can be nitric acid, ammonium fluoride, hydrofluoric acid, ethylenediamine, sodium carbonate, etc. In one specific embodiment, the etching solution includes ammonium fluoride and hydrofluoric acid.

[0064] Please continue reading. Figure 2The bit line 300 includes a first bit line conductive layer 301, a second bit line conductive layer 302, and a bit line protective layer 303 stacked sequentially from bottom to top. The bit line contact structure 200 is located between the first bit line conductive layer 301 and the substrate 100. As an example of the material selection for the first bit line conductive layer 301, the material includes, but is not limited to, titanium nitride, tungsten, or titanium tungsten. As an example of the material selection for the second bit line conductive layer 302, the material includes, but is not limited to, tungsten, titanium tungsten, or titanium nitride. As an example of the material selection for the bit line protective layer 303, the material includes, but is not limited to, silicon nitride, silicon oxynitride, or silicon dioxide. In a specific example, the materials of the first bit line conductive layer 301, the second bit line conductive layer 302, and the bit line protective layer 303 are titanium nitride, tungsten, and titanium nitride, respectively.

[0065] Please continue reading. Figure 2 When the bit line 300 includes a first bit line conductive layer 301, a second bit line conductive layer 302, and a bit line protective layer 303 stacked sequentially from bottom to top, forming a bit line material layer on the upper surface of the bit line contact material layer includes: sequentially forming a first bit line conductive material layer, a second bit line conductive material layer, and a bit line protective material layer on the upper surface of the bit line contact material layer. Optionally, the sequential formation of the first bit line conductive material layer, the second bit line conductive material layer, and the bit line protective material layer on the upper surface of the bit line contact material layer can be performed using a deposition process. That is, the first bit line conductive material layer, the second bit line conductive material layer, and the bit line protective material layer are sequentially formed on the upper surface of the bit line contact material layer through a deposition process. Alternatively, the deposition process can be a chemical vapor deposition process. Understandably, after the first bit line conductive material layer, the second bit line conductive material layer, and the bit line protective material layer are sequentially formed on the upper surface of the bit line contact material layer through a deposition process, the first bit line conductive material layer, the second bit line conductive material layer, and the bit line protective material layer are etched to obtain the first bit line conductive layer 301, the second bit line conductive layer 302, and the bit line protective layer 303 that are sequentially stacked from bottom to top.

[0066] Optionally, the bit line 300 includes a first bit line conductive layer 301, a second bit line conductive layer 302, and a bit line protective layer 303 stacked sequentially from bottom to top. Forming the bit line contact structure 200 and the bit line 300 on the substrate 100 includes: forming a bit line contact hole 101 in the substrate 100, forming a bit line contact material layer in the bit line contact hole 101, and sequentially forming a first bit line conductive material layer, a second bit line conductive material layer, and a bit line protective material layer on the upper surface of the bit line contact material layer; etching the bit line contact material layer, the first bit line conductive material layer, the second bit line conductive material layer, and the bit line protective material layer to obtain the bit line contact structure 200 and the bit line 300.

[0067] Please see Figure 1 , Figure 3 and Figure 4 ,in Figure 4 for Figure 3 A top view of the corresponding semiconductor structure. In some embodiments of this disclosure, in step S30, the lower sidewalls of the bit line contact structure 200 are subjected to ion doping to form a doped region 201, such as... Figure 3 and Figure 4 As shown. Through ion doping, a doped region 201 can be formed on the lower sidewall of the bit line contact structure 200. This region serves as the target for nitriding. During nitriding, the doped region 201 on the lower sidewall of the bit line contact structure 200 can be consumed. The bit line contact structure 200 outside the doped region 201 is not easily consumed by nitriding. This can effectively remove the tilt angle of the lower sidewall of the bit line contact structure 200, improve the uniformity of the width of the bit line contact structure 200, and thus provide a basis for reducing the linewidth of the bit line 300.

[0068] In some embodiments of this disclosure, the height of the doped region 201 formed on the lower sidewall of the bit line contact structure 200 in the direction perpendicular to the substrate surface is less than one-third of the height of the bit line contact structure 200 in the direction perpendicular to the substrate surface. Optionally, in other embodiments, the height of the doped region 201 formed on the lower sidewall of the bit line contact structure 200 in the direction perpendicular to the substrate surface is less than one-quarter of the height of the bit line contact structure 200 in the direction perpendicular to the substrate surface. Optionally, in other embodiments, the height of the doped region 201 formed on the lower sidewall of the bit line contact structure 200 in the direction perpendicular to the substrate surface is less than one-fifth of the height of the bit line contact structure 200 in the direction perpendicular to the substrate surface.

[0069] Please continue reading. Figure 3 and Figure 4 In some embodiments of this disclosure, on one hand, the ion dose of the ion doping treatment is 10. 4 cm -2 ~10 5 cm -2 For example, the ion dose for ion doping treatment can be 2 × 10⁻⁶. 4 cm -2 4×10 4 cm -2 5×10 4 cm -2 7×10 4 cm -2 8×10 4 cm -2 Of course, the ion dose for ion doping can also be less than 10. 4 cm -2 or greater than 10 5cm -2 Other suitable selections can be made within the range. On the other hand, the doping depth of ion doping is 10 nm to 20 nm. For example, the doping depth of ion doping can be 11 nm, 12 nm, 14 nm, 16 nm, or 18 nm. Of course, other suitable selections can also be made within the range of less than 10 nm or greater than 20 nm.

[0070] Optionally, as an example of ion doping, an ion implantation process, such as remote plasma technology, can be used to implant ions into the lower sidewalls of the bit line contact structure 200, thereby forming a doped region 201 on the lower sidewalls of the bit line contact structure 200. When implanting ions using the ion implantation process, the ion implantation angle is perpendicular to the substrate surface to avoid nitriding the vertical sidewalls of the bit line contact structure, thus maintaining the vertical morphology of the bit line contact structure and the bit lines. Furthermore, depending on the doping process requirements, one or more ion implantations can be performed to ensure that the implanted ions meet the requirements for ion doping in terms of depth and concentration.

[0071] In some embodiments of this disclosure, the ions used in the ion doping treatment include ions of Group V elements. Optionally, the ions used in the ion doping treatment include at least one of arsenic ions and phosphorus ions.

[0072] Please see Figure 1 and Figure 5 In some embodiments of this disclosure, in step S40, the doped region 201 is nitrided to transform the doped region 201 into a nitrided structure 202, such as... Figure 5 As shown. Nitriding treatment can be used to nitride the bit line contact structure 200 of the doped region 201, removing the tilt angle of the lower sidewall of the bit line contact structure 200. Optionally, nitriding the doped region 201 includes: nitriding the doped region 201 using nitrogen gas reaction; or forming a silicon nitride layer on the surface of the doped region 201.

[0073] In some embodiments of this disclosure, the doped region 201 can be nitrided using a plasma nitrogen doping process to transform it into a nitrided structure 202. For example, in a nitrogen-containing atmosphere of 0.1 to 10 Torr, a DC voltage is applied to ionize nitrogen gas, and then the ionized nitrogen-containing gas is sputtered onto the surface of the doped region 201.

[0074] In some embodiments of this disclosure, after nitriding the doped region 201, the process further includes annealing the semiconductor structure obtained after nitriding. Annealing can make the nitriding effect more complete, promote the consumption of the bit line contact structure 200 in the doped region 201, and improve the top-to-bottom collimation of the bit line contact structure 200.

[0075] Optionally, as an example of selecting the annealing temperature, the annealing temperature is 550℃ to 650℃. For example, the annealing temperature can be selected from 550℃, 580℃, 600℃, 630℃, and 640℃. Of course, other suitable selections can also be made within the range of below 550℃ or above 650℃.

[0076] Optionally, as an example of selecting the annealing time, the annealing time is 50 min to 70 min. For example, the annealing time can be selected from 50 min, 55 min, 60 min, 65 min, and 70 min. Of course, other suitable selections can also be made within the range of less than 50 min or greater than 70 min.

[0077] In some embodiments of this disclosure, prior to nitriding the doped region 201, the process further includes: performing rapid thermal treatment on the doped region 201. Rapid thermal treatment can activate the dopant ions in the doped region 201, making it easier for the doped region 201 to be nitrided, which helps reduce the difficulty of the nitriding process and improves its efficiency.

[0078] Optionally, as an example of selecting conditions for rapid thermal processing, the temperature for rapid thermal processing is 800℃ to 1200℃, and the heating rate for rapid thermal processing is 10℃ / s to 100℃ / s. In this case, when performing rapid thermal processing on the doped region 201, the doped semiconductor structure is heated from the initial temperature to 800℃ to 1200℃ at a heating rate of 10℃ / s to 100℃ / s. Further optionally, the temperature for rapid thermal processing can be, but is not limited to, 850℃, 900℃, 1000℃, 1050℃, or 1150℃. The heating rate for rapid thermal processing can be, but is not limited to, 20℃ / s, 30℃ / s, 50℃ / s, 60℃ / s, or 90℃ / s. Of course, the temperature for rapid thermal processing can also be other suitable selections within the range below 800℃ or above 1200℃. The heating rate for rapid thermal processing can also be other suitable selections within the range below 10℃ / s or above 100℃ / s. Optionally, during rapid thermal processing, the initial temperature of the doped semiconductor structure can be room temperature. That is, during rapid thermal processing, the doped semiconductor structure is heated from room temperature to 800℃ to 1200℃ at a heating rate of 10℃ / s to 100℃ / s. Optionally still, the processing time for rapid thermal processing at the 800℃ to 1200℃ temperature is in the millisecond range.

[0079] In some embodiments of this disclosure, the doped region 201 is transformed into a nitrided structure 202 comprising nitrogen-doped polycrystalline silicon.

[0080] Please see Figures 6-7In some embodiments of this disclosure, after nitriding the doped region 201, the process further includes: forming a first dielectric layer 400 on the surface of the nitrided bit line contact structure 200 and bit line 300; and forming a second dielectric layer 500 on the surface of the first dielectric layer 400; wherein the first dielectric layer 400 and the second dielectric layer 500 fill the bit line contact hole 101. After nitriding, the bit line contact structure 200 of the doped region 201 is consumed, and the first dielectric layer 400 is formed on the surface of the nitrided bit line contact structure 200 and bit line 300, such as... Figure 6 As shown. A second dielectric layer 500 is formed on the surface of the first dielectric layer 400, as... Figure 7 As shown. Optionally, the material of the first dielectric layer 400 may include, but is not limited to, silicon oxide or silicon nitride, and the material of the second dielectric layer 500 may include, but is not limited to, silicon oxide or silicon nitride. It is understood that the first dielectric layer 400 is formed on the surface of the bit line contact structure 200 and the bit line 300 after nitriding; the formation of the second dielectric layer 500 on the surface of the first dielectric layer 400 can be performed using deposition processes respectively.

[0081] Please see Figure 8 After forming the second dielectric layer 500 on the surface of the first dielectric layer 400, the method further includes forming a third dielectric layer 600 on the surface of the second dielectric layer 500, such as... Figure 8 As shown. Optionally, the material of the third dielectric layer 600 may include, but is not limited to, silicon oxide or silicon nitride. It is understood that the formation of the third dielectric layer 600 on the surface of the second dielectric layer 500 may be performed using a deposition process.

[0082] In some embodiments of this disclosure, the first dielectric layer 400 is made of silicon nitride, the second dielectric layer 500 is made of silicon oxide, and the third dielectric layer 600 is made of silicon nitride. In this case, the first dielectric layer 400-the second dielectric layer 500-the third dielectric layer 600 is a silicon nitride-silicon oxide-silicon nitride structure, i.e., a "NON" sandwich structure.

[0083] In some other embodiments of this disclosure, the first dielectric layer 400 is made of silicon oxide, the second dielectric layer 500 is made of silicon nitride, and the third dielectric layer 600 is made of silicon oxide. In this case, the first dielectric layer 400-the second dielectric layer 500-the third dielectric layer 600 is a silicon oxide-silicon nitride-silicon oxide structure, i.e., an "ONO" sandwich structure.

[0084] Please see Figure 9 In some embodiments of this disclosure, when the material of the first dielectric layer 400 is silicon nitride, the nitride structure 202 can be incorporated into the first dielectric layer 400.

[0085] Please see Figure 10In some embodiments of this disclosure, the method for fabricating the semiconductor structure includes:

[0086] Step S100: Provide substrate 100;

[0087] Step S200: A bit line contact structure 200 and a bit line 300 are formed on the substrate 100; the bit line contact structure 200 is located between the bit line 300 and the substrate 100.

[0088] Step S300: Ion doping is performed on the lower sidewall of the position line contact structure 200 to form a doped region 201;

[0089] Step S400: Perform rapid heat treatment on the doped region 201;

[0090] Step S500: Nitride the doped region 201 to transform it into a nitrided structure 202;

[0091] Step S600: Anneal the semiconductor structure obtained after nitriding treatment;

[0092] Step S700: A first dielectric layer 400 is formed on the surface of the bit line contact structure 200 and bit line 300 after annealing; a second dielectric layer 500 is formed on the surface of the first dielectric layer 400.

[0093] Step S800: A third dielectric layer 600 is formed on the surface of the second dielectric layer 500.

[0094] In some embodiments of this disclosure, before forming the bit line contact structure 200 and bit line 300 on the substrate 100, the method further includes: forming a shallow trench isolation structure 102 within the substrate 100, wherein the shallow trench isolation structure 102 isolates a plurality of spaced active regions 103 within the substrate 100; the bit line 300 extends along a first direction, and the active regions 103 extend along a second direction, wherein the first direction and the second direction intersect. Optionally, the first direction and the second direction may intersect obliquely or perpendicularly.

[0095] The positions of the shallow trench isolation structure 102 and the active region 103 can be found in the reference. Figures 2-9Optionally, when forming the shallow trench isolation structure 102 within the substrate 100, etching can be used. Specifically, when forming the shallow trench isolation structure 102 within the substrate 100, either dry etching or wet etching can be used. When dry etching is used, ion milling, plasma etching, or reactive ion etching can be employed. In a specific embodiment, gas plasma is used for dry etching. For example, a reactive etching gas is selected for etching during dry etching; the reactive etching gas can be Cl2, CF4, etc. When wet etching is used, the etching solution can be nitric acid, ammonium fluoride, hydrofluoric acid, ethylenediamine, sodium carbonate, etc. In a specific embodiment, the etching solution includes ammonium fluoride and hydrofluoric acid.

[0096] Examples of the extension directions of bit line 300 and active region 103 can be found in [reference needed]. Figure 4 ,exist Figure 4 In the illustrated embodiment, bit line 300 extends along a first direction, and active region 103 extends along a second direction, with the first and second directions intersecting obliquely. It is understood that in this embodiment, the oblique intersection of the first and second directions indicates that the angle formed between the first and second directions is an acute angle. It is understood that an acute angle generally refers to an angle greater than 0° and less than 90°. Optionally, the angle formed between the first and second directions can also be an obtuse angle. It is understood that an obtuse angle generally refers to an angle greater than 90° and less than 180°. In some specific embodiments, the angle formed between the first and second directions can also be 0° and 180°.

[0097] Please refer to it again. Figure 5 In another embodiment of this disclosure, a semiconductor structure is provided. The semiconductor structure is prepared according to the above-described method for preparing a semiconductor structure; the semiconductor structure includes:

[0098] Substrate 100;

[0099] Bit line contact structure 200 is located on the surface of substrate 100 and in contact with substrate 100;

[0100] The nitride structure 202 is located on the sidewall of the lower part of the bit line contact structure 200 and is in contact with the substrate 100.

[0101] Bit line 300 is located on bit line contact structure 200.

[0102] In some embodiments of this disclosure, the bit line 300 includes a first bit line conductive layer 301, a second bit line conductive layer 302, and a bit line protective layer 303 stacked sequentially from bottom to top.

[0103] Please refer to it again. Figure 4In some embodiments of this disclosure, a shallow trench isolation structure 102 is formed within the substrate 100, and the shallow trench isolation structure 102 isolates a plurality of spaced active regions 103 within the substrate 100; wherein, the bit line 300 extends along a first direction, and the active regions 103 extend along a second direction, and the first direction intersects the second direction. Optionally, the first direction and the second direction may intersect obliquely or perpendicularly.

[0104] Please refer to it again. Figure 7 In some embodiments of this disclosure, the semiconductor structure includes:

[0105] The first dielectric layer 400 covers the surfaces of the bit line contact structure 200, the nitrided structure 202, and the bit line 300.

[0106] The second dielectric layer 500 covers the surface of the first dielectric layer 400.

[0107] Please refer to it again. Figure 8 In some embodiments of this disclosure, the semiconductor structure includes:

[0108] The third dielectric layer 600 covers the surface of the second dielectric layer 500.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A bit line contact structure and a bit line are formed on the substrate; The bit line contact structure is located between the bit line and the substrate; The lower sidewall of the bit line contact structure is subjected to ion doping to form a doped region, wherein the nitriding rate of the doped region is higher than the nitriding rate of other regions of the bit line contact structure. The doped region is subjected to nitriding treatment to selectively consume the doped region and transform it into a nitrided structure, thereby eliminating the tilt angle of the lower sidewall of the bit line contact structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The ion dose for the ion doping treatment is 10. 4 cm -2 ~10 5 cm -2 .

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The ions used in the ion doping treatment include ions of Group V main elements.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The ions used in the ion doping treatment include at least one of arsenic ions and phosphorus ions.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, After nitriding the doped region, the process further includes: The semiconductor structure obtained after nitriding is then subjected to annealing.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The annealing temperature is 550℃~650℃; and / or, The annealing process takes 50 to 70 minutes.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before performing nitriding treatment on the doped region, the method further includes: The doped region is subjected to rapid thermal treatment.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, The nitriding treatment of the doped region includes: The doped region is nitrided using a nitrogen reaction; or, A silicon nitride layer is formed on the surface of the doped region to nitride the doped region.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, The formation of the bit line contact structure and bit line on the substrate includes: Bit line contact holes are formed within the substrate; A bit line contact material layer is formed inside the bit line contact hole; A bit line material layer is formed on the upper surface of the bit line contact material layer; The bit line contact material layer and the bit line material layer are etched to obtain the bit line contact structure and the bit line.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, After nitriding the doped region, the process further includes: A first dielectric layer is formed on the nitrided bit line contact structure and the surface of the bit line; A second dielectric layer is formed on the surface of the first dielectric layer; wherein the first dielectric layer and the second dielectric layer fill the bit line contact hole.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, Before forming the bit line contact structure and bit line on the substrate, the method further includes: A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolating a plurality of spaced active regions in the substrate; the bit line extends along a first direction, the active regions extend along a second direction, and the first direction and the second direction intersect.

12. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, The bit line includes a first bit line conductive layer, a second bit line conductive layer, and a bit line protective layer stacked sequentially from bottom to top.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The material of the first bit line conductive layer includes titanium nitride; and / or, The material of the second bit line conductive layer includes tungsten; and / or, The material of the bit line protection layer includes silicon nitride.

14. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1-13; the semiconductor structure comprises: Substrate; Bit line contact structure, located on the surface of the substrate and in contact with the substrate; A nitrided structure is located on the sidewall of the lower part of the bit line contact structure and is in contact with the substrate; Bit lines are located on the bit line contact structure.

15. The semiconductor structure according to claim 14, characterized in that, include: A first dielectric layer covers the surface of the bit line contact structure, the nitrided structure, and the bit line; A second dielectric layer covers the surface of the first dielectric layer.

Images