Chip heat dissipation device and manufacturing method

Abstract

The application relates to the technical field of chip packaging, in particular to a chip heat dissipation device, which comprises a substrate, a first cantilever beam, a second cantilever beam and an air passage; the first opening and the second opening of the air passage are arranged on the upper surface of the substrate, and the air passage is arranged in the interior of the substrate; the first cantilever beam is arranged on the first opening, and the second cantilever beam is arranged on the second opening. The chip heat dissipation device constructs a heat dissipation structure of a three-dimensional chip, is favorable for the integration of the heat dissipation structure and multiple chips, improves the heat dissipation efficiency of the chip, and does not affect the performance and utilization of the chip under the condition of guaranteeing the heat dissipation efficiency of the multiple chips in the three-dimensional chip.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip heat dissipation device and its manufacturing method. Background Technology

[0002] Three-dimensional integration technology is used to stack and bond multiple layers of chips to form a three-dimensional chip. In a three-dimensional chip, due to the three-dimensional layout of the chips, high-power chips are typically placed at the bottom layer and low-power chips at the top, resulting in the stacking of heat sources across multiple layers and a significant thermal coupling effect. Simultaneously, the reduced package size of a three-dimensional chip leads to a higher volumetric heat flux density, resulting in lower heat dissipation efficiency. Summary of the Invention

[0003] This application provides a chip heat dissipation device and manufacturing method, which solves the technical problem of low chip heat dissipation efficiency in the prior art of three-dimensional chips. Furthermore, by using MEMS technology, a heat dissipation structure for three-dimensional chips is realized, which is beneficial for the integration of heat dissipation structure and multiple chips, thereby improving the chip's heat dissipation efficiency. Under the condition of ensuring the heat dissipation efficiency of multiple chips in the three-dimensional chip, the performance and utilization rate of the chip are not affected.

[0004] In a first aspect, embodiments of the present invention provide a chip heat dissipation device, comprising: a substrate, a first cantilever beam, a second cantilever beam, and an air channel;

[0005] The first opening and the second opening of the air channel are both provided on the upper surface of the substrate, and the air channel is provided inside the substrate.

[0006] The first cantilever beam is disposed on the first opening, and the second cantilever beam is disposed on the second opening.

[0007] Preferably, the substrate includes a first wafer and a second wafer, wherein the second wafer is bonded below the first wafer;

[0008] The air channel further includes: a first groove, a second groove, and a pipe; the first groove and the second groove are both disposed on the first wafer; one end of the pipe is connected to the bottom of the first groove, and the other end is connected to the bottom of the second groove, and the pipe is disposed at the connection between the first wafer and the second wafer, wherein the opening of the first groove is the first opening, and the opening of the second groove is the second opening.

[0009] Preferably, the air channel further includes: a first through hole, a second through hole, and a channel; the first through hole and the second through hole are both disposed on the first wafer; the channel is disposed on the second wafer, one end of the channel is connected to one end of the first through hole, and the other end of the channel is connected to one end of the second through hole, wherein the other end of the first through hole is the first opening, and the other end of the second through hole is the second opening.

[0010] Preferably, the first cantilever beam includes a plurality of piezoelectric cantilever beams; each piezoelectric cantilever beam in the first cantilever beam includes a first electrode film, a piezoelectric film and a second electrode film, wherein the first electrode film is disposed on the first opening, the piezoelectric film is disposed on the first electrode film and the second electrode film is disposed on the piezoelectric film.

[0011] Preferably, there are multiple pipes.

[0012] Preferably, the system further includes a chip located on the substrate and between the first cantilever beam and the second cantilever beam.

[0013] Based on the same inventive concept, in a second aspect, the present invention also provides a method for manufacturing a chip heat dissipation device, comprising:

[0014] A first opening and a second opening for an air channel are formed on the substrate; wherein both the first opening and the second opening are disposed on the upper surface of the substrate;

[0015] A first cantilever beam is formed on the first opening, and a second cantilever beam is formed on the second opening;

[0016] After the first cantilever beam and the second cantilever beam are formed, the air channel is formed inside the substrate.

[0017] Preferably, the substrate includes a first wafer and a second wafer, wherein the second wafer is located below the first wafer;

[0018] The first and second openings forming air channels on the substrate include:

[0019] A first groove and a second groove are etched in the first wafer, wherein the opening of the first groove is the first opening, and the opening of the second groove is the second opening;

[0020] The air channel is formed inside the substrate, including:

[0021] A first channel is etched at the bottom of the first wafer, wherein one end of the first channel is connected to the bottom of the first groove, and the other end of the first channel is connected to the bottom of the second groove.

[0022] A second channel is etched on the second wafer, wherein the shape of the second channel is consistent with the shape of the first channel, and the second channel fits the first channel.

[0023] The first wafer is bonded onto the second wafer, wherein a channel is formed through the first channel and the second channel, and an air channel is formed through the first groove, the second groove, and the channel.

[0024] Preferably, the first opening and the second opening forming the air channel on the substrate include:

[0025] A first through-hole and a second through-hole are etched in the first wafer, wherein one end of the first through-hole is the first opening and one end of the second through-hole is the second opening;

[0026] The formation of the air channel inside the substrate includes:

[0027] A channel is etched on the second wafer, wherein one end of the channel is connected to the other end of the first through hole, and the other end of the channel is connected to the other end of the second through hole;

[0028] The first wafer is bonded onto the second wafer, wherein the air channel is formed through the first via, the second via, and the channel.

[0029] Preferably, after forming the air channel inside the substrate, the method further includes:

[0030] The chip is placed on the substrate, and the chip is located between the first cantilever beam and the second cantilever beam.

[0031] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0032] In this embodiment of the invention, the chip heat dissipation device includes: a substrate, a first cantilever beam, a second cantilever beam, and an air channel; both the first opening and the second opening of the air channel are disposed on the upper surface of the substrate, and the air channel is disposed inside the substrate; the first cantilever beam is disposed on the first opening, and the second cantilever beam is disposed on the second opening. Under the action of voltage, both the first and second cantilever beams vibrate, increasing the airflow velocity, causing the air to accelerate through the first cantilever beam and the first opening of the air channel into the air channel, then through the air channel inside the substrate, and finally out of the air channel through the second cantilever beam and the second opening of the air channel, thus facilitating airflow and carrying away the heat from the chip. Therefore, the chip heat dissipation device is beneficial for heat dissipation structures and multi-chip integration, improving the chip's heat dissipation efficiency, and ensuring the heat dissipation efficiency of multiple chips in a three-dimensional chip without affecting the chip's performance and utilization rate. Attached Figure Description

[0033] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 A schematic diagram of the chip heat dissipation device in an embodiment of the present invention is shown;

[0035] Figure 2 A schematic diagram of the structure of the first air channel form in an embodiment of the present invention is shown;

[0036] Figure 3 A top view showing the pipes arranged side by side in an embodiment of the present invention is shown;

[0037] Figure 4 A top view showing the pipes arranged in an X-shape in an embodiment of the present invention is shown;

[0038] Figure 5 A top view showing the pipes arranged in an H-shape in an embodiment of the present invention is shown;

[0039] Figure 6 A schematic diagram of a second air channel configuration in an embodiment of the present invention is shown;

[0040] Figure 7 This diagram illustrates a structure in which a first groove and a second groove are etched on a first wafer in an embodiment of the present invention.

[0041] Figure 8 This diagram illustrates a structure in which a piezoelectric layer is formed on the first and second grooves according to an embodiment of the present invention.

[0042] Figure 9 This shows a schematic diagram of the structure in which a first cantilever beam is formed on a first groove and a second cantilever beam is formed on a second groove, according to an embodiment of the present invention.

[0043] Figure 10 A schematic diagram of the structure forming the first flow channel in an embodiment of the present invention is shown;

[0044] Figure 11 A schematic diagram of the structure forming the second flow channel in an embodiment of the present invention is shown;

[0045] Figure 12 This diagram illustrates a structure in an embodiment of the present invention where a first wafer and a second wafer are bonded together after the formation of the first and second flow channels.

[0046] Figure 13 This diagram illustrates a structure in which a first through-hole and a second through-hole are formed on a first wafer in an embodiment of the present invention.

[0047] Figure 14 This shows a schematic diagram of the structure in an embodiment of the present invention, in which a first cantilever beam is formed on a first through hole and a second cantilever beam is formed on a second through hole;

[0048] Figure 15 A schematic diagram of the structure for forming a channel in an embodiment of the present invention is shown;

[0049] Figure 16 This diagram illustrates a structure in an embodiment of the present invention where a first wafer and a second wafer are bonded after the formation of a channel.

[0050] Figure 17 A flowchart illustrating the steps of manufacturing a chip heat dissipation device according to an embodiment of the present invention is shown. Detailed Implementation

[0051] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0052] Example 1

[0053] The first embodiment of the present invention provides a chip heat dissipation device, such as... Figure 1As shown, it includes: a substrate 100, a first cantilever beam 200, a second cantilever beam 300, and an air channel 400; the first opening and the second opening of the air channel 400 are both disposed on the upper surface of the substrate 100, and the air channel 400 is disposed inside the substrate 100; the first cantilever beam 200 is disposed on the first opening, and the second cantilever beam 300 is disposed on the second opening.

[0054] In this embodiment, the substrate 100 includes a first wafer 101 and a second wafer 102, with the second wafer 102 bonded beneath the first wafer 101. Figure 1 In the image, the black area represents substrate 100.

[0055] The first cantilever beam 200 includes multiple piezoelectric cantilever beams, Figure 1 The small square indicated by 200 is a piezoelectric cantilever beam, i.e. Figure 1 The first cantilever beam 200 includes two piezoelectric cantilever beams. Each piezoelectric cantilever beam in the first cantilever beam 200 includes a first electrode film, a piezoelectric film, and a second electrode film, wherein the first electrode film is disposed on a first opening, the piezoelectric film is disposed on top of the first electrode film, and the second electrode film is disposed on top of the piezoelectric film. Similarly, the second cantilever beam 300 includes multiple piezoelectric cantilever beams. Each piezoelectric cantilever beam in the second cantilever beam 300 includes a first electrode film, a piezoelectric film, and a second electrode film, wherein the first electrode film is disposed on a second opening, the piezoelectric film is disposed on top of the first electrode film, and the second electrode film is disposed on top of the piezoelectric film. Based on the first cantilever beam 200 and the second cantilever beam 300, it can be seen that both the first cantilever beam 200 and the second cantilever beam 300 exhibit the characteristics of the piezoelectric effect.

[0056] It should also be noted that the materials of the piezoelectric thin film include, but are not limited to, aluminum nitride. The materials of the first electrode thin film include, but are not limited to, copper, gold, or molybdenum. The materials of the second electrode thin film include, but are not limited to, copper, gold, or molybdenum.

[0057] Because the first cantilever beam 200 and the second cantilever beam 300 exhibit piezoelectric properties, both vibrate under voltage. This causes air to accelerate through the first cantilever beam 200 into the air channel 400, and then flow out through the second cantilever beam 300, effectively carrying away heat from the chip. Under voltage control, the vibration phases of the first cantilever beam 200 and the second cantilever beam 300 are opposite, with a phase difference of 180°. This allows the first cantilever beam 200 and the first opening to form an air inlet, while the second cantilever beam 300 and the second opening form an air outlet. Therefore, the arrangement of the first cantilever beam 200 and the second cantilever beam 300 in this embodiment facilitates airflow, accelerates heat dissipation, and improves the chip's heat dissipation efficiency. This ensures the heat dissipation efficiency of multiple chips within the three-dimensional chip without affecting chip performance and utilization.

[0058] The chip heat dissipation device also includes a chip, which is located on the substrate 100 and between the first cantilever beam 200 and the second cantilever beam 300.

[0059] The air channel 400 in this embodiment has two forms, which are described in detail below:

[0060] The first type of air passage 400, such as Figure 2 As shown, the air channel 400 further includes a first groove 411, a second groove 412, and a conduit 413. Both the first groove 411 and the second groove 412 are disposed on the first wafer 101. One end of the conduit 413 communicates with the bottom of the first groove 411, and the other end communicates with the bottom of the second groove 412. The conduit 413 is disposed at the connection between the first wafer 101 and the second wafer 102. The opening of the first groove 411 is a first opening, and the opening of the second groove 412 is a second opening. Figure 2 In the diagram, the dashed line divides the substrate 100 into two parts: the part above the dashed line is the first wafer 101, and the part below the dashed line is the second wafer 102.

[0061] The first cantilever beam 200 is disposed at the opening of the first groove 411, and the second cantilever beam 300 is disposed at the opening of the second groove 412. The chip is disposed on the first wafer 101, and the chip is disposed between the first cantilever beam 200 and the second cantilever beam 300.

[0062] Furthermore, the number of pipes 413 in the air passage 400 is multiple. The shape of a single pipe 413 includes, but is not limited to, an S-shape or a shape with bends. The arrangement of multiple pipes 413 includes, but is not limited to: multiple pipes 413 arranged side-by-side, multiple pipes 413 arranged in an X-shape, or multiple pipes 413 arranged in an H-shape. For example, as... Figure 3As shown, in the chip heat dissipation device, four pipes 413 are arranged side by side, with no intersections between them. Figure 3 The black area represents the cantilever beam, and the dashed area represents pipe 413. (Example) Figure 4 As shown, in the four pipes 413, every two pipes 413 intersect in an X-shape. Figure 4 There are two X-shaped pipes 413. In Figure 4 The black area represents the cantilever beam, and the dashed area represents pipe 413. (Example) Figure 5 As shown, each pair of adjacent pipes 413 in the four pipes 413 forms an H-shape. Figure 5 The black area represents the cantilever beam, and the dashed area represents pipe 413.

[0063] In the first form of air channel 400, one end of pipe 413 is connected to the bottom of the first groove 411 and the other end is connected to the bottom of the second groove 412. Pipe 413 is disposed between the first wafer 101 and the second wafer 102 to allow air to circulate within the wafer, carry away the heat of the chip, and play a role in heat dissipation, thereby further improving the heat dissipation efficiency of the chip. Under the condition of ensuring the heat dissipation efficiency of multiple chips in the three-dimensional chip, the performance and utilization rate of the chip are not affected.

[0064] The second type of air passage 400, such as Figure 6 As shown, the air channel 400 further includes: a first through-hole 421, a second through-hole 422, and a channel 423; both the first through-hole 421 and the second through-hole 422 are disposed on the first wafer 101; the channel 423 is disposed on the second wafer 102, one end of the channel 423 is connected to one end of the first through-hole 421, and the other end of the channel 423 is connected to one end of the second through-hole 422, wherein the other end of the first through-hole 421 is a first opening, and the other end of the second through-hole 422 is a second opening. Figure 6 In the diagram, the dashed line divides the substrate 100 into two parts: the part above the dashed line is the first wafer 101, and the part below the dashed line is the second wafer 102.

[0065] The first cantilever beam 200 is disposed at the other end of the first through hole 421, and the second cantilever beam 300 is disposed at the other end of the second through hole 422. The chip is disposed on the first wafer 101, and the chip is disposed between the first cantilever beam 200 and the second cantilever beam 300.

[0066] In addition, the air passage 400 has multiple channels 423. The shape of a single channel 423 includes, but is not limited to, an S-shape or a shape with a bend. The arrangement of multiple channels 423 includes, but is not limited to, multiple channels 423 arranged side by side, multiple channels 423 arranged in an X-shape, or multiple channels 423 arranged in an H-shape. The arrangement of channels 423 can be referred to the arrangement of pipes 413, and will not be repeated here.

[0067] In the second form of air channel 400, the arrangement of the channel 423 allows air to circulate within the wafer, carrying away the heat of the chip and playing a heat dissipation role, further improving the heat dissipation efficiency of the chip. Under the condition of ensuring the heat dissipation efficiency of multiple chips in the three-dimensional chip, the performance and utilization rate of the chip are not affected.

[0068] The working principle of the chip heat dissipation device in this embodiment is as follows: due to the piezoelectric effect of the first cantilever beam 200 and the second cantilever beam 300, both vibrate under the action of voltage, thereby providing airflow. The chip heat dissipation device allows air to enter the air channel 400 through the first opening of the first cantilever beam 200 and the air channel 400, pass through the air channel 400 inside the substrate 100, and then flow out of the air channel 400 through the second opening of the second cantilever beam 300 and the air channel 400, so as to facilitate the flow of airflow, carry away the heat of the chip, and improve the heat dissipation efficiency of the chip.

[0069] The method for manufacturing a chip heat dissipation device in the form of the first type of air channel 400 is as follows:

[0070] The first step involves etching a first groove 411 and a second groove 412 on the first wafer 101 using a through-silicon via (TSV) process, and filling the first groove 411 and the second groove 412 with phosphosilicate glass (PSG), such as... Figure 7 As shown. In Figure 7 In the diagram, the black areas represent the first groove 411 and the second groove 412, respectively.

[0071] The second step, as Figure 8 As shown, after filling the first groove 411 and the second groove 412 with phosphosilicate glass, a first electrode film, a piezoelectric film, and a second electrode film are sequentially deposited to form a piezoelectric layer 600. The piezoelectric film is made of materials including, but not limited to, aluminum nitride; the first electrode film is made of materials including, but not limited to, copper, gold, and molybdenum; and the second electrode film is made of materials including, but not limited to, copper, gold, and molybdenum. Figure 8 In the diagram, the black areas represent the first groove 411 and the second groove 412, respectively.

[0072] The third step, as Figure 9 As shown, a piezoelectric layer, a first groove 411, and a second groove 412 are etched. A first cantilever beam 200 is formed on the opening of the first groove 411, and a second cantilever beam 300 is formed on the opening of the second groove 412. Figure 9 In the diagram, the recessed white areas on the first wafer 101 are respectively the first groove 411 and the second groove 412. Figure 9The black areas represent the first cantilever beam 200 and the second cantilever beam 300, respectively.

[0073] Step four, as Figure 10 As shown, a first channel 4131 is etched on the bottom of the first wafer 101 using a deep reactive ion etching (DRIE) process. One end of the first channel 4131 is connected to the bottom of the first groove 411, and the other end of the first channel 4131 is connected to the bottom of the second groove 412. Figure 10 In the diagram, the black areas represent the first cantilever beam 200 and the second cantilever beam 300, respectively.

[0074] Step 5, as Figure 11 As shown, a second channel 4132 is etched on the second wafer 102, wherein the shape of the second channel 4132 is consistent with the shape of the first channel 4131, and the second channel 4132 fits the first channel 4131. Figure 11 In the second wafer 102, the recessed blank area is the second flow channel 4132. Specifically, the second flow channel 4132 is etched using the DRIE process, and the etching gas materials used include, but are not limited to, a mixture of carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), and oxygen.

[0075] Step 6, as follows Figure 12 As shown, a first wafer 101 is bonded onto a second wafer 102, wherein a channel 413 is formed through a first channel 4131 and a second channel 4132, and an air channel 400 is formed through a first groove 411, a second groove 412, and a channel 413. Figure 12 In the diagram, the dashed line represents the connection between the first wafer 101 and the second wafer 102. The wafer above the dashed line is the first wafer 101, and the wafer below the dashed line is the second wafer 102.

[0076] Step 7, as Figure 2 As shown, the chip is placed on the first wafer 101, and the chip is positioned between the first cantilever beam 200 and the second cantilever beam 300. This results in a complete chip heat dissipation device.

[0077] The method for manufacturing a chip heat dissipation device in the form of the second type of air channel 400 is as follows:

[0078] First step, such as Figure 13 As shown, a first through-hole 421 and a second through-hole 422 are etched on the first wafer 101 using a through-silicon via (TSV) process, and phosphosilicate glass is filled into the first through-hole 421 and the second through-hole 422. Figure 13 In the diagram, the black areas represent the first through hole 421 and the second through hole 422, respectively.

[0079] In the second step, after filling the first via 421 and the second via 422 with phosphosilicate glass, a first electrode film, a piezoelectric film, and a second electrode film are sequentially deposited to form a piezoelectric layer. The materials of the piezoelectric film include, but are not limited to, aluminum nitride; the materials of the first electrode film include, but are not limited to, copper, gold, and molybdenum; and the materials of the second electrode film include, but are not limited to, copper, gold, and molybdenum. This step can be referred to in the second step of the fabrication method of a chip heat dissipation device formed in the form of a first type of air channel 400.

[0080] The third step, as Figure 14 As shown, a piezoelectric layer, a first through-hole 421, and a second through-hole 422 are etched. A first cantilever beam 200 is formed at one end of the first through-hole 421, and a second cantilever beam 300 is formed at one end of the second through-hole 422. Figure 14 In the diagram, the black areas represent the first cantilever beam 200 and the second cantilever beam 300, respectively. The blank area below the first cantilever beam 200 is the first through hole 421, and the blank area below the second cantilever beam 300 is the second through hole 422.

[0081] Step four, as Figure 15 As shown, a channel 423 is etched on the second wafer 102, wherein one end of the channel 423 is connected to the other end of the first through-hole 421, and the other end of the channel 423 is connected to the other end of the second through-hole 422. Figure 15 In the second wafer 102, the recessed blank area is the channel 423. Specifically, the channel 423 is etched using the DRIE process, and the etching gas material used includes, but is not limited to, a mixture of CF4, SF6 and oxygen.

[0082] Step 5, as Figure 16 As shown, a first wafer 101 is bonded onto a second wafer 102, wherein an air channel 400 is formed through a first through-hole 421, a second through-hole 422, and a channel 423. Figure 16 In the diagram, the dashed line represents the connection between the first wafer 101 and the second wafer 102. The wafer above the dashed line is the first wafer 101, and the wafer below the dashed line is the second wafer 102.

[0083] Step 6, as follows Figure 6 As shown, the chip is placed on the first wafer 101, and the chip is positioned between the first cantilever beam 200 and the second cantilever beam 300. This results in a complete chip heat dissipation device.

[0084] In this embodiment, the chip heat dissipation device is fabricated using MEMS (Microfabrication Process) technology to realize the heat dissipation structure of the three-dimensional chip, which facilitates the integration of the heat dissipation structure and the chip. Furthermore, a piezoelectric cantilever beam is used as the airflow pump inlet, allowing air to carry away the heat from the chip, thus improving heat dissipation efficiency. The TSV (Transient Voltage Suppressor) process and air channel 400 are also combined to transfer heat from the chip, further improving heat dissipation efficiency. This chip heat dissipation device fabrication method ensures the heat dissipation efficiency of multiple chips within the three-dimensional chip without affecting chip performance and utilization.

[0085] It should also be noted that another form of the second type of air channel 400 is that the air channel 400 further includes: a first through hole 421, a second through hole 422, and a channel 423; the first through hole 421 and the second through hole 422 are both disposed on the first wafer 101; the channel 423 is disposed in the second wafer 102, one end of the channel 423 is connected to one end of the first through hole 421, and the other end of the channel 423 is connected to one end of the second through hole 422, the other end of the first through hole 421 is a first opening, and the other end of the second through hole 422 is a second opening.

[0086] The aperture 423 is disposed in the second wafer 102, indicating that the aperture 423 is disposed inside the second wafer 102.

[0087] The fabrication method of the chip heat dissipation device formed in another form of the second air channel 400 can refer to the fabrication method of the chip heat dissipation device formed in the form of the second air channel 400. However, in the fabrication method of the chip heat dissipation device formed in another form of the second air channel 400, the step of setting the channel 423 in the second wafer 102 is different from the step of forming the channel 423 on the second wafer 102 in the fabrication method of the chip heat dissipation device formed in the form of the second air channel 400. The step of setting the channel 423 in the second wafer 102 is performed according to actual operation.

[0088] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0089] In this embodiment, the chip heat dissipation device includes a substrate, a first cantilever beam, a second cantilever beam, and an air channel. Both the first and second openings of the air channel are located on the upper surface of the substrate, and the air channel is disposed inside the substrate. The first cantilever beam is disposed on the first opening, and the second cantilever beam is disposed on the second opening. Under voltage, both the first and second cantilever beams vibrate, increasing the airflow velocity. This causes the air to accelerate through the first cantilever beam and the first opening of the air channel into the air channel, then through the air channel inside the substrate, and finally out of the air channel through the second cantilever beam and the second opening of the air channel, facilitating airflow and carrying away heat from the chip. Therefore, the chip heat dissipation device is beneficial for heat dissipation structures and multi-chip integration, improving chip heat dissipation efficiency. While ensuring the heat dissipation efficiency of multiple chips in a three-dimensional chip, it does not affect the chip's performance and utilization rate.

[0090] Example 2

[0091] Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a chip heat dissipation device, such as... Figure 17 As shown, it includes:

[0092] S101, a first opening and a second opening for an air channel are formed on the substrate; wherein, both the first opening and the second opening are disposed on the upper surface of the substrate;

[0093] S102, a first cantilever beam is formed on the first opening, and a second cantilever beam is formed on the second opening;

[0094] S103, after forming the first cantilever beam and the second cantilever beam, the air channel is formed inside the substrate.

[0095] As an optional embodiment, the substrate includes a first wafer and a second wafer, wherein the second wafer is located below the first wafer;

[0096] The first and second openings forming air channels on the substrate include:

[0097] A first groove and a second groove are etched in the first wafer, wherein the opening of the first groove is the first opening, and the opening of the second groove is the second opening;

[0098] The air channel is formed inside the substrate, including:

[0099] A first channel is etched at the bottom of the first wafer, wherein one end of the first channel is connected to the bottom of the first groove, and the other end of the first channel is connected to the bottom of the second groove.

[0100] A second channel is etched on the second wafer, wherein the shape of the second channel is consistent with the shape of the first channel, and the second channel fits the first channel.

[0101] The first wafer is bonded onto the second wafer, wherein a channel is formed through the first channel and the second channel, and an air channel is formed through the first groove, the second groove, and the channel.

[0102] As an optional embodiment, the first opening and the second opening for forming air channels on the substrate include:

[0103] A first through-hole and a second through-hole are etched in the first wafer, wherein one end of the first through-hole is the first opening and one end of the second through-hole is the second opening;

[0104] The formation of the air channel inside the substrate includes:

[0105] A channel is etched on the second wafer, wherein one end of the channel is connected to the other end of the first through hole, and the other end of the channel is connected to the other end of the second through hole;

[0106] The first wafer is bonded onto the second wafer, wherein the air channel is formed through the first via, the second via, and the channel.

[0107] As an optional embodiment, after forming the air channel inside the substrate, the method further includes:

[0108] The chip is placed on the substrate, and the chip is located between the first cantilever beam and the second cantilever beam.

[0109] Since the chip heat dissipation device manufacturing method described in this embodiment is the same as that used in the chip heat dissipation device of Embodiment 1 of this application, those skilled in the art can understand the specific implementation methods and various variations of the chip heat dissipation device manufacturing method described in Embodiment 1 of this application based on the chip heat dissipation device. Therefore, how the chip heat dissipation device manufacturing method implements the chip heat dissipation device of Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the manufacturing method used in the chip heat dissipation device of Embodiment 1 of this application, they are all within the scope of protection of this application.

[0110] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0111] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A chip heat dissipation device, characterized in that, include: Substrate, first cantilever beam, second cantilever beam, and air channel; The first opening and the second opening of the air channel are both provided on the upper surface of the substrate, and the air channel is provided inside the substrate. The first cantilever beam is disposed on the first opening, and the second cantilever beam is disposed on the second opening; The first cantilever beam and the second cantilever beam have a piezoelectric effect. Under the action of voltage, both the first cantilever beam and the second cantilever beam vibrate, and the vibration phases are opposite. The first cantilever beam includes a plurality of piezoelectric cantilever beams; each piezoelectric cantilever beam in the first cantilever beam includes a first electrode film, a piezoelectric film and a second electrode film, wherein the first electrode film is disposed on the first opening, the piezoelectric film is disposed on the first electrode film and the second electrode film is disposed on the piezoelectric film; The chip heat dissipation device further includes a chip, and the substrate includes a first wafer and a second wafer, with the second wafer bonded below the first wafer; the chip is placed on the first wafer; The air channel further includes: a first groove, a second groove, and a pipe; the first groove and the second groove are both disposed on the first wafer; one end of the pipe is connected to the bottom of the first groove, and the other end is connected to the bottom of the second groove, and the pipe is disposed at the connection between the first wafer and the second wafer, wherein the opening of the first groove is the first opening, and the opening of the second groove is the second opening.

2. The chip heat dissipation device as described in claim 1, characterized in that, The air channel further includes: a first through hole, a second through hole, and a channel; the first through hole and the second through hole are both disposed on the first wafer; the channel is disposed on the second wafer, one end of the channel is connected to one end of the first through hole, and the other end of the channel is connected to one end of the second through hole, wherein the other end of the first through hole is the first opening, and the other end of the second through hole is the second opening.

3. The chip heat dissipation device as described in claim 1, characterized in that, There are multiple pipes.

4. The chip heat dissipation device as described in claim 1, characterized in that, The chip is located on the substrate and between the first cantilever beam and the second cantilever beam.

5. A method for manufacturing a chip heat dissipation device, characterized in that, The method for manufacturing a chip heat dissipation device according to any one of claims 1-4 includes: A first opening and a second opening for an air channel are formed on the substrate; wherein both the first opening and the second opening are disposed on the upper surface of the substrate; A first cantilever beam is formed on the first opening, and a second cantilever beam is formed on the second opening; the first cantilever beam and the second cantilever beam have a piezoelectric effect, and under the action of voltage, both the first cantilever beam and the second cantilever beam vibrate, and the vibration phases are opposite. The first cantilever beam includes a plurality of piezoelectric cantilever beams; each piezoelectric cantilever beam in the first cantilever beam includes a first electrode film, a piezoelectric film and a second electrode film, wherein the first electrode film is disposed on the first opening, the piezoelectric film is disposed on the first electrode film and the second electrode film is disposed on the piezoelectric film; After the first cantilever beam and the second cantilever beam are formed, the air channel is formed inside the substrate.

6. The method as described in claim 5, characterized in that, The substrate includes a first wafer and a second wafer, wherein the second wafer is located below the first wafer; The first and second openings forming air channels on the substrate include: A first groove and a second groove are etched in the first wafer, wherein the opening of the first groove is the first opening, and the opening of the second groove is the second opening; The air channel is formed inside the substrate, including: A first channel is etched at the bottom of the first wafer, wherein one end of the first channel is connected to the bottom of the first groove, and the other end of the first channel is connected to the bottom of the second groove. A second channel is etched on the second wafer, wherein the shape of the second channel is consistent with the shape of the first channel, and the second channel fits the first channel. The first wafer is bonded onto the second wafer, wherein a channel is formed through the first channel and the second channel, and an air channel is formed through the first groove, the second groove, and the channel.

7. The method as described in claim 6, characterized in that, The first and second openings forming air channels on the substrate include: A first through-hole and a second through-hole are etched in the first wafer, wherein one end of the first through-hole is the first opening and one end of the second through-hole is the second opening; The formation of the air channel inside the substrate includes: A channel is etched on the second wafer, wherein one end of the channel is connected to the other end of the first through hole, and the other end of the channel is connected to the other end of the second through hole; The first wafer is bonded onto the second wafer, wherein the air channel is formed through the first via, the second via, and the channel.

8. The method as described in claim 5, characterized in that, After the air channel is formed inside the substrate, the method further includes: The chip is placed on the substrate, and the chip is located between the first cantilever beam and the second cantilever beam.

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