Semiconductor package

Abstract

A semiconductor package includes a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one through via penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first back surface cap disposed on a first inactive surface of the first semiconductor substrate, and a first back surface pseudo-conductive layer penetrating a portion of the first back surface cap; a second semiconductor chip including a second front surface cap disposed on a second active surface of a second semiconductor substrate, and a second front surface pseudo-conductive layer penetrating a portion of the second front surface cap; and at least one first bonding pad penetrating the first back surface cap and the second front surface cap.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0030941, filed with the Korean Intellectual Property Office on March 9, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to semiconductor packaging, and more specifically, to semiconductor packaging comprising stacked semiconductor chips. Background Technology

[0004] With the increasing demands for miniaturization, multifunctionality, and high performance in electronic products, there are also requirements for high integration and high speed in semiconductor packaging. To address this, semiconductor packages comprising multiple semiconductor chips, including stacked semiconductor chips, have been developed. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor package comprising stacked semiconductor chips, which improves operational reliability.

[0006] The embodiments provide the following semiconductor package.

[0007] A semiconductor package includes: a first semiconductor chip, a second semiconductor chip, and at least one first bonding pad connecting the first and second semiconductor chips. The first semiconductor chip includes: a first semiconductor substrate including a first active surface and a first passive surface opposite to each other; a plurality of first front surface pads disposed on the first active surface of the first semiconductor substrate; at least one first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first front surface pads; a first rear surface cover layer disposed on the first passive surface of the first semiconductor substrate; and a first rear surface alignment pattern disposed in the first rear surface cover layer. The second semiconductor chip includes: a second semiconductor substrate stacked on the first semiconductor chip and including a second semiconductor element on its second active surface; a second front surface cover layer disposed on the second active surface of the second semiconductor substrate; and a second front surface alignment pattern disposed in the second front surface cover layer and separated from the rear surface alignment pattern. The height of the first bonding pad is greater than the sum of the thickness of the first rear surface cover layer and the thickness of the second front surface cover layer, and is equal to or less than twice the sum of the thickness of the first rear surface alignment pattern and the thickness of the second front surface alignment pattern.

[0008] A semiconductor package includes: a first semiconductor chip, a second semiconductor chip, and at least one first bonding pad connecting the first and second semiconductor chips, wherein the first semiconductor chip includes: a first semiconductor substrate including a first semiconductor element on a first active surface thereon; a plurality of first front surface pads disposed on the first active surface of the first semiconductor substrate; at least one first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first front surface pads; a first rear surface capping layer disposed on a first passive surface of the first semiconductor substrate; and a first rear surface pseudo-conductive layer including a first rear surface alignment pattern and penetrating a portion of the first rear surface capping layer; wherein the second semiconductor chip includes: a second semiconductor substrate stacked on the first semiconductor chip and including a second semiconductor element on a second active surface thereon; a second front surface capping layer disposed on the second active surface; and a second front surface pseudo-conductive layer including a second front surface alignment pattern separated from the first rear surface alignment pattern and penetrating a portion of the second front surface capping layer; and wherein the first bonding pad penetrates the first rear surface capping layer and the second front surface capping layer and is connected to the first through electrode.

[0009] A semiconductor package includes: a first semiconductor chip; at least two second semiconductor chips stacked on the first semiconductor chip; at least one first bonding pad connecting the lowermost second semiconductor chip of the two second semiconductor chips to the first semiconductor chip; and at least one second bonding pad connecting the two second semiconductor chips to each other, wherein the first semiconductor chip includes: a first semiconductor substrate including a first active surface and a first passive surface opposite to each other; a plurality of first front surface pads disposed on the first active surface; at least one first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first bonding pad; a first rear surface capping layer including a first lower rear surface capping layer disposed on the first passive surface and a first upper rear surface capping layer disposed on the first lower rear surface capping layer; and a first rear surface pseudo-conductive layer disposed in the first lower rear surface capping layer and including a first rear surface alignment pattern, wherein the two second semiconductor chips include: a second semiconductor substrate including a second active surface opposite to each other. The second passive surface; a second front surface capping layer, including a second lower front surface capping layer disposed on the second active surface and a second upper front surface capping layer disposed on the second lower front surface capping layer; a second front surface pseudo-conductive layer disposed in the second lower front surface capping layer and including a second front surface alignment pattern; at least one second through electrode, penetrating at least a portion of the second semiconductor substrate and connecting the first bonding pad to the second bonding pad; a second rear surface capping layer, including a second lower rear surface capping layer disposed on the second passive surface and a second upper rear surface capping layer disposed on the second lower rear surface capping layer; and a second rear surface pseudo-conductive layer disposed in the second rear surface capping layer and including a second rear surface alignment pattern, wherein the first bonding pad penetrates the first rear surface capping layer and the second front surface capping layer of the lowermost second semiconductor chip, wherein the second bonding pad penetrates the second front surface capping layers facing each other and the second rear surface capping layer of another of the at least two second semiconductor chips. Attached Figure Description

[0010] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment, and Figure 2A and Figure 2B This is its enlarged cross-sectional view;

[0012] Figures 3A to 3G The images show cross-sectional views of a semiconductor package manufacturing method according to an embodiment.

[0013] Figure 4 This is a cross-sectional view of a semiconductor package according to an embodiment;

[0014] Figure 5 This is a cross-sectional view of a semiconductor package according to an embodiment, and Figure 6 This is its enlarged cross-sectional view;

[0015] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor package according to an embodiment;

[0016] Figure 8 and Figure 9 A cross-sectional view of a semiconductor package according to an embodiment; and

[0017] Figure 10A and Figure 10B This is a plan view of a plurality of bonding pads in a semiconductor package according to an embodiment. Detailed Implementation

[0018] The embodiments described herein are exemplary embodiments, and therefore the inventive concept is not limited thereto and can be implemented in various other forms.

[0019] It will be understood that when an element or layer is referred to as being "above," "on top of," "above," "below," "below," "connected to," or "coupled to" another element or layer, it can be directly above, above, above, below, below, or below that other element or layer, or there can be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "above," "above," "below," "below," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers.

[0020] It will be understood that although the terms “first,” “second,” “third,” “fourth,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or portion discussed below may be a second element, component, region, layer, or portion.

[0021] For ease of description, spatial relative terms such as “above,” “below,” “over,” “upper,” “under,” “below,” “lower,” “lower,” etc., are used herein to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to include not only the orientation shown in the drawings but also different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” other elements or features will be oriented “above” other elements or features. Thus, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted accordingly.

[0022] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment, and Figure 2A and Figure 2B This is its enlarged cross-sectional view. Figure 2A and 2B yes Figure 1 Enlarged cross-sectional views of regions IIa and IIb.

[0023] Reference Figures 1 to 2B The semiconductor package 1000 may include a first semiconductor chip 100 and a plurality of second semiconductor chips 200. The semiconductor package 1000 may further include a packaging molding layer 300 surrounding the side surfaces of the second semiconductor chips on the first semiconductor chip 100. Figures 1 to 2B In this embodiment, semiconductor package 1000 is shown to include four second semiconductor chips 200, but the embodiments are not limited thereto. For example, semiconductor package 1000 may include two or more second semiconductor chips 200. In some embodiments, semiconductor package 1000 may include a multiple of four second semiconductor chips 200. The second semiconductor chips 200 may be stacked on top of the first semiconductor chip 100. Semiconductor package 1000 may be referred to as a sub-semiconductor package.

[0024] In the semiconductor package 1000, a first semiconductor chip 100 can be electrically connected via a plurality of first bonding pads BP1 to a second semiconductor chip 200 closest to the first semiconductor chip 100 (e.g., the second semiconductor chip 200 at the bottom of the plurality of second semiconductor chips 200), transmitting and receiving signals and providing power and ground. Two adjacent second semiconductor chips 200 in the semiconductor package 1000 can be electrically connected to each other via a plurality of second connection pads BP2, and transmit and receive signals and provide or be provided with power and ground.

[0025] The first semiconductor chip 100 may include: a first semiconductor substrate 110, including a first active surface and a first passive surface formed opposite to each other; a first semiconductor element 112 formed on the first active surface of the first semiconductor substrate 110; a first front surface wiring structure 120 formed on the first active surface of the first semiconductor substrate 110; a plurality of first through electrodes 130 connected to the first front surface wiring structure 120 and penetrating at least a portion of the first semiconductor chip 100; and a first rear surface wiring structure 150 formed on the first passive surface of the first semiconductor substrate 110 and connected to the first through electrodes 130. The first semiconductor chip 100 may further include a plurality of first front surface pads 142 connected to the first front surface wiring structure 120.

[0026] In a semiconductor package 1000, a first semiconductor chip 100 may be configured such that the first active surface of a first semiconductor substrate 110 faces downward and its first passive surface faces upward. However, unless otherwise stated herein, the upper surface of the first semiconductor chip 100 in the semiconductor package 1000 may refer to the side facing the first passive surface of the first semiconductor substrate 110, and the lower surface of the first semiconductor chip 100 may refer to the side facing the first active surface of the first semiconductor substrate 110. However, when described with reference to the first semiconductor chip 100, the lower surface of the first semiconductor chip 100 facing the first active surface of the first semiconductor substrate 110 may be referred to as the front surface of the first semiconductor chip 100, and the upper surface of the first semiconductor chip 100 facing the first passive surface of the first semiconductor substrate 110 may be referred to as the rear surface of the first semiconductor chip 100.

[0027] The second semiconductor chip 200 may include a second semiconductor substrate 210 having a second active surface and a second passive surface formed opposite to each other, a second semiconductor element 212 formed on the second active surface of the second semiconductor substrate 210, and a second front surface wiring structure 220 formed on the second active surface of the second semiconductor substrate 210.

[0028] The first and second active surfaces on which the first conductor element 112 and the second semiconductor element 212 are formed can be active regions of the first semiconductor substrate 110 and the second semiconductor substrate 210, respectively. These first and second active regions can include the source / drain regions and / or channel regions of a transistor.

[0029] The second semiconductor chip 200 may further include a plurality of second through electrodes 230 connected to and penetrating at least a portion of the second semiconductor chip 200, and a second rear surface wiring structure 250 formed on a second passive surface of the second semiconductor substrate 210 and connected to the second through electrodes 230. In some embodiments, the second semiconductor chip 200 that is furthest from the first semiconductor chip 100 and thus located at the uppermost end of the semiconductor package 1000 may not include the second through electrodes 230 and the second rear surface wiring structure 250. In some embodiments, the thickness of the second semiconductor chip 200 that is furthest from the first semiconductor chip 100 and thus located at the uppermost end of the semiconductor package 1000 may be greater than the thickness of the other second semiconductor chips 200.

[0030] In the semiconductor package 1000, each of the second semiconductor chips 200 can be sequentially stacked in the vertical direction (Z direction), with the second active surface of each of the second semiconductor chips 200 facing downwards, i.e., facing the first semiconductor chip 100. Therefore, unless otherwise specified herein, the upper surface of the second semiconductor chip 200 in the semiconductor package 1000 may refer to the side facing the second passive surface of the second semiconductor substrate 210, and the lower surface of the second semiconductor chip 210 may refer to the side facing the second active surface of the second semiconductor substrate 210. However, when described with reference to the second semiconductor chip 200, the lower surface of the semiconductor chip 200 facing the second active surface of the second semiconductor substrate 210 may be referred to as the front surface of the second semiconductor chip 200, and the upper surface of the second semiconductor chip 200 facing the second passive surface of the second semiconductor substrate 210 may be referred to as the rear surface of the second semiconductor chip 200.

[0031] The first semiconductor substrate 110 and the second semiconductor substrate 210 may comprise semiconductor materials such as silicon (Si). Alternatively, the first semiconductor substrate 110 and the second semiconductor substrate 210 may comprise semiconductor materials such as germanium (Ge). Each of the first semiconductor substrate 110 and the second semiconductor substrate 210 may have an active surface and a passive surface opposite to the active surface. The first semiconductor substrate 110 and the second semiconductor substrate 210 may comprise conductive regions, such as wells doped with impurities. The first semiconductor substrate 110 and the second semiconductor substrate 210 may have various element isolation structures, such as shallow trench isolation (STI) structures.

[0032] Each of the first semiconductor element 112 and the second semiconductor element 212 may include multiple individual elements of various types. The individual elements may include various microelectronic components, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), image sensors (e.g., system-on-large-scale integration (LSI) and CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active components, passive components, etc. The individual elements may be electrically connected to conductive regions of the first semiconductor substrate 110 or the second semiconductor substrate 210. Each of the first semiconductor element 112 and the second semiconductor element 212 may further include at least two of the individual elements, or conductive wiring or conductive plugs electrically connecting the individual elements to conductive regions of each of the first semiconductor substrate 110 and the second semiconductor substrate 210. Furthermore, each of the individual elements may be electrically isolated from other adjacent individual elements by an insulating layer.

[0033] In some embodiments, at least one of the first semiconductor chip 100 and the second semiconductor chip 200 may include a memory semiconductor chip. In some embodiments, at least one of the first semiconductor chip 100 and the second semiconductor chip 200 may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0034] In some embodiments, the semiconductor package 1000 including the first semiconductor chip 100 and the second semiconductor chip 200 may be referred to as a high-bandwidth memory (HBM) dynamic random access memory (DRAM) semiconductor chip. For example, the first semiconductor chip 100 may include a buffer chip including serial-to-parallel conversion circuitry for controlling the second semiconductor chip 200, and the second semiconductor chip 200 may include a core chip including DRAM memory cells. In some embodiments, the first semiconductor chip 100 may be referred to as a master chip, and each of the second semiconductor chips 200 may be referred to as a slave chip.

[0035] The first front surface wiring structure 120 and the second front surface wiring structure 220 may include materials such as aluminum (Al), copper (Cu), and tungsten (W). In some embodiments, the first front surface wiring structure 120 and the second front surface wiring structure 220 may include a wiring barrier layer and a wiring metal layer. The wiring barrier layer may include a metal, a metal nitride, or an alloy. The wiring metal layer may include at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0036] The second front surface wiring structure 220 may include a plurality of second front surface wiring patterns 222 and a plurality of second front surface wiring vias 224 connected to the second front surface wiring patterns 222. In some embodiments, the thickness of the second front surface wiring patterns 222 may be equal to or less than about 0.5 μm. In some embodiments, the second front surface wiring structure 220 may have a multilayer wiring structure, wherein the second front surface wiring patterns 222 and the second front surface wiring vias 224 are formed at different vertical heights.

[0037] The second semiconductor chip 200 may include a second front surface wiring inter-wiring insulating layer 226 surrounding the second front surface wiring structure 220. When the second front surface wiring structure 220 has a multilayer wiring structure, the second front surface wiring inter-wiring insulating layer 226 may have a multilayer structure, wherein multiple insulating layers are stacked corresponding to the multilayer wiring structure of the second front surface wiring structure 220. For example, the second front surface wiring inter-wiring insulating layer 226 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), an insulating polymer, or a combination thereof.

[0038] Similar to the case where the second semiconductor chip 200 includes a second front surface wiring structure 220 (including a second front surface wiring pattern 222 and a second front surface wiring via 224) and a second front surface wiring inter-insulating layer 226 surrounding the second front surface wiring structure 220, the first semiconductor chip 100 may include a first front surface wiring structure 120 (including a plurality of first front surface wiring patterns and a plurality of first front surface wiring vias connected to the first front surface wiring patterns) and a first front surface wiring inter-insulating layer surrounding the first front surface wiring structure 120.

[0039] Each of the first through-hole electrode 130 and the second through-hole electrode 230 may include a through-silicon via (TSV). Each of the first through-hole electrode 130 and the second through-hole electrode 230 may include a conductive plug penetrating each of the first semiconductor substrate 110 and the second semiconductor substrate 210, and a conductive barrier layer surrounding the conductive plug. The conductive plug may have a circular shape, and the conductive barrier layer may have a cylindrical shape surrounding the sidewalls of the conductive plug. A via insulating layer may be formed between the first through-hole electrode 130 and the first semiconductor substrate 110 and between the second through-hole electrode 230 and the second semiconductor substrate 210, and may surround the sidewalls of the first through-hole electrode 130 and the second through-hole electrode 230. The first through-hole electrode 130 and the second through-hole electrode 230 may be formed as any of the following structures: via-first, via-middle, and via-later.

[0040] The first rear surface wiring structure 150 and the second rear surface wiring structure 250 may include materials such as aluminum, copper, and tungsten. In some embodiments, the first rear surface wiring structure 150 and the second rear surface wiring structure 250 may include a wiring barrier layer and a wiring metal layer.

[0041] The first rear surface wiring structure 150 may include a plurality of first rear surface wiring patterns 152 and a plurality of first rear surface wiring vias 154 connected to the first rear surface wiring patterns 152. The second rear surface wiring structure 250 may include a plurality of second rear surface wiring patterns 252 and a plurality of second rear surface wiring vias 254 connected to the second rear surface wiring patterns 252. In some embodiments, the thickness of each of the first rear surface wiring patterns 152 and the second rear surface wiring patterns 252 may be equal to or less than about 0.5 μm. In some embodiments, the first rear surface wiring structure 150 may have a multi-layer wiring structure, wherein the first rear surface wiring patterns 152 and the first rear surface wiring vias 154 are located at different vertical heights from each other, and the second rear surface wiring structure may have a multi-layer wiring structure, wherein the second rear surface wiring patterns 252 and the second rear surface wiring vias 254 are located at different vertical heights from each other.

[0042] The first semiconductor chip 100 may include a first rear surface wiring inter-insulation layer 156 surrounding the first rear surface wiring structure 150, while the second semiconductor chip 200 may include a second rear surface wiring inter-insulation layer 256 surrounding the second rear surface wiring structure 250. When the first rear surface wiring structure 150 has a multilayer wiring structure, the first rear surface wiring inter-insulation layer 156 may have a multilayer structure, wherein multiple insulating layers are stacked corresponding to the multilayer wiring structure of the first rear surface wiring structure 150, and when the second rear surface wiring structure 250 has a multilayer wiring structure, the second rear surface wiring inter-insulation layer 256 may have a multilayer structure, wherein multiple insulating layers are stacked corresponding to the multilayer wiring structure of the second rear surface wiring structure 250.

[0043] For example, each of the first back surface inter-wiring insulation layer 156 and the second back surface inter-wiring insulation layer 256 may include SiO, SiN, SiON, an insulating polymer, or a combination thereof. For example, at least a portion of each of the first back surface inter-wiring insulation layer 156 and the second back surface inter-wiring insulation layer 256 may include a polymer formed of photosensitive polyimide (PSPI). For example, each of the first back surface inter-wiring insulation layer 156 and the second back surface inter-wiring insulation layer 256 may have a multilayer structure, including nitride layers and a stack of layers formed of PSPI. Alternatively, for example, each of the first back surface inter-wiring insulation layer 156 and the second back surface inter-wiring insulation layer 256 may have a multilayer structure, including nitride layers and a stack of layers formed of tetraethyl orthosilicate (TEOS). For example, the thickness of each of the first back surface inter-wiring insulation layer 156 and the second back surface inter-wiring insulation layer 256 may be from about 2 μm to about 5 μm.

[0044] The first rear surface cover layer 190 may be formed on the first rear surface wiring structure 150. The first rear surface cover layer 190 may include a first lower rear surface cover layer 192 covering the first rear surface wiring structure 150 and a first upper rear surface cover layer 194 covering the first lower rear surface cover layer 192.

[0045] The second front surface cover layer 280 may be formed on the second front surface wiring structure 220. The second front surface cover layer 280 may include a second lower front surface cover layer 282 covering the second front surface wiring structure 220 and a second upper front surface cover layer 284 covering the second lower front surface cover layer 282.

[0046] The second rear surface cover layer 290 may be formed on the second rear surface wiring structure 250. The second rear surface cover layer 290 may include a second lower rear surface cover layer 292 covering the second rear surface wiring structure 250 and a second upper rear surface cover layer 294 covering the second lower rear surface cover layer 292.

[0047] Each of the first lower rear surface cover layer 192, the second lower front surface cover layer 282, and the second lower rear surface cover layer 292 may include at least one of SiO, SiN, silicon carbonitride (SiCN), and silicon carbide (SiCO). Each of the first upper rear surface cover layer 194, the second upper front surface cover layer 284, and the second upper rear surface cover layer 294 may include at least one of SiO, SiN, SiCN, SiCO, and a polymer material. For example, the polymer material may include benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone resin, acrylate, or epoxy resin. In some embodiments, the first lower rear surface cover layer 192, the second lower front surface cover layer 282, and the second lower rear surface cover layer 292 may be formed of the same material, and the first upper rear surface cover layer 194, the second upper front surface cover layer 284, and the second upper rear surface cover layer 294 may be formed of the same material. In some embodiments, the materials of the first lower rear surface cover 192, the second lower front surface cover 282, and the second lower rear surface cover 292 may be different from the materials of the first upper rear surface cover 194, the second upper front surface cover 284, and the second upper rear surface cover 294.

[0048] A first rear surface pseudo-conductive layer 170 may be formed in a first rear surface cover layer 190, a second front surface pseudo-conductive layer 260 may be formed in a second front surface cover layer 280, and a second rear surface pseudo-conductive layer 270 may be formed in a second rear surface cover layer 290. The first rear surface pseudo-conductive layer 170, the second front surface pseudo-conductive layer 260, and the second rear surface pseudo-conductive layer 270 may be formed to penetrate the first lower rear surface cover layer 192, the second lower front surface cover layer 282, and the second lower rear surface cover layer 292, respectively. In some embodiments, the upper and lower surfaces of each of the first rear surface pseudo-conductive layer 170, the second front surface pseudo-conductive layer 260, and the second rear surface pseudo-conductive layer 270 may be located at the same vertical height, so as to be coplanar with the upper and lower surfaces of each of the first lower rear surface cover layer 192, the second lower front surface cover layer 282, and the second lower rear surface cover layer 292, respectively.

[0049] The first rear surface pseudo-conductive layer 170 may include at least one first rear surface alignment pattern 172 and a plurality of first rear surface pseudo-patterns 175. The second front surface pseudo-conductive layer 260 may include at least one second front surface alignment pattern 262 and a plurality of second front surface pseudo-patterns 265. The second rear surface pseudo-conductive layer 270 may include at least one second rear surface alignment pattern 272 and a plurality of second rear surface pseudo-patterns 275.

[0050] The first rear surface dummy conductive layer 170 and the second front surface dummy conductive layer 260 can be separated from each other, with the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 located therebetween. The second rear surface dummy conductive layer 270 and the second front surface dummy conductive layer 260 can be separated from each other, with the second upper rear surface cover layer 294 and the second upper front surface cover layer 284 located therebetween. The first rear surface alignment pattern 172 and the second front surface alignment pattern 262, which face each other, can overlap each other and can also be separated from each other, with the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 located therebetween.

[0051] The horizontal widths of the first rear surface alignment pattern 172 and the second front surface alignment pattern 262 facing each other can be the same, and the horizontal widths of the second rear surface alignment pattern 272 and the second front surface alignment pattern 262 can also be the same. The second rear surface alignment pattern 272 and the second front surface alignment pattern 262 facing each other can overlap each other and can be separated from each other, with the second upper rear surface cover layer 294 and the second upper front surface cover layer 284 located therebetween.

[0052] The horizontal widths of opening 174 and opening 176 of the first rear surface dummy pattern 175 can be different. The horizontal widths of opening 264 and opening 266 of the second front surface dummy pattern 265 can be different. The horizontal widths of opening 274 and opening 276 of the second rear surface dummy pattern 275 can be different.

[0053] In some embodiments, at least one of the first rear surface alignment pattern 172 and the first rear surface dummy pattern 175 of the first rear surface dummy conductive layer 170, at least one of the second front surface alignment pattern 262 and the second front surface dummy pattern 265 of the second front surface dummy conductive layer 260, and at least one of the second rear surface alignment pattern 272 and the second rear surface dummy pattern 275 of the second rear surface dummy conductive layer 270 may be completely surrounded by an insulating material and be electrically floating. In some embodiments, the openings of at least one of the first rear surface alignment pattern 172 and the first rear surface dummy pattern 175 of the first rear surface dummy conductive layer 170, the openings of at least one of the second front surface alignment pattern 262 and the second front surface dummy pattern 265 of the second front surface dummy conductive layer 260, and the openings of at least one of the second rear surface alignment pattern 272 and the second rear surface dummy pattern 275 of the second rear surface dummy conductive layer 270 may be provided with grounding.

[0054] The corresponding first bonding pad BP1, second through electrode 230, and second connecting pad BP2, with reference to a first through electrode 130, can be aligned vertically and formed on a straight line extending vertically. The corresponding first through electrode 130 and second through electrode 230 can overlap with the corresponding first bonding pad BP1 and second connecting pad BP2 in the vertical direction.

[0055] At least one of the first rear surface alignment pattern 172 and the first rear surface pseudo-pattern 175 in the first rear surface pseudo-conductive layer 170, at least one of the second front surface alignment pattern 262 and the second front surface pseudo-pattern 265 in the second front surface pseudo-conductive layer 260, and at least one of the second rear surface alignment pattern 272 and the second rear surface pseudo-pattern 275 in the second rear surface pseudo-conductive layer 270 may not overlap with the first through electrode 130 and the second through electrode 230 in the vertical direction.

[0056] The first rear surface dummy conductive layer 170, the second front surface dummy conductive layer 260, and the second rear surface dummy conductive layer 270 can be separated from the first bonding pad BP1 and the second connection pad BP2. For example, the first rear surface alignment pattern 172 and the first rear surface dummy pattern 175 of the first rear surface dummy conductive layer 170 can be horizontally separated from each other, with the first bonding pad BP1 and the first lower rear surface cover layer 192 located therebetween. Similarly, the second front surface alignment pattern 262 and the second front surface dummy pattern 265 of the second front surface dummy conductive layer 260 can be horizontally separated from each other, with the first bonding pad BP1 and the second lower front surface cover layer 282 located therebetween. Furthermore, the second rear surface alignment pattern 272 and the plurality of second rear surface dummy patterns 275 of the second rear surface dummy conductive layer 270 can be horizontally separated from each other, with the second bonding pad BP2 and the second lower rear surface cover layer 292 located therebetween. Each of the first rear surface pseudo-conductive layer 170, the second front surface pseudo-conductive layer 260, and the second rear surface pseudo-conductive layer 270 may include a material comprising Cu or a material comprising Al.

[0057] Multiple first bonding pads BP1 can penetrate the first rear surface cover layer 190 and the second front surface cover layer 280, and can be electrically connected to the corresponding first through electrode 130 and second through electrode 230.

[0058] The first bonding pad BP1 can extend into the first rear surface wiring interlayer insulation layer 156, and one end of the first bonding pad BP1 can be electrically connected to the first rear surface wiring structure 150. The first bonding pad BP1 can extend into the second front surface wiring interlayer insulation layer 226, and the other end of the first bonding pad BP1 can be electrically connected to the second front surface wiring structure 220.

[0059] A first rear surface under bump metal (UBM) layer 148 may be formed between one end of the first bonding pad BP1 and the first rear surface wiring structure 150, while a second front surface UBM layer 246 may be formed between the other end of the first bonding pad BP1 and the second front surface wiring structure 220. In some embodiments, one end of the first bonding pad BP1 may contact the first rear surface wiring pattern 152, with the first rear surface UBM layer 148 located therebetween, and the other end of the first bonding pad BP1 may contact the second front surface wiring pattern 222, with the second front surface UBM layer 246 located therebetween.

[0060] A portion of the first bonding pad BP1 that penetrates the first rear surface cover layer 190 and extends into the first rear surface inter-wiring insulation layer 156 can be referred to as the first lower pad unit BP1L, while a portion of the first bonding pad BP1 that penetrates the second front surface cover layer 280 and extends into the second front surface inter-wiring insulation layer 226 can be referred to as the first upper pad unit BP1H. The corresponding first lower pad unit BP1L and first upper pad unit BP1H can be formed as a single unit.

[0061] The second connection pad BP2 can penetrate the second front surface cover layer 280 and the second rear surface cover layer 290, and can be electrically connected to the second through electrode 230 corresponding to the second semiconductor chip 200, respectively.

[0062] Each of the second connection pads BP2 can extend into the second rear surface wiring interlayer insulating layer 256 of the plurality of second semiconductor chips 200, and one end of each of the second connection pads BP2 can be electrically connected to the second rear surface wiring structure 250. Furthermore, each of the second connection pads BP2 can extend into the second front surface wiring interlayer insulating layer 226 of another second semiconductor chip 200 vertically adjacent to the aforementioned second semiconductor chip 200, and the other end of each of the second connection pads BP2 can be electrically connected to the second front surface wiring structure 220.

[0063] The second semiconductor chip UBM layer 248 can be formed between one end of each of the second connection pads BP2 and the second rear surface wiring structure 250 of the second semiconductor chip 200 among the plurality of second semiconductor chips 200, while the second front surface UBM layer 246 can be formed between the other end of each of the second connection pads BP2 and the second front surface wiring structure 220 of another second semiconductor chip 200 that is vertically adjacent to the aforementioned second semiconductor chip 200. In some embodiments, one end of each of the second connection pads BP2 can contact the second semiconductor chip UBM layer 248 and can contact the second rear surface wiring pattern 252 of the second semiconductor chip 200 among the plurality of second semiconductor chips 200, while the other end of each of the second connection pads BP2 can contact the second front surface UBM layer 246 and can contact the second front surface wiring pattern 222 of another second semiconductor chip 200 among the plurality of second semiconductor chips 200.

[0064] A portion of each of the second bonding pads BP2 that penetrates the second rear surface cover layer 290 and extends into the second rear surface inter-wiring insulation layer 256 can be referred to as a second lower pad unit BP2L, while a portion of each of the second bonding pads BP2 that penetrates the second front surface cover layer 280 and extends into the second front surface inter-wiring insulation layer 226 can be referred to as a second upper pad unit BP2H. The corresponding second lower pad units BP2L and second upper pad units BP2H can be formed as a single unit.

[0065] For example, the first bonding pad BP1 and the second connection pad BP2 may include a material containing Cu.

[0066] Each of the first bonding pads BP1 can be formed by the following process: separately forming a portion of a first rear surface capping layer 190 penetrating the first semiconductor chip 100 and a portion of a second front surface capping layer 280 penetrating the second semiconductor chip 200, then using heat to expand and bond these portions, and then using the diffusion of metal atoms in these portions to perform diffusion bonding, so that these portions are formed as a single unit. Each of the second bonding pads BP2 can be formed by the following process: separately forming a portion of a second rear surface capping layer 290 penetrating one of the plurality of second semiconductor chips 200 and a portion of a second front surface capping layer 280 penetrating another of the plurality of second semiconductor chips 200 vertically adjacent to the first semiconductor chip 200, then using heat to expand and bond these portions, and then using the diffusion of metal atoms in these portions to perform diffusion bonding, so that these portions are formed as a single unit.

[0067] In some embodiments, the first upper rear surface cover layer 194 of the first semiconductor chip 100 and the second upper front surface cover layer 284 of the second semiconductor chip 200 that are in contact with each other can be bonded to each other in the process of forming the first bonding pad BP1 to form an integrated first bonding cover layer BI1, and the second upper rear surface cover layer 294 and the second upper front surface cover layer 284 of each of the two second semiconductor chips 200 that are in contact with each other can be bonded to each other in the process of forming the second bonding pad BP2 to form an integrated second bonding cover layer BI2.

[0068] The first lower rear surface cover layer 192 may have a first thickness T1, while the first upper rear surface cover layer 194 may have a second thickness T2. The first thickness T1 may have a value equal to or greater than the second thickness T2. For example, the first thickness T1 may have a value of about 50% to about 70% of the sum of the first thickness T1 and the second thickness T2. The second upper front surface cover layer 284 may have a third thickness T3, while the second lower front surface cover layer 282 may have a fourth thickness T4. The fourth thickness T4 may have a value equal to or greater than the third thickness T3. For example, the fourth thickness T4 may have a value of about 50% to about 70% of the sum of the third thickness T3 and the fourth thickness T4. The second lower rear surface cover layer 292 may have a fifth thickness T1a, while the second upper rear surface cover layer 294 may have a sixth thickness T2a. The fifth thickness T1a may have a value equal to or greater than the sixth thickness T2a. For example, the fifth thickness T1a may have a value of about 50% to about 70% of the sum of the fifth thickness T1a and the sixth thickness T2a.

[0069] In some embodiments, the first thickness T1 and the fifth thickness T1a may be substantially the same, while the second thickness T2 and the sixth thickness T2a may be substantially the same. In some embodiments, the first thickness T1 and the fourth thickness T4 may be substantially the same, while the second thickness T2 and the third thickness T3 may be substantially the same. For example, each of the first thickness T1, the fourth thickness T4, and the fifth thickness T1a may be in the range of about 0.2 μm to about 1 μm. For example, the sum of the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 may be in the range of about 0.7 μm to about 4 μm. For example, the sum of the fifth thickness T1a, the sixth thickness T2a, the third thickness T3, and the fourth thickness T4 may be in the range of about 0.7 μm to about 4 μm.

[0070] The lower surface of the first bonding pad BP1 can be located at a first vertical height LV1, the lower surface of the first rear surface pseudo-conductive layer 170 can be located at a second vertical height LV2 that is higher than the first vertical height LV1, the upper surface of the second front surface pseudo-conductive layer 260 of the second semiconductor chip 200 adjacent to the first semiconductor chip 100 can be located at a third vertical height LV3 that is higher than the second vertical height LV2, and the upper surface of the first bonding pad BP1 can be located at a fourth vertical height LV4 that is higher than the third vertical height LV3.

[0071] Between two adjacent second semiconductor chips 200, the lower surface of the second connection pad BP2 may be located at a fifth vertical height LV1a, the lower surface of the second rear surface dummy conductive layer 270 may be located at a sixth vertical height LV2a, which is higher than the fifth vertical height LV1a, the upper surface of the second front surface dummy conductive layer 260 may be located at a seventh vertical height LV3a, which is higher than the sixth vertical height LV2a, and the upper surface of the second connection pad BP2 may be located at an eighth vertical height LV4a, which is higher than the seventh vertical height LV3a. In some embodiments, the height of each of the second vertical height LV2, the third vertical height LV3, and the fourth vertical height LV4, with reference to the first vertical height LV1, may be substantially the same as the height of each of the sixth vertical height LV2a, the seventh vertical height LV3a, and the eighth vertical height LV4a, with reference to the fifth vertical height LV1a.

[0072] The first bonding pad BP1 may have a first height H1, while the second connection pad BP2 may have a second height H2. In some embodiments, the first height H1 and the second height H2 may be substantially the same. For example, each of the first height H1 and the second height H2 may be in the range of about 0.8 μm to about 4.2 μm. The horizontal width of each of the first bonding pad BP1 and the second connection pad BP2 may be in the range of about 0.5 μm to about 8 μm.

[0073] The first rear surface dummy conductive layer 170 may have a first thickness T1, the second front surface dummy conductive layer 260 may have a fourth thickness T4, and the second rear surface dummy conductive layer 270 may have a fifth thickness T1a. In some embodiments, the sum of the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 may be less than the first height H1, and the sum of the fifth thickness T1a, the sixth thickness T2a, the third thickness T3, and the fourth thickness T4 may be less than the second height H2. In some embodiments, the first height H1 may be equal to or less than twice the sum of the first thickness T1 and the fourth thickness T4, and the second height H2 may be equal to or less than twice the sum of the fifth thickness T1a and the fourth thickness T4. The horizontal width of each of the first rear surface alignment pattern 172, the second front surface alignment pattern 262, and the second rear surface alignment pattern 272 may be in the range of about 20 μm to about 50 μm. The horizontal width of each of the first rear surface pseudo-pattern 175, the second front surface pseudo-pattern 265, and the second rear surface pseudo-pattern 275 may be smaller than the horizontal width of each of the first rear surface alignment pattern 172, the second front surface alignment pattern 262, and the second rear surface alignment pattern 272.

[0074] The first rear surface pseudo-conductive layer 170 and the first bonding pad BP1 can overlap each other in the horizontal direction, and the second front surface pseudo-conductive layer 260 and the first bonding pad BP1 or the second connection pad BP2 can overlap each other in the horizontal direction, and the second rear surface pseudo-conductive layer 270 and the second connection pad BP2 can overlap each other in the horizontal direction.

[0075] In the semiconductor package 1000 according to an embodiment, the first rear surface pseudo-conductive layer 170 and the second front surface pseudo-conductive layer 260, which are corresponding to each other, can be separated from each other, with a first bonding cover layer BI1, including a first upper rear surface cover layer 194 and a second upper front surface cover layer 284, located therebetween. Similarly, the second front surface pseudo-conductive layer 260 and the second rear surface pseudo-conductive layer 270, which are corresponding to each other, can be separated from each other, with a second bonding cover layer BI2, including a second upper rear surface cover layer 294 and a second upper front surface cover layer 284, located therebetween. It should be noted that in the process of forming the first rear surface alignment pattern 172, the second front surface alignment pattern 262, and the second rear surface alignment pattern 272, which have relatively large widths, due to recesses, one or more patterns with relatively large depths (equal to or greater than) may be generated. The recessed portion of the semiconductor package 1000 is filled with a first upper rear surface cover layer 194, a second upper front surface cover layer 284, and a second upper rear surface cover layer 294. This prevents the formation of voids inside the semiconductor package 1000 and thus improves the reliability of the semiconductor package 1000.

[0076] Figures 3A to 3GThe images show cross-sectional views of a semiconductor package manufacturing method according to an embodiment. Figures 3A to 3G Is with Figure 1 An enlarged cross-sectional view of the portion corresponding to region IIa in the diagram.

[0077] Reference Figure 3A The first rear surface wiring structure 150, the first semiconductor element 112, and the first through electrode 130 connected to the first through electrode 130 can be formed in the first semiconductor substrate 110.

[0078] The first through electrode 130 can penetrate the first semiconductor substrate 110. The first semiconductor element 112 can be formed on the first active surface of the first semiconductor substrate 110, while the first back surface wiring structure 150 can be formed on the first passive surface of the first semiconductor substrate 110.

[0079] The first rear surface wiring structure 150 may include a first rear surface wiring pattern 152 and a first rear surface wiring via 154 connected to the first rear surface wiring pattern 152, and may be surrounded by a first rear surface inter-wiring insulating layer 156. The first rear surface wiring structure 150 may be formed to connect a first through electrode 130 to a portion of the first rear surface wiring pattern 152. A portion of the first rear surface inter-wiring insulating layer 156 may be removed to expose another portion of the first rear surface wiring pattern 152. A first rear surface UBM layer 148 may be formed on the other portion of the first rear surface wiring pattern 152 that is not covered by the first rear surface inter-wiring insulating layer 156 but is exposed. The first rear surface UBM layer 148 may be formed to cover the other portion of the first rear surface wiring pattern 152 and a portion of the adjacent first rear surface inter-wiring insulating layer 156. In some embodiments, the minimum height of the upper surface of the first rear surface UBM layer 148 may be lower than the height of the upper surface of the first rear surface inter-wiring insulating layer 156.

[0080] Reference Figure 3B A first lower rear surface capping layer 192 can be formed to cover the first rear surface wiring structure 150, the first rear surface inter-wiring insulation layer 156, and the first rear surface UBM layer 148. The first lower rear surface capping layer 192 may include at least one of SiO, SiN, SiCN, and SiCO. The first lower rear surface capping layer 192 may be formed with a thickness in the range of about 0.2 μm to about 1 μm.

[0081] Reference Figure 3CBy removing a portion of the first lower rear surface cover layer 192, a plurality of first holes 192H are formed to expose the first rear surface wiring insulation layer 156 on the lower surface of the first holes 192H, and a first rear surface dummy conductive layer 170 can be formed to fill the first holes 192H. The first rear surface dummy conductive layer 170 may include at least one first rear surface alignment pattern 172 and a first rear surface dummy pattern 175. The horizontal widths of the opening 174 and the other opening 176 of the first rear surface dummy pattern 175 may be different from each other. The first rear surface dummy conductive layer 170 may include a material comprising Cu or Al. The horizontal width of at least one first rear surface alignment pattern 172 may be in the range of about 20 μm to about 50 μm. The first rear surface dummy pattern 175 may have a variety of different horizontal widths.

[0082] In some embodiments, a first rear surface pseudo-conductive layer 170 can be formed by filling the first hole 192H with a first conductive material layer and then performing an inlay process to remove a portion of the first conductive material layer, thereby exposing the upper surface of the first lower rear surface cover layer 192.

[0083] Reference Figure 3D A first upper rear surface capping layer 194 can be formed to cover the first lower rear surface capping layer 192 and the first rear surface pseudo-conductive layer 170. The first upper rear surface capping layer 194 may include at least one of SiO, SiN, SiCN, SiCO and polymer materials. The first upper rear surface capping layer 194 may be formed with a thickness equal to or less than the thickness of the first lower rear surface capping layer 192.

[0084] The first lower rear surface cover layer 192 and the first upper rear surface cover layer 194 may be collectively referred to as the first rear surface cover layer 190. In some embodiments, when the first lower rear surface cover layer 192 and the first upper rear surface cover layer 194 comprise the same material, the first lower rear surface cover layer 192 and the first upper rear surface cover layer 194 may be indistinguishable from each other, and the first rear surface cover layer 190 may be formed integrally by an inlay process.

[0085] Reference Figure 3E A portion of the first upper rear surface capping layer 194 and the first lower rear surface capping layer 192 can be removed to form a plurality of second holes 194H, exposing the first rear surface UBM layer 148 on the lower surface of the second holes 194H, and a second conductive material layer 144P can fill the second holes 194H to cover the first upper rear surface capping layer 194. The horizontal width of each of the second holes 194H can be in the range of about 0.5 μm to about 8 μm. The second conductive material layer 144P can be formed of a material including Cu.

[0086] Reference Figure 3E and Figure 3FA dicing process can be performed to remove a portion of the second conductive material layer 144P, thereby exposing the upper surface of the first upper rear surface capping layer 194, and a first semiconductor chip 100 including a plurality of first rear surface connection pads 144 filling the second hole 194H can be formed.

[0087] In some embodiments, during the formation of the first rear surface connection pad 144, a dishing phenomenon may occur, causing excessive removal of the second conductive material layer 144P below the upper surface of the first upper rear surface capping layer 194. Therefore, a first dishing recess 144D may be formed on the upper surface of the first rear surface connection pad 144. In some embodiments, the lowest portion of the upper surface of the first rear surface connection pad 144 may be approximately 40 to approximately 80 angstroms lower than the upper surface of the first upper rear surface capping layer 194.

[0088] Reference Figure 3G By reference Figures 3A to 3F The described manufacturing method can prepare a second semiconductor chip 200. The second semiconductor chip 200 may include: a second front surface cover layer 280, which includes a second lower front surface cover layer 282 covering a second front surface wiring structure 220 and a second upper front surface cover layer 284 covering the second lower front surface cover layer 282; a second front surface pseudo-conductive layer 260 penetrating the second lower front surface cover layer 282 and including at least one second front surface alignment pattern 262 and a second front surface pseudo-pattern 265; and a plurality of second front surface connection pads 242 penetrating the second front surface cover layer 280 and connected to the second front surface UBM layer 246.

[0089] Subsequently, the second semiconductor chip 200 can be attached to the first semiconductor chip 100 such that the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 are in contact with each other, and the first rear surface bonding pad 144 and the second front surface bonding pad 242 correspond to each other. In the process of attaching the second semiconductor chip 200 to the first semiconductor chip 100, the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 can be bonded to each other by applying heat and / or pressure. In some embodiments, the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 can be bonded in a shared combination manner. In some other embodiments, the first upper rear surface cover layer 194 and the second upper front surface cover layer 284 can form an integrated first bonding cover layer B11. For example, heat at a first temperature can be applied in the process of attaching the second semiconductor chip 200 to the first semiconductor chip 100.

[0090] Subsequently, the first rear surface connection pad 144 and the second front surface connection pad 242 are bonded to each other by applying heat at a second temperature higher than the first temperature. After the corresponding first rear surface connection pad 144 and second front surface connection pad 242 are heated and expanded and bonded to each other, a first bonding pad BP1 can be formed, which has been diffusely bonded by the diffusion of the metal atoms included therein to form a single unit.

[0091] The first rear surface bonding pad 144 can correspond to the first lower pad unit BP1L of the first bonding pad BP1, while the second front surface bonding pad 242 can correspond to the first upper pad unit BP1H of the first bonding pad BP1.

[0092] The second front surface UBM layer 246, the second front surface capping layer 280, the second front surface dummy conductive layer 260, and the second front surface connection pad 242 formed on the second active surface of the second semiconductor substrate 210 can be formed using a method similar to that used to form the first rear surface UBM layer 148, the first rear surface capping layer 190, the first rear surface dummy conductive layer 170, and the first rear surface connection pad 144 on the first passive surface of the first semiconductor substrate 110. The second front surface connection pad 242 may also include a second dish-shaped recess 242D similar to the first dish-shaped recess 144D in the first rear surface connection pad 144.

[0093] Furthermore, a method similar to that used to form the first rear surface connection pad 144 corresponding to the first rear surface UBM layer 148, the first rear surface capping layer 190, the first rear surface pseudo-conductive layer 170, and the first lower pad unit BP1L on the first passive surface of the first semiconductor substrate 110 can be used to form the first rear surface connection pad 144. Figure 2B The portion corresponding to the second rear surface semiconductor chip UBM layer 248, the second rear surface capping layer 290, the second rear surface pseudo-conductive layer 270, and the second lower pad unit BP2L shown in the diagram. Furthermore, the second bonding pad BP2 can also be formed in a similar manner to the first bonding pad BP1, thus enabling the formation of... Figures 1 to 2B The semiconductor package shown is 1000.

[0094] Refer to together Figures 1 to 3G According to an embodiment, in the process of forming the first rear surface alignment pattern 172, the second front surface alignment pattern 262, and the second rear surface alignment pattern 272, even if one or more recesses with a relatively large depth of about 100 angstroms are generated due to the dishing phenomenon, the recesses can be filled by the first upper rear surface cover layer 194, the second upper front surface cover layer 284, and the second upper rear surface cover layer 294. Therefore, it is possible to prevent the formation of voids inside the semiconductor package 1000 and to improve the reliability of the semiconductor package 1000.

[0095] Figure 4 This is a cross-sectional view of the semiconductor package 2000 according to an embodiment.

[0096] Reference Figure 4 The semiconductor package 2000 may include a motherboard 600 on which an interposer 500 is mounted, at least one sub-semiconductor package 1000 attached to the interposer 500 and including a first semiconductor chip 100 and a second semiconductor chip 200, and a third semiconductor chip 400. The sub-semiconductor package 1000 may be... Figure 1 The semiconductor package 1000 shown is referenced together. Figure 1 Semiconductor package 1000 is described. Furthermore, semiconductor package 2000 can be referred to as a system.

[0097] The sub-semiconductor package 1000 can be attached to the interposer layer 500 via a plurality of first connection bumps 160. The first connection bumps 160 can be attached to first front surface pads 142 and can be electrically connected to the first front surface wiring structure 120 of the first semiconductor chip 100. The first connection bumps 160 can provide at least one of signal, power or ground to the sub-semiconductor package 1000.

[0098] exist Figure 4 In the diagram, semiconductor package 2000 is shown as including two sub-semiconductor packages 1000. For example, semiconductor package 2000 may include one sub-semiconductor package 1000, or three or more sub-semiconductor packages 1000.

[0099] The third semiconductor chip 400 may include a third semiconductor substrate 410 (on which a third semiconductor element 412 is formed) and a plurality of upper surface connection pads 420. In some embodiments, each of the upper surface connection pads 420 may include at least one of Al, Cu, and Ni. The third semiconductor chip 400 may be attached to the interposer 500 via a plurality of second connection bumps 460. The second connection bumps 460 may be attached to the upper surface connection pads 420. The third semiconductor chip 400 may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0100] The third semiconductor substrate 410 can be... Figure 1 The third semiconductor element 412 may be a component substantially similar to the first semiconductor substrate 110 or the second semiconductor substrate 210 shown. Figure 1The components shown, such as the first semiconductor element 112 or the second semiconductor element 212, are generally similar to each other, and the second connecting bump 460 may be generally similar to the first connecting bump 160; therefore, their detailed description is omitted.

[0101] Intermediate layer 500 may include a base layer 510, a plurality of first upper surface pads 522 and a plurality of first lower surface pads 524 formed on the upper and lower surfaces of the base layer 510, respectively, and a plurality of first wiring paths 530 electrically connecting the first upper surface pads 522 to the first lower surface pads 524 via the base layer 510. The base layer 510 may include a semiconductor material, glass, ceramic, or plastic. For example, the base layer 510 may include silicon. In the wiring layer and / or base layer 510 connected to the first upper surface pads 522 and / or the first lower surface pads 524 on the upper and / or lower surfaces of the base layer 510, the first wiring paths 530 may include internal through electrodes electrically connecting the first upper surface pads 522 to the first lower surface pads 524. The first upper surface pads 522 may be connected to a first connection bump 160 electrically connecting the sub-semiconductor package 1000 to the intermediate layer 500, and a second connection bump 460 electrically connecting the third semiconductor chip 400 to the intermediate layer 500.

[0102] A first bottom filler layer 380 may be formed between the semiconductor package 1000 and the interposer layer 500, while a second bottom filler layer 480 may be formed between the third semiconductor chip 400 and the interposer layer 500. The first bottom filler layer 380 and the second bottom filler layer 480 may surround the first connecting bump 160 and the second connecting bump 460, respectively.

[0103] The semiconductor package 2000 may further include a packaging molding layer 900 surrounding the side surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400 on an interposer 500. The packaging molding layer 900 may include, for example, an epoxy molding compound (EMC). In some embodiments, the packaging molding layer 900 may cover the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. In some other embodiments, the packaging molding layer 900 may not cover the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. For example, a heat dissipation member may be attached to the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400, with a thermal interface material (TIM) located therebetween.

[0104] Multiple board connection terminals 540 can be attached to the first lower surface pad 524. The board connection terminals 540 can electrically connect the interposer layer 500 to the motherboard 600.

[0105] The motherboard 600 may include a substrate layer 610, a plurality of second upper surface pads 622 and a plurality of second lower surface pads 624 formed on the upper and lower surfaces of the substrate layer 610, respectively, and a plurality of second wiring paths 630 electrically connecting the second upper surface pads 622 to the second lower surface pads 624 via the substrate layer 610.

[0106] In some embodiments, motherboard 600 may include a printed circuit board. For example, motherboard 600 may include a multilayer printed circuit board. Substrate layer 610 may include at least one material selected from phenolic resin, epoxy resin, and polyimide.

[0107] Solder mask layers (not shown) exposing the second upper surface pad 622 and the second lower surface pad 624 can be formed on the upper and lower surfaces of the substrate layer 610, respectively. Board connection terminals 540 can be connected to the second upper surface pad 622, while external connection terminals 640 can be connected to the second lower surface pad 624. Board connection terminals 540 can electrically connect the first lower surface pad 524 to the second upper surface pad 622. The external connection terminals 640 connected to the second lower surface pad 624 can be connected to the outside of the semiconductor package 2000.

[0108] In some embodiments, the semiconductor package 2000 may not include the motherboard 600, and the board connection terminal 540 may perform the function of an external connection terminal.

[0109] Figure 5 This is a cross-sectional view of the semiconductor package 3000 according to an embodiment, and Figure 6 This is its enlarged cross-sectional view. Figure 6 yes Figure 5 Enlarged cross-sectional view of region VI in the middle. Figure 5 and Figure 6 References are omitted in the text. Figures 1 to 2B The given description is repetitive.

[0110] Reference Figure 5 and Figure 6The semiconductor package 3000 may include a first semiconductor chip 100a and at least one second semiconductor chip 200a / 200b. The semiconductor package 3000 may be referred to as a sub-semiconductor package. At least one second semiconductor chip 200a / 200b may include a second even semiconductor chip 200a and a second odd semiconductor chip 200b. Each of the second even semiconductor chip 200a and the second odd semiconductor chip 200b may be attached to the first semiconductor chip 100a. In some embodiments, the second even semiconductor chip 200a and the second odd semiconductor chip 200b may be separate from each other and may be stacked on the first semiconductor chip 100a. In some embodiments, the second even semiconductor chip 200a and the second odd semiconductor chip 200b may include semiconductor chips of the same type. In other embodiments, the second even semiconductor chip 200a and the second odd semiconductor chip 200b may include semiconductor chips of different types.

[0111] exist Figure 5 In this embodiment, semiconductor package 3000 is shown to include a first semiconductor chip 100 and two second semiconductor chips 200a / 200b (i.e., a second even semiconductor chip 200a and a second odd semiconductor chip 200b), but the embodiment is merely exemplary and is not limited thereto. In some embodiments, semiconductor package 3000 may include a second semiconductor chip mounted on a first semiconductor chip. In some other embodiments, semiconductor package 3000 may include three or more second semiconductor chips mounted on a first semiconductor chip. In another embodiment, semiconductor package 3000 may include one, two or more second semiconductor chips stacked on top of two or more first semiconductor chips.

[0112] In addition to the first semiconductor chip 100a including a plurality of first even bonding pads BP1a and a plurality of first odd bonding pads BP1b corresponding to the second semiconductor chip 200a and the second semiconductor chip 200b respectively, such that two or more second semiconductor chips 200a / 200b (e.g., second even semiconductor chip 200a and second odd semiconductor chip 200b) are attached to the upper surface of the first semiconductor chip 100a, the first semiconductor chip 100a can be coupled with... Figures 1 to 2A The first semiconductor chip 100 shown is identical, therefore its detailed description is omitted.

[0113] In each of the first mating pads BP1a, a portion penetrating the first rear surface cover layer 190 and extending into the first rear surface inter-wiring insulation layer 156 may be referred to as a first lower pad unit BP1L, while a portion penetrating the second front surface cover layer 280 of the second mating semiconductor chip 200a and extending into the second front surface inter-wiring insulation layer 226 may be referred to as a first upper pad unit BP1Ha. The corresponding first lower pad units BP1L and first upper pad units BP1Ha may be formed integrally. Although not shown separately, each of the plurality of first odd-pair pads BP1b may include an integrally formed first lower pad unit BP1L and first upper odd-pair pad unit.

[0114] The second even-signal semiconductor chip 200a and the second odd-signal semiconductor chip 200b may respectively include a second even-signal semiconductor element 212a and a second odd-signal semiconductor element 212b, and may be coupled with... Figure 1 The uppermost second semiconductor chip 200 shown is substantially similar to or identical to the second semiconductor chip 200 shown, therefore a detailed description thereof is omitted; this uppermost second semiconductor chip 200 does not include the second through electrode 230. The second even semiconductor element 212a and the second odd semiconductor element 212b can be used with... Figures 1 to 2B The second semiconductor element 212 shown is the same as or similar to the one shown.

[0115] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor package according to an example embodiment. Figure 7 yes Figure 5 Enlarged cross-sectional view of region VI.

[0116] Reference Figure 7 , in order to refer to Figures 3A to 3GA second dipole semiconductor chip 200a can be fabricated in a manner similar to the given description. The second dipole semiconductor chip 200a may include a second front surface capping layer 280, wherein a second lower front surface capping layer 282 covers the second front surface wiring structure 220, and a second upper front surface capping layer 284 covers the second lower front surface capping layer 282. The second dipole semiconductor chip 200a may also include a second front surface pseudo-conductive layer 260 penetrating the second lower front surface capping layer 282 and including at least one second front surface alignment pattern 262 and a second front surface pseudo-pattern 265. Furthermore, the second dipole semiconductor chip 200a may include a plurality of dipole front surface connection pads 242a penetrating the second front surface capping layer 280 and connected to the second front surface UBM layer 246. The first rear surface connection pad 144 may correspond to the first lower pad unit BP1L of the first bonding pad BP1, and the second front surface connection pads 242 may correspond to the first dipole upper pad unit BP1Ha of the first dipole bonding pad BP1a. The second matte front surface connection pad 242a may also include a second matte disc-shaped recess 242Da similar to the first disc-shaped recess 144D in the first rear surface connection pad 144.

[0117] Subsequently, the second dipole semiconductor chip 200a can be attached to the first semiconductor chip 100a, such that the first upper rear surface capping layer 194 and the second upper front surface capping layer 284 are in contact with each other, and the first rear surface connection pad 144 and the second dipole front surface connection pad 242a are in contact with each other. The corresponding first rear surface connection pad 144 and second dipole front surface connection pad 242a can be bonded to each other to form a first dipole bonding pad BP1a.

[0118] Similar to attaching a second even semiconductor chip 200a to a first semiconductor chip 100a, a second odd semiconductor chip 200b can be attached to the first semiconductor chip 100a, and can form... Figure 5 The first odd-joint pad BP1b is shown.

[0119] Figure 8 and Figure 9 These are cross-sectional views of semiconductor packages 4000 and 5000 according to embodiments.

[0120] Reference Figure 8 Semiconductor package 4000 may include upper semiconductor package 4020 stacked on lower semiconductor package 4010. Semiconductor package 4000 may be a stacked package (PoP).

[0121] The lower semiconductor package 4010 may include a support wiring structure 4100, an extension layer 4160 formed on the support wiring structure 4100, a sub-semiconductor package 3000 formed in the extension layer 4160, and a cover wiring structure 4200 formed on the extension layer 4160. The sub-semiconductor package 3000 may be... Figure 5 and Figure 6 The semiconductor package shown is 3000.

[0122] The lower semiconductor package 4010 may include a fan-out semiconductor package, wherein the horizontal width and planar area of ​​each of the support wiring structure 4100 and the cover wiring structure 4200 are greater than the horizontal width and planar area of ​​the sub-semiconductor package 3000, respectively. In some embodiments, the horizontal width and planar area of ​​the support wiring structure 4100 may be the same as the horizontal width and planar area of ​​the cover wiring structure 4200. In some embodiments, the corresponding side surfaces of the support wiring structure 4100, the extension layer 4160, and the cover wiring structure 4200 may be coplanar with each other.

[0123] The supporting cabling structure 4100 can be referred to as the lower cabling structure or the first cabling structure, while the covering cabling structure 4200 can be referred to as the upper cabling structure or the second cabling structure.

[0124] The supporting wiring structure 4100 and the covering wiring structure 4200 may include, for example, a printed circuit board, a ceramic plate, a package manufacturing wafer, or an interposer. In some embodiments, the supporting wiring structure 4100 and the covering wiring structure 4200 may include a multilayer printed circuit board. When the supporting wiring structure 4100 includes a printed circuit board (PCB), the supporting wiring structure 4100 may be referred to as a supporting PCB, a lower PCB, or a first PCB. When the covering wiring structure 4200 includes a PCB, the covering wiring structure 4200 may also be referred to as a covering PCB, an upper PCB, or a second PCB.

[0125] The supporting wiring structure 4100 may include at least one first substrate insulating layer 4110 and a plurality of first wiring patterns 4120. The covering wiring structure 4200 may include at least one second substrate insulating layer 4210 and a plurality of second wiring patterns 4220. The first substrate insulating layer 4110 and the second substrate insulating layer 4210 may include at least one of phenolic resin, epoxy resin and polyimide.

[0126] The first wiring pattern 4120 may include a first upper surface wiring pattern formed on the upper surface of at least one first base insulating layer 4110 and including a plurality of first upper surface pads 4122, a first lower surface wiring pattern formed on the lower surface of the first base insulating layer 4110 and including a plurality of first lower surface pads 4124, and a plurality of first conductive vias 4128 penetrating at least one first base insulating layer 4110 and electrically connecting the first wiring patterns 4120 formed on different wiring layers in the first base insulating layer 4110. In some embodiments, when the supporting wiring structure 4100 includes a first base insulating layer 4110, the first wiring pattern 4120 may further include a first internal wiring pattern 4126 forming a wiring layer between two adjacent first base insulating layers 4110.

[0127] The second wiring pattern 4220 may include a second upper surface wiring pattern formed on the upper surface of at least one second base insulating layer 4210 and including a plurality of second upper surface pads 4222, a second lower surface wiring pattern formed on the lower surface of at least one second base insulating layer 4210 and including a plurality of second lower surface pads 4224, and a plurality of second conductive vias 4228 that penetrate at least one second base insulating layer 4210 and electrically connect the second wiring patterns 4220 on different wiring layers to each other. The first wiring pattern 4120 and the second wiring pattern 4220 may include at least one of Cu, Ni, stainless steel and beryllium copper.

[0128] The supporting wiring structure 4100 may further include a first solder mask layer 4130 on its upper and lower surfaces. The first solder mask layer 4130 may include a first upper surface solder mask layer 4132 covering the upper surface of at least one first base insulating layer 4110 and exposing a first upper surface pad 4122, and a first lower surface solder mask layer 4134 covering the lower surface of at least one first base insulating layer 4110 and exposing a first lower surface pad 4124. In some embodiments, the first lower surface solder mask layer 4134 may be formed, but the first upper surface solder mask layer 4132 may not be formed.

[0129] The overlay wiring structure 4200 may further include a second solder mask layer 4230 on its upper and lower surfaces. The second solder mask layer 4230 may include a second upper surface solder mask layer 4232 covering the upper surface of at least one second substrate insulating layer 4210 and exposing a second upper surface wiring pattern on a second upper surface pad 4222, and a second lower surface solder mask layer 4234 covering the lower surface of at least one second substrate insulating layer 4210 and exposing a second lower surface wiring pattern on a second lower surface pad 4224.

[0130] Multiple first chip connection terminals 4018 may be formed between the first upper surface pad 4122 and the first front surface pad 142, electrically connecting the sub-semiconductor package 3000 to the support wiring structure 4100. For example, the first chip connection terminals 4018 may include solder balls or bumps. In some embodiments, an underfill layer 4055 surrounding the first chip connection terminals 4018 may be formed between the sub-semiconductor package 3000 and the support wiring structure 4100. In some embodiments, the underfill layer 4055 may include a non-conductive film (NCF).

[0131] The semiconductor package 4000 may include a plurality of external connection terminals 4150 attached to a first lower surface pad 4124. For example, the height of each of the external connection terminals 4150 may be approximately 150 μm. For example, the external connection terminals 4150 may include solder balls.

[0132] The extension layer 4160 may include a plurality of connection structures 4162, a filler member 4164 surrounding the connection structures 4162, and a sub-semiconductor package 3000. The filler member 4164 may fill the space between the support wiring structure 4100 and the cover wiring structure 4200, and surround the sub-semiconductor package 3000. The connection structures 4162 may be separate from the sub-semiconductor package 3000 and formed around it. The connection structures 4162 may penetrate the filler member 4164 and electrically connect the space between the support wiring structure 4100 and the cover wiring structure 4200. The upper and lower ends of each of the connection structures 4162 may contact and connect to any one of the second lower surface pads 4224 of the cover wiring structure 4200 and any one of the plurality of first upper surface pads 4122 of the support wiring structure 4100.

[0133] The upper semiconductor package 4020 may include at least one third semiconductor chip 400a. The upper semiconductor package 4020 may be electrically connected to the lower semiconductor package 4010 via a plurality of package connection terminals 4550 attached to a second upper surface pad 4222 of the lower semiconductor package 4010.

[0134] The third semiconductor chip 400a may include a third semiconductor substrate 410a and a plurality of chip connection pads 420a formed on the active surface of the third semiconductor substrate 410a, the third semiconductor substrate 410a including third semiconductor elements 412a formed on its active surface. At least one third semiconductor chip 400a may include a memory semiconductor chip.

[0135] exist Figure 8In the embodiment, at least one third semiconductor chip 400a in the upper semiconductor package 4020 is shown mounted on the package substrate 4500 using a flip-chip method; however, this embodiment is exemplary and not limited thereto. As the upper semiconductor package, the semiconductor package 4000 may include all types of semiconductor packages, including at least one third semiconductor chip 400a, and package connection terminals 4550 may be attached to the underside of the semiconductor package 4000 for electrical connection to the lower semiconductor package 4010.

[0136] The packaging substrate 4500 may include a substrate layer 4510 and a plurality of board pads 4520 disposed on the upper and lower surfaces of the substrate layer 4510. The board pads 4520 may include a plurality of upper surface pads 4522 formed on the upper surface of the substrate layer 4510 and a plurality of lower surface pads 4524 formed on the lower surface of the substrate layer 4510. In some embodiments, the packaging substrate 4500 may include a PCB. A solder mask layer 4530 exposing the board pads 4520 may be formed on the upper and lower surfaces of the substrate layer 4510. The solder mask layer 4530 may include an upper solder mask layer 4532 covering the upper surface of the substrate layer 4510 and exposing the upper surface pads 4522, and a lower solder mask layer 4534 covering the lower surface of the substrate layer 4510 and exposing the lower surface pads 4524.

[0137] The packaging substrate 4500 may include board wiring 4540 in the substrate layer 4510 that electrically connects the upper surface pad 4522 to the lower surface pad 4524. The board wiring 4540 may include board wiring and board wiring vias.

[0138] The on-board surface pads 4522 can be electrically connected to the third semiconductor chip 400a. For example, a plurality of second chip connection terminals 460a can be formed between the chip connection pads 420a of the third semiconductor chip 400a and the on-board surface pads 4522 of the package substrate 4500, and can electrically connect the third semiconductor chip 400a to the package substrate 4500. In some embodiments, a second underfill layer 4450 surrounding the second chip connection terminals 460a can be formed between the third semiconductor chip 400a and the package substrate 4500. The second underfill layer 4450 may comprise, for example, an epoxy resin formed using a capillary underfill method.

[0139] A molding layer 4490 surrounding the third semiconductor chip 400a can be formed on the packaging substrate 4500. The molding layer 4490 may include, for example, epoxy molding compound (EMC).

[0140] Reference Figure 9Semiconductor package 5000 may include upper semiconductor package 4020 stacked on lower semiconductor package 5010. Upper semiconductor package 4020 is related to reference... Figure 8 The description is basically the same as that of the semiconductor package 4020, so a detailed description of it is omitted.

[0141] The lower semiconductor package 5010 may include a support wiring structure 5140, an extension layer 5170 formed on the support wiring structure 5140 and including a mounting space 5176G, a sub-semiconductor package 3000 formed in the mounting space 5176G, and a cover wiring structure 5200 formed on the extension layer 5170. The extension layer 5170 may surround the periphery of the sub-semiconductor package 3000. The sub-semiconductor package 3000 may be... Figure 5 and Figure 6 The semiconductor package shown is 3000.

[0142] The lower semiconductor package 5010 may include a fan-out semiconductor package. In some embodiments, the extension layer 5170 may include a panel, and the lower semiconductor package 5010 may be a fan-out panel-level package (FOPLP). For example, the lower semiconductor package 5010 may be a chip-first FOPLP, wherein a support wiring structure 5140 is formed after the overlay wiring structure 5200 is attached to the extension layer 5170. The support wiring structure 5140 may be referred to as a redistribution layer.

[0143] In some embodiments, the horizontal width and planar area of ​​the mounting space 5176G may be greater than the horizontal width and planar area of ​​the occupied area formed by the sub-semiconductor package 3000. The side surface of the sub-semiconductor package 3000 may be separated from the inner surface of the mounting space 5176G.

[0144] The supporting wiring structure 5140 may include a redistribution conductive structure 5145 and a plurality of redistribution insulating layers 5146. The redistribution conductive structure 5145 and the redistribution insulating layer 5146 may be referred to as a first wiring pattern and a first substrate insulating layer, respectively. The redistribution conductive structure 5145 may include a plurality of redistribution line patterns 5142 formed on at least one of the upper and lower surfaces of each of the redistribution insulating layers 5146, and a plurality of redistribution vias 5144 penetrating at least one of the redistribution insulating layers 5146 and contacting and connecting with some of the redistribution line patterns 5142. In some embodiments, at least some of the redistribution line patterns 5142 may be integrally formed with some of the redistribution vias 5144. In some embodiments, the redistribution vias 5144 may have a tapered shape with a horizontal width decreasing in the upward direction. In other words, the redistribution vias 5144 may have a larger horizontal width as they move away from the first semiconductor chip 100. The first front surface pad 142 of the semiconductor package 3000 can be electrically connected to the redistribution conductive structure 5145. The semiconductor package 5000 may include a plurality of external connection terminals 5150 attached to the lower surface of the support wiring structure 5140.

[0145] The extension layer 5170 may include, for example, a PCB, a ceramic substrate, a package manufacturing wafer, or an interposer. In some embodiments, the extension layer 5170 may include a multilayer PCB. A mounting space 5176G may be formed as an opening or cavity in the extension layer 5170. The mounting space 5176G may be formed in some regions, such as the central region of the extension layer 5170. The mounting space 5176G may be recessed to a certain depth from the upper surface of the extension layer 5170, or it may be formed to extend from the upper surface of the extension layer 5170 to the lower surface of the extension layer 5170 and be open. The extension layer 5170 may include a plurality of connection structures 5175 and at least one substrate 5176. The connection structure 5175 may include a connection wiring pattern 5172 and a connection conductive via 5174.

[0146] The lower semiconductor package 5010 may further include a filler member 5164 that fills the space between the sub-semiconductor package 3000 and the extension layer 5170, and the space between the extension layer 5170 and the overlay wiring structure 5200. The filler member 5164 may surround the sub-semiconductor package 3000. The filler member 5164 may include, for example, epoxy molding compound (EMC).

[0147] On the extension layer 5170, a cover wiring structure 5200 may be formed, including a second wiring pattern 5220 electrically connected to the connection structure 5175. The cover wiring structure 5200 may include at least one second substrate insulating layer 5210 and a second wiring pattern 5220. The second wiring pattern 5220 may include a second upper surface wiring pattern disposed on the upper surface of at least one second substrate insulating layer 5210 and including a plurality of second upper surface pads 5222, a second lower surface wiring pattern disposed on the lower surface of at least one second substrate insulating layer 5210 and including a plurality of second lower surface pads 5224, and a plurality of second conductive vias 5228 penetrating at least one second substrate insulating layer 5210 and electrically connecting the second wiring patterns 5220 formed on different wiring layers to each other. In some embodiments, a plurality of internal connection terminals 5178 may be formed between the connection structure 5175 and the second lower surface pads 5224, and the connection structure 5175 may be electrically connected to the second wiring pattern 5220. The cover wiring structure 5200 may also include a second solder mask layer 5230 on its upper and lower surfaces. The second solder mask layer 5230 may include: a second upper surface solder mask layer 5232 that covers the upper surface of at least one second substrate insulating layer 5210 and exposes a second upper surface pad 5222 of a second upper surface wiring pattern; and a second lower surface solder mask layer 5234 that covers the lower surface of at least one second substrate insulating layer 5210 and exposes a second lower surface pad 5224 of a second lower surface wiring pattern.

[0148] Figure 10A and Figure 10B This is a plan view of a plurality of bonding pads in a semiconductor package according to an embodiment.

[0149] Reference Figure 10A Semiconductor package 1 may include multiple bonding pads BP. Semiconductor package 1 may include reference... Figures 1 to 9 The semiconductor package described is any one of 1000, 2000, 3000, 4000, and 5000. The bonding pad BP can be a first bonding pad BP1, a first even bonding pad BP1a, a first odd bonding pad BP1b, or a second bonding pad BP2.

[0150] The first horizontal width W1 of each of the bonding pads BP can be the same. The first horizontal width W1 can range from about 0.5 μm to about 8 μm. The bonding pads BP can be arranged with the same first pitch P1. In some embodiments, the bonding pads BP can be arranged to form a matrix array of rows and columns.

[0151] Reference Figure 10B Semiconductor package 1a may include multiple bonding pads BPa. Semiconductor package 1a may include reference... Figures 1 to 9The semiconductor package described is any one of 1000, 2000, 3000, 4000, and 5000. The bonding pad BPa can be a first bonding pad BP1, a first even bonding pad BP1a, a first odd bonding pad BP1b, or a second bonding pad BP2.

[0152] The bonding pads BPa may include multiple signal bonding pads BPS and multiple power / ground bonding pads BPP. The first horizontal width W1 of each of the signal bonding pads BPS may be identical. The first horizontal width W1 may range from about 0.5 μm to about 8 μm. The signal bonding pads BPS may be arranged with the same first spacing P1. The second horizontal width W2 of each of the power / ground bonding pads BPP may be greater than the first horizontal width W1. The second horizontal width W2 may be greater than the first horizontal width W1 by about 5% to about 50%.

[0153] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package comprising a first semiconductor chip, a second semiconductor chip, and at least one first bonding pad connecting the first semiconductor chip and the second semiconductor chip. in, The first semiconductor chip includes: A first semiconductor substrate includes a first active surface and a first passive surface that are opposite to each other; Multiple first front surface pads are disposed on the first active surface of the first semiconductor substrate; At least one first through electrode penetrates at least a portion of the first semiconductor substrate and is connected to the first front surface pad; A first rear surface capping layer is disposed on the first passive surface of the first semiconductor substrate; and A first rear surface alignment pattern is disposed in the first rear surface cover layer. The second semiconductor chip includes: A second semiconductor substrate, stacked on the first semiconductor chip and including a second semiconductor element on its second active surface; A second front surface capping layer is disposed on the second active surface of the second semiconductor substrate; and A second front surface alignment pattern is disposed within the second front surface cover layer and separated from the first rear surface alignment pattern. The first bonding pad penetrates the first rear surface cover layer and the second front surface cover layer, and connects to the first through electrode. Wherein, the height of the first bonding pad is greater than the sum of the thickness of the first rear surface overlay and the thickness of the second front surface overlay, and is equal to or less than twice the sum of the thickness of the first rear surface alignment pattern and the thickness of the second front surface alignment pattern.

2. The semiconductor package according to claim 1, wherein, The lower surface of the first bonding pad is at a height lower than the lower surface of the first rear surface alignment pattern, and the upper surface of the first bonding pad is at a height higher than the upper surface of the second front surface alignment pattern.

3. The semiconductor package according to claim 1, wherein, The first through electrode overlaps with the first bonding pad in the vertical direction, and The first rear surface alignment pattern and the second front surface alignment pattern do not overlap with the first through electrode in the vertical direction.

4. The semiconductor package according to claim 1, wherein, The first rear surface alignment pattern is at the same height as a portion of the first bonding pad, and the second front surface alignment pattern is at the same height as another portion of the first bonding pad.

5. The semiconductor package according to claim 1, wherein, The first rear surface cover layer and the second front surface cover layer each include a first rear surface alignment pattern and a second front surface alignment pattern, and are separated from each other.

6. The semiconductor package according to claim 1, further comprising: A first rear surface wiring structure is disposed between the first semiconductor substrate and the first rear surface cover layer; A first rear surface wiring interlayer insulating layer surrounds the first rear surface wiring structure; A second front surface wiring structure is disposed between the second semiconductor substrate and the second front surface cover layer; as well as A second front surface wiring interlayer insulating layer surrounds the second front surface wiring structure. Wherein, one end of the first bonding pad extends into the insulating layer between the first rear surface wirings and is connected to the first rear surface wiring structure via the under-bump metal UBM layer. The other end of the first bonding pad extends into the second front surface wiring interlayer insulation layer and is connected to the second front surface wiring structure through the second front surface UBM layer.

7. The semiconductor package according to claim 1, wherein, The first bonding pads include a plurality of first bonding pads arranged at the same spacing. Wherein, each of the first bonding pads has the same horizontal width, and Wherein, the horizontal width of the first bonding pad is less than the horizontal width of each of the first rear surface alignment pattern and the second front surface alignment pattern.

8. A semiconductor package comprising a first semiconductor chip, a second semiconductor chip, and at least one first bonding pad connecting the first semiconductor chip and the second semiconductor chip. in, The first semiconductor chip includes: A first semiconductor substrate, including a first semiconductor element on its first active surface; Multiple first front surface pads are disposed on the first active surface of the first semiconductor substrate; At least one first through electrode penetrates at least a portion of the first semiconductor substrate and is connected to the first front surface pad; A first rear surface capping layer is disposed on a first passive surface of the first semiconductor substrate; and A first rear surface pseudo-conductive layer includes a first rear surface alignment pattern and penetrates a portion of the first rear surface cover layer; The second semiconductor chip includes: A second semiconductor substrate is stacked on the first semiconductor chip and includes a second semiconductor element on its second active surface; A second front surface cover layer is disposed on the second active surface; and A second front surface pseudo-conductive layer includes a second front surface alignment pattern separated from the first rear surface alignment pattern and penetrating a portion of the second front surface cover layer; and The first bonding pad penetrates the first rear surface cover layer and the second front surface cover layer, and is connected to the first through electrode.

9. The semiconductor package according to claim 8, wherein, The first rear surface pseudo-conductive layer and the second front surface pseudo-conductive layer overlap a portion of the first bonding pad in the horizontal direction, respectively.

10. The semiconductor package according to claim 8, wherein, The first through electrode overlaps with the first bonding pad in the vertical direction.

11. The semiconductor package of claim 10, wherein, The first rear surface pseudo-conductive layer and the second front surface pseudo-conductive layer do not overlap with the first through electrode in the vertical direction.

12. The semiconductor package of claim 8, further comprising: A first rear surface wiring structure is disposed between the first semiconductor substrate and the first rear surface cover layer; A first rear surface wiring interlayer insulating layer surrounds the first rear surface wiring structure; A second front surface wiring structure is disposed between the second semiconductor substrate and the second front surface cover layer; as well as A second front surface wiring interlayer insulating layer surrounds the second front surface wiring structure. Wherein, one end of the first bonding pad extends into the insulating layer between the first rear surface wirings and connects to the first rear surface wiring structure, and The other end of the first bonding pad extends into the second front surface wiring interlayer insulation layer and connects to the second front surface wiring structure.

13. The semiconductor package of claim 12, further comprising: A first rear surface bump under metal UBM layer is disposed between one end of the first bonding pad and the first rear surface wiring structure. as well as A second front surface UBM layer is disposed between the other end of the first bonding pad and the second front surface wiring structure.

14. The semiconductor package of claim 12, wherein, The first rear surface cover layer includes a first lower rear surface cover layer disposed on the first rear surface wiring structure and the insulating layer between the first rear surface wirings, and a first upper rear surface cover layer disposed on the first lower rear surface cover layer. The second front surface cover layer includes a second lower front surface cover layer disposed on the second front surface wiring structure and the insulating layer between the second front surface wiring, and a second upper front surface cover layer disposed on the second lower front surface cover layer. The first rear surface pseudo-conductive layer penetrates the first lower rear surface cover layer, and the second front surface pseudo-conductive layer penetrates the second lower front surface cover layer.

15. The semiconductor package of claim 14, wherein, The first rear surface pseudo-conductive layer and the second front surface pseudo-conductive layer are separated from each other, and the first upper rear surface cover layer and the second upper front surface cover layer are located between the first rear surface pseudo-conductive layer and the second front surface pseudo-conductive layer.

16. The semiconductor package according to claim 8, wherein, The second semiconductor chip further includes at least one second through electrode, which is configured to penetrate at least a portion of the second semiconductor substrate and is connected to the first bonding pad.

17. The semiconductor package of claim 16, wherein, The first through electrode, the first bonding pad, and the second through electrode are aligned in the vertical direction.

18. A semiconductor package, comprising: First semiconductor chip; At least two second semiconductor chips are stacked on top of the first semiconductor chip; At least one first bonding pad connects the lowest end of the at least two second semiconductor chips to the first semiconductor chip; as well as At least one second bonding pad connects the at least two second semiconductor chips to each other. The first semiconductor chip includes: A first semiconductor substrate includes a first active surface and a first passive surface that are opposite to each other; Multiple first front surface pads are arranged on the first active surface; At least one first through electrode penetrates at least a portion of the first semiconductor substrate and is connected to the first bonding pad; A first rear surface cover layer includes a first lower rear surface cover layer disposed on the first passive surface and a first upper rear surface cover layer disposed on the first lower rear surface cover layer; and A first rear surface pseudo-conductive layer is disposed within the first lower rear surface cover layer and includes a first rear surface alignment pattern. Each of the at least two second semiconductor chips includes: The second semiconductor substrate includes a second active surface and a second passive surface that are opposite to each other; The second front surface cover layer includes a second lower front surface cover layer disposed on the second active surface and a second upper front surface cover layer disposed on the second lower front surface cover layer; A second front surface pseudo-conductive layer is disposed in the second lower front surface cover layer and includes a second front surface alignment pattern; At least one second through electrode penetrates at least a portion of the second semiconductor substrate and connects the first bonding pad to the second bonding pad; The second rear surface cover layer includes a second lower rear surface cover layer disposed on the second passive surface and a second upper rear surface cover layer disposed on the second lower rear surface cover layer; and A second rear surface pseudo-conductive layer is disposed in the second rear surface cover layer and includes a second rear surface alignment pattern; Wherein, the first bonding pad penetrates the first rear surface cover layer and the second front surface cover layer of the lowest second semiconductor chip, and Wherein, the second bonding pad penetrates the second rear surface cover layer of one of the at least two second semiconductor chips and the second front surface cover layer of the adjacent second semiconductor chip above the one second semiconductor chip.

19. The semiconductor package of claim 18, wherein, Each of the first bonding pad and the second bonding pad has a horizontal width ranging from 0.5 μm to 8 μm and a height ranging from 0.8 μm to 4.2 μm, and Each of the first rear surface alignment pattern, the second front surface alignment pattern, and the second rear surface alignment pattern has a horizontal width ranging from 20 μm to 50 μm.

20. The semiconductor package of claim 18, wherein, The first through electrode, the first bonding pad, the second through electrode, and the second bonding pad are aligned in the vertical direction.

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