Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device having high reliability and a manufacturing method thereof. The semiconductor memory device includes: a first stack including a first polycrystal semiconductor layer having a first average crystal grain diameter, a second polycrystal semiconductor layer having a second average crystal grain diameter smaller than the first average crystal grain diameter, an intermediate layer between the first polycrystal semiconductor layer and the second polycrystal semiconductor layer, and a third polycrystal semiconductor layer disposed in contact with the second polycrystal semiconductor layer and having a third average crystal grain diameter smaller than the first average crystal grain diameter; a second stack disposed above the first stack, including a plurality of conductive layers and a plurality of insulating layers, each of the conductive layers and each of the insulating layers being alternately stacked and extending in a first direction; a semiconductor layer penetrating the second stack in a second direction intersecting the first direction and disposed in contact with the third polycrystal semiconductor layer; and a memory layer penetrating the second stack in the second direction and disposed between the semiconductor layer and the conductive layer in the first direction.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-36203 (filed on March 8, 2021). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] In recent years, semiconductor memory devices with peripheral circuitry located beneath the memory cell array have become known. Summary of the Invention

[0005] The embodiments provide a semiconductor memory device with high reliability and a method for manufacturing the same.

[0006] The semiconductor memory device according to the embodiment includes: a first stack having a first polycrystalline semiconductor layer having a first average crystal grain size, a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size, an intermediate layer disposed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer, and a third polycrystalline semiconductor layer disposed in contact with the second polycrystalline semiconductor layer and having a third average crystal grain size smaller than the first average crystal grain size; a second stack disposed above the first stack having a plurality of conductive layers and a plurality of insulating layers, wherein the conductive layers and the insulating layers are alternately stacked and extend along a first direction; a semiconductor layer penetrating the second stack along a second direction intersecting the first direction and disposed in contact with the third polycrystalline semiconductor layer; and a memory layer penetrating the second stack along the second direction and disposed between the semiconductor layer and the conductive layer in the first direction. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system.

[0008] Figure 2 This is a circuit diagram showing the circuit configuration of the memory cell array 110.

[0009] Figure 3 This is a cross-sectional schematic diagram used to illustrate an example of the cross-sectional structure of a semiconductor memory device.

[0010] Figure 4 It means Figure 3 A magnified view of a specific part.

[0011] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor memory device.

[0012] Figures 6 to 14 This is a diagram illustrating an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0013] Figure 15 It is a timing diagram showing the voltage of each wiring when the erase pulse is applied during the block erase operation.

[0014] Figure 16 This is a schematic diagram illustrating an example of a method for diffusing phosphorus into semiconductor layer 234.

[0015] Figure 17 This is a schematic diagram showing the overlap between the semiconductor layer 214 and the memory pillar MP in the XY plane. Detailed Implementation

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings. The relationships between the thickness and planar dimensions of each component, and the proportions of the thicknesses of each component shown in the drawings, may differ from the actual object. Furthermore, in the embodiments, substantially identical components are labeled with the same reference numerals, and descriptions are appropriately omitted.

[0017] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system. The memory system includes a semiconductor memory device 101 and a memory controller 102.

[0018] The semiconductor memory device 101 includes a memory cell array 110, a command register 111, an address register 112, a sequencer 113, a driver 114, a line decoder 115, and a sense amplifier 116.

[0019] The memory cell array 110 contains multiple blocks BLK [BLK0 to BLK(L-1) (where L is a natural number greater than 2)]. A block BLK is a collection of multiple memory transistors MT that non-volatilely store data.

[0020] The memory cell array 110 is connected to the sense amplifier 116 via multiple bit lines BL. As described later, the memory cell array 110 includes multiple word lines WL, which are connected to the line decoder 115. Each memory transistor MT (memory cell) is connected to one of the multiple word lines WL and one of the multiple bit lines BL.

[0021] Command register 111 holds command signals CMD received from memory controller 102. Command signals CMD include, for example, command data that causes sequencer 113 to perform read, write, and erase operations.

[0022] Address register 112 holds the address signal ADD received from memory controller 102. The address signal ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word line WL, and bit line BL, respectively.

[0023] The sequencer 113 controls the operation of the semiconductor memory device 101. For example, the sequencer 113 controls the driver 114, the line decoder 115, and the sense amplifier 116 based on the command signal CMD held in the command register 111 to perform operations such as reading, writing, and erasing.

[0024] Driver 114 generates the voltages used for read, write, and erase operations. Furthermore, driver 114 applies the generated voltages to the signal lines corresponding to the selected word line WL, for example, based on the page address PA held in address register 112.

[0025] The line decoder 115 selects a block BLK within the corresponding memory cell array 110 based on the block address BA held in the address register 112. Furthermore, the line decoder 115 transmits, for example, the voltage applied to the signal line corresponding to the selected word line WL within the selected block BLK to the selected word line WL.

[0026] During a write operation, the sense amplifier 116 applies the required voltage to each bit line BL in accordance with the write data DAT received from the memory controller 102. Conversely, during a read operation, the sense amplifier 116 determines the data stored in the memory cell based on the voltage of the bit line BL, and transmits the determination result to the memory controller 102 as read data DAT.

[0027] Communication between the semiconductor memory device 101 and the memory controller 102 supports, for example, the NAND interface standard. For instance, communication between the semiconductor memory device 101 and the memory controller 102 uses the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEN, the read enable signal REn, the ready / busy signal RBn, and input / output (I / O) signals.

[0028] The command latch enable signal CLE indicates that the input / output signal (I / O) received by the semiconductor memory device 101 is a command signal CMD. The address latch enable signal ALE indicates that the received I / O signal is an address signal ADD. The write enable signal WEn is a signal that commands the semiconductor memory device 101 to perform input / output signal (I / O). The read enable signal REn is a signal that commands the semiconductor memory device 101 to perform output / output signal (I / O).

[0029] The ready / busy signal RBn is a signal that notifies the memory controller 102 whether the semiconductor memory device 101 is in a ready state to receive commands from the memory controller 102 or a busy state that cannot receive commands.

[0030] Input / output (I / O) signals are, for example, 8-bit wide signals, which may include command signals (CMD), address signals (ADD), write data signals (DAT), etc.

[0031] The semiconductor memory device 101 and memory controller 102 described above can also be combined to form a memory system. Examples of such a memory system include memory cards and solid-state drives (SSDs).

[0032] The circuit configuration example of the memory cell array 110 is described below. Figure 2 This is a circuit diagram showing the circuit configuration of the memory cell array 110. Figure 2 Block BLK0 is shown as an example, but the structure of other blocks BLK is the same.

[0033] Block BLK contains multiple string units SU. Each string unit SU contains multiple NAND strings NS. Furthermore, Figure 2 The diagram shows three string units SU (SU0~SU2), but the number of string units SU is not particularly limited.

[0034] Each NAND string NS is connected to one of multiple bit lines BL [BL0 ~ BL(N-1) (where N is a natural number greater than 2)]. Each NAND string NS contains a storage transistor MT, a dummy storage transistor MTDD, a dummy storage transistor MTDS, a select transistor ST1, and a select transistor ST2.

[0035] The storage transistor MT includes a control gate and a charge storage layer, which non-volatilely retains data. Figure 2 The illustration shows multiple storage transistors MT (MT00 to MT159), but the number of storage transistors MT is not particularly limited.

[0036] The dummy storage transistors MTDD and MTDS each contain a control gate and a charge storage layer. Both MTDD and MTDS have the same construction as the storage transistor MT, but are not used for data retention.

[0037] The storage transistor MT, the dummy storage transistor MTDD, and the dummy storage transistor MTDS can each be either a MONOS type with an insulating film in the charge storage layer or an FG type with a conductive layer in the charge storage layer. In this embodiment, the MONOS type will be used as an example for explanation.

[0038] Transistor ST1 is selected for the selection of the serial cell SU during various operations. Figure 2 Multiple selection transistors ST1 (ST1a, ST1b) are shown, but the number of selection transistors ST1 is not particularly limited.

[0039] Transistor ST2 is selected to supply the required voltage to the string unit SU during various operations. Figure 2 Multiple selection transistors ST2 (ST2a, ST2b) are shown, but the number of selection transistors ST2 is not particularly limited.

[0040] In each NAND string NS, the drain of select transistor ST1 is connected to the corresponding bit line BL. The source of select transistor ST1 is connected to one end of the series-connected storage transistor MT. The other end of the series-connected storage transistor MT is connected to the drain of select transistor ST2.

[0041] Within the same block BLK, the source of select transistor ST2 is connected to its source line SL. The gates of select transistors ST1a in each string cell SU are connected to their corresponding select gate lines SGD. The gates of select transistors ST1b are connected to their corresponding select gate lines SGDT. The control gates of storage transistors MT are connected to their corresponding word lines WL. The control gates of dummy storage transistors MTDD are connected to their corresponding dummy word lines DD and MTDS. The control gates of select transistors MT2a are connected to their select gate line SGS. The gate of select transistor ST2b is connected to its select gate line SGSB.

[0042] Multiple NAND strings NS assigned the same column address CA are connected to the same bit line BL across multiple blocks BLK. The source line SL is connected across multiple blocks BLK.

[0043] The following describes a cross-sectional structure example of the semiconductor memory device 101. Figure 3 This is a cross-sectional schematic diagram illustrating an example of the cross-sectional structure of the semiconductor memory device 101. It shows the X-axis direction which is substantially parallel to the surface of the semiconductor substrate 100, the Y-axis direction which is along the surface and substantially perpendicular to the X-axis, and the Z-axis direction which intersects the surface substantially perpendicularly. Figure 4 It means Figure 3 A magnified view of a portion of the image. "Approximately parallel" can include, for example, a direction deviated ±10 degrees from the parallel direction. "Approximately perpendicular" can include, for example, a direction deviated ±10 degrees from the perpendicular direction.

[0044] The semiconductor memory device 101 of this embodiment includes peripheral circuits such as a command register 111, an address register 112, a sequencer 113, a driver 114, a line decoder 115, and a sense amplifier 116 below the memory cell array 110.

[0045] Figure 3 The semiconductor memory device shown includes: a field-effect transistor TR disposed on a semiconductor substrate 100. N and field-effect transistors (TR) P The memory cell array 110 comprises the following layers: conductive layer 201, conductive layer 202, insulating layer 203, source line SL, insulating layer 220, conductive layer 221, insulating layer 222, insulating layer 223, block insulating film 231, charge storage film 232, tunnel insulating film 233, semiconductor layer 234, core insulating layer 235, capping layer 236, conductive layer 241, insulating layer 251, contact layer 252, and conductive layer 261 (bit line BL). Furthermore, the source line SL, conductive layer 221, insulating layer 222, block insulating film 231, charge storage film 232, tunnel insulating film 233, semiconductor layer 234, core insulating layer 235, capping layer 236, and conductive layer 241.

[0046] Field-effect transistor TR N and field-effect transistors (TR) P Located below the memory cell array 110. Field-effect transistor TR N It is an N-channel transistor. A field-effect transistor (TR). P It is a P-channel transistor. A field-effect transistor (TR). N and field-effect transistors (TR) P Each of these constitutes one of the aforementioned peripheral circuits.

[0047] Each of the multiple conductive layers 201 functions as a contact plug. Each of the multiple conductive layers 202 functions as a wiring layer, and each conductive layer 202 functions as a wiring within that wiring layer. Each conductive layer 202 connects, for example, to a field-effect transistor TR via the conductive layer 201. N or field-effect transistor TR P One of the gate, source, and drain electrodes is connected. Conductive layers 201 and 202 contain metallic materials.

[0048] Insulating layer 203 will hold the field-effect transistor TR N With field-effect transistor TR P The insulating layer 203 is insulated between areas such as between multiple conductive layers 201 and between multiple conductive layers 202. The insulating layer 203 contains, for example, oxygen and silicon. Furthermore, the field-effect transistor TR... N and field-effect transistors (TR) PIt is connected to the memory cell array 110 not only through conductive layers 201 and 202, but also through other wiring layers and contact plugs, but these connections are omitted here for convenience.

[0049] The source line SL has a first-layer stack. For example... Figure 4 As shown, the first stack has a semiconductor layer 211, a semiconductor layer 212, an intermediate layer 213, a semiconductor layer 214, a semiconductor layer 215, a semiconductor layer 216, and an intermediate layer 217.

[0050] Semiconductor layers 211, 212, 214, 215, and 216 are each, for example, polycrystalline semiconductor layers containing N-type impurity elements, such as polycrystalline silicon. Examples of N-type impurity elements include phosphorus.

[0051] Semiconductor layer 211 is disposed on Figure 3 Above the semiconductor substrate 100 shown. The semiconductor layer 211 has a first average crystal grain size. The first average crystal grain size is, for example, 300 nm or more. If it is less than 300 nm, the resistance of the source line SL may increase. The upper limit of the first average crystal grain size is not particularly limited, for example, it is 400 nm or more. By increasing the average crystal grain size of the semiconductor layer 211, the resistance of the source line SL can be reduced.

[0052] Semiconductor layer 212 is disposed above intermediate layer 213. Semiconductor layer 212 has a second average crystal grain size smaller than the first average crystal grain size. The second average crystal grain size is, for example, 100 nm to 150 nm. If it is less than 100 nm, the resistance of the source line SL may increase. If it is greater than 150 nm, as described later, it may contribute to an increase in the average crystal grain size of semiconductor layer 214. Semiconductor layer 212 is thinner than semiconductor layer 211. The thinner semiconductor layer 212 is, the easier it is to reduce the average crystal grain size of semiconductor layer 212.

[0053] Intermediate layer 213 is, for example, a compound layer containing oxygen, nitrogen, or carbon. Intermediate layer 213 is disposed above semiconductor layer 211. Intermediate layer 213 is disposed between semiconductor layer 211 and semiconductor layer 212, separating semiconductor layer 211 and semiconductor layer 212. This suppresses the increase in the average crystal grain size (second average crystal grain size) of semiconductor layer 212 caused by semiconductor layer 211. Intermediate layer 213 is thinner than semiconductor layer 212. The thickness of intermediate layer 213 is, for example, 50 nm or less. If it is greater than 50 nm, intermediate layer 213 may be removed during the formation process of source line SL. Furthermore, the thickness of intermediate layer 213 is preferably less than the spacing of the memory pillars described later.

[0054] Semiconductor layer 214 is disposed between semiconductor layer 212 and semiconductor layer 216. Semiconductor layer 214 is in contact with semiconductor layer 212 and semiconductor layer 216. Semiconductor layer 214 has a third average crystal grain size that is smaller than the first average crystal grain size. The third average crystal grain size is, for example, 100 nm or more and 150 nm or less.

[0055] Semiconductor layer 214 penetrates block insulating film 231, charge storage film 232 and tunnel insulating film 233 in a direction approximately parallel to the X-axis and is connected to semiconductor layer 234.

[0056] A semiconductor layer 215 is disposed on top of the intermediate layer 217. The semiconductor layer 215 has a fourth average crystal grain size. This fourth average crystal grain size is, for example, 300 nm or larger. If it is smaller than 300 nm, the resistance of the source line SL may increase. The upper limit of the fourth average crystal grain size is not particularly limited, but is, for example, 400 nm or larger. By increasing the average crystal grain size of the semiconductor layer 215, the resistance of the source line SL can be reduced.

[0057] Semiconductor layer 216 is disposed on semiconductor layer 214. Semiconductor layer 216 has a fifth average crystal grain size that is smaller than the fourth average crystal grain size. The fifth average crystal grain size can be smaller than the first average crystal grain size. The fifth average crystal grain size is, for example, between 100 nm and 150 nm. If it is less than 100 nm, the resistance of the source line SL may increase. If it is greater than 150 nm, as will be explained later, it may contribute to an increase in the average crystal grain size of semiconductor layer 214. Semiconductor layer 216 is thinner than semiconductor layer 215. The thinner semiconductor layer 216 is, the easier it is to reduce the average crystal grain size of semiconductor layer 216.

[0058] Intermediate layer 217 is, for example, a compound layer containing oxygen, nitrogen, or carbon. Intermediate layer 217 is disposed above semiconductor layer 216. Intermediate layer 217 is disposed between semiconductor layer 215 and semiconductor layer 216, separating semiconductor layer 215 and semiconductor layer 216. This suppresses the increase in the average crystal grain size (fifth average crystal grain size) of semiconductor layer 216 caused by semiconductor layer 215. Intermediate layer 217 is thinner than semiconductor layer 216. The thickness of intermediate layer 217 is, for example, 50 nm or less. If it is greater than 50 nm, intermediate layer 213 may be removed during the formation process of source line SL. Furthermore, the thickness of intermediate layer 217 is preferably less than the spacing of the memory pillars described later.

[0059] Not limited to Figure 4In the illustrated configuration, the first stack only needs to have at least one intermediate layer chosen from intermediate layer 213 and intermediate layer 217. Without intermediate layer 213, semiconductor layer 212 is not formed; instead, semiconductor layer 211 is connected to semiconductor layer 214. Without intermediate layer 217, semiconductor layer 216 is not formed; instead, semiconductor layer 215 is connected to semiconductor layer 214. That is, the first stack of the source line SL only needs to have at least one polycrystalline semiconductor layer chosen from semiconductor layer 212 and semiconductor layer 216.

[0060] The average crystal grain size of each of semiconductor layers 211, 212, 214, 215, and 216 can be calculated by observing a cross-section parallel to the XY plane of each polycrystalline semiconductor layer using, for example, a transmission electron microscope (TEM), and based on the acquired image. For example, the average crystal grain size can be calculated using the Intercept method (also known as the Heyn method) or the Planimetric method (also known as the Jeffries method) based on a TEM image with a field of view of approximately 3 μm in both length and width.

[0061] An insulating layer 220 is disposed above the first layer stack. The insulating layer 220 contains, for example, oxygen and silicon.

[0062] The memory cell array 110 has a second stack. The second stack has multiple conductive layers 221 and multiple insulating layers 222 stacked alternately. The multiple conductive layers 221 can respectively form select gate lines SGSB, SGS, dummy word lines DS0-DS3, word lines WL00-WL159, dummy word lines DD0-DD3, select gate lines SGD0-SGD2, and select gate lines SGDT0-SGDT2. Furthermore, select gate lines SGD0-SGD2 are arranged at different positions in the XY plane but on the same layer in the Z-axis direction. Similarly, select gate lines SGDT0-SGDT2 are arranged at different positions in the XY plane but on the same layer in the Z-axis direction. Therefore, in Figure 3 The diagram illustrates, as an example, select gate line SGD0 and select gate line SGDT0. Conductive layer 221 contains a metallic material such as tungsten. Insulating layer 222 contains, for example, oxygen and silicon.

[0063] An insulating layer 223 is disposed on the second laminate. The insulating layer 223 contains, for example, oxygen and silicon formed using tetraethyl orthosilicate (TEOS).

[0064] The columnar structure (memory column) has a block insulating film 231, a charge storage film 232, a tunnel insulating film 233, a semiconductor layer 234, and a core insulating layer 235. The block insulating film 231, charge storage film 232, tunnel insulating film 233, semiconductor layer 234, and core insulating layer 235 extend in a direction substantially parallel to the Z-axis. One memory column corresponds to one NAND string NS. The memory column has a memory layer. The memory layer has the block insulating film 231, charge storage film 232, and tunnel insulating film 233. The memory layer penetrates the second stack in a direction substantially perpendicular to the Z-axis. The memory layer is disposed between the semiconductor layer 234 and the conductive layer 221 in a direction substantially parallel to the X-axis.

[0065] The block insulating film 231 and the core insulating layer 235 contain, for example, oxygen and silicon. The charge storage film 232 contains, for example, nitrogen and silicon. The tunnel insulating film 233 contains, for example, oxygen and silicon. In addition, the block insulating film 231 and the tunnel insulating film 233 may also contain, for example, nitrogen.

[0066] More specifically, holes corresponding to storage pillars are formed through multiple conductive layers 221. Block insulating film 231, charge storage film 232, and tunnel insulating film 233 are sequentially stacked on the sides of the holes. Furthermore, a semiconductor layer 234 is formed in such a way that its sides are in contact with the tunnel insulating film 233 and the semiconductor layer 214.

[0067] Semiconductor layer 234 extends through the second stack in a direction substantially parallel to the Z-axis and is connected to the source line SL and bit line BL. Semiconductor layer 234 has channel formation regions for select transistor ST1, select transistor ST2, storage transistor MT, dummy storage transistor MTDS, and dummy storage transistor MTDD. Thus, semiconductor layer 234 functions as a signal line connecting the current paths of select transistor ST1, select transistor ST2, storage transistor MT, dummy storage transistor MTDS, and dummy storage transistor MTDD.

[0068] The semiconductor layer 234 is in contact with the surface of the tunnel insulating film 233. The semiconductor layer 234 may contain, for example, a polycrystalline semiconductor layer such as polycrystalline silicon. The semiconductor layer 234 may also be formed, for example, by crystallizing an amorphous silicon film.

[0069] The core insulating layer 235 is disposed inside the semiconductor layer 234. The core insulating layer 235 penetrates the second stack in a direction substantially parallel to the Z-axis.

[0070] like Figure 3As shown, a capping layer 236 is disposed above the core insulating layer 235 and is in contact with the semiconductor layer 234. The capping layer 236 may contain, for example, oxygen and silicon, or polycrystalline silicon containing N-type impurity elements. For example, when the capping layer 236 contains oxygen and silicon, the diffusion of impurity elements can be suppressed. When the capping layer 236 is an insulating layer, N-type impurity elements such as phosphorus and arsenic can be implanted onto the surface of the capping layer 236. Furthermore, when the capping layer 236 comprises a polycrystalline semiconductor layer such as polycrystalline silicon containing N-type impurity elements, the connection resistance between the capping layer 236 and the contact layer 252 can be reduced.

[0071] The conductive layer 241 is a contact layer referred to as the Local Interconnect (Li). The conductive layer 241 extends through the second stack in a direction substantially parallel to the Z-axis and is connected to the source line SL. The conductive layer 241 is connected to the semiconductor layer 214. The conductive layer 241 may contain, for example, tungsten.

[0072] Insulating layer 251 is located above the second laminate and disposed above insulating layer 223. Insulating layer 251 contains, for example, oxygen and silicon formed using TEOS. Contact layer 252 functions as a contact plug. Conductive layer 261 is connected to capping layer 236 via contact layer 252. Conductive layer 261 functions as bit line BL. Contact layer 252 and conductive layer 261 contain metallic material.

[0073] The intersection of the memory pillar and the conductive layer 221 constituting each word line WL functions as a memory transistor MT. The intersection of the memory pillar and the conductive layer 221 constituting each dummy word line DD functions as a dummy memory transistor MTDD. The intersection of the memory pillar and the conductive layer 221 constituting each dummy word line DS functions as a dummy memory transistor MTDS. The intersection of the memory pillar and the conductive layer 221 constituting each select gate line SGD functions as a select transistor ST1a. The intersection of the memory pillar and the conductive layer 221 constituting each select gate line SGDT functions as a select transistor ST1b. The intersection of the memory pillar and the conductive layer 221 constituting each select gate line SGS functions as a select transistor ST2a. The intersection of the memory pillar and the conductive layer 221 constituting each select gate line SGSB functions as a select transistor ST2b.

[0074] Below, on Figure 3 The manufacturing method of the semiconductor memory device shown will be described. Figure 5 This is a flowchart illustrating an example of a semiconductor memory device manufacturing method. Here, a series of manufacturing steps related to the formation of the source line SL are specifically described. Figures 6 to 14 China indicates Figure 4 The diagram shows the cross-sectional structure during the manufacturing process of the part shown; other parts are omitted from the diagram.

[0075] like Figure 5 As shown, an example of a method for manufacturing a semiconductor memory device includes: a stacking process S1, a memory pillar formation process S2, an aperture formation process S3, a sacrificial layer removal process S4, a memory layer processing process S5, a semiconductor layer formation process S6, and a replacement process S7. These processes are not limited to... Figure 5 The sequence of processes is shown.

[0076] [Lamination Process S1]

[0077] like Figure 6 As shown, a third laminate is formed by stacking semiconductor layer 211, intermediate layer 213, semiconductor layer 212, protective layer 214b, sacrificial layer 214a, protective layer 214c, semiconductor layer 216, intermediate layer 217, and semiconductor layer 215. This third laminate will later become the first laminate. The third laminate is formed in... Figure 3 The peripheral circuit shown is disposed above the surface of the semiconductor substrate 100.

[0078] When intermediate layer 213 or intermediate layer 217 contains oxygen, intermediate layer 213 or intermediate layer 217 can be formed by oxidizing the surface of semiconductor layer 211 or semiconductor layer 216 at a temperature below 350°C. The oxygen-containing intermediate layer 213 or intermediate layer 217 formed by the above oxidation is also called a low-temperature oxide film (LTO film). Not limited thereto, the oxygen-containing intermediate layer 213 or intermediate layer 217 can also be formed by methods such as exposing the semiconductor layer 211 or semiconductor layer 216 to an oxygen environment, or by immersion in a solution containing hydrogen peroxide (H2O2) or ozone (O3). Alternatively, when intermediate layer 213 or intermediate layer 217 contains nitrogen, intermediate layer 213 or intermediate layer 217 can be formed by nitriding the surface of semiconductor layer 211 or semiconductor layer 216, for example. In addition, if the intermediate layer 213 or intermediate layer 217 contains carbon, for example, carbon can be implanted into the surface of the semiconductor layer 211 or semiconductor layer 216 to form the intermediate layer 213 or intermediate layer 217.

[0079] A sacrificial layer 214a is formed on top of a protective layer 214b. The sacrificial layer 214a is disposed between the protective layers 214b and 214c. The sacrificial layer 214a is used to form the semiconductor layer 214. The sacrificial layer 214a contains, for example, nitrogen and silicon. The sacrificial layer 214a can be formed, for example, using chemical vapor deposition (CVD).

[0080] A protective layer 214b is formed on the semiconductor layer 212. The protective layer 214b is disposed between the sacrificial layer 214a and the semiconductor layer 212. It is formed to protect the semiconductor layer 212 when the sacrificial layer 214a is removed. The protective layer 214b contains, for example, oxygen and silicon. The protective layer 214b can be formed, for example, using CVD.

[0081] A protective layer 214c is formed on top of the sacrificial layer 214a. The protective layer 214c is disposed between the sacrificial layer 214a and the semiconductor layer 216. The protective layer 214c is formed to protect the semiconductor layer 216 when the sacrificial layer 214a is removed. The protective layer 214c contains, for example, oxygen and silicon. The protective layer 214c can be formed, for example, using CVD.

[0082] Further, an insulating layer 220 is formed on the semiconductor layer 215. Additionally, a fourth laminate having multiple sacrificial layers 221a and multiple insulating layers 222 is formed on the insulating layer 220 by alternately stacking sacrificial layers 221a and insulating layers 222; this fourth laminate will subsequently become the second laminate. Further, an insulating layer 223 is formed on the fourth laminate. The insulating layer 220, sacrificial layer 221a, insulating layer 222, and insulating layer 223 can be formed, for example, using CVD.

[0083] The sacrificial layer 221a is provided for forming the conductive layer 221. The sacrificial layer 221a extends together with the insulating layer 222, for example, in a direction substantially parallel to the X-axis. The sacrificial layer 221a contains, for example, nitrogen and silicon.

[0084] [Storage column formation process S2]

[0085] Semiconductor layer 211, semiconductor layer 212, intermediate layer 213, sacrificial layer 214a, protective layer 214b, protective layer 214c, semiconductor layer 215, semiconductor layer 216, intermediate layer 217, insulating layer 220, sacrificial layer 221a, insulating layer 222, and insulating layer 223 are partially removed along a direction substantially parallel to the Z-axis to form an opening (memory hole). The laminate can be partially removed, for example, using reactive ion etching (RIE).

[0086] Then, as Figure 7 As shown, a block insulating film 231, a charge storage film 232, a tunnel insulating film 233, a semiconductor layer 234, and a core insulating layer 235 are formed in the memory hole. These films can be formed, for example, by CVD, sputtering, or atomic layer deposition (ALD).

[0087] Further, a capping layer 236 is formed. The capping layer 236 can be formed, for example, using CVD or ALD. Alternatively, N-type impurity elements such as arsenic and phosphorus, or P-type impurity elements such as boron, can be implanted into the semiconductor layer 234 before or after the formation of the capping layer 236. This allows, for example, the formation of an impurity semiconductor region in the region of the semiconductor layer 234 overlapping with the select gate lines SGD and SGDT. Alternatively, the capping layer 236 can be formed using a semiconductor layer containing N-type impurity elements such as phosphorus, and the impurity elements contained in the capping layer 236 can be diffused through a heat treatment described later to form the impurity semiconductor region.

[0088] The block insulating film 231, charge storage film 232, tunnel insulating film 233, semiconductor layer 234 and capping layer 236 are partially removed, for example, by using RIE, dry etching back etching to expose the surface (upper surface) of insulating layer 223.

[0089] [Opening Formation Process S3]

[0090] like Figure 8 As shown, an opening H is formed in a direction substantially parallel to the Z-axis, penetrating the insulating layer 220, sacrificial layer 221a, insulating layer 222, and insulating layer 223 to reach the semiconductor layer 215. The opening H is formed, for example, by partially removing the insulating layer 220, sacrificial layer 221a, insulating layer 222, and insulating layer 223 in a direction substantially parallel to the Z-axis using a resonant electrical separation (RIE).

[0091] Below, as Figure 8 As shown, protective layers 242 and 243 are sequentially formed on the inner wall and bottom surface of the opening H. Protective layer 242 contains, for example, oxygen and silicon. Protective layer 243 contains, for example, a semiconductor layer such as amorphous silicon. Protective layers 242 and 243 are formed to protect the inner wall surface of the opening H. Protective layers 242 and 243 can be formed, for example, using CVD or ALD.

[0092] Furthermore, such as Figure 9 As shown, at the bottom of opening H, protective layer 242, protective layer 243, semiconductor layer 215, intermediate layer 217, semiconductor layer 216, protective layer 214c, sacrificial layer 214a, protective layer 214b, semiconductor layer 212, intermediate layer 213, and semiconductor layer 211 are partially removed along a direction generally parallel to the Z-axis. These layers can be partially removed, for example, using RIE (Removal by Intermediate Etching). Then, an oxide layer 244 is formed on the portions of protective layer 243, semiconductor layer 211, semiconductor layer 215, semiconductor layer 214, and semiconductor layer 216 facing opening H. The oxide layer 244 contains, for example, oxygen and silicon. The oxide layer 244 can be formed by oxidizing the portions of each layer facing opening H.

[0093] [Sacrificial layer removal process S4]

[0094] like Figure 10 As shown, the space S is formed by removing the sacrificial layer 214a. The sacrificial layer 214a can be removed, for example, by wet etching using phosphoric acid. Furthermore, as described above, an oxide layer 244 is formed before the sacrificial layer removal process S4, thereby protecting the semiconductor layers 211, 212, 215, and 216 from the effects of the aforementioned wet etching.

[0095] [Memory layer processing step S5]

[0096] like Figure 11 As shown, by partially removing the block insulating film 231, the charge storage film 232, and the tunnel insulating film 233, a portion of the semiconductor layer 234 is exposed in a direction substantially parallel to the X-axis. At this time, the block insulating film 231, the charge storage film 232, and the tunnel insulating film 233 are also partially removed in a direction substantially parallel to the Z-axis. The block insulating film 231 can be partially removed, for example, by wet etching using hydrofluoric acid (dilute hydrofluoric acid). Furthermore, the protective layer 214b, the protective layer 214c, and the oxide layer 244 are also removed by the aforementioned wet etching. The charge storage film 232 can be partially removed, for example, by wet etching using phosphoric acid. The tunnel insulating film 233 can be partially removed, for example, by wet etching using hydrofluoric acid (dilute hydrofluoric acid) or chemical dry etching (CDE).

[0097] [Semiconductor layer formation process S6]

[0098] like Figure 12 As shown, a semiconductor layer 214 is formed to fill the opening H and the space S. The semiconductor layer 214 can be formed, for example, by forming an amorphous semiconductor layer containing phosphorus or the like using CVD or ALD, and then crystallizing it by heat treatment as described later.

[0099] Then, as Figure 13 As shown, in the opening H, the semiconductor layer 214 and the protective layer 243 are partially removed along a direction approximately parallel to the Z-axis, exposing the portions of semiconductor layers 211, 212, 213, 214, 215, 216, 217, and 243 facing the opening H. The semiconductor layer 214 can be partially removed, for example, by chemical dry etching using a nitrogen trifluoride gas. Subsequently, it is removed by wet etching or dry etching, such as... Figure 14 The protective layer 242 is removed as shown.

[0100] Furthermore, when using amorphous semiconductor layers such as amorphous silicon layers for semiconductor layers 214, 234, capping layers 236, etc., a polycrystalline semiconductor layer is formed by crystallizing the amorphous semiconductor layer through heat treatment. Additionally, the doped impurity elements are activated through heat treatment.

[0101] Semiconductor layer 214 is formed in contact with semiconductor layers 212 and 216. Compared to semiconductor layers 211 and 215, semiconductor layers 212 and 216 have smaller average crystal grain sizes. Therefore, semiconductor layer 214 crystallizes along the crystal planes of semiconductor layers 212 and 216. This allows the average crystal grain size of semiconductor layer 214 to be smaller than that of semiconductor layers 211 and 216. As a result of the crystallization of semiconductor layer 214, the third stack becomes the first stack.

[0102] [Replacement process S7]

[0103] Multiple sacrificial layers 221a are removed, and a conductive layer 221 is formed at the removed portions. The multiple sacrificial layers 221a can be removed, for example, by dry etching or wet etching. The conductive layer 221 can be formed, for example, by CVD or ALD. The result of removing the sacrificial layers 221a and forming the conductive layer 221 is that the fourth layer stack becomes the second layer stack. Subsequently, by sequentially forming a conductive layer 241, an insulating layer 251, a contact layer 252, and a conductive layer 261, a structure can be manufactured. Figure 3 The semiconductor memory device shown.

[0104] In the semiconductor memory device of this embodiment, the channel formation region (semiconductor layer 234) of the storage transistor MT is not directly connected to the semiconductor substrate 100. Therefore, an erase operation is performed by applying a reverse bias voltage between the gate and drain of at least one of the selection transistors, such as selection transistor ST1a and selection transistor ST2b, causing Gate Induced Drain Leakage (GIDL). Through GIDL, holes can be injected through the channel of the storage transistor MT to eliminate the charge on the charge storage film 232.

[0105] The erasure operation will be explained here. As an example, block erasure will be explained here. Block erasure selects one block (BLK) and performs the erasure operation.

[0106] The erase operation generally includes an erase pulse application and an erase verification operation. The erase pulse application is performed to lower the threshold voltage of the storage transistor MT. The erase verification operation determines whether the result of the erase pulse application is that the threshold voltage of the storage transistor MT is lower than the target value. In the erase operation, the threshold voltage of the storage transistor MT is lowered to the erase level by repeatedly performing a combination of erase pulse application and erase verification operations.

[0107] Figure 15This is a timing diagram showing the voltage of each wiring line when the erase pulse is applied during the block erase operation. At time t0, Figure 1 The line decoder 115 applies, for example, a power supply voltage, namely voltage VDD, to the select gate lines SGDT, SGD, SGSB, SGS, word line WL, dummy word line DD, and dummy word line DS of the block BLK (hereinafter also referred to as "select block BLK") that is to be erased. Additionally, the line decoder 115 applies voltage VDD to the word line WL, dummy word line DD, and dummy word line DS of the block BLK that is not to be erased (hereinafter also referred to as "non-select block BLK"). Furthermore, the voltage on the word line WL, dummy word line DD, and dummy word line DS may not be voltage VDD.

[0108] The voltages of word lines WL, dummy word lines DD, and dummy word lines DS can also be lower than the voltage VDD, so that holes generated in GIDL are injected into the charge storage films 232 of the corresponding storage transistors MT, dummy storage transistor MTDD, and dummy storage transistor MTDS. Alternatively, the line decoder 115 can also leave the word lines WL, dummy word lines DD, and dummy word lines DS of the non-selected block BLK unapplied, allowing them to float.

[0109] At time t1, a voltage Vera is applied to the source line SL. Additionally, at time t1, a voltage Vera is applied to the bit line BL via the source line SL. The voltage Vera is a high voltage used to generate GIDL. Furthermore, the line decoder 115 applies the voltage Vera to the select gate lines SGD and SGS to suppress hole injection into the charge storage films 232 of the select transistors ST1a and ST2a. Alternatively, voltages different from Vera can be applied to the select gate lines SGD and SGS. In this case, the voltages applied to the select gate lines SGD and SGS can also be different. For example, voltages higher than VDD can be applied to the select gate lines SGD and SGS.

[0110] During the period from time t2 to t3, the line decoder 115 applies a voltage Verasgdt to the select gate line SGDT of the select block BLK. Additionally, the line decoder 115 applies a voltage Verasgsb to the select gate line SGSB of the select block BLK. The voltage Verasgdt is a high voltage used to generate GIDL in the select transistor ST1b, which is lower than the voltage Vera but higher than the voltage VDD. The voltage Verasgsb is a high voltage used to generate GIDL in the select transistor ST2b, which is lower than the voltage Vera but higher than the voltage VDD. The voltages Verasgdt and Verasgsb can be different or the same. This generates GIDL flowing between the gate and drain of the select transistors ST1b and ST2b in the select block BLK. The holes generated by the GIDL are injected into the charge storage films 232 of the storage transistors MT, dummy storage transistors MTDD and dummy storage transistors MTDS within the select block BLK. In other words, holes are supplied from the source line SL to the storage transistor MT, the dummy storage transistor MTDD, and the dummy storage transistor MTDS (data is erased).

[0111] During the period from time t2 to t3, the line decoder 115 makes the word lines WL, dummy word lines DD, and dummy word lines DS of the non-selected block BLK float. Since the word lines WL and dummy word lines DD and DS of the non-selected block BLK are in a floating state, they rise to, for example, the voltage Vera through coupling with the semiconductor layer 234 (channel) to which the voltage Vera is applied. Therefore, the storage transistor MT, dummy storage transistor MTDD, and dummy storage transistor MTDS of the non-selected block BLK are not supplied with holes (data is not erased).

[0112] Then, at time t3, a refresh operation is performed, applying voltage VSS to each wiring. The above describes the erase operation.

[0113] For the above-mentioned erasure action, it is preferable to diffuse N-type impurity elements such as phosphorus into the region of semiconductor layer 234 that overlaps with the selected gate lines SGDT and SGSB, thereby increasing the amount of holes generated through GIDL.

[0114] Figure 16 This is a schematic diagram illustrating an example of a method for diffusing phosphorus into semiconductor layer 234. For example... Figure 16 As shown, through the above heat treatment, the phosphorus contained in the semiconductor layer 214 diffuses through the contact portion with the semiconductor layer 234 to the region of the semiconductor layer 234 that overlaps with the select gate line SGSB.

[0115] N-type impurity elements such as phosphorus readily diffuse along the grain boundaries of semiconductor layer 214. Therefore, if the average crystal grain size (third average crystal grain size) of semiconductor layer 214 is large, it may lead to uneven diffusion of the aforementioned impurity elements in multiple memory pillars MP.

[0116] Figure 17 This is a schematic diagram showing the overlap between the semiconductor layer 214 and the memory pillar MP in the XY plane. Figure 17 The illustration shows multiple memory pillars MP and the grain boundaries GB of semiconductor layer 214.

[0117] like Figure 17 As shown, semiconductor layer 214 overlaps with multiple memory pillars MP in the XY plane. The multiple memory pillars MP are arranged with a specified spacing P. The spacing P is the distance between the centers of adjacent memory pillars MP in the XY plane. When the average crystal grain size of semiconductor layer 214 is large, due to the presence of memory pillars MP that overlap with and do not overlap with the grain boundary GB in the XY plane, uneven diffusion of impurity elements occurs between these memory pillars MP. This causes unevenness in the amount of holes generated through GIDL, reducing the reliability of the semiconductor memory device.

[0118] In contrast, in the semiconductor memory device of this embodiment, by suppressing the increase in the average crystal grain size of the semiconductor layer 214, the number of memory pillars MP overlapping with the grain boundary GB can be increased. Therefore, since the uneven diffusion of impurity elements between the memory pillars MP can be suppressed, a semiconductor memory device with high reliability can be provided. Furthermore, in order to increase the number of memory pillars MP overlapping with the grain boundary GB, it is preferable that the average crystal grain size of the semiconductor layer 214 is smaller than the spacing P of the memory pillars MP.

[0119] Several embodiments of the present invention have been described, but these embodiments are shown by way of example and are not intended to limit the scope of the invention. These new embodiments can also be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.

[0120] Explanation of the label

[0121] 100…Semiconductor substrate, 101…Semiconductor memory device, 102…Memory controller, 110…Memory cell array, 111…Command register, 112…Address register, 113…Sequencer, 114…Driver, 115…Line decoder, 116…Sense amplifier, 201…Conductive layer, 202…Conductive layer, 203…Insulating layer, 211…Semiconductor layer, 212…Semiconductor layer, 213…Intermediate layer, 214…Semiconductor layer, 214a…Sacrificial layer, 214b…Protective layer, 214c…Protective layer 215…Sheath layer, 216…Semiconductor layer, 217…Intermediate layer, 220…Insulating layer, 221…Conductive layer, 221a…Sacrificial layer, 222…Insulating layer, 223…Insulating layer, 231…Block insulating film, 232…Charge storage film, 233…Tunnel insulating film, 234…Semiconductor layer, 235…Core insulating layer, 236…Cap layer, 241…Conductive layer, 242…Protective layer, 243…Protective layer, 244…Oxide layer, 251…Insulating layer, 252…Contact layer, 261…Conductive layer.

Claims

1. A semiconductor memory device comprising: The first stack includes a first polycrystalline semiconductor layer having a first average crystal grain size, a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size, an intermediate layer disposed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer, and a third polycrystalline semiconductor layer disposed in contact with the second polycrystalline semiconductor layer and having a third average crystal grain size smaller than the first average crystal grain size; The second layer stack is disposed above the first layer stack and has multiple conductive layers and multiple insulating layers, wherein each of the conductive layers and each of the insulating layers are alternately stacked and extend along the first direction; A semiconductor layer extends through the second stack along a second direction intersecting the first direction and is disposed in contact with the third polycrystalline semiconductor layer; as well as A memory layer, which penetrates the second layer stack along the second direction, is disposed between the semiconductor layer and the conductive layer in the first direction. Each of the plurality of pillars, including the semiconductor layer and the memory layer, is arranged at a predetermined spacing, the spacing being the distance between the centers of adjacent pillars in a plane perpendicular to the second direction, and the third average crystal grain size is smaller than the spacing.

2. The semiconductor memory device according to claim 1, wherein, The second polycrystalline semiconductor layer is thinner than the first polycrystalline semiconductor layer.

3. The semiconductor memory device according to claim 1 or 2, wherein, The intermediate layer is thinner than the second polycrystalline semiconductor layer.

4. The semiconductor memory device according to claim 1 or 2, wherein, The intermediate layer contains oxygen, carbon, or nitrogen.

5. The semiconductor memory device according to claim 1 or 2, wherein, The third polycrystalline semiconductor layer contains phosphorus.

6. A semiconductor memory device comprising: First layer of stacked body; A second layer, disposed above the first layer, has multiple conductive layers and multiple insulating layers, wherein the conductive layers and insulating layers are alternately stacked and extend along a first direction; and Multiple columnar bodies penetrate the second layer along a second direction intersecting the first direction. The first layer of the stack comprises: The first polycrystalline semiconductor layer has a first average crystal grain size; The second polycrystalline semiconductor layer has a smaller average crystal grain size compared to the first average crystal grain size; A first intermediate layer is disposed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer; The third polycrystalline semiconductor layer has a third average crystal grain size; The fourth polycrystalline semiconductor layer has a fourth average crystal grain size; A fifth polycrystalline semiconductor layer having a fifth average crystal grain size smaller than the fourth average crystal grain size; and The second intermediate layer is disposed between the fourth polycrystalline semiconductor layer and the fifth polycrystalline semiconductor layer. The columnar body comprises: A semiconductor layer, which penetrates the second layer stack along the second direction and is disposed in contact with the third polycrystalline semiconductor layer; and A charge storage layer is disposed in the first direction between the semiconductor layer and at least one of the plurality of conductive layers. The third polycrystalline semiconductor layer is disposed between the second polycrystalline semiconductor layer and the fifth polycrystalline semiconductor layer, and is in contact with both the second and fifth polycrystalline semiconductor layers. The third average crystal grain size is smaller than the first average crystal grain size and smaller than the fourth average crystal grain size. The plurality of columnar bodies are arranged at a predetermined spacing, the spacing being the distance between the centers of adjacent columnar bodies in a plane perpendicular to the second direction, and the third average crystal grain size is smaller than the spacing.

7. The semiconductor memory device according to claim 6, wherein, The second polycrystalline semiconductor layer is thinner than the first polycrystalline semiconductor layer. The fifth polycrystalline semiconductor layer is thinner than the fourth polycrystalline semiconductor layer.

8. The semiconductor memory device according to claim 6 or 7, wherein, The first intermediate layer is thinner than the second polycrystalline semiconductor layer. The second intermediate layer is thinner than the fifth polycrystalline semiconductor layer.

9. The semiconductor memory device according to claim 6 or 7, wherein, The first intermediate layer and the second intermediate layer each contain oxygen, carbon, or nitrogen.

10. A method for manufacturing a semiconductor memory device, wherein, A first multilayer stack is formed, the first multilayer stack comprising a first polycrystalline semiconductor layer having a first average crystal grain size, a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size, a first intermediate layer between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer, and a first sacrificial layer adjoining the second polycrystalline semiconductor layer. Above the first laminate, a second laminate is formed by alternately stacking insulating layers and second sacrificial layers, each extending along a first direction. A columnar structure is formed, the columnar structure having a semiconductor layer and a memory layer, the semiconductor layer penetrating the second layer stack along a second direction intersecting the first direction, and the memory layer being disposed between the semiconductor layer and at least one of the plurality of second sacrificial layers in the first direction. The first sacrificial layer is removed in a manner that exposes the semiconductor layer to form a first space, and a third polycrystalline semiconductor layer having a third average crystal grain size smaller than the first average crystal grain size is formed in the first space. The second sacrificial layer is removed to form a second space, and a conductive layer is formed in the second space.

11. The method for manufacturing a semiconductor memory device according to claim 10, wherein, The second polycrystalline semiconductor layer is thinner than the first polycrystalline semiconductor layer.

12. The method of manufacturing a semiconductor memory device according to claim 10 or 11, wherein, The first intermediate layer is thinner than the second polycrystalline semiconductor layer.

13. The method of manufacturing a semiconductor memory device according to claim 10 or 11, wherein, The first intermediate layer contains oxygen, carbon, or nitrogen.

14. The method of manufacturing a semiconductor memory device according to claim 10 or 11, wherein, The third average crystal grain size is smaller than the spacing between the plurality of columnar structures, each comprising the semiconductor layer and the memory layer.

15. The method of manufacturing a semiconductor memory device according to claim 10 or 11, wherein, The third polycrystalline semiconductor layer contains phosphorus.

16. The method of manufacturing a semiconductor memory device according to claim 10 or 11, wherein, The first layer of the stack also has: The fourth polycrystalline semiconductor layer has a fourth average crystal grain size; The fifth polycrystalline semiconductor layer has a smaller average crystal grain size compared to the fourth average crystal grain size; as well as The second intermediate layer is disposed between the fourth polycrystalline semiconductor layer and the fifth polycrystalline semiconductor layer. The first sacrificial layer is disposed between the second polycrystalline semiconductor layer and the fifth polycrystalline semiconductor layer, and is in contact with the fifth polycrystalline semiconductor layer. The third average crystal grain size is smaller than the fourth average crystal grain size.

17. The method of manufacturing a semiconductor memory device according to claim 16, wherein, The fifth polycrystalline semiconductor layer is thinner than the fourth polycrystalline semiconductor layer.

18. The method of manufacturing a semiconductor memory device according to claim 16, wherein, The second intermediate layer is thinner than the fifth polycrystalline semiconductor layer.

19. The method for manufacturing a semiconductor memory device according to claim 16, wherein, The second intermediate layer contains oxygen, carbon, or nitrogen.

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