Three-dimensional memory and methods of making the same, memory systems

Abstract

The application provides a three-dimensional memory, a preparation method thereof, and a storage system. The preparation method of the three-dimensional memory comprises the following steps: forming a stack structure, wherein the stack structure comprises a core region and a step region; forming a channel structure penetrating through the stack structure in the core region and the stack structure in the step region, respectively; removing at least part of the stack structure in the step region which is not penetrated by the channel structure to form a step structure, wherein the stack structure in the step region which is penetrated by the channel structure forms a connection structure, and the channel structure in the step region comprises a first channel structure extending along the extension direction of the connection structure; and forming a dummy channel structure penetrating through the step structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a three-dimensional memory and its fabrication method and storage system. Background Technology

[0002] With the rapid development of integrated circuit technology, the integration requirements for three-dimensional memories (such as 3D NAND memories) are becoming increasingly stringent, and the challenges in their fabrication processes are also growing. Existing 3D NAND memories typically consist of a core region with storage functionality and a stepped region connected to the core region. An array of mechanically supported dummy channel structures is set within the stepped region. Generally, these dummy channel structures can be divided into two categories based on their location within the stepped region: one is located within the connecting structure region that isolates the stepped structure into multiple independent parts, and the other is located within the stepped structure region itself.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure, wherein the stacked structure includes a core region and a stepped region; forming a channel structure that penetrates the stacked structure within the core region and the stacked structure within the stepped region; removing at least a portion of the stacked structure within the stepped region that is not penetrated by the channel structure to form a stepped structure, wherein the stacked structure in the stepped region through which the channel structure penetrates forms a connecting structure, and the channel structure located in the stepped region includes a first channel structure extending along the extension direction of the connecting structure; and forming a dummy channel structure penetrating the stepped structure.

[0005] In one embodiment, the stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the method further includes: forming a trench extending through the connection structure in a first direction and extending in a second direction; and removing a portion of the sacrificial layer within the connection structure via the trench, wherein the first direction is the direction in which the dielectric layers and the sacrificial layers are stacked, the second direction is the direction in which the connection structure extends, and the second direction is perpendicular to the first direction.

[0006] In one embodiment, the first channel structure extends through the connecting structure along the direction in which the connecting structure extends.

[0007] In one embodiment, the step of forming the channel structure includes: providing a first mask layer having a channel hole pattern on the stacked structure, wherein the projection of the channel hole pattern on the stacked structure is located in the core region and the connecting structure, respectively; etching the stacked structure via the channel hole pattern to form a channel hole penetrating the stacked structure; and sequentially filling the channel hole with a functional layer and a channel layer to form the channel structure.

[0008] In one embodiment, the step of forming the dummy channel structure includes: providing a second mask layer having a dummy channel hole pattern on the stacked structure, wherein the projection of the dummy channel hole pattern on the stacked structure is located in a region outside the connecting structure of the step region; removing a portion of the stacked structure via the dummy channel hole pattern to form a dummy channel hole; and forming a filling layer within the dummy channel hole.

[0009] In one embodiment, the channel hole pattern includes a first pattern and a second pattern projected within the connecting structure, the first pattern extending along the second direction, and the channel structure within the step region further includes a second channel structure, wherein the steps of forming the first channel structure and the second channel structure include: removing a portion of the stacked structure via the first pattern and the second pattern to form the first channel hole and the second channel hole respectively; and filling the functional layer and the channel layer into the first channel hole and the second channel hole respectively to form the first channel structure and the second channel structure.

[0010] In one embodiment, after forming the step structure, the method further includes: covering the step structure with a step medium layer, and in the step of forming the dummy channel structure, the dummy channel structure penetrates the step medium layer.

[0011] In one embodiment, the projections of a plurality of second channel structures in a plane perpendicular to the first direction are arranged in an array, the array comprising a plurality of rows extending along the second direction, and the projections of the first channel structures in the plane perpendicular to the first direction are located in the array and parallel to the rows.

[0012] In one embodiment, the projection of the trench in a plane perpendicular to the first direction lies within the array and is parallel to the first channel structure.

[0013] This application also provides a three-dimensional memory, comprising: a stacked structure including a core region and a stepped region, wherein the stepped region has a connecting structure and a stepped structure, the connecting structure isolating the stepped structure into multiple independent parts; a channel structure penetrating the stacked structure and the connecting structure in the core region, wherein the channel structure penetrating the connecting structure includes a first channel structure extending in the direction of the connecting structure; and a dummy channel structure penetrating the stepped structure.

[0014] In one embodiment, the stacked structure includes alternately stacked dielectric and gate layers, and the three-dimensional memory further includes a trench structure extending through the connection structure in a first direction and extending in a second direction, wherein the first direction includes the direction in which the dielectric and gate layers are stacked, and the second direction is perpendicular to the first direction and includes the direction in which the connection structure extends.

[0015] In one embodiment, the channel structure penetrating the connecting structure further includes a second channel structure, and the dimension of the first channel structure in the extension direction of the connecting structure is greater than the dimension of the second channel structure in the same direction.

[0016] In one embodiment, the first channel structure extends through the connecting structure along the direction in which the connecting structure extends.

[0017] In one embodiment, the channel structure includes a functional layer and a channel layer, and the dummy channel structure includes a filling layer.

[0018] In one embodiment, the projections of a plurality of first channel structures in a plane perpendicular to the first direction are arranged in an array, the array comprising a plurality of rows extending along the extension direction of the connecting structure, and the projections of the second channel structures in the plane perpendicular to the first direction are located in the array and parallel to the rows.

[0019] In one embodiment, the projection of the trench structure onto a plane perpendicular to the first direction lies within the array and is parallel to the first trench structure.

[0020] In one embodiment, the three-dimensional memory further includes a stepped dielectric layer covering the stepped structure, wherein the dummy channel structure penetrates the stepped dielectric layer and the stepped structure.

[0021] In another aspect, this application provides a three-dimensional memory system, comprising: a three-dimensional memory as described in any of the above embodiments, wherein the three-dimensional memory includes a storage string for storing data; and a controller electrically connected to the three-dimensional memory and configured to control the operation of the storage string.

[0022] In one embodiment, the three-dimensional memory includes a 3D NAND memory.

[0023] The method for fabricating the three-dimensional memory provided in this application can have at least one of the following beneficial effects:

[0024] According to some embodiments of this application, replacing the channel hole filling material in the stepped region connection structure with a composite filling material with excellent mechanical properties can provide good support for the device stacking structure, thereby reducing defects such as gate layer bending and reducing the risk of electrical problems such as voltage breakdown; and

[0025] According to some embodiments of this application, a high-performance support structure can be formed during the process steps of forming the channel structure without introducing additional processes, which helps to reduce costs. Attached Figure Description

[0026] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0027] Figure 1 This is a planar layout diagram of the stepped area of ​​a three-dimensional memory according to an exemplary embodiment;

[0028] Figure 2 This is a planar layout diagram of the core area of ​​a three-dimensional memory according to an exemplary embodiment;

[0029] Figure 3 This is a schematic diagram of a three-dimensional memory channel structure according to an exemplary embodiment;

[0030] Figure 4 This is a schematic diagram of a three-dimensional memory virtual channel structure according to an exemplary embodiment; Figure 5 These are scanning electron microscope images of the stacked structure of a three-dimensional memory according to an exemplary embodiment;

[0031] Figure 6 and Figure 7 yes Figure 5 Enlarged view of the area within the dashed box;

[0032] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of this application;

[0033] Figures 9 to 14 This is a schematic diagram of the fabrication process of a semiconductor structure according to an exemplary embodiment of this application;

[0034] Figure 15This is a planar layout diagram of a semiconductor structure according to an exemplary embodiment of this application; and

[0035] Figure 16 This is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of this application. Detailed Implementation

[0036] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the second channel structure discussed herein may also be referred to as the first channel structure, and the first region may also be referred to as the second region, and vice versa.

[0038] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the dielectric layer shown in the drawings in this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0039] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0040] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] The features, principles and other aspects of this application are described in detail below.

[0043] Figure 1 This is a plan view of the stepped area 100 of a three-dimensional memory according to an exemplary embodiment. Figure 2 This is a planar layout diagram of the core region 200 of a three-dimensional memory based on related technology. The three-dimensional memory includes a stepped region 100 and a core region 200. Understandably... Figure 1 and Figure 2 This is not a top view of a partial structure of the three-dimensional memory, but rather a planar layout of the stepped area 100 and the core area 200 of the three-dimensional memory, respectively. Figure 1 As shown, the step region 100 may include a first step structure 110, a connecting structure 120, and a second step structure 130. Virtual channel structures 111 are distributed within the first step structure 110, the connecting structure 120, and the second step structure 130, forming an array. The processing of the first step structure 110, the connecting structure 120, and the second step structure 130 is performed before the formation of the virtual channel structures 111. Specifically, a mask layer 112 with a pattern of the first step structure 110 and the second step structure 130 can be covered on the step region 100, and the step region 100 can be etched multiple times through this pattern to form the first step structure 110 and the second step structure 130. The connecting structure 120 is protected by the mask layer 112 and is retained after the etching process.

[0044] like Figure 2 As shown, the core region 200 includes a channel structure 210 and a channel structure 220, which may have different critical dimensions. A dummy channel structure 111 runs through the step region 100 connected to the core region 200. In the process steps of forming the first step structure 110, the connecting structure 120, and the second step structure 130, the first channel structure 210, the second channel structure 220 within the core region 200, and the dummy channel structure 111 located in the boundary region between the core region 200 and the step region 100 are all covered by a mask layer 112, thus preventing them from being etched in this etching step.

[0045] The inventors of this application have discovered that, in order to meet the functional requirements of storing charge, the first channel structure 210 and the second channel structure 220 are respectively filled with a functional layer, a channel layer, and a channel dielectric layer. Figure 3 (As shown). Due to cost limitations, in the fabrication process of three-dimensional memory such as 3D NAND, insulating material is typically filled into the dummy channel holes to form a dummy channel structure 111 ( Figure 4 (As shown). The dummy channel structure 111 plays a supporting role in the device structure. If the supporting force it provides is insufficient, the dielectric layer will bend and shift under the action of surface tension during the subsequent sacrificial layer removal process, causing the gate layer to also bend after filling. Figures 5 to 7 The scanning electron microscope image of the stacked structure shows the gate layer ( Figures 5 to 7 The black stripes in the middle show a clear concave trend, which may cause electrical problems such as voltage breakdown. The mechanical properties of the insulating material filled in the dummy channel are insufficient to provide good device support, posing a risk of degraded device performance.

[0046] This application proposes a three-dimensional memory and a method for manufacturing the same, which can at least partially improve or solve the aforementioned problems, and significantly enhance the performance of the device without significantly increasing costs. The three-dimensional memory described in this application context can be a semiconductor structure, or may include semiconductor structures and other components.

[0047] Figure 8 This is a flowchart of a semiconductor structure fabrication method 1000 according to an embodiment of this application. For example... Figure 8 As shown, this application provides a method 1000 for fabricating a semiconductor structure, comprising:

[0048] Step S1100: A layered structure is formed, wherein the layered structure includes a core area and a step area;

[0049] Step S1200: Forming a channel structure that runs through the stacked structure in the core area and the stacked structure in the stepped area respectively;

[0050] Step S1300: Remove at least a portion of the stacked structure within the stepped area that is not penetrated by the channel structure to form a stepped structure, wherein the stacked structure in the stepped area penetrated by the channel structure forms a connecting structure, and the channel structure in the stepped area includes a first channel structure extending along the extension direction of the connecting structure; and

[0051] Step S1400: A virtual channel structure is formed that runs through the stepped structure.

[0052] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps shown may be performed simultaneously or in a manner different from [the steps described in the original text]. Figure 8 The execution is performed in the order shown.

[0053] Figures 9 to 14 This is a schematic diagram of a method 1000 for fabricating a semiconductor structure 300 according to an embodiment of this application. Exemplarily, the semiconductor structure 300 can serve as an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. The following is in conjunction with... Figures 9 to 14 The above steps S1100 to S1400 are further described.

[0054] Step S1100: A layered structure is formed, wherein the layered structure includes a core area and a step area.

[0055] like Figure 9 As shown, the steps for forming the stacked structure 310 include sequentially and alternately stacking a dielectric layer 311 and a sacrificial layer 312. The stacked structure 310 may include a core region C1 and a step region SS. In some embodiments, during the process of removing the sacrificial layer, the sacrificial layer 312 and the dielectric layer 311 may have a high etch selectivity under a first etch condition, so that the dielectric layer 311 is hardly removed when the sacrificial layer 312 is completely removed. In processes such as forming channel contact holes, step structures, and gate gaps, the sacrificial layer 312 and the dielectric layer 311 may have a smaller etch selectivity under another etch condition, making it easier to remove both simultaneously.

[0056] Exemplarily, the material used for the sacrificial layer 312 includes, for example, silicon nitride, and the material used for the dielectric layer 311 includes, for example, silicon oxide. Exemplarily, a stacked structure 310 can be formed by alternately forming multiple sacrificial layers 312 and dielectric layers 311 through thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0057] In some embodiments, the semiconductor structure 300 further includes a substrate 320 on which a stacked structure 310 perpendicular or substantially perpendicular to the substrate 320 may be formed. Exemplarily, the material of the substrate 320 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof.

[0058] In other embodiments, the substrate 320 may be a composite structure, such as including a substrate and a composite layer located on the substrate, wherein the substrate has a certain thickness and can serve as a structural support for a device structure (e.g., stacked structure 310) formed thereon, and alternatively, the substrate may be removed in some subsequent process steps.

[0059] Step S1200: Forming a channel structure that runs through the stacked structure in the core area and the stacked structure in the stepped area respectively.

[0060] refer to Figure 9 and Figure 10 As shown, a channel hole 330 is formed by penetrating the portion of the stacked structure 310 located within the core region C1 and the portion of the stacked structure 310 located within the step region SS. The channel hole 330 is then filled with subsequent processes to form a channel structure 330'. Figure 11 (See illustration). It should be noted that the channel structures 330' located in the step region SS and the core region C1 are both filled with the same material and can have the same structure. However, the channel structure 330' located in the core region C1 can be connected to the conductive interconnect layer through conductive metal in subsequent processes and is controlled by external circuits, thus having a storage function; the channel structure 330' located in the step region SS is not connected to the external circuit, does not have a storage function, and can provide mechanical support for the step region SS.

[0061] Figure 10 This is a schematic diagram of the arrangement of channel holes 330 within the stepped region SS. Exemplarily, the stepped region SS can be divided into a first region 10, a second region 20, and a third region 30, with the first region 10 separating the second region 20 and the third region 30. Channel holes 330 are formed in the first region 10 within the stepped region SS. The core region C1 may be located on at least one side of the first region 10 along the x-direction and along the opposite x-direction.

[0062] It should be understood that the size, shape, and position of the first region 10, the second region 20, and the third region 30 of the laminated structure 310 of this application are merely illustrative examples and not intended to limit its scope. Those skilled in the art can design the first region 10, the second region 200, the third region 30, or even more regions within the step region SS according to actual needs. It should also be understood that the number of layers in the laminated structure 310 is not limited to... Figure 9 The number of layers shown is not the actual number of layers. The number of stacked layers and the stacking height of the stacked structure 310 can be designed according to actual needs. This application does not make specific limitations on this.

[0063] In some embodiments, a first mask layer 340 with a channel hole pattern may be formed on the stacked structure 310 (along the z-direction), the projection of which onto the stacked structure 310 is located within a first region 10 in the core region C1 and the step region SS, respectively. A portion of the stacked structure 310 may be removed via the channel hole pattern using a process such as etching to form a channel hole 330. The channel hole 330 may penetrate the stacked structure 310 and extend into the substrate 320.

[0064] In some embodiments, the aforementioned via pattern may include a first pattern and a second pattern, and the via 330 includes a first via 331 and a second via 332. The projection of the first pattern in the first region 10 corresponds to the first via 331, and the projection of the second pattern in the first region 10 corresponds to the second via. The first via 331 / first pattern may penetrate the stacked structure 310 in the opposite direction of z (first direction) and extend in the direction extending from the first region 10 (second direction, including the x direction). The second via 332 penetrates the stacked structure in the opposite direction of z. In some embodiments, the first via 331 penetrates the first region 10 in the x direction. The projection shape of the first via 331 on the substrate 320 may be a regular and / or irregular shape extending in the x direction, such as a rectangular shape, the long side of which is parallel to the x direction. The projection of the second via 332 on the substrate 320 includes a rectangular, circular, or irregular shape, and forms an array, with the projections of multiple via structures 332 extending in the x direction to form rows of the array. The projection of the first channel hole 331 onto the substrate 320 lies within the array projection range and is parallel to the aforementioned row.

[0065] For example, a combination of photolithography and etching processes can be used to etch the portion of the stacked structure 310 located in the first region 10 into a first channel hole 331 and a second channel hole 332.

[0066] In some embodiments, the via 330 may consist of N (N≥2) sub-channel holes. Exemplarily, a first sub-stack structure 310-1 may be formed on the substrate 320. A first sub-channel hole 330-1 extending through the first sub-stack structure 310-1 and into the substrate 320 may be formed in the first sub-stack structure 310-1 using, for example, an etching process. The first sub-channel hole 330-1 is then filled with filler. Subsequent sub-stack structures and sub-channel holes are formed on the side of the first sub-stack structure 310-1 away from the substrate 320, until the Nth sub-stack structure (not shown) and the Nth sub-channel hole (not shown) are formed. N-1 fillers are correspondingly filled into the N-1 sub-channel holes, excluding the Nth sub-channel hole. For example, an etching process can be used to remove the filler in the N-1 sub-channel holes based on the Nth sub-channel hole, so that the upper and lower adjacent sub-channel holes in the N sub-channel holes are at least partially aligned with each other to form channel hole 330.

[0067] like Figure 11 As shown, after forming the channel via 330, the fabrication process of the semiconductor structure 300 further includes filling the channel via 330 with a functional layer 350 and a channel layer 360 to form a channel structure 330'. The channel structure 330' may also include a channel dielectric layer 370 located in the remaining space after the formation of the channel layer 360. The functional layer 350 may include a barrier layer 351, a charge trapping layer 352, and a tunneling layer 353, which may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. Exemplarily, the barrier layer 351, the charge trapping layer 352, the tunneling layer 353, the channel layer 360, and the channel dielectric layer 370 are sequentially formed on the inner wall and bottom of the channel via 330. In some examples, the channel layer 360 in the channel structure 330' located in the core region can be used to transport the required charge (electrons or holes). The material of the channel layer 360 includes, for example, doped polysilicon. The material of the channel dielectric layer 370 includes, for example, silicon oxide or silicon oxynitride.

[0068] In some embodiments, the channel 330' penetrating the connecting structure 10' includes a first channel structure 331' and a second channel structure 332', wherein the first channel structure 331' extends in the direction of extension of the connecting structure 10' (e.g., the x-direction). Both the first channel structure 331' and the second channel structure 332' are filled with a functional layer 350 and a channel layer 360.

[0069] For example, a barrier layer 351, a charge trapping layer 352, and a tunneling layer 353 may be deposited sequentially using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). Then, a channel layer 360 may be deposited on the side of the tunneling layer 353 away from the channel hole 330, and a channel dielectric layer 370 may be deposited within the space defined after the formation of the channel layer 360.

[0070] In some embodiments, the channel structure 330' further includes a channel plug 371 formed on top of the channel dielectric layer 370, the channel plug 371 contacting the channel layer 360 to achieve electrical connection. The channel plug 371 may be made of the same material as the channel layer 360, such as doped polysilicon. In one example of this application, the portion of the channel dielectric layer 370 located on top of the channel via 330 may be processed by wet etching and / or dry etching to form a recess on top of the channel via 330, and then a semiconductor material such as polysilicon may be deposited into the recess by one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to form the channel plug 371.

[0071] In some implementations, one side of the channel plug 371 may be electrically connected to the channel layer 360, and the other side of the channel plug 371 may be electrically connected to the back-end interconnect structure (Array BEOL), and electrically connected to the peripheral circuit wafer based on the back-end interconnect structure.

[0072] In some embodiments, the channel structure 330' may further include a selective epitaxial layer 372 located at the bottom of the channel hole 330 and in contact with the substrate 320. The lower end of the channel layer 360 (in the opposite direction of z) is connected to the selective epitaxial layer 372. The selective epitaxial layer 372 may be made of the same material as the channel layer 360, such as doped polysilicon.

[0073] Step S1300: Remove at least a portion of the stacked structure in the step area that is not penetrated by the channel structure to form a step structure, wherein the stacked structure in the step area that is penetrated by the channel structure forms a connecting structure, and the channel structure in the step area includes a first channel structure extending along the extension direction of the connecting structure.

[0074] Figure 12 This is a view of the semiconductor structure 300 according to an embodiment of this application, taken along the z-reverse direction. Figure 12 As shown, a portion of the stacked structure 310 within the step region SS can be removed to form a step structure 380. This removed portion includes the portion of the stacked structure 310 located within the step region SS that is not penetrated by the channel structure 330'. The step structure 380 includes a first step structure 381 and a second step structure 382. Exemplarily, a portion of the second region 20 can be removed to form the first step structure 381, and a portion of the third region 30 can be removed to form the second step structure 382. The portion of the stacked structure 310 located within the first region 10 forms a connecting structure 10'. The first step structure 381 and the second step structure 382 are isolated into independent portions by the connecting structure 10', which extends along the x-direction.

[0075] For example, a portion of the second region 20 and the third region 30 can be removed by a combination of photolithography and etching processes. Specifically, a second mask layer 341 including a pattern of a first step structure 381 and a second step structure 382 can be formed on the stacked structure 310, and the stacked structure 310 can be etched through the patterned area. Since the first region 10 is covered by the second mask layer 341, it is retained in the etching step, forming a connection structure 10' that blocks the first step structure 381 and the second step structure 382.

[0076] Step S1400: A virtual channel structure is formed that runs through the stepped structure.

[0077] Combination Figure 12 and Figure 13As shown, after forming the stepped structure 380, a stepped dielectric layer 383 is covered on the stepped structure 380, and a dummy channel hole 390 is formed penetrating the stepped dielectric layer 383 and the stepped structure 380. Exemplarily, the dummy channel hole 390 may include a first dummy channel hole 391 and a second dummy channel hole 392. The first dummy channel hole 391, located in the second region 20, penetrates the stepped dielectric layer 383 and the first stepped structure 381 and extends to the substrate 320. The second dummy channel hole 392, located in the third region 30, penetrates the stepped dielectric layer 383 and the second stepped structure 382 and extends to the substrate 320. The projections of the first dummy channel hole 391 and the second dummy channel hole 392 onto the substrate 320 are arranged as a second array and a third array, respectively. Both the second array and the third array consist of multiple rows extending in the x-direction and multiple columns extending in the y-direction. Their projection shapes can include circles, rectangles, or any irregular shapes.

[0078] For example, one or more thin film deposition processes (e.g., CVD, PVD, ALD or any combination thereof) can be used to cover the step dielectric layer 383 on the first step structure 381 and the second step structure 382, ​​and a combination of photolithography and etching processes can be used to etch the step dielectric layer 383 and the second region 20 and the third region 30 of the stacked structure 310 to form a dummy channel hole 390.

[0079] In some embodiments, a filling layer 394 is deposited within the dummy channel via 390 to form a dummy channel structure 390'. For example, one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) may be used to fill the dummy channel via 390 with an insulating material (including silicon oxide) to form the dummy channel structure 390'.

[0080] In the context of this invention, some steps, such as planarization, surface cleaning, and slag removal, are omitted from the manufacturing methods of the channel hole 330, the dummy channel hole 390, the first step structure 381, the second step structure 382, ​​and the step medium layer 383. These are not the focus of this invention and will not be described further here. Those skilled in the art can add or remove steps from the manufacturing method of this invention as needed.

[0081] like Figure 14As shown, in some embodiments, the fabrication process of the semiconductor structure 300 further includes forming trenches 393 within the stacked structure 310, the trenches 393 being located within the first region 10; in other embodiments, the trenches 393 are also located within the second region 20 and the third region 30 (not shown). The number of trenches 393 may include multiple trenches, extending along the x-direction, the length of the trenches 393 in the x-direction being less than the length of the first channel structure 331' in the same direction. In subsequent processes, the sacrificial layer 312 within the connection structure 10' can be removed via the trenches 393, and the trench structure 393' can be formed by filling it with, for example, an insulating material (see reference). Figure 15 (As shown).

[0082] In some embodiments, the projection of trench 393 onto substrate 320 lies within the array formed by the projection of second channel structure 332' onto substrate 320 and is parallel to first channel structure 331'.

[0083] Another aspect of this application provides a three-dimensional memory, which can be prepared using any of the preparation methods described in the above embodiments.

[0084] Figure 15 This is a planar layout diagram of the semiconductor structure 400 according to an embodiment of this application. Exemplarily, the semiconductor structure 400 can serve as an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. Figure 15 As shown, the semiconductor structure 400 may include a stacked structure 310', a channel structure 330', and a dummy channel structure 390'. The stacked structure 310' may include a core region C1 and a step region SS. Figure 9 (As shown), the step region SS may have a connecting structure 10' and a step structure 380. A channel structure 330' penetrates both the stacked structure 310' within the core region C1 and the connecting structure 10' within the step region SS. The channel structure penetrating the connecting structure 10' includes a first channel structure 331' and a second channel structure 332'. The first channel structure 331' is located within an array of multiple second channel structures 332' and extends along the extension direction (x-direction) of the connecting structure 10'. A dummy channel structure 390' penetrates the step structure 380.

[0085] Exemplarily, the stacked structure 310' may be divided into a first region 10, a second region 20, and a third region 30. The stepped structure 380 may include a first stepped structure 381 and a second stepped structure 382. Exemplarily, the first stepped structure 381 is located within the second region 20, and the second stepped structure 382 is located within the third region 30, with the first region 10 separating the second region 20 and the third region 30. It is understood that the first region 10 may isolate the first stepped structure 381 and the second stepped structure 382 into mutually independent parts.

[0086] In some embodiments, the semiconductor structure 400 further includes a trench structure 393' located within the first region 10; in other embodiments, the trench structure 393' is also located within a second region 20 and a third region 30 (not shown). The number of trench structures 393' may be multiple, and they extend along the x-direction, with the length of the trench structure 393' in the x-direction being less than the length of the first channel structure 331' in the same direction.

[0087] In some embodiments, the portion of the channel structure 330' located within the first region 10 includes a first channel structure 331' and a second channel structure 332'. (See reference...) Figure 11 The channel structure 330' may be formed by a functional layer 350 and a channel layer 360, and may further include a channel dielectric layer 370 located in the remaining space after the formation of the channel layer 360. The functional layer 350 may include a barrier layer 351, a charge trapping layer 352, and a tunneling layer 353, and may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer 360 can be used to transport the required charge. The material of the channel layer 360 includes, for example, doped polysilicon. The material of the channel dielectric layer 370 includes, for example, silicon oxide or silicon oxynitride.

[0088] In some embodiments, the semiconductor structure 400 further includes a semiconductor layer on which the stacked structure 310' is located. Both the first channel structure 331' and the second channel structure 332' penetrate the portion of the stacked structure 310' located within the first region 10 and extend to the semiconductor layer. The first channel structure 331' may penetrate the stacked structure 310' in the opposite z-direction. The second channel structure 332' penetrates the stacked structure 310' in the opposite z-direction and also penetrates the portion of the stacked structure 310' located within the first region 10 in the x-direction. In some embodiments, the core region 200 may be located on at least one side of the first region 10 in the x-direction and in the opposite x-direction. The projection shape of the first channel structure 331' onto the semiconductor layer may be rectangular, circular, or any irregular shape. The projection of the second channel structure 332' onto the semiconductor layer forms an array consisting of multiple rows extending in the x-direction. The projection shape of the first channel structure 331' onto the semiconductor layer extends in the x-direction and is parallel to the aforementioned rows.

[0089] In some embodiments, the first channel structure 331' extends through the connecting structure 10' in the direction (x-direction). The groove structure 393' is within the connecting structure 10' and parallel to the first channel structure 331'.

[0090] In some embodiments, the semiconductor structure 400 further includes a stepped dielectric layer 383 and a dummy channel structure 390' penetrating the stepped dielectric layer 383 (see reference). Figure 13A stepped dielectric layer 383 covers the first stepped structure 381 and the second stepped structure 382. A dummy channel structure 390' located in the second region 20 penetrates the stepped dielectric layer 383 and the first stepped structure 381; a dummy channel structure 390' located in the third region 30 penetrates the stepped dielectric layer 383 and the second stepped structure 382. The dummy channel structure 390' includes a filler layer 394. Exemplarily, the filler layer 394 is made of, for example, silicon oxide.

[0091] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0092] Another aspect of this application provides a three-dimensional memory system, such as Figure 16 As shown, the three-dimensional storage system includes a three-dimensional memory 401 and a controller 402 as described in any embodiment of this application. The three-dimensional memory includes multiple memory strings with storage functions, and each memory string may be composed of multiple memory cells. The controller 402 can be electrically connected to the three-dimensional memory 401 via peripheral circuitry and is configured to control the operation of the memory strings.

[0093] In some embodiments, memory 401 is electrically connected to and controlled by controller 402. Controller 402 may, for example, control the application of different voltage signals to memory cells (not shown) in memory 401 to achieve the effect of controlling memory 401 to perform at least one of, for example, read operations, programming operations, and erase operations. Controller 402 may be configured to control the operation of memory 401, such as read, programming, and erase operations. Controller 402 may also be configured to manage various functions related to data stored or to be stored in memory 401, such as bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0094] In some embodiments, the three-dimensional memory system includes a solid-state drive (SSD), a memory card, or any combination thereof. The three-dimensional memory 401 includes 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the three-dimensional memory system also includes a connector 403, which can be connected to a device such as a host computer for transmitting data.

[0095] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A stacked structure is formed, the stacked structure including dielectric layers and sacrificial layers alternately stacked along a first direction, wherein the stacked structure includes a core region and a step region along a second direction; the step region includes a first region, a second region and a third region along a third direction, the first region being located between the second region and the third region; the first direction, the second direction and the third direction are perpendicular to each other; A channel structure is formed that runs through the stacked structure in the core area and the stacked structure in the first region, respectively. The stacked structures of the second region and the third region are removed to form a first step structure and a second step structure, respectively. The total number of dielectric layers and sacrificial layers in the first region is equal to the total number of dielectric layers and sacrificial layers in the core region. The stacked structure of the first region forms a connecting structure that extends along the second direction and is located between the first step structure and the second step structure in the third direction. A virtual channel structure is formed that runs through the first step structure and the second step structure.

2. The method according to claim 1, wherein, The method further includes: A groove is formed that penetrates the connection structure along the first direction and extends along the second direction; and The portion of the sacrificial layer located within the connection structure is removed via the trench.

3. The method according to claim 1, wherein, The channel structure of the first region includes a first channel structure, which penetrates the connecting structure along the second direction.

4. The method according to claim 3, wherein, The steps for forming the channel structure include: A first mask layer with a channel hole pattern is provided on the stacked structure, wherein the projection of the channel hole pattern on the stacked structure is located in the core region and the first region, respectively; The stacked structure is etched via the aforementioned channel pattern to form channel holes penetrating the stacked structure; and The channel structure is formed by sequentially filling the channel holes with functional layers and channel layers.

5. The method according to claim 1, wherein, The steps for forming the virtual channel structure include: A second mask layer with a dummy channel hole pattern is provided on the stacked structure, wherein the projection of the dummy channel hole pattern on the stacked structure is located in the second region and the third region; A dummy channel is formed by removing a portion of the stacked structure via the dummy channel pattern; and A filling layer is formed inside the dummy channel hole.

6. The method according to claim 4, wherein, The channel hole pattern includes a first pattern and a second pattern projected within the connecting structure, the first pattern extending along the second direction, and the channel structure within the first region further includes a second channel structure. The steps for forming the first channel structure and the second channel structure include: A portion of the stacked structure is removed via the first pattern and the second pattern to form a first channel hole and a second channel hole, respectively; and The functional layer and the channel layer are filled into the first channel hole and the second channel hole, respectively, to form the first channel structure and the second channel structure.

7. The method according to claim 1, wherein, After forming the stepped structure, the method further includes: A step medium layer is covered on the step structure, and In the step of forming the dummy channel structure, the dummy channel structure penetrates the step medium layer.

8. The method according to claim 6, wherein, The first region has multiple second channel structures comprising multiple rows arranged along the third direction, with the multiple rows of second channel structures distributed on both sides of the first channel structure along the third direction.

9. The method according to claim 2, wherein, The trench extends along the second direction and is formed within the stacked structure of the first region.

10. A three-dimensional memory, comprising: A stacked structure includes dielectric layers and gate layers alternately stacked along a first direction, and a core region and a stepped region along a second direction. The stepped region has a connection structure, a first stepped structure and a second stepped structure, along a third direction. The stacked structure of the stepped region forms the connection structure, which extends along the second direction and is located between the first and second stepped structures in the third direction. The total number of dielectric and gate layers in the connection structure is equal to the total number of dielectric and gate layers in the core region. The first direction, the second direction, and the third direction are perpendicular to each other. Multiple channel structures, along the first direction, respectively penetrate the stacked structure in the core area and the connecting structure, and A fictitious channel structure is constructed, penetrating both the first and second step structures.

11. The three-dimensional memory according to claim 10, wherein, The three-dimensional memory also includes: The groove structure penetrates the connecting structure along the first direction and extends along the second direction.

12. The three-dimensional memory according to claim 10, wherein, The channel structure penetrating the connecting structure includes a first channel structure and a second channel structure, wherein the first channel structure extends along the second direction, and The dimension of the first channel structure in the second direction is greater than the dimension of the second channel structure in the second direction.

13. The three-dimensional memory according to claim 12, wherein, The first channel structure penetrates the connecting structure along the second direction.

14. The three-dimensional memory according to claim 10 or 12, wherein, The channel structure includes a functional layer and a channel layer, and the virtual channel structure includes a filling layer.

15. The three-dimensional memory according to claim 12, wherein, The connection structure includes multiple second channel structures arranged in multiple rows along the third direction, with the multiple rows of second channel structures distributed on both sides of the first channel structure along the third direction.

16. The three-dimensional memory according to claim 11, wherein, The groove structure extends along the second direction and is formed within the stacked structure of the connecting structure.

17. The three-dimensional memory according to claim 10, wherein, Also includes: A step medium layer covers the step structure. The dummy channel structure penetrates both the stepped medium layer and the stepped structure.

18. A three-dimensional memory system, comprising: The three-dimensional memory as described in any one of claims 10-17, wherein the three-dimensional memory includes a storage string for storing data; and A controller, electrically connected to the three-dimensional memory, is configured to control the operation of the memory string.

19. The three-dimensional memory system according to claim 18, wherein, The three-dimensional memory includes 3D NAND memory.

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