Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a metal oxide active portion, a gate, an insulating portion, source and drain electrodes, and a conductive portion. The metal oxide active portion is disposed on the substrate and includes a semiconductor portion connected and disposed on the same layer and conductive portions disposed on both sides of the semiconductor portion. The gate is disposed on one side of the metal oxide active portion and is disposed corresponding to the semiconductor portion. The insulating portion is disposed between the metal oxide active portion and the gate. The source and drain electrodes are disposed on the metal oxide active portion and connected to the metal oxide active portion. The conductive portion is disposed on the side of the metal oxide active portion away from the source and drain electrodes and is in contact with the metal oxide active portion. The conductive portion is disposed corresponding to the conductive portion. The conductive portion contains electrons, therefore, by disposing of the conductive portion below and in contact with the metal oxide active portion, the carrier concentration of the metal oxide active portion can be increased, thereby increasing the on-state current of the device.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] With the advent of the information age, display devices are rapidly developing towards flat panel and energy-efficient designs. Among these, active array driven display devices using thin-film transistors (TFTs) as switching elements have become the leading flat panel display technologies. A TFT is a field-effect semiconductor device, comprising several important components such as a substrate, active layer, insulating layer, gate, source, and drain. The active layer has a crucial impact on device performance and manufacturing processes. In the past decade or so, TFTs using amorphous silicon and polycrystalline silicon as active layers have experienced rapid development due to their advantages of small size, light weight, and high quality. However, amorphous silicon TFTs suffer from drawbacks such as low field-effect mobility, high photosensitivity, and material opacity, while polycrystalline silicon TFTs have complex large-area fabrication processes and are difficult to achieve with low-temperature processes.

[0003] In this context, it has been found that replacing silicon with metal oxides such as IGZO (indium gallium zinc oxide) as the active layer of thin-film transistors has minimal impact on the original TFT structural design, and the process flow for the remaining structures remains largely unchanged, making equipment modification relatively simple.

[0004] However, existing metal-oxide thin-film transistors (MOSTs) also have their own drawbacks. For example, the low carrier concentration in the active layer of the MOST results in a small on-state current, leading to poor device performance. Summary of the Invention

[0005] This application provides an array substrate and a display panel to solve the problem of low carrier concentration in the active part of the metal oxide.

[0006] This application provides an array substrate, comprising:

[0007] Substrate;

[0008] A metal oxide active portion is disposed on the substrate, and the metal oxide active portion includes a semiconductor portion connected and disposed in the same layer and a conductive portion disposed on both sides of the semiconductor portion;

[0009] A gate is disposed on one side of the active portion of the metal oxide and is disposed corresponding to the semiconductor portion;

[0010] An insulating portion is disposed between the metal oxide active portion and the gate.

[0011] Source and drain electrodes, wherein the source and drain electrodes are disposed on and connected to the active portion of the metal oxide; and

[0012] A conductive portion is disposed on the side of the metal oxide active portion away from the source and drain electrodes and is in contact with the metal oxide active portion. The conductive portion is disposed correspondingly to the conductive portion.

[0013] Optionally, in some embodiments of this application, the conductive portion includes a first portion and a second portion that are on the same layer and connected. The first portion is located on the side of the insulating portion away from the semiconductor portion, and the second portion is located on the side of the insulating portion close to the semiconductor portion. The first portion is disposed corresponding to the conductive portion, and the second portion is disposed corresponding to a portion of the semiconductor portion.

[0014] Optionally, in some embodiments of this application, the length of the second portion is 15-22% of the length of the semiconductor portion.

[0015] Optionally, in some embodiments of this application, the edge of the orthographic projection of the first portion on the substrate is located within the orthographic projection of the conductive portion on the substrate.

[0016] Optionally, in some embodiments of this application, the edge of the orthographic projection of the first portion on the substrate overlaps with the edge of the orthographic projection of the conductive portion on the substrate.

[0017] Optionally, in some embodiments of this application, the gate is disposed on the substrate, the insulating portion is disposed on the substrate and the gate, the conductive portion is disposed on the insulating portion, the metal oxide active portion is disposed on the insulating portion and the conductive portion, and the source and drain are disposed on the metal oxide active portion.

[0018] Optionally, in some embodiments of this application, the conductive portion is disposed on the substrate, the metal oxide active portion is disposed on the conductive portion and the substrate, the insulating portion is disposed on the metal oxide active portion, the gate is disposed on the insulating portion, and the source and drain are disposed on the metal oxide active portion.

[0019] Optionally, in some embodiments of this application, the orthographic projection of the conductive portion on the substrate lies within the orthographic projection of the conductive portion on the substrate.

[0020] Optionally, in some embodiments of this application, the edge of the orthographic projection of the conductive portion on the substrate overlaps with the edge of the orthographic projection of the conductive portion on the substrate.

[0021] This application also provides a display panel, including the array substrate and a light-emitting structure layer disposed on the array substrate.

[0022] This application discloses an array substrate and a display panel. The array substrate includes a substrate, a metal oxide active portion, a gate, an insulating portion, source and drain electrodes, and a conductive portion. The metal oxide active portion is disposed on the substrate and includes a semiconductor portion connected and disposed on the same layer and conductive portions disposed on both sides of the semiconductor portion. The gate is disposed on one side of the metal oxide active portion and is disposed corresponding to the semiconductor portion. The insulating portion is disposed between the metal oxide active portion and the gate. The source and drain electrodes are disposed on the metal oxide active portion and connected to the metal oxide active portion. The conductive portion is disposed on the side of the metal oxide active portion away from the source and drain electrodes and is in contact with the metal oxide active portion. The conductive portion is disposed corresponding to the conductive portion. The conductive portion contains electrons, therefore, by disposing a conductive portion below and in contact with the metal oxide active portion, the carrier concentration of the metal oxide active portion can be increased, resulting in a high on-state current of the device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic cross-sectional view of the array substrate provided in the embodiments of this application.

[0025] Figure 2 This is a planar schematic diagram of the transistors in the array substrate provided in the embodiments of this application.

[0026] Figure 3 This is a second cross-sectional schematic diagram of the array substrate provided in the embodiments of this application.

[0027] Figure 4 This is a third cross-sectional schematic diagram of the array substrate provided in the embodiments of this application.

[0028] Figure 5 This is a fourth cross-sectional schematic diagram of the array substrate provided in the embodiments of this application.

[0029] Figure label:

[0030] Array substrate 10; substrate 100; gate 200; insulating portion 300; conductive portion 400; first portion 410; second portion 420; metal oxide active portion 500; semiconductor portion 510; conductive portion 520; source / drain electrode 600; buffer layer 700; light-shielding portion 800; insulating film 900; interlayer dielectric layer 1000. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In this application, "reaction" can be a chemical reaction or a physical reaction.

[0032] This application discloses an array substrate and a display panel. The array substrate includes a substrate, a metal oxide active portion, a gate, an insulating portion, a source / drain electrode, and a conductive portion. The metal oxide active portion is disposed on the substrate and includes a semiconductor portion connected and disposed in the same layer and a conductive portion disposed on both sides of the semiconductor portion. The gate is disposed on one side of the metal oxide active portion and is disposed corresponding to the semiconductor portion. The insulating portion is disposed between the metal oxide active portion and the gate. The source / drain electrode is disposed on the metal oxide active portion and is connected to the metal oxide active portion. The conductive portion is disposed on the side of the metal oxide active portion away from the source / drain electrode and is in contact with the metal oxide active portion. The conductive portion and the conductive portion are disposed corresponding to each other.

[0033] In this application, the conductive part contains charge carriers, which are electrons. Therefore, a conductive part is provided below the active part of the metal oxide and in contact with it, so that the conductive part can provide charge carriers to the active part of the metal oxide, thereby increasing the charge carrier concentration in the active part of the metal oxide. This results in the array substrate having a high on-state current and improving the performance of the array substrate.

[0034] Please see Figure 1 This application provides an array substrate 10. The array substrate 10 includes a substrate 100, a metal oxide active portion 500, a gate 200, an insulating portion 300, a source / drain electrode 600, and a conductive portion 400.

[0035] The substrate 100 is a glass substrate or a flexible substrate.

[0036] A metal oxide active portion 500 is disposed on a substrate 100. The metal oxide active portion 500 includes a semiconductor portion 510 connected and disposed on the same layer, and conductive portions 520 disposed on both sides of the semiconductor portion 510. A gate 200 is disposed on one side of the metal oxide active portion 500 and is disposed corresponding to the semiconductor portion 510. An insulating portion 300 is disposed between the metal oxide active portion 500 and the gate 200. A source / drain electrode 600 is disposed on the metal oxide active portion 500 and connected to it. A conductive portion 400 is disposed on the side of the metal oxide active portion 500 away from the source / drain electrode 600 and is in contact with the metal oxide active portion 500. The conductive portion 400 is disposed corresponding to the conductive portions 520. Specifically, the gate 200 is disposed on the substrate 100. The insulating portion 300 is disposed on the substrate 100 and the gate 200. The conductive portion 400 is disposed on the insulating portion 300. A metal-oxide active portion 500 is disposed on an insulating portion 300 and a conductive portion 400, and a source / drain terminal 600 is disposed on the metal-oxide active portion 500. The gate 200, insulating portion 300, metal-oxide active portion 500, and source / drain terminal 600 constitute a transistor. The transistor is an N-type transistor. The transistor is a bottom-gate transistor.

[0037] It should be noted that corresponding settings refer to one membrane layer being located directly above or below another membrane layer.

[0038] In this application, since the conductive part 400 contains charge carriers, and the charge carriers are electrons, the conductive part 400 is provided directly below the metal oxide active part 500 and is in contact with the metal oxide active part 500. The conductive part 400 is provided in correspondence with the conductive part 520, so that the conductive part 400 can provide charge carriers to the metal oxide active part 500, thereby increasing the number of charge carriers in the metal oxide active part 500, that is, increasing the charge carrier concentration in the metal oxide, thereby increasing the on-state current of the array substrate 10. The increase in the on-state current will improve the performance of the array substrate 10.

[0039] In one embodiment, the material of the conductive portion 400 includes at least one selected from ITO, Al, Ti, and Mo.

[0040] Please see Figure 2 In one embodiment, the orthographic projection of the conductive portion 400 on the substrate 100 is located within the orthographic projection of the conductive portion 520 on the substrate 100, that is, the edge of the orthographic projection of the conductive portion 400 on the substrate 100 is located within the orthographic projection of the conductive portion 520 on the substrate 100.

[0041] It should be noted that, Figure 2 Only some of the film layers are shown in the figure; the fact that other film layers are not drawn does not mean that they do not exist.

[0042] In this application, the orthographic projection of the conductive portion 400 on the substrate 100 is located within the orthographic projection of the conductive portion 520 on the substrate 100. This design ensures that the conductive portion 400 is not arranged along the entire surface of the conductive portion 520, meaning that the area of ​​the conductive portion 400 is smaller than the area of ​​the conductive portion 520. This reduces the amount of material used, thereby lowering the cost of the array substrate 10. Furthermore, it ensures that the conductive portion 400 can provide charge carriers to the metal oxide active portion 500, thus guaranteeing the performance of the array substrate 10.

[0043] In another embodiment, the edge of the orthographic projection of the conductive portion 400 on the substrate 100 overlaps with the edge of the orthographic projection of the conductive portion 520 on the substrate 100, that is, the area of ​​the conductive portion 400 is equal to the area of ​​the conductive portion 520.

[0044] In this application, the edge of the orthographic projection of the conductive portion 400 on the substrate 100 overlaps with the edge of the orthographic projection of the conductive portion 520 on the substrate 100, thereby increasing the area of ​​the conductive portion 400. The increased area allows the conductive portion 400 to provide more charge carriers, thereby improving the on-state current of the transistor and thus the performance of the array substrate 10.

[0045] Please see Figure 3 It should be noted that the second structure differs from the first structure in that:

[0046] The transistor is a top-gate transistor. Specifically, the conductive portion 400 is disposed on the substrate 100. The metal-oxide active portion 500 is disposed on the conductive portion 400 and the substrate 100. The insulating portion 300 is disposed on the metal-oxide active portion 500. The gate 200 is disposed on the insulating portion 300. The source and drain terminals 600 are disposed on the metal-oxide active portion 500. The rest is the same as the first structure, and will not be described again here.

[0047] In one embodiment, the transistor further includes an insulating film 900 and a light-shielding portion 800. The array substrate 10 further includes a buffer layer 700 and an interlayer dielectric layer 1000. The buffer layer 700 covers the substrate 100. The light-shielding portion 800 is disposed on the buffer layer 700. The light-shielding portion 800 is disposed corresponding to the metal oxide active portion 500. The material of the light-shielding portion 800 is a conductive material. The insulating film 900 is disposed between the conductive portion 400 and the light-shielding portion 800. The interlayer dielectric layer 1000 covers the insulating portion 300, the metal oxide active portion 500, the insulating film 900, and the gate 200. The source and drain terminals 600 are disposed on the interlayer dielectric layer 1000 and connected to the conductive portion 520 through vias.

[0048] In this application, a light-shielding part 800 is provided directly below the metal oxide active part 500, which can prevent impurities from the underlying film layer or the outside from entering the semiconductor part 510. The impurities include water vapor and free hydrogen, which can improve the stability of the transistor and thus improve the performance of the transistor.

[0049] Please see Figure 4 It should be noted that the third structure differs from the first structure in that:

[0050] The conductive portion 400 includes a first portion 410 and a second portion 420 that are on the same layer and connected. The first portion 410 is located on the side of the insulating portion 300 away from the semiconductor portion 510. The second portion 420 is located on the side of the insulating portion 300 closer to the semiconductor portion 510. The first portion 410 is disposed corresponding to the conductive portion 520. The second portion 420 is disposed corresponding to a portion of the semiconductor portion 510, that is, the second portion 420 overlaps with only a portion of the semiconductor portion 510. The effective channel length L of the metal-oxide-semiconductor portion 510 is the distance between the two conductive portions 520.

[0051] In this application, the second portion corresponds to the conducting portion 520. Setting the second portion to overlap with a portion of the semiconductor portion 510 is equivalent to moving the two conducting portions 520 towards the center of the semiconductor portion 510. This increases the carrier concentration of the metal-oxide active portion 500 while reducing the effective channel of the metal-oxide semiconductor portion 510, thereby reducing the transistor size and improving the performance of the array substrate 10. Furthermore, the second portion also corresponds to a blocking structure. Setting the second portion to overlap with a portion of the semiconductor portion 510 is equivalent to having a blocking structure below the semiconductor portion 510. This reduces the risk of impurities below the metal-oxide active portion 500 entering the semiconductor portion 510. For example, it blocks hydrogen from entering the semiconductor portion 510, preventing free hydrogen from combining with oxygen in the metal-oxide active portion 500 to form oxygen vacancies, which would degrade the performance of the oxide transistor. This improves transistor stability and reduces leakage current.

[0052] In one embodiment, the length t of the second portion 420 is 15-22% of the length h of the semiconductor portion 510, that is, the effective channel length L of the metal oxide active portion 500 is reduced by 15-22%. Specifically, the length t of the second portion 420 is 15%, 18%, 20% or 22% of the length h of the semiconductor portion 510, etc.

[0053] It should be noted that the length t here refers to the total length of the second part.

[0054] Normally, the length h of the semiconductor portion 510 is equal to the length L of the effective channel. However, in this application, the length t of the second portion 420 is set to 15-22% of the length h of the semiconductor portion 510. This allows the carrier concentration of the metal oxide active portion 500 to be increased while the effective channel length L of the metal oxide active portion 500 is reduced by 15-22%, thereby reducing the size of the transistor and improving the performance of the array substrate 10.

[0055] Please see Figure 5 The fourth structure differs from the third structure in that:

[0056] The first section 410 and the second section 420 are insulated from each other. The first section 410 is disposed corresponding to the conducting section 520. The second section 420 is disposed corresponding to the semiconductor section 510. At this time, the effective channel length L of the metal oxide active section 500 is the sum of length L1 and length L2. Other aspects are the same as the third structure, and will not be described again here.

[0057] In one embodiment, a portion of the edge of the orthographic projection of the first portion onto the substrate 100 lies within the orthographic projection of the conductive portion 520 onto the substrate 100.

[0058] In another embodiment, the edge of the orthographic projection of the first portion on the substrate 100 is located within the orthographic projection of the conductive portion 520 on the substrate 100.

[0059] In another embodiment, the edge of the orthographic projection of the first portion 410 onto the substrate 100 overlaps with the edge of the orthographic projection of the conductive portion 520 onto the substrate 100. That is, the area of ​​the first portion 410 is equal to the area of ​​the conductive portion 520.

[0060] In this application, the edge of the orthographic projection of the first portion 410 on the substrate 100 overlaps with the edge of the orthographic projection of the conductive portion 520 on the substrate 100, thereby increasing the area of ​​the first portion 410. The increased area allows the conductive portion 400 to provide more charge carriers, thereby improving the on-state current of the transistor and thus the performance of the array substrate 10.

[0061] This application also provides a display panel, including an array substrate 10 provided in this application and a light-emitting structure layer disposed on the array substrate 10. Applying the array substrate 10 provided in this application to a display panel can improve the display effect of the display panel.

[0062] This application discloses an array substrate 10 and a display panel. The array substrate 10 includes a substrate 100, a metal oxide active portion 500, a gate 200, an insulating portion 300, a source / drain electrode 600, and a conductive portion 400. The metal oxide active portion 500 is disposed on the substrate 100. The metal oxide active portion 500 includes a semiconductor portion 510 connected and disposed on the same layer and a conductive portion 520 disposed on both sides of the semiconductor portion 510. The gate 200 is disposed on one side of the metal oxide active portion 500 and is disposed corresponding to the semiconductor portion 510. The insulating portion 300 is disposed between the metal oxide active portion 500 and the gate 200. The source / drain electrode 600 is disposed on the metal oxide active portion 500 and connected to the metal oxide active portion 500. The conductive portion 400 is disposed on the side of the metal oxide active portion 500 away from the source / drain electrode 600 and is in contact with the metal oxide active portion 500. The conductive portion 400 is disposed corresponding to the conductive portion 520. In this application, the conductive portion 400 contains charge carriers, which are electrons. Therefore, the conductive portion 400 is disposed below the active portion 500 and in contact with it, so that the conductive portion 400 can provide charge carriers to the active portion 500, thereby increasing the charge carrier concentration in the active portion 500. As a result, the array substrate 10 has a high on-state current, which improves the performance of the array substrate 10.

[0063] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized by, include: Substrate; A metal oxide active portion is disposed on the substrate, and the metal oxide active portion includes a semiconductor portion connected and disposed in the same layer and a conductive portion disposed on both sides of the semiconductor portion; A gate is disposed on one side of the active portion of the metal oxide and is disposed corresponding to the semiconductor portion; An insulating portion is disposed between the metal oxide active portion and the gate. Source and drain electrodes, wherein the source and drain electrodes are disposed on the active portion of the metal oxide and connected to the active portion of the metal oxide; as well as A conductive portion is disposed on the side of the metal oxide active portion away from the source and drain electrodes and is in contact with the metal oxide active portion; the conductive portion is disposed correspondingly to the conductive portion. The conductive portion includes a first portion and a second portion that are on the same layer and connected. The first portion is located on the side of the insulating portion away from the semiconductor portion and on the side of the insulating portion close to the semiconductor portion. The second portion covers the first portion. The first portion is correspondingly disposed to the conductive portion and the second portion is correspondingly disposed to a portion of the semiconductor portion.

2. The array substrate of claim 1, wherein, The length of the second portion is 15-22% of the length of the semiconductor portion.

3. The array substrate of claim 2, wherein, The edge of the orthographic projection of the first portion on the substrate is located within the orthographic projection of the conductive portion on the substrate.

4. The array substrate of claim 2, wherein, The edge of the orthographic projection of the first portion on the substrate overlaps with the edge of the orthographic projection of the conductive portion on the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein, The gate is disposed on the substrate, the insulating portion is disposed on the substrate and the gate, the conductive portion is disposed on the insulating portion, the metal oxide active portion is disposed on the insulating portion and the conductive portion, and the source and drain are disposed on the metal oxide active portion.

6. The array substrate according to any one of claims 1 to 4, wherein, The conductive portion is disposed on the substrate, the metal oxide active portion is disposed on the conductive portion and the substrate, the insulating portion is disposed on the metal oxide active portion, the gate is disposed on the insulating portion, and the source and drain are disposed on the metal oxide active portion.

7. The array substrate of claim 1, wherein, The orthographic projection of the conductive part on the substrate is located within the orthographic projection of the conductive part on the substrate.

8. The array substrate of claim 1, wherein, The edge of the orthogonal projection of the conductive part on the substrate overlaps with the edge of the orthogonal projection of the conductive part on the substrate.

9. A display panel, characterized by, It includes the array substrate as described in any one of claims 1-8 and the light-emitting structure layer disposed on the array substrate.

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