Transistor and method of manufacturing the same

Abstract

Some embodiments described herein provide a transistor and a method of manufacturing the same. The method includes forming a channel structure of the transistor. The method includes forming a work function material including aluminum and carbon around the channel structure. Forming the work function material around the channel structure includes applying a chemical soak solution, where a material of the chemical soak solution includes aluminum, carbon, and a hydrogen-based material. The work function material includes a concentration of titanium that is 0% to less than 1.5% of the work function material. Some embodiments described herein provide a transistor. The transistor includes a channel structure and an aluminum carbide (AlC)-based work function material disposed around the channel structure. The work function material includes a concentration of titanium that is 0% to less than 1.5% of the work function material.

Description

Technical Field

[0001] This disclosure relates to a transistor and a method for manufacturing the same, and more particularly to a transistor having a work function material and a method for manufacturing the same. Background Technology

[0002] A field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current. An FET has three terminals: a source, a gate, and a drain. During operation, the voltage controls the current flow to the gate, which alters the conductivity between the drain and source. The most commonly used type of FET is the metal-oxide-semiconductor field-effect transistor (MOSFET). For example, MOSFETs can be used as switches for electronic signals (e.g., radio frequency (RF) switches) or amplifiers for electronic signals (e.g., low-noise amplifiers, LNAs), among other specific examples. A gate-all-around (GAA) structure can be formed as a type of MOSFET, where the channel is a gate material extending through the epitaxial structure. Compared to a fin field-effect transistor (FinFET), the gate-all-around structure can have optimized device density in the width dimension (e.g., the critical dimension). For example, the gate-all-around structure is formed to have a scale of less than 7 nanometers. Summary of the Invention

[0003] One aspect of this disclosure is a transistor. The transistor includes nanostructures vertically disposed on a substrate. The transistor includes a channel structure of nanostructures, comprising multiple nanostructure channels on the substrate and extending between the source and drain of the transistor. The transistor includes a work function material disposed around the multiple nanostructure channels of the channel structure and separated from the source and drain by one or more internal spacer walls, wherein the work function material comprises aluminum and carbon, and the concentration of titanium in the work function material is 0% to less than 1.5% of the work function material.

[0004] Another aspect of this disclosure is a method for manufacturing a transistor. The method includes forming a channel structure for the transistor, the channel structure comprising a plurality of nanostructured channels on a substrate and extending between the source and drain of the transistor. The method includes forming a work function material comprising aluminum and carbon around the channel structure, wherein forming the work function material around the channel structure involves applying a chemical soaking solution, the chemical soaking solution comprising aluminum, carbon, and hydrogen-based materials, and the concentration of titanium in the work function material is from 0% to less than 1.5% of the work function material.

[0005] Another aspect of this disclosure is to provide a transistor. The transistor includes source / drain electrodes formed on the surface of a transistor substrate. The transistor includes a channel extending between the source / drain electrodes and in the substrate. The transistor includes a work function material disposed on the channel, comprising aluminum and carbon, wherein the concentration of titanium in the work function material is 0% to less than 1.5% of the work function material. The transistor includes a gate disposed on the work function material. Attached Figure Description

[0006] A better understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0007] Figure 1 This is a schematic diagram illustrating an environment in which the system and / or method described herein is performed;

[0008] Figures 2A to 2E This is a schematic diagram of the illustrated transistor;

[0009] Figures 3A to 3F This is a schematic diagram of the exemplary embodiment described above;

[0010] Figures 4A to 4B This is a schematic diagram of a specific example of the work function material layer described above;

[0011] Figure 5 This is a schematic diagram of an exemplary electronic device containing the plurality of transistors;

[0012] Figure 6 This is a schematic diagram of the illustrated transistor;

[0013] Figure 7 It is the aforementioned Figure 1 A schematic diagram illustrating one or more device elements;

[0014] Figure 8 This is a flowchart illustrating an example fabrication process for forming the transistor;

[0015] Figures 9A to 9H This is a schematic diagram of the exemplary embodiment.

[0016] [Symbol Explanation]

[0017] 100: Environment

[0018] 102: Semiconductor manufacturing tools / deposition tools

[0019] 104: Semiconductor Process Tools / Etching Tools

[0020] 106: Semiconductor Process Tools / Planarization Tools

[0021] 108: Wafer / Die Transfer Tools

[0022] 200: Transistor

[0023] 202: Substrate

[0024] 202A: Part 1

[0025] 202B: Part Two

[0026] 204: Source / Drain

[0027] 206: Filler metal

[0028] 206A: First filler metal

[0029] 206B: Second filler metal

[0030] 208: High-k dielectric layer

[0031] 210: Gate spacer wall

[0032] 212: Interlayer Dielectric

[0033] 214: Channel Structure

[0034] 214A: First Channel Structure

[0035] 214B: Second Channel Structure

[0036] 216: Channel

[0037] 216A: First channel

[0038] 216B: Second set of channels

[0039] 218: Interface Layer

[0040] 218A: First Interface Layer

[0041] 218B: Second Interface Layer

[0042] 220: High-k dielectric layer

[0043] 220A: First high-k dielectric layer

[0044] 220B: Second High-k Dielectric Layer

[0045] 222: Work Function Materials

[0046] 222A, 222B: Work function materials

[0047] 224: Internal spacer wall

[0048] 300: Example

[0049] 302: Sacrificial Material

[0050] 310: Chemical soaking operation

[0051] 400,402: Specific examples

[0052] 404: Material with Additional Work Function

[0053] 500: Electronic devices

[0054] 500A, 500B: Transistors

[0055] 600: Transistor

[0056] 602: Substrate

[0057] 604: Source / Drain

[0058] 606: Channel

[0059] 608: Tunneling Dielectric

[0060] 610: Work Function Materials

[0061] 612: Floating gate

[0062] 614: Dielectric layer

[0063] 616: Control Gate

[0064] 700: Device

[0065] 710: Bus

[0066] 720: Processor

[0067] 730: Memory

[0068] 740: Input Component

[0069] 750: Output Component

[0070] 760: Communication Components

[0071] 800: Process

[0072] 810, 820: Square

[0073] T1, T2: Thickness

[0074] X: Section line

[0075] Y: Profile line

[0076] Z1, Z2: Section lines Detailed Implementation

[0077] The following disclosure provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying this disclosure. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters are repeated in various specific examples in this disclosure. This repetition is for the purpose of simplifying and clarifying the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0078] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to facilitate the description of the relationship between a part or feature depicted in the accompanying drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this disclosure can also be interpreted in this way.

[0079] Electronic devices can be configured to have one or more threshold voltages (V). ts The transistors used are field-effect transistors (FETs). For example, an electronic device may include a first transistor configured to have a relatively high threshold voltage and a second transistor configured to have a relatively low threshold voltage. The first transistor may be configured to optimize a first application, and the second transistor may be configured to optimize a second application. Based on the optimized transistors for different applications, when the relatively high threshold voltage optimizes device performance (e.g., reduced leakage current and / or operating speed, and other specific examples), the electronic device may manage the operation using the first transistor (e.g., accompanied by a set of similarly configured transistors), and when the relatively low threshold voltage optimizes device performance (e.g., power consumption, and other specific examples), the electronic device may manage the operation using the second transistor (e.g., accompanied by a set of similarly configured transistors).

[0080] The fabrication process for configuring the threshold voltage of a transistor based on the work function material (WFM) presents challenges. Transistors can be manufactured using work function materials formed from titanium, aluminum, and carbon (e.g., titanium aluminum carbide (TiAlC)), or titanium nitride (e.g., TiN), and other specific examples. During atomic layer deposition, titanium can be used to bond the work function material to the dielectric material disposed on the channel structure of the transistor. However, titanium imposes a minimum thickness limitation on the work function. For example, based on a work function material containing titanium, the minimum possible thickness of the work function material is 12 angstroms. This minimum thickness limits the threshold voltage of the transistor. For example, the minimum thickness corresponds to the maximum threshold voltage (e.g., the largest contribution to the threshold voltage is attributed to the work function material).

[0081] Some of the embodiments provide techniques and apparatus for configuring the threshold voltage of a transistor. The transistor is configured to have a work function material comprising aluminum and carbon, which is disposed around a channel structure. The work function material can be used to replace or be added to a titanium-based work function material to provide a configuration that optimizes the threshold voltage of the work function material. One or more semiconductor process tools can form the work function material using chemical soak deposition. In some embodiments, one or more semiconductor process tools can soak the transistor in triethylaluminum (Al2(C2H5)6)(TEA) to form the work function material.

[0082] The work function material can be titanium-free (e.g., the titanium concentration is 0% to less than 1.5% of the work function material). In this case, the thickness of the work function material can be in the range of greater than 0 Å and less than 12 Å and / or can be adjusted to a thickness range of greater than 12n Å and less than 12(n+1) Å, where n is based on the number of layers of the titanium-based work function material. Based on the threshold voltage of the transistor with optimized tuning, the transistor can be optimized to improve power efficiency, operating speed, and / or leakage current, and other specific examples.

[0083] Figure 1 This is a schematic diagram illustrating environment 100, which is where the system and / or methods can be executed. Figure 1 As shown, environment 100 may include multiple semiconductor process tools 102 to 106 and wafer / die transfer tools 108. The multiple semiconductor process tools 102 to 106 may include deposition tools 102, etching tools 104, planarization tools 106, and / or other semiconductor process tools. The tools included in the illustrated environment 100 may be located in a semiconductor cleaning chamber, a semiconductor manufacturing plant, a semiconductor process and / or process facility, or other locations.

[0084] The deposition tool 102 is a semiconductor manufacturing tool capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin-coating tool capable of depositing a photoresist layer onto a substrate, such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced ALD (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the deposition tool 102 includes a chemical immersion tool, wherein a fluid (e.g., a liquid or gas) is applied to the substrate for a specified period of time. In some embodiments, the exemplary environment 100 includes various types of deposition tools 102.

[0085] Etching tool 104 is a semiconductor manufacturing tool that can etch substrates, wafers, or semiconductor devices of various material types. For example, etching tool 104 may include wet etching tools, dry etching tools, and / or other types of etching tools. Wet etching tools may include chemical etching tools or other types of wet etching tools containing a chamber filled with etchant. The substrate is placed in the chamber for a specific duration to remove one or more portions of the substrate in a specific amount. Dry etching tools may include plasma etching tools, laser etching tools, reactive ion etching tools, or vapor phase etching tools, and other specific examples. Dry etching tools may utilize sputtering techniques or plasma-assisted etching techniques (e.g., plasma sputtering techniques or other types of techniques involving the use of ionized gases to etch one or more portions isotropically or directionally) or other types of dry etching techniques to remove one or more portions of the substrate.

[0086] Planarization tool 106 is a semiconductor manufacturing tool that can grind or planarize layers of a wafer or semiconductor device. For example, planarization tool 106 may include chemical mechanical planarization (CMP) tools and / or other types of planarization tools that can grind or planarize layers or surfaces of deposited or plated materials. Planarization tool 106 can combine chemical and mechanical forces (e.g., chemical etching and abrasive-free polishing) to grind or planarize the surface of the semiconductor device. Planarization tool 106 can utilize abrasives and corrosive chemical polishing slurries combined with a polishing pad and a retaining ring (typically having a diameter larger than that of the semiconductor device). The polishing pad and semiconductor device can be pressed together by a powered polishing head and held in place by the retaining ring. The powered polishing head can rotate on different axes of rotation to remove material and homogenize irregular surface morphologies of the semiconductor device, thus planarizing or planarizing the semiconductor device.

[0087] The wafer / die transfer tool 108 includes mobile robots, robotic arms, trams or railcars, overhead hoist transfer (OHT) vehicles, automated materially handling systems (AMHS), and / or other types of devices used to transfer wafers and / or dies between and / or from other locations (e.g., wafer racks, storage rooms, and / or similar) of semiconductor process tools 102 to 106. In some embodiments, the wafer / die transfer tool 108 may be a programmable tool to operate via a specific path and / or semi-automatically or automatically.

[0088] Figure 1 The number and configuration of tools shown are provided as one or more specific examples. In practice, there may be additional tools, fewer tools, different tools, or different configurations. Figure 1 The tool configuration shown. Furthermore, Figure 1 The two or more tools shown can be used with a single tool, or Figure 1 The single tool shown can be used with a variety of distributed tools. Alternatively, a set of devices in environment 100 (e.g., one or more devices) can perform the one or more functions described above, as well as through another set of tools in environment 100.

[0089] Figures 2A to 2E This is a schematic diagram illustrating the transistor 200 described herein. The transistor 200 may include... Figures 2A to 2E One or more additional layers and / or structures, not shown, such as one or more additional transistors. For example, an electronic device may include layers formed on... Figures 2A to 2EAdditional layers and / or dies on the layers above and / or below the transistor 200 shown. The transistor 200 can be utilized with reference to... Figures 3A to 3F The illustrated process described above is used for fabrication. Transistor 200 may be contained within or may be contained within a nanosheet transistor. This disclosure is also applicable to other types of transistors, such as fin field-effect transistors.

[0090] like Figure 2A As shown, transistor 200 includes substrate 202. Substrate 202 may include semiconductor die substrate, semiconductor wafer, or other types of substrate in which semiconductor devices may be formed and / or on. In some embodiments, substrate 202 is composed of silicon (Si), silicon-containing materials, III-V compound semiconductor materials such as gallium arsenide (GaAs), or other types of semiconductor materials. Substrate 202 may include one or more fin structures disposed on a semiconductor material (e.g., silicon-based material) and / or one or more dielectric structures (e.g., trench isolation structures) disposed around one or more fin structures.

[0091] Transistor 200 may also include a source / drain 204 extending upward from the top surface of substrate 202. The source / drain 204 may comprise an epitaxial material, such as silicon, silicon germanium, and / or gallium nitride-based materials, and other specific examples thereof.

[0092] Transistor 200 may further include fill metal 206 disposed between source / drain 204 (e.g., between the source / drain 204 on the left side of transistor 200 and the source / drain 204 on the right side of transistor 200). Fill metal 206 may comprise a conductive material, such as titanium nitride and / or tungsten, and other specific examples. Fill metal 206 provides electrical conduction between work function material and conductive structures that electrically connect bit lines or other electrical connections to fill metal 206.

[0093] The filler metal 206 can be insulated from the source / drain 204 via the high-k dielectric layer 208, the gate spacer 210, and / or the interlayer dielectric 212. The high-k dielectric layer 208 may comprise a hafnium-based material (e.g., hafnium silicate or hafnium dioxide, and other specific examples) or a zirconium-based material (zirconium silicate or zirconium dioxide, and other specific examples), and other specific examples. The high-k dielectric layer 208 may be disposed between the filler metal 206 and the gate spacer 210. The thickness of the high-k dielectric layer 208 may be approximately [missing information]. to approximately The gate spacer 210 may comprise a dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride, and other specific examples. The gate spacer 210 may be disposed between the high-k dielectric layer 208 and the interlayer dielectric 212. The thickness of the gate spacer 210 may be approximately [missing information - likely a number]. to approximately Interlayer dielectric 212 may surround the source / drain 204 on the front, back, and / or top surfaces of the source / drain 204. Interlayer dielectric 212 may comprise a low-k material, such as silicon dioxide, silicon nitride, or silicon oxide nitride, and other specific examples. Interlayer dielectric 212 may provide structural support for transistor 200 and electrical insulation between structures within transistor 200. The thickness of interlayer dielectric 212 may be approximately [missing information - likely a value]. to approximately

[0094] Figure 2A It is an X-section line (e.g., a logic dividing line) extending between the left and right sides of transistor 200 to show the interior of transistor 200. Figure 2A The Y-section line extending between the rear side and the front side of transistor 200 is also shown.

[0095] Figure 2B It is drawn along Figure 2A An internal view of transistor 200 shown in the Y-section. Figure 2B As shown, channel structure 214 is disposed within fill metal 206. Channel structure 214 includes one or more channels 216 (e.g., nanostructured channels) that extend through fill metal 206 between source / drain 204. Based on the interaction with fill metal 206, one or more channels 216 can carry charge from fill metal 206 to source / drain 204 during operation of transistor 200. One or more channels 216 may comprise silicon-based materials and other semiconductor materials.

[0096] Transistor 200 may include an interface layer 218 and / or a high-k dielectric layer 220 disposed around one or more channels 216. For example, the interface layer 218 may be disposed directly on one or more channels 216, and the high-k dielectric layer 220 may be disposed directly on the interface layer 218. In some embodiments, the interface layer 218 may include a tunneling dielectric (e.g., an oxide layer, a silicon oxide layer, and / or a silicon dioxide layer, and other specific examples) disposed directly on the channel structure 214 (e.g., directly on one or more channels 216). In some embodiments, the high-k dielectric layer 220 may include a hafnium oxide-based material (e.g., hafnium oxide or hafnium dioxide) and other high-k materials.

[0097] like Figure 2B As shown, the materials of the interface layer 218 and / or the high-k dielectric layer 220 can be disposed on the top surface of the substrate 202. The foregoing is based on the technique used for depositing the interface layer 218 and / or the high-k dielectric layer 220 (e.g., chemical vapor deposition).

[0098] Transistor 200 further includes a work function material 222 disposed around channel structure 214, which comprises aluminum and carbon. In some embodiments, the work function material 222 has a titanium concentration of 0% to less than 1.5% (e.g., the work function material may be titanium-free). Based on the titanium concentration of less than 1.5% in the work function material 222, the thickness of the work function material 222 is less than 12 μm / or a work function material 222 with a thickness that avoids unevenness.

[0099] Work function material 222 may be disposed around the individual channels 216 of channel structure 214. Work function material 222 may be disposed between the individual channels 216 of channel structure 214. In some embodiments, work function material 222 may be disposed between the individual channels 216 to exclude filler metal 206 between the individual channels 216. In some embodiments, work function material 222 is disposed between channel structure 214 and filler metal 206. In some embodiments, high-k dielectric layer 220 is disposed between interface layer 218 and work function material 222. In some embodiments, work function material 222 is in direct contact with high-k dielectric layer 220 or interface layer 218.

[0100] The work function material 222 may comprise an n-type work function material or a p-type work function material. For example, when the source / drain 204 is a p-type metal-oxide-semiconductor region or an n-type metal-oxide-semiconductor region of an electronic device, the work function material 222 may be used as a work function material.

[0101] Figure 2C It is drawn along Figure 2A An internal view of transistor 200 shown in the X-section. (See figure) Figure 2C As shown, one or more channels 216 of the channel structure 214 extend through the gate region of the transistor 200 between the source and drain 204, wherein the gate region includes work function material 222 and fill metal 206 (together forming the gate).

[0102] like Figure 2C As shown, the gate region includes one or more channels 216 that are surrounded (e.g., covered) by an interface layer 218 between inner spacer walls 224 (e.g., a low-k dielectric material), and then covered by the inner spacer walls 224 between the interface layer 218 and the source / drain 204. In this way, the one or more channels 216 are electrically insulated from the gate. In addition, the inner spacer walls 224 provide additional electrical insulation between the gate and the source / drain 204. The thickness of the inner spacer walls 224 ranges from approximately... to approximately

[0103] Just like Figure 2CAs shown, the work function material 222 can be covered by a high-k dielectric layer 220 and / or liner a high-k dielectric layer. In this way, the work function material 222 can avoid contact with the interface layer 218, which would otherwise cause damage to the interface layer 218 and / or failure of the transistor 200.

[0104] Figure 2C The Z1 cross-section is drawn, which extends through the work function material 222 between the left and right sides of transistor 200. Figure 2C The Z2 cross-section is also shown, which extends through the single channel 216 between the left and right sides of transistor 200.

[0105] Figure 2D It is drawn along Figure 2C An internal view of transistor 200 with the Z1 cross-section shown. Figure 2D yes Figure 2A The diagram shows a top view of transistor 200, which is a view showing transistor 200 at a height, wherein transistor 200 is located between one or more channels 216.

[0106] like Figure 2D As shown, the work function material 222 is lining the sidewalls with a high-k dielectric layer 208. The work function material 222 is insulated from the source / drain 204 by a gate spacer 210 (e.g., replaced from one or more channels 216 in the top view) and by an inner spacer 224 (e.g., disposed directly under one or more channels 216 in the top view).

[0107] Figure 2E It is drawn along Figure 2C An internal view of transistor 200 with the Z2 cross-section shown. Figure 2E yes Figure 2A The diagram shows a top view of transistor 200, which is a view showing transistor 200 at a height, wherein transistor 200 includes channel 216.

[0108] like Figure 2E As shown, channel 216 is lined with an interface layer 218 in the middle portion of channel 216 and with a gate spacer 210 (e.g., adjacent to source / drain 204) in the end portion. The end portion of channel 216 can be directly disposed in... Figure 2D On and / or below the inner spacer wall 224 shown.

[0109] Just like Figure 2E As shown, the work function material 222 is disposed on the front surface of the channel 216 in the middle part of the channel 216 (e.g., Figure 2E The bottom surface shown) and the rear surface (as shown) Figure 2E(The top surface shown). The work function material 222 is separated from the channel by the interface layer 218 and the high-k dielectric layer 208.

[0110] Based on the use of work function material 222 as the work function material of transistor 200 (e.g., nanosheet transistor), the threshold voltage of transistor 200 is adjusted to have optimized accuracy (e.g., compared to transistors with titanium-based work function materials) and / or higher than the threshold voltage of conventional transistors (e.g., devices with higher threshold voltages due to the work function material). In this way, transistor 200 is optimized for use with a threshold voltage configuration that optimizes leakage current and / or power consumption.

[0111] Figures 3A to 3F This is a schematic diagram of an exemplary embodiment 300 of forming transistor 200 as described herein. Embodiment 300 may include one or more operations (e.g., lithography, operations performed on different parts of an electronic device including transistor 200) and / or the operations shown in the exemplary process may be related to... Figures 3A to 3F The order shown is different. Transistor 200 may contain... Figures 3A to 3F One or more additional devices, structures, and / or layers not shown. For example, transistor 200 may include layers formed on... Figures 3A to 3F Additional layers and / or dies on the upper and / or lower layers of the transistor 200 shown. In addition, or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of the electronic device, having lateral displacement, such as... Figures 3A to 3F The transistor 200 shown.

[0112] like Figure 3A As shown, embodiment 300 may include forming a channel structure 214 in the sacrificial material 302. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) may deposit the channel structure 214 within alternating layers having the sacrificial material 302, and then may etch to the alternating layers to form one or more channels 216 of the channel structure 214. In some embodiments, the sacrificial material 302 may be disposed only vertically between the one or more channels 216, and not laterally between the one or more channels 216.

[0113] like Figure 3B As shown, embodiment 300 may include etching to remove sacrificial material 302. For example, one or more semiconductor process tools (e.g., etching tool 104) may apply an etchant (e.g., a chemical etchant) to the sacrificial material 302 to remove it. In some embodiments, the etchant may be configured to selectively etch material of the sacrificial material 302. In some embodiments, the etchant may remove portions of one or more channels 216 at a slower rate than the removal of the sacrificial material 302.

[0114] Further as Figure 3B As shown, one or more channels 216 can be suspended on the substrate 202. After the sacrificial material 302 is removed, one or more channels 216 can be accessed through the inner sidewall (e.g., Figure 2D The inner wall 224 shown is supported. Alternatively, after the sacrificial material 302 is removed, one or more channels 216 can be supported by connecting the source / drain 204.

[0115] like Figure 3C As shown, embodiment 300 may include a deposited interface layer 218 on one or more channels 216 of the channel structure 214. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) may deposit material of the interface layer 218 on one or more channels 216, utilizing chemical vapor deposition or atomic layer deposition, and other specific examples thereof. In some embodiments, the interface layer 218 may surround one or more channels 216 to form a pad of one or more channels 216 in the gate region of the transistor 200.

[0116] like Figure 3D As shown, embodiment 300 may include depositing a high-k dielectric layer 220 on one or more channels 216 of the channel structure 214. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) may deposit material of the high-k dielectric layer 220 in the interface layer 218, which may be done using chemical vapor deposition or atomic layer deposition, and other specific examples thereof. In some embodiments, the high-k dielectric layer 220 may surround the interface layer 218 and / or may provide a pad on the interface layer 218 and / or gate spacer wall (e.g., gate gap 210) in the gate region of the transistor 200.

[0117] like Figure 3EAs shown, Embodiment 300 may include depositing a work function material 222 comprising aluminum and carbon in the gate region and surrounding the channel structure 214 (e.g., surrounding a high-k dielectric layer 220). In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) may utilize a chemical immersion operation 310 to deposit the work function material 222. The chemical immersion operation 310 may include applying triethylaluminum to the transistor 200 for a period of time, which is configured to produce a work function material 222 having a target thickness. In some embodiments, one or more semiconductor process tools may perform the chemical immersion operation 310 at a temperature range of about 250 degrees Celsius to about 600 degrees Celsius. In this way, the temperature is high enough to support the bonding of aluminum carbide (AlC) molecules within the triethylaluminum to the high-k dielectric layer 220, and cold enough to avoid damaging the transistor 200 and / or other semiconductor devices on the electronic device. Alternatively, one or more semiconductor process tools can perform chemical immersion operations 310 at chamber pressures ranging from about 0.5 torr to about 50 torr. This ensures that the pressure used is within the normal operating range of the deposition tool.

[0118] In some embodiments, the chemical immersion operation 310 may deposit a work function material 222 having a titanium concentration of 0% to less than 1.5% (e.g., it may be deposited without a titanium source). In this way, the thickness of the work function material 222 may be greater than 0 angstroms to less than 12 angstroms (e.g., less than 12 angstroms) and / or may be configured to have a thickness between multiples of 12 angstroms (e.g., based on a thickness with a higher titanium concentration).

[0119] In some embodiments, one or more semiconductor process tools may perform a chemical immersion operation 310 while atomic layer deposition of a work function material is performed. In some embodiments, one or more semiconductor process tools may perform a chemical immersion operation 310 prior to atomic layer deposition of an additional work function material.

[0120] like Figure 3F As shown, embodiment 300 may include depositing fill metal 206 around the work function material 222 in the gate region of transistor 200. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) may fill the material of metal 206 around the work function material 222 using reflow, chemical vapor deposition, or plasma vapor deposition, and other specific examples. In some embodiments, semiconductor process tools (e.g., planarization tool 106) may grind and / or planarize the top surface of fill metal 206 to form a generally flat top surface of transistor 200. In this way, the top surface of transistor 200 is suitable for depositing additional material and / or for optimizing the consistency of subsequent etching processes.

[0121] As mentioned above, Figures 3A to 3FThis is provided as a specific example. Other specific examples may differ from this. Figures 3A to 3F Related explanations. Figures 3A to 3F The number and arrangement of the devices, layers and / or materials shown are provided as a specific example. In reality, compared to Figures 3A to 3F It may have additional devices, layers and / or materials, fewer devices, layers and / or materials, different devices, layers and / or materials, or devices, layers and / or materials with different configurations.

[0122] Figures 4A to 4B These are schematic diagrams of specific examples 400 and 402 of the work function material layer described herein. Specific examples 400 and 402 may include those not shown in the diagram. Figures 4A to 4B One or more additional layers and / or structures. Specific examples 400 and 402 may be included in a transistor, such as... Figures 2A to 2E The transistor 200 shown and / or with Figures 3A to 3F The transistor 200 is manufactured using the process shown. The transistor 200 may include an additional layer formed on... Figures 4A to 4B The work function shown is above and / or below the material layer. Figures 4A to 4B The work function material layer shown may be contained in or may be contained in nanosheet transistors and / or fin field-effect transistors (e.g., Figure 6 (As shown).

[0123] like Figure 4A As shown, Example 400 includes a channel 216 having an interface layer 218 and / or a high-k dielectric layer 220 disposed thereon. Example 400 also includes a work function material 222 disposed on the interface layer and / or high-k dielectric layer 220, which comprises aluminum and carbon. Example 400 further includes a filler metal 206 disposed on the work function material 222. In some embodiments, the work function material 222 may be a single work function material disposed between the channel 216 and the filler metal 206. In this way, the thickness of the work function material is greater than 0 angstroms and less than 12 angstroms. The above can support a threshold voltage higher than a thickness greater than 12 angstroms, which can optimize the regulation of the transistor 200 applicable at relatively high threshold voltages. The above can optimize the power consumption and / or leakage current of the transistor 200.

[0124] like Figure 4BAs shown, Specific Example 402 includes a channel 216 having an interface layer 218 and / or a high-k dielectric layer 220 disposed thereon. Specific Example 402 also includes a work function material 222 disposed on the interface layer 218 and / or the high-k dielectric layer 220. Specific Example 402 further includes an additional work function material 404 disposed on (e.g., around) the work function material 222. The additional work function material 404 may comprise a titanium aluminum carbide (TiAlC) based material or a titanium nitride (TiN) based material. Specific Example 400 further includes a filler metal 206 disposed on the additional work function material 404.

[0125] Based on the inclusion of work function material 222 and additional work function material 404, transistor 200 can be configured to have a thickness adjusted to provide a threshold voltage with a relevant thickness greater than 12 angstroms. For example, transistor 200 may include multiple layers of additional work function material 404 to provide a coarse thickness of the work function material to adjust the threshold voltage, and may include the thickness of the work function metal 222 to provide a fine-tuned threshold voltage. The aforementioned can support adjusting the threshold voltage of the transistor to be lower than the threshold voltage of specific example 400. The aforementioned can optimize the power consumption and / or leakage current of transistor 200.

[0126] As mentioned above, Figures 4A to 4B This is a schematic diagram illustrating the work function of the material layer described in this article. Other specific examples may differ from the reference. Figures 4A to 4B The person mentioned. Figures 4A to 4B The number and arrangement of the devices, layers and / or materials shown are provided as a specific example. In reality, compared to Figures 4A to 4B It may have additional devices, layers and / or materials, fewer devices, layers and / or materials, different devices, layers and / or materials, or devices, layers and / or materials with different configurations. In addition, refer to... Figures 4A to 4B The features described in any of them may be compared with those described in reference. Figures 2A to 3F The aforementioned feature combination.

[0127] Figure 5 This is a schematic diagram of an exemplary electronic device 500 comprising multiple transistors 500A and 500B as described herein. The electronic device 500 may include components not shown in the diagram. Figure 5 One or more additional layers and / or structures. Electronic device 500 may include one or more additional semiconductor structures, such as one or more additional transistors. For example, electronic device 500 may include structures formed on... Figure 5 Additional layers and / or dies on the layers above and / or below transistors 500A and 500B shown. Electronic device 500 may utilize reference... Figures 3A to 3F The illustrated process is used for manufacturing. The electronic device 500 may include nanosheet transistors and / or fin field-effect transistors.

[0128] like Figure 5As shown, the electronic device 500 includes a first transistor 500A comprising a first portion 202A of a substrate and a first channel structure 214A comprising a first set of channels 216A. A first interface layer 218A is disposed around the first set of channels 216A, and a first high-k dielectric layer 220A is disposed around the first interface layer 218A. The first transistor 500A further includes a work function material 222A disposed around the first set of channels 216A (e.g., around the first interface layer 218A and / or the first high-k dielectric layer 220A), which comprises aluminum and carbon and has a thickness T1. The first transistor 500A also includes a first filler metal 206A disposed around the work function material 222A.

[0129] Further as Figure 5 As shown, the electronic device 500 includes a second transistor 500B comprising a second portion 202B of a substrate and a second channel structure 214B comprising a second set of channels 216B. A second interface layer 218B is disposed around the second set of channels 216B, and a second high-k dielectric layer 220B is disposed around the second interface layer 218B. The second transistor 500B further includes a work function material 222B disposed around the second set of channels 216B (e.g., around the second interface layer 218B and / or the second high-k dielectric layer 220B), which has a thickness T2 (different from thickness T1). The second transistor 500B also includes a second filler metal 206B disposed around the work function material 222B.

[0130] For reference Figure 5 The electronic device 500 may include different transistors adjusted to have different threshold voltages based on work function materials of varying thicknesses (e.g., at least one work function material). Thus, the electronic device 500 can be configured with a first set of transistors and a second set of transistors, wherein the first set of transistors is used to optimize a first application related to a first threshold voltage, and the second set of transistors is used to optimize a second application related to a second threshold voltage. The aforementioned ability to assign different transistor bases to different transistors with different threshold voltage adjustments within a single electronic device can optimize the power consumption and / or leakage current of the electronic device.

[0131] As mentioned above, Figure 5 This is a schematic diagram of an exemplary electronic device containing multiple transistors described herein. Other specific examples may differ from those described herein. Figure 5 The person mentioned. Figure 5 The number and arrangement of the devices, layers and / or materials shown are provided as a specific example. In reality, compared to Figure 5 It may have additional devices, layers and / or materials, fewer devices, layers and / or materials, different devices, layers and / or materials, or devices, layers and / or materials with different configurations. In addition, refer to... Figure 5The aforementioned features can be compared with reference to Figures 2A to 4B The aforementioned feature combination.

[0132] Figure 6 This is a schematic diagram illustrating the transistor 600 described herein. The electronic transistor 600 may include... Figure 6 One or more additional layers and / or structures not shown. Transistor 600 may include one or more additional semiconductor structures, such as one or more additional transistors. Transistor 600 may include a fin field-effect transistor.

[0133] like Figure 6 As shown, transistor 600 includes a substrate 602. Substrate 602 may comprise a semiconductor die substrate, a semiconductor wafer, or other types of substrate in which a semiconductor device may be formed and / or on. In some embodiments, substrate 602 is composed of silicon (Si), a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), or other types of semiconductor materials. Substrate 602 may form fins of a fin field-effect transistor structure.

[0134] Transistor 600 also includes a source / drain 604 formed on the top surface of substrate 602. In some embodiments, the source / drain 604 is formed based on a doped substrate 602. Transistor 600 includes a channel 606 disposed in substrate 602 and between the source / drain 604. Channel 606 is configured to carry charge between the source / drain 604 during operation of transistor 600. Transistor 600 includes a tunneling dielectric 608 disposed on channel 606. In some embodiments, tunneling dielectric 608 may comprise an oxygen-based material, such as a silicon oxide layer and / or a silicon dioxide layer, and other specific examples.

[0135] Transistor 600 includes a work function material 610, comprising aluminum and carbon, disposed on tunneling dielectric 608 and over channel 606. In some embodiments, work function material 610 may have the same characteristics as referenced material. Figures 2A to 5 The work function material 222 has similar characteristics and / or advantages. For example, the work function material 610 contains titanium at a concentration of 0% to less than 1.5%. The thickness of the work function material 610 can be greater than 0 Å and less than 12 Å. Alternatively, the thickness of the work function material 610 ranges from greater than 12n Å to less than 12(n+1) Å, where n is the number of titanium-based work function material layers.

[0136] The work function material 610 may be included or may be included within the floating gate 612 of the transistor 600. The floating gate 612 may further include a filler metal, such as tungsten or cobalt, and other specific examples. The transistor 600 may include a dielectric layer 614 configured to provide electrical insulation between the floating gate 612 and the control gate 616. The dielectric layer 614 may include silicon dioxide and / or silicon nitride. For example, the dielectric layer 614 may include an oxygen-nitrogen-oxygen structure to provide electrical insulation between the floating gate 612 and the control gate 616.

[0137] Based on the fact that the floating gate 612 incorporates a work function material 610, the transistor 600 can be tuned to achieve a threshold voltage with optimized precision. For example, the thickness of the work function material 610 can be modified to increase or decrease the threshold voltage without changing the height of the top surface of the floating gate 612. In this way, based on the optimized precision, the transistor 600 can have optimized power consumption.

[0138] As mentioned above, Figure 6 This is a schematic diagram illustrating the transistor described herein. Other specific examples may differ from the reference. Figure 6 The person mentioned. Figure 6 The number and arrangement of the devices, layers and / or materials shown are provided as a specific example. In reality, compared to Figure 6 It may have additional devices, layers and / or materials, fewer devices, layers and / or materials, different devices, layers and / or materials, or devices, layers and / or materials with different configurations. In addition, refer to... Figure 6 The aforementioned features can be compared with reference to Figures 2A to 5 The aforementioned feature combination.

[0139] Figure 7 This is a schematic diagram illustrating exemplary components of device 700, corresponding to deposition tool 102, etching tool 104, planarization tool 106, and / or wafer / die transfer tool 108. In some embodiments, deposition tool 102, etching tool 104, planarization tool 106, and / or wafer / die transfer tool 108 may comprise one or more devices 700 and / or components of one or more devices 700. Figure 7 As shown, the device 700 may include a bus 710, a processor 720, a memory 730, an input component 740, an output component 750, and a communication component 760.

[0140] Bus 710 includes one or more components that enable wired and / or wireless communication between components of device 700. Bus 710 can connect to... Figure 7Two or more components, for example, via operative connections, communication connections, electronic coupling, and / or electrical coupling. Processor 720 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or other types of process elements. Processor 720 executes within hardware, firmware, or a combination of hardware and software. In some embodiments, processor 720 includes one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0141] Memory 730 is a volatile and / or non-volatile memory. For example, memory 730 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 730 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory [e.g., connected via a universal serial bus]. Memory 730 may be a non-transitory computer-readable medium. Memory 730 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of device 700. In some embodiments, memory 730 includes one or more memory modules connected to one or more processors (e.g., processor 720), for example, via bus 710. Input component 740 enables device 700 to receive input, such as user input and / or sensor input. For example, input component 740 may include a touchscreen, keyboard, keypad, mouse, buttons, microphone, transceiver, sensor, GPS sensor, accelerometer, gyroscope, and / or actuator. Output component 750 enables device 700 to provide output, such as through a screen, speaker, and / or LEDs. Communication component 760 enables device 700 to communicate with other devices via wired and / or wireless connections. For example, communication component 760 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0142] Device 700 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 730) may store a set of instructions (e.g., one or more instructions or code) to be executed by processor 720. Processor 720 may execute this set of instructions to perform one or more operations or processes described herein. In some embodiments, a set of instructions executed by one or more processors 720 causes one or more processors 720 and / or device 700 to perform one or more operations or processes described herein. Alternatively or concurrently, processor 720 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0143] Figure 7 The number and configuration of components shown are provided as an example. Compared to Figure 7 As shown, device 700 may include additional components, fewer components, different components, or different component configurations. In addition, or instead, a set of components of device 700 (e.g., one or more components) may perform one or more functions performed by another set of components of device 700.

[0144] Figure 8 This is a flowchart illustrating an example process 800 related to work function materials and their manufacturing processes. In some embodiments, Figure 8 One or more process blocks are performed using one or more semiconductor process tools (e.g., deposition tool 102, etching tool 104, planarization tool 106, and / or wafer / die transfer tool 108). Alternatively, Figure 8 One or more process blocks can be implemented through one or more components of the device 700, such as processor 720, memory 730, input component 740, output component 750 and communication component 760.

[0145] like Figure 8 As shown, process 800 may include a channel structure (block 810) for forming a transistor. For example, one or more semiconductor process tools may form a channel structure 214 of transistor 200, as described above. In some embodiments, channel structure 214 includes a plurality of nanochannels 216 that are on substrate 202 and extend between the source and drain of the transistor.

[0146] Further as Figure 8As shown, process 800 may include forming a work function material around a channel structure (block 820). For example, one or more semiconductor process tools may form a work function material 222 around a channel structure 214, as described above. The work function material 222 may comprise aluminum and carbon. In some embodiments, forming the work function material 222 around the channel structure 214 involves applying a chemical soaking solution. In some embodiments, the chemical soaking solution comprises aluminum, carbon, and hydrogen-based materials. In some embodiments, the concentration of titanium contained in the work function material 222 is from 0% to less than 1.5% of the work function material 222.

[0147] Process 800 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or one or more other processes described elsewhere herein.

[0148] In a first embodiment, the chemical soaking solution is applied to a material at a temperature of about 250 degrees Celsius to about 600 degrees Celsius.

[0149] In the second embodiment, alone or in combination with the first embodiment, process 800 includes depositing an interface layer 218 on the channel structure 214 and depositing a high-k dielectric layer 220 on the interface layer 218.

[0150] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, a work function material 222 is formed around the channel structure 214, comprising a deposited work function material 222 around the high-k dielectric layer 220.

[0151] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, after forming the work function material 222 around the channel structure 214, process 800 includes depositing filler metal around the work function material 222.

[0152] In the fifth embodiment, the thickness of the work function material 222 is greater than 0 angstroms and less than 12 angstroms, either alone or in combination with one or more of the first to fourth embodiments.

[0153] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the channel structure 214 includes a plurality of channels 216 extending between the source / drain 204 of the transistor 200, and a work function material is formed around the channel structure 214, including a deposited work function material 222 around each of the plurality of channels 216.

[0154] Although Figure 8 The illustrated block for process 800, in some embodiments, is compared to Figure 8As illustrated, process 800 may include additional blocks, fewer blocks, different blocks, or blocks with different configurations. In addition, or instead, two or more blocks of process 800 may be processed simultaneously.

[0155] Figures 9A to 9H This is a schematic diagram illustrating the semiconductor device 900 described herein. The semiconductor device 900 can utilize... Figures 9A to 9H The illustrated process is used for manufacturing. The illustrated process may include one or more operations (e.g., lithography, operations performed on different parts of an electronic device including semiconductor device 900) and / or the operations shown in the illustrated process may be combined with… Figures 9A to 9H The order shown may differ from the order in which they are performed. For example, semiconductor device 900 may include one or more components not shown. Figures 9A to 9H Additional devices, structures, and / or layers. For example, semiconductor device 900 may include layers formed on... Figures 9A to 9H Additional layers and / or grains on the upper and / or lower layers of the semiconductor device 900 shown. In addition, or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of the electronic device containing the semiconductor device, having lateral displacement, such as... Figures 9A to 9H The semiconductor device 900 is shown. The semiconductor device 900 can be used in applications with narrow critical dimensions (e.g., Figures 9A to 9H The fin field-effect transistor structure (shown in lateral dimensions), such as an N3 fin field-effect transistor structure and / or a gate-all-around field-effect transistor structure. In some embodiments, the semiconductor device 900 may include... Figures 2A to 2E , Figures 3A to 3F and / or Figures 4A to 4B The transistor 200, electronic device 500 and / or shown Figure 6 The transistor 600 shown.

[0156] like Figure 9A As shown, the semiconductor device 900 includes a stack of nanostructures (e.g., superlattice growth) deposited on a substrate 902. In some embodiments, one or more semiconductor processing tools (e.g., deposition tool 102) deposit a stack of fins having alternating layers (nanofes) of silicon-based material. The alternating layers of silicon-based material may include a set of silicon-germanium layers 904 and a set of silicon layers 906.

[0157] like Figure 9BAs shown, the semiconductor device 900 includes a set of fin stacks comprising alternating layers of silicon-based material. In some embodiments, one or more semiconductor processing tools (e.g., etching tool 104) etch the alternating layers of the nanostructure stack and portions of the substrate 902 to form this set of fin stacks. One or more semiconductor processing tools (e.g., deposition tool 102) may deposit trench isolation structures 908 (e.g., shallow trench isolation structures) between the fin stacks of this set of fin stacks. The trench isolation structure 908 may comprise silicon oxide or silicon germanium, and other specific examples, and is configured to provide electrical insulation and / or isolation between the substrate 902 and the portion of the set of fins containing this set of fin stacks.

[0158] like Figure 9C As shown, semiconductor device 900 includes a gate structure disposed on top of, between, and / or around the set of fin stacks, and on top of trench isolation structure 908. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102 and / or etching tool 104) form the gate structure (e.g., having a sacrificial structure 910, fin sidewall spacers 912, and / or hard mask layer 914) on top of, between, and / or around the fin stacks. For example, one or more semiconductor process tools may deposit a layer of sacrificial structure 910 (e.g., sacrificial material 302) having a generally flat top surface. One or more process tools may etch the sacrificial structure 910 to form the internal structure of the gate structure. One or more semiconductor process tools may deposit a layer of fin sidewall spacers 912 on the internal structure of the gate structure (e.g., sacrificial structure 910). One or more semiconductor process tools can etch portions of the fin sidewall gap wall 912 deposited on the top surface of the sacrificial structure 910, and one or more semiconductor process tools can deposit a hard mask layer 914 on the top surface of the sacrificial structure 910.

[0159] like Figure 9D As shown, semiconductor device 900 includes recessed portions of a fin stack, wherein the recessed portions separate the fin stack into a separate fin stack. In some embodiments, one or more semiconductor process tools (e.g., etching tool 104) may etch the fin stack to form the recessed portions, which are then used to form source / drain regions. Figure 9D Includes the first section (e.g.) Figure 9D (as shown on the upper left) and the second section (e.g.) Figure 9D (shown on the right side above), where a first cross-section shows a portion of the semiconductor device 900 between the fin stacks, and a second cross-section shows a portion of the semiconductor device 900 on the fin stacks.

[0160] like Figure 9EAs shown, the semiconductor device 900 includes recessed portions of this set of silicon-germanium layers 904. For example, one or more process tools (e.g., etching tool 104) can etch away portions of this set of silicon-germanium layers 904 exposed to the recessed portions and / or etch away silicon nitride and / or silicon carbonitride oxynitride (SiCON) fin sidewall material. For example, one or more semiconductor process tools can provide methane, trifluoromethane, oxygen, hydrogen bromide, silicon tetrachloride, sulfur dioxide, sulfur hexafluoride, helium and / or hydrogen, and other specific examples, as gas-based etchants. Gas-based etchants can be applied at pressures of about 5 mTorr to about 100 mTorr and / or at temperatures of about 25 degrees Celsius to about 150 degrees Celsius.

[0161] like Figure 9F As shown, the semiconductor device 900 includes an inner spacer wall 916 deposited on the surface of a recessed portion of the silicon-germanium layer 904. In some embodiments, one or more process tools (e.g., deposition tool 102) deposit material of the inner spacer wall 916 in the recessed portion of the silicon-germanium layer 904 and on other material formed on the surface of the recessed portion. One or more process tools (e.g., etching tool 104) may remove a portion of the material of the inner spacer wall 916 to fill the recessed portion of the silicon-germanium layer 904 with the inner spacer wall 916, thereby forming a substantially flat surface of the recessed portion of the semiconductor device.

[0162] like Figure 9G As shown, the semiconductor device 900 includes epitaxial material 918, which is formed as a source / drain between portions of the fin stack of the semiconductor device 900. In some embodiments, one or more semiconductor process tools (e.g., deposition tool 102) deposit the source / drain material as described herein (e.g., refer to...). Figures 2A to 2E and / or refer to Figures 3A to 3F ).

[0163] like Figure 9H As shown, the semiconductor device 900 includes apertures between the fin sidewall spacer 912 and the silicon nanostructure 906 (e.g., one or more channels). For example, one or more process tools (e.g., etching tool 104) can etch a hard mask 914 and a sacrificial structure 910 to form apertures between the fin sidewall spacer 912 and the silicon nanostructure 906 (e.g., see reference 104). Figure 3B The above).

[0164] In some embodiments, one or more semiconductor fabrication tools may deposit one or more gate materials in the apertures to form the gate of a semiconductor device, which operates together with the silicon nanostructure 906 (e.g., as a channel) and epitaxial material 918 (e.g., as a source / drain) of the semiconductor device 900. For example, one or more semiconductor fabrication tools may perform one or more reference... Figures 3B to 3FThe aforementioned operation.

[0165] As mentioned above, Figures 9A to 9H This is provided as a specific example. Other specific examples may differ from this. Figures 9A to 9H Related explanations. Figures 9A to 9H The number and arrangement of the devices, layers and / or materials shown are provided as a specific example. In reality, compared to Figures 9A to 9H The semiconductor device 900 may have additional devices, layers, and / or materials, fewer devices, layers, and / or materials, different devices, layers, and / or materials, or devices, layers, and / or materials with different configurations. In some embodiments, after a deposition or etching operation, the planarization tool 106 is used to planarize one or more materials of the semiconductor device 900. In this way, the top surface of the semiconductor device 900 is more suitable for further deposition and / or etching operations.

[0166] Based on the use of work function materials containing aluminum and carbon (e.g., titanium-free work function materials), the thickness of the work function material is between 0 angstroms and less than 12 angstroms and / or adjustable to a thickness greater than 12n angstroms and less than 12(n+1) angstroms, where n is the number of layers of the titanium-based work function material. Based on the transistor having an optimized threshold voltage, the transistor is optimized to optimize power consumption and / or leakage current, and other specific examples.

[0167] As described in more detail above, some embodiments described herein provide a transistor. The transistor includes nanostructures vertically disposed on a substrate. The transistor includes a channel structure of nanostructures comprising a plurality of nanostructure channels on the substrate and extending between the source and drain of the transistor. The transistor includes a work function material disposed around the plurality of nanostructure channels of the channel structure and separated from the source and drain by one or more inner spacers, wherein the work function material comprises aluminum and carbon, and the concentration of titanium in the work function material is from 0% to less than 1.5% of the work function material.

[0168] In one embodiment, the work function material is disposed between the nanostructure channel and the filler metal of the transistor. In one embodiment, the transistor comprises a nanosheet transistor. In one embodiment, the channel structure comprises multiple channels, and the work function material is disposed around a single channel. In one embodiment, the transistor further comprises one or more of the following: an interface layer disposed between the work function material and the channel structure; a high-k dielectric layer disposed between the work function material and the channel structure; and additional work function material disposed around the work function material. In one embodiment, the aforementioned interface layer comprises an oxide layer directly disposed on the channel structure. In one embodiment, the aforementioned high-k dielectric layer comprises a hafnium oxide-based material disposed between the interface layer and the work function material. In one embodiment, the aforementioned additional work function material comprises one or more of a titanium aluminum carbide (TiAlC)-based material or a titanium nitride (TiN)-based material. In one embodiment, the work function material is an n-type work function material or a p-type work function material.

[0169] As described in more detail above, some embodiments described herein provide a method. The method includes forming a channel structure of a transistor, the channel structure comprising a plurality of nanostructured channels on a substrate and extending between the source and drain of the transistor. The method includes forming a work function material comprising aluminum and carbon around the channel structure, wherein forming the work function material around the channel structure comprises applying a chemical soaking solution, the material of which comprises aluminum, carbon, and hydrogen-based materials, and the concentration of titanium in the work function material is from 0% to less than 1.5% of the work function material.

[0170] In one embodiment, the chemical soaking solution is a material for which the chemical soaking solution is applied at a temperature of 250°C to 600°C. In one embodiment, the method further includes depositing an interface layer on the channel structure and depositing a high-k dielectric layer on the interface layer. In one embodiment, forming a work function material around the channel structure includes depositing a work function material around the high-k dielectric layer. In one embodiment, after forming the work function material around the channel structure, the method further includes depositing a filler metal around the work function material. In one embodiment, the method further includes forming an additional channel structure of work function material around an additional transistor of the same electronic element as the transistor, wherein the work function material has a first thickness around the channel structure, the work function material has a second thickness around the additional channel structure, and the first thickness is different from the second thickness. In one embodiment, the thickness of the work function material is greater than... And less than 12 angstroms. In one embodiment, the channel structure includes multiple channels, wherein the channels extend between the source and drain of the transistor, and the forming work function material around the channel structure includes deposited work function material around each individual channel.

[0171] As described in more detail above, some embodiments described herein provide a transistor. The transistor includes source / drain electrodes formed on the surface of a substrate. The transistor includes a channel extending between the source / drain electrodes and in the substrate. The transistor includes a work function material disposed on the channel, comprising aluminum and carbon, wherein the work function material includes titanium at a concentration of 0% to less than 1.5% of the work function material. The transistor includes a gate disposed on the work function material.

[0172] In one embodiment, the transistor comprises a finned field-effect transistor. In another embodiment, the transistor further comprises a tunneling dielectric between the channel and the work function material.

[0173] The foregoing outlines features of many embodiments, thus enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that other processes and structures can be designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the described embodiments. Those skilled in the art should also understand that equivalent architectures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A transistor, characterized in that, Include: A nanostructure, vertically disposed on a substrate; The nanostructure has a channel structure, wherein the channel structure comprises multiple nanostructure channels on the substrate, and the channel structure extends between the source and drain of the transistor; and A work function material is disposed around the nanostructure channels of the channel structure and separated from the source / drain by one or more internal spacer walls, wherein the work function material comprises aluminum, carbon, and titanium. The concentration of titanium in the work function material is less than 1.5% of the work function material.

2. The transistor according to claim 1, characterized in that, The work function material is disposed between the nanostructure channels and a filler metal of the transistor.

3. The transistor according to claim 1, characterized in that, The transistor contains a nanosheet transistor.

4. The transistor according to claim 1, characterized in that, The channel structure contains multiple channels, and the work function material is disposed around each of the individual channels.

5. The transistor according to claim 1, characterized in that, It also includes one or more of the following: An interface layer is disposed between the work function material and the channel structure; A high-k dielectric layer is disposed between the work function material and the channel structure; or An additional work function material is placed around the work function material.

6. The transistor according to claim 5, characterized in that, This interface layer contains: An oxide layer is directly applied to the channel structure.

7. The transistor according to claim 5, characterized in that, This high-k dielectric layer contains: A hafnium oxide-based material is disposed between the interface layer and the work function material.

8. The transistor according to claim 5, characterized in that, The additional work function material contains one or more of the following: Titanium carbide aluminum-based materials or titanium nitride-based materials.

9. The transistor according to claim 1, characterized in that, The work function material is either an n-type work function material or a p-type work function material.

10. A method for manufacturing a transistor, characterized in that, Include: A channel structure is formed for a transistor, wherein the channel structure includes a plurality of nanostructured channels on a substrate, and the channel structure extends between the source and drain of the transistor; and A work function material is formed around the channel structure, wherein the work function material comprises aluminum, carbon, and titanium. The material forming the work function is surrounded by a chemical soaking solution. The chemical immersion solution contains aluminum, carbon and hydrogen-based materials, and The concentration of titanium in the work function material is less than 1.5% of the work function material.

11. The method for manufacturing a transistor according to claim 10, characterized in that, The step of applying the chemical soaking solution includes: The material is subjected to the chemical soaking solution at a temperature of 250°C to 600°C.

12. The method for manufacturing a transistor according to claim 10, characterized in that, Also includes: An interface layer is deposited on the channel structure; and A high-k dielectric layer is deposited on the interface layer.

13. The method for manufacturing a transistor according to claim 12, characterized in that, The steps involved in forming the work function material around the channel structure include: The work function material is deposited around the high-k dielectric layer.

14. The method for manufacturing a transistor according to claim 10, characterized in that, Also includes: After the work function material is formed around the channel structure, a filler metal is deposited around the work function material.

15. The method for manufacturing a transistor according to claim 10, characterized in that, Also includes: The work function material forms an additional channel structure around an additional transistor, which is an electronic component identical to the transistor. The work function material has a first thickness around the channel structure. The work function material has a second thickness around the additional channel structure. Furthermore, the first thickness is different from the second thickness.

16. The method for manufacturing a transistor according to claim 10, characterized in that, The thickness of the work function material is greater than 0 angstroms and less than 12 angstroms.

17. The method for manufacturing a transistor according to claim 10, characterized in that, The channel structure includes multiple channels that extend between the source and drain of the transistor, and The step of forming the work function material around the channel structure includes depositing the work function material around a single channel of these channels.

18. A transistor, characterized in that, Include: The source and drain are formed on a surface of a substrate of the transistor. A channel extends between the source and drain electrodes and on the substrate; as well as A work function material is deposited on the channel, wherein the work function material comprises aluminum, carbon, and titanium, and the concentration of titanium in the work function material is less than 1.5% of the work function material; and A gate is disposed on the work function material.

19. The transistor according to claim 18, characterized in that, The transistor contains a fin field-effect transistor.

20. The transistor according to claim 18, characterized in that, Also includes: A tunneling dielectric, between the channel and the work function material.

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