A method for manufacturing a GaN HEMT device with a gradually doped step fluorine ion terminal

Abstract

The present invention belongs to the field of power semiconductor technology, and relates to a method for manufacturing a GaN HEMT device with a gradually doped step fluorine ion terminal. In the manufacturing method, a photolithography process is first used to form a window with a successively smaller width, and then a step groove with a successively shallower depth is realized by a one-time dry etching of the window with a successively smaller width, and finally a one-time fluorine ion implantation is performed to form a gradually doped step fluorine ion terminal. The terminal can better optimize the surface electric field and improve the device withstand voltage, and the manufacturing method forms a fluorine ion region under the gate and a gradually doped step fluorine ion terminal by a one-time fluorine ion implantation, and at the same time realizes the enhancement type and improves the device withstand voltage, and reduces the difficulty of the process. In addition, in the manufacturing method, the fluorine ions are implanted into the passivation layer instead of directly into the barrier layer AlGaN, which can reduce the influence on the mobility of the two-dimensional electron gas, suppress the increase of dynamic resistance and the current collapse effect, and improve the forward conduction and dynamic characteristics of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a method for manufacturing a GaN HEMT device with a gradually doped step fluorine ion terminal. Background Art

[0002] GaN HEMT (high electron mobility transistor) devices have broad application prospects in the field of high current, low power consumption, medium and low voltage switching devices. However, the electric field concentrates and excites hot electrons under high field, causing gate failure or a sharp increase in leakage current, and the device withstand voltage is far from its theoretical limit. At present, the main methods for improving the breakdown voltage of the device are: field plate technology, fluorine ion implantation, terminal technology, polarization super junction technology and compensation doping technology. In addition, due to the presence of high-density two-dimensional electron gas at the heterojunction interface, it is difficult to obtain enhanced high-voltage devices with high threshold voltage. This not only increases the risk of circuit mis-starting, but also increases the power consumption of the entire circuit and the difficulty of designing the drive circuit. At present, typical ways to achieve enhancement include: groove gate technology, P-GaN technology, cascode cascade technology, fluorine ion implantation technology and thin barrier technology. Summary of the invention

[0003] Based on the needs of GaN HEMT device applications, the present invention proposes a method for manufacturing a GaN HEMT device with a gradually doped step fluorine ion terminal. First, a photolithography process is used to form a window with a successively smaller width, and then a step groove with a successively shallower depth is realized through a one-time etching of the window with a successively smaller width, and finally a one-time fluorine ion implantation is performed to form a gradually doped step fluorine ion terminal, thereby realizing an enhanced type and optimizing the surface electric field, improving the device withstand voltage, and reducing the difficulty of the process.

[0004] To achieve the above-mentioned object of the invention, the technical solution of the present invention is as follows:

[0005] A method for manufacturing a GaN HEMT device with a gradually doped step fluorine ion terminal, characterized by comprising the following steps:

[0006] Step 1: Material preparation, the materials include, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, and an AlGaN barrier layer 4;

[0007] Step 2: depositing a dielectric on the AlGaN barrier layer 4 to form a dielectric passivation layer 5;

[0008] Step 3: etching the two ends of the dielectric passivation layer 5 by an etching process, and exposing the source hole and the drain hole at the two ends of the AlGaN barrier layer 4, depositing the first conductive material, and forming the source 6 and the drain 12 by an etching or stripping process;

[0009] Step 4: using an etching process to etch a gate groove 7 on the upper surface of the dielectric passivation layer 5, wherein the depth of the gate groove 7 is less than the thickness of the dielectric passivation layer 5;

[0010] Step 5: Coating a photoresist 11 on the dielectric passivation layer 5, and photolithographically forming a window region 9, wherein the window region 9 comprises a plurality of windows 90 to 9N that are narrowed in sequence along the direction from the source to the drain, wherein the window closest to the source is aligned with the gate groove 7 in the vertical direction, and the window closest to the drain is spaced from the drain;

[0011] Step 6: using a dry etching process, etching the dielectric passivation layer 5 through the window area 9 to form a plurality of dielectric grooves 101 to 10N whose depths gradually become shallower along the direction from the source to the drain, and the dielectric passivation layer 5 is still retained at the bottom of the deepest dielectric groove, and the gate groove 7 is further etched;

[0012] Step 7: injecting fluorine ions into the dielectric passivation layer 5 through the window area 9 to form a plurality of fluorine ion injection areas, wherein the fluorine ion injection area located below the gate groove 7 passes through the dielectric passivation layer 5 and enters the AlGaN barrier layer 4, while the other fluorine ion areas are only in the dielectric passivation layer 5, and the dielectric groove and the fluorine ion injection area together constitute a gradient doping step fluorine ion terminal 8; removing the photoresist 11, and performing annealing;

[0013] Step 8: deposit a second conductive material, and form a gate 13 by etching or stripping.

[0014] As a preferred embodiment, the spacings between the fluorine ion regions 81 to 8N in the gradient-doped step fluorine ion terminal 8 in the lateral direction of the device are equal.

[0015] As a preferred embodiment, the spacings between the fluorine ion regions 81 to 8N in the gradually doped step fluorine ion terminal 8 in the lateral direction of the device are unequal, and the spacings increase successively along the direction from the source to the drain.

[0016] As a preferred embodiment, the first conductive material is one or a combination of Ti, TiN, Al, Ni, and Au.

[0017] As a preferred embodiment, the second conductive material is a combination of Ni and Au.

[0018] As a preferred embodiment, the material used for the substrate 1 is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO, and GaAs.

[0019] As a preferred embodiment, the material used for the passivation layer 5 is SiN x 、SiO 2 、Al 2 O 3 , one of AlN.

[0020] The beneficial effect of the present invention is that a photolithography process is first used to form a window with a decreasing width, and then a step groove with a decreasing depth is realized by dry etching the window with a decreasing width at one time, and finally a one-time fluorine ion implantation is performed to form a fluorine ion region under the gate and a gradually doped step fluorine ion terminal, thereby achieving enhanced and optimized surface electric field, improving device withstand voltage, and reducing process difficulty. Compared with the common fluorine ion terminal, the gradually doped step fluorine ion terminal can better optimize the surface electric field and improve the device withstand voltage, and at the same time, the fluorine ion implantation into the passivation layer improves the forward conduction and dynamic characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the two-dimensional structure of Example 1;

[0022] Figure 2 It is the process flow chart of Example 1;

[0023] Figure 3 It is the specific process steps of Example 1, wherein:

[0024] (a) is a schematic diagram of the device structure after the dielectric passivation layer is formed in step 2 of the process flow of Example 1;

[0025] (b) is a schematic diagram of the device structure after the source and drain conductive materials are formed in step 3 of the process flow of Example 1;

[0026] (c) is a schematic diagram of the device structure after the dielectric groove is formed in step 4 of the process flow of Example 1;

[0027] (d) is a schematic diagram of the device structure after forming a masking layer and photolithography in step 5 of the process flow of Example 1;

[0028] (e) is a schematic diagram of the device structure after etching in step 6 of the process flow of Example 1;

[0029] (f) is a schematic diagram of the device structure after fluorine ion implantation in step 7 of the process flow of Example 1;

[0030] (g) is a schematic diagram of the device structure after the gate conductive material is formed in step 8 of the process flow of Example 1; DETAILED DESCRIPTION

[0031] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0032] Embodiment 1:

[0033] Step 1: Material preparation, the materials include, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, and an AlGaN barrier layer 4;

[0034] Step 2: depositing a dielectric on the AlGaN barrier layer 4 to form a dielectric passivation layer 5;

[0035] Step 3: etching the two ends of the dielectric passivation layer 5 by an etching process, and exposing the source hole and the drain hole at the two ends of the AlGaN barrier layer 4, depositing the first conductive material, and forming the source 6 and the drain 12 by an etching or stripping process;

[0036] Step 4: using an etching process to etch a gate groove 7 on the upper surface of the dielectric passivation layer 5, wherein the depth of the gate groove 7 is less than the thickness of the dielectric passivation layer 5;

[0037] Step 5: Coating a photoresist 11 on the dielectric passivation layer 5, and photolithographically forming a window area 9, wherein the window area 9 includes a plurality of windows that are narrowed in sequence along the direction from the source to the drain, wherein the window closest to the source is aligned with the gate groove 7 in the vertical direction, and the window closest to the drain has a spacing with the drain;

[0038] Step 6: using a dry etching process, etching the dielectric passivation layer 5 through the window area 9 to form a plurality of dielectric grooves 101 to 10N whose depths gradually become shallower along the direction from the source to the drain, and the dielectric passivation layer 5 is still retained at the bottom of the deepest dielectric groove, and the gate groove 7 is further etched;

[0039] Step 7: injecting fluorine ions into the dielectric passivation layer 5 through the window area 9 to form a plurality of fluorine ion injection areas, wherein the fluorine ion injection area located below the gate groove 7 passes through the dielectric passivation layer 5 and enters the AlGaN barrier layer 4, while the other fluorine ion areas are only in the dielectric passivation layer 5, and the dielectric groove and the fluorine ion injection area together constitute a gradient doping step fluorine ion terminal 8; removing the photoresist 11, and performing annealing;

[0040] Step 8: deposit a second conductive material, and form a gate 13 by etching or stripping.

[0041] The GaN HEMT device with a gradually doped step fluorine ion terminal prepared by the above manufacturing method first uses a photolithography process to form a window with a decreasing width, then a step groove with a decreasing depth is realized through a one-time etching of the window with a decreasing width, and finally a one-time fluorine ion implantation is performed to form a fluorine ion region under the gate and a gradually doped step fluorine ion terminal, while realizing the device enhancement mode and optimizing the surface electric field, improving the device withstand voltage, and reducing the difficulty of the process. Compared with the common fluorine ion terminal, the gradually doped step fluorine ion terminal can better optimize the surface electric field and improve the device withstand voltage. At the same time, the fluorine ion implantation into the passivation layer improves the forward conduction and dynamic characteristics of the device.

Claims

1. A method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination, It is characterized in that The following steps are involved: Step 1: material preparation, including a substrate (1), a GaN buffer layer (2), a GaN channel layer (3) and an AlGaN barrier layer (4) stacked from bottom to top; Step 2: depositing a dielectric on the AlGaN barrier layer (4) to form a dielectric passivation layer (5); Step 3: etching the two ends of the dielectric passivation layer (5) by an etching process, exposing a source hole and a drain hole at the two ends of the AlGaN barrier layer (4), depositing a first conductive material, and forming a source electrode (6) and a drain electrode (12) by an etching or stripping process; Step 4: using an etching process to etch a gate groove (7) on the upper surface of the dielectric passivation layer (5), wherein the depth of the gate groove (7) is less than the thickness of the dielectric passivation layer (5); Step 5: coating a photoresist (11) on the dielectric passivation layer (5), and photolithographically forming a window region (9), wherein the window region (9) comprises a plurality of windows that are narrowed in sequence along a direction from the source electrode to the drain electrode, the number of windows being N and N>2, wherein the window closest to the source electrode is aligned with the gate groove (7) in a vertical direction, and the window closest to the drain electrode is spaced apart from the drain electrode; Step 6: using a dry etching process to etch the dielectric passivation layer (5) through the window area (9) to form a plurality of dielectric grooves whose depths gradually become shallower along the direction from the source electrode to the drain electrode, and the dielectric passivation layer (5) is still retained at the bottom of the deepest dielectric groove; Step 7: injecting fluorine ions into the dielectric passivation layer (5) through the window area (9) to form a plurality of fluorine ion injection areas, wherein the fluorine ion injection area located below the gate groove (7) passes through the dielectric passivation layer (5) and enters the AlGaN barrier layer (4), while the other fluorine ion areas are only in the dielectric passivation layer (5), and the dielectric groove and the fluorine ion injection area together form a gradient doping step fluorine ion terminal (8); removing the photoresist (11), and performing annealing; Step 8: Deposit a second conductive material and use an etching or stripping process to form a gate (13).

2. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The spacings between the fluorine ion regions in the gradient doping step fluorine ion terminal (8) in the lateral direction of the device are equal.

3. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The spacings of the fluorine ion regions in the gradually doped step fluorine ion terminal (8) in the lateral direction of the device are not equal, and the spacings increase successively along the direction from the source to the drain.

4. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The first conductive material is one or a combination of Ti, TiN, Al, Ni, and Au.

5. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The second conductive material is a combination of Ni and Au.

6. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The material used for the substrate (1) is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO and GaAs.

7. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, It is characterized in that The material used for the dielectric passivation layer (5) is SiN x 、SiO 2 、Al 2 O 3 , one of AlN.

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