Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate, a source and a drain. The first oxide layer is located on the substrate. The insulating pattern is located on the first oxide layer and includes a silicon nitride layer and a second oxide layer. The silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewall of the insulating pattern and the upper surface of the insulating pattern. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. Part of the insulating pattern is located between the gate and the substrate. The source and the drain are electrically connected to the metal oxide layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] At present, common thin film transistors usually use amorphous silicon semiconductors as channels, wherein amorphous silicon semiconductors are widely used in various thin film transistors due to their simple process and low cost.

[0003] With the advancement of display technology, the resolution of display panels has been increasing year by year. In order to shrink the thin film transistors in the pixel circuit, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material. Summary of the invention

[0004] The invention provides a semiconductor device and a manufacturing method thereof, which can improve the hot carrier effect at the drain, thereby improving the reliability.

[0005] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate, a source and a drain. The first oxide layer is located on the substrate. The insulating pattern is located on the first oxide layer and includes a silicon nitride layer and a second oxide layer. The silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewall of the insulating pattern and the upper surface of the insulating pattern. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. Part of the insulating pattern is located between the gate and the substrate. The source and the drain are electrically connected to the metal oxide layer.

[0006] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first oxide layer on a substrate; forming an insulating pattern on the first oxide layer, and the insulating pattern includes a silicon nitride layer and a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; forming a metal oxide layer on the upper surface of the first oxide layer, the sidewall of the insulating pattern and the upper surface of the insulating pattern; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer, wherein a portion of the insulating pattern is located between the gate and the substrate; forming a source and a drain electrically connected to the metal oxide layer.

[0007] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a drain, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate and a source. The drain is located on the substrate. The insulating pattern is located on the drain, and the drain is located below a first contact hole of the insulating pattern. The metal oxide layer is located on the insulating pattern and filled in the first contact hole. The metal oxide layer contacts the upper surface of the insulating pattern, the sidewall of the first contact hole of the insulating pattern and the drain. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. The source is electrically connected to the metal oxide layer.

[0008] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including forming a drain on a substrate; forming a silicon nitride layer blanketing the drain; forming an oxide layer blanketing the silicon nitride layer; performing a first patterning process on the silicon nitride layer and the oxide layer to form a first contact hole and an opening, wherein the first contact hole passes through the oxide layer and the silicon nitride layer, and the opening passes through the oxide layer but not through the silicon nitride layer; forming a metal oxide layer on the silicon nitride layer and the oxide layer, and the metal oxide layer fills the first contact hole and contacts the upper surface of the oxide layer, the sidewall of the first contact hole and the drain; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer; and forming a source electrically connected to the metal oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a top view of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 1B yes Figure 1A Schematic cross-sectional view of line a-a'.

[0011] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0012] Figure 3A is a top view of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 3B yes Figure 3A Schematic cross-sectional view of line a-a'.

[0014] Figure 4A is a top view of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 4B yes Figure 4A Schematic cross-sectional view of line a-a'.

[0016] Figures 5A to 10Ais a top view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] Figures 5B to 10B They are FIG. 5A to FIG. 10A Schematic cross-sectional view of line a-a'.

[0018] Fig.11A is a top view of a display device according to an embodiment of the present invention.

[0019] Fig. 11B yes Fig.11A A partial enlarged schematic diagram of .

[0020] Description of reference numerals:

[0021] 10A, 10B, 10C: Semiconductor devices

[0022] 100: Substrate

[0023] 110: First oxide layer

[0024] 120: Insulation pattern

[0025] 122: Silicon nitride layer

[0026] 124 Second oxide layer

[0027] 130: Gate dielectric layer

[0028] 140: Interlayer dielectric layer

[0029] AA: Display area

[0030] a-a': line

[0031] BA: Peripheral area

[0032] ch: channel area

[0033] D: Drain

[0034] dr: drain region

[0035] G: Gate

[0036] HD: Height Difference

[0037] HDF: Heat Dissipation Structure

[0038] h: Hydrogen concentration gradient zone

[0039] ND: Normal Direction

[0040] OP: Opening

[0041] OS, OS': Metal oxide layer

[0042] P: Doping process

[0043] PR: Patterned photoresist layer

[0044] S: Source

[0045] sr: source region

[0046] sw,sw1a,sw1b,sw2: side wall

[0047] T: Connecting electrode

[0048] t1, t2, t3, t4: thickness

[0049] ts1, ts2: upper surface

[0050] V1: First contact hole

[0051] V2: Second contact hole

[0052] V3: The third contact hole DETAILED DESCRIPTION

[0053] Figure 1A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 1B yes Figure 1A Schematic cross-sectional view of line a-a'.

[0054] Please refer to Figure 1A and Figure 1B , the semiconductor device 10A includes a substrate 100, a first oxide layer 110, an insulating pattern 120, a metal oxide layer OS, a gate dielectric layer 130, a gate G, a source S and a drain D, wherein the insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In this embodiment, the semiconductor device 10A further includes an interlayer dielectric layer 140. For convenience of description, Figure 1A The metal oxide layer OS, the silicon nitride layer 122, the gate G, the source S, and the drain D are shown, and other components are omitted.

[0055] The material of the substrate 100 may be glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil or other flexible materials.

[0056] The first oxide layer 110 is located on the substrate 100. In some embodiments, the first oxide layer 110 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, the thickness t1 of the first oxide layer 110 is 500 angstroms to 3000 angstroms.

[0057] The insulating pattern 120 is located on the first oxide layer 110 and includes a silicon nitride layer 122 and a second oxide layer 124. In some embodiments, the silicon nitride layer 122 contains hydrogen. In some embodiments, the thickness t2 of the silicon nitride layer 122 is 100 angstroms to 1500 angstroms. The second oxide layer 124 is located on the silicon nitride layer 122, and the silicon nitride layer 122 is located between the first oxide layer 110 and the second oxide layer 124. The second oxide layer 124 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, both the first oxide layer 110 and the second oxide layer 124 are silicon oxide or silicon oxynitride, and the oxygen concentration of the first oxide layer 110 is greater than the oxygen concentration of the second oxide layer 124. For example, the first oxide layer 110 includes SiOx, the second oxide layer 124 includes SiOy, and x is greater than y. In some embodiments, the thickness t3 of the second oxide layer 124 is 100 angstroms to 1500 angstroms.

[0058] The metal oxide layer OS is located on the first oxide layer 110 and the insulating pattern 120. The metal oxide layer OS contacts the upper surface ts1 of the first oxide layer 110, the sidewall sw of the insulating pattern 120, and the upper surface ts2 of the insulating pattern 120. In some embodiments, the sidewall sw of the insulating pattern 120 includes the silicon nitride layer 122 and the second oxide layer 124, and the metal oxide layer OS contacts the silicon nitride layer 122 and the second oxide layer 124 at the position of the sidewall sw.

[0059] The metal oxide layer OS includes a source region sr, a drain region dr, and a channel region ch located between the source region sr and the drain region dr. The source region sr and the drain region dr are doped to have a lower resistivity than the channel region ch. In the present embodiment, the source region sr contacts the upper surface ts1 of the first oxide layer 110, the channel region ch contacts the upper surface ts1 of the first oxide layer 110 and the sidewall sw of the insulating pattern 120, and the drain region dr contacts the upper surface ts2 of the insulating pattern 120. In some embodiments, the distance between the source region sr and the substrate 100 is smaller than the distance between the drain region dr and the substrate 100. In some embodiments, there is a height difference HD between the bottom surface of the drain region dr and the bottom surface of the source region sr, and the height difference HD is, for example, approximately equal to the thickness of the insulating pattern 120. In the present embodiment, the portion of the channel region ch connected to the drain region dr extends along the vertical direction (normal direction ND), which can reduce the hot carrier effect generated by the lateral electric field in the metal oxide layer OS near the drain D.

[0060] In some embodiments, since the drain region dr is located on the silicon nitride layer 122 containing hydrogen, the hydrogen concentration of the drain region dr is greater than that of the source region sr. Therefore, the hydrogen resistivity of the drain region dr is lower than that of the source region sr.

[0061] In some embodiments, the material of the metal oxide layer OS includes quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or an oxide composed of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W).

[0062] The gate dielectric layer 130 is located on the metal oxide layer OS. The gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials. In some embodiments, the thickness t4 of the gate dielectric layer 130 is 500 angstroms to 3000 angstroms.

[0063] The gate G is located on the gate dielectric layer 130. A portion of the insulating pattern 120 is located between the gate G and the substrate 100. In the present embodiment, in the normal direction ND of the top surface of the substrate 100, a portion of the gate G overlaps the insulating pattern 120, and another portion of the gate G does not overlap the insulating pattern 120. In the present embodiment, the drain region dr extends between the gate G and the substrate 100. A portion of the gate G overlaps the drain region dr, and another portion overlaps the channel region ch.

[0064] In some embodiments, the material of the gate G may include metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or alloys of any combination of the above metals or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The gate G may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.

[0065] The interlayer dielectric layer 140 is disposed on the gate dielectric layer 130. The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials.

[0066] The drain D and the source S are disposed on the interlayer dielectric layer 140. In the normal direction ND, the drain D overlaps the insulating pattern 120, while the source S does not overlap the insulating pattern 120. The drain D and the source S are electrically connected to the drain region dr and the source region sr of the metal oxide layer OS through the first contact hole V1 and the second contact hole V2 in the interlayer dielectric layer 140, respectively. In some embodiments, the material of the drain D and the source S may include a metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy of any combination of the above metals or a stack of the above metals and / or alloys, but the present invention is not limited thereto. The drain D and the source S may also use other conductive materials, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

[0067] FIG. 2A to FIG. 2E yes Figure 1A and Figure 1B A cross-sectional schematic diagram of a method for manufacturing a semiconductor device 10A.

[0068] Please refer to Figure 2A, forming a first oxide layer 110 on the substrate 100. Then, forming an insulating pattern 120 on the first oxide layer 110. In some embodiments, the method of forming the insulating pattern 120 includes forming a silicon nitride material layer blanketing on the first oxide layer 110. Then, forming an oxide material layer blanketing on the silicon nitride material layer. Then, the oxide material layer and the silicon nitride material layer are patterned by a photolithography etching process to form a silicon nitride layer 122 and a second oxide layer 124. In some embodiments, the method of forming the oxide material layer and the silicon nitride material layer includes chemical vapor deposition or plasma enhanced chemical vapor deposition, and the gas used to form the silicon nitride material layer includes silane (SiH4), nitrogen (N2), ammonia (NH3) and other suitable gases, so that the silicon nitride layer 122 includes hydrogen elements.

[0069] Please refer to Figure 2B , metal oxide OS' is formed on the upper surface ts1 of the first oxide layer 110, the sidewall sw of the insulating pattern 120, and the upper surface ts2 of the insulating pattern 120. In the present embodiment, there is a step between the upper surface ts1 of the first oxide layer 110 and the upper surface ts2 of the insulating pattern 120, and the metal oxide OS' covers the step position between the upper surface ts1 of the first oxide layer 110 and the upper surface ts2 of the insulating pattern 120.

[0070] In some embodiments, the first oxide layer 110 has a function of storing oxygen. When the metal oxide OS' is deposited, part of the oxygen diffuses into the first oxide layer 110. At this time, the first oxide layer 110 has a relatively high oxygen concentration. However, since the second oxide layer 124 of the insulating pattern 120 has a poor ability to store oxygen, the second oxide layer 124 has a relatively low oxygen concentration.

[0071] A gate dielectric layer 130 is formed on the metal oxide layer OS'. In some embodiments, the metal oxide layer OS' is heated when the gate dielectric layer 130 is deposited, so that the oxygen in the metal oxide layer OS' diffuses out, for example, diffuses into the first oxide layer 110 or the gate dielectric layer 130, and generates oxygen vacancies in the metal oxide layer OS', so that the resistivity of the metal oxide layer OS' decreases. Since the second oxide layer 124 has a poorer ability to store oxygen, the oxygen in the metal oxide layer OS' above the second oxide layer 124 is less likely to diffuse downward into the second oxide layer 124. In addition, in some embodiments, the hydrogen in the silicon nitride layer 122 diffuses upward into the metal oxide layer OS' above the second oxide layer 124, further reducing the resistivity of the metal oxide layer OS' above the second oxide layer 124.

[0072] Please refer to Figure 2CIn some embodiments, after the gate dielectric layer 130 is deposited, an annealing process is performed to diffuse the oxygen elements stored in the first oxide layer 110 and the gate dielectric layer 130 into the metal oxide layer OS'. The oxygen elements combine with the oxygen vacancies in the metal oxide layer OS' to increase the resistivity of the metal oxide layer OS', for example, the resistivity is increased from about 1E+4ohm / sq to more than 1E+8ohm / sq.

[0073] In some embodiments, since the oxygen element stored in the first oxide layer 110 is greater than the oxygen element stored in the second oxide layer 124, more oxygen element will diffuse into the portion of the metal oxide layer OS' located on the first oxide layer 110, so that the oxygen concentration of the portion of the metal oxide layer OS' located on the first oxide layer 110 is increased more, while the oxygen concentration of another portion of the metal oxide layer OS' located on the second oxide layer 124 is relatively increased less. In other words, after the formation annealing process, the resistivity of the portion of the metal oxide layer OS' located on the first oxide layer 110 is higher than the resistivity of the other portion of the metal oxide layer OS' located on the second oxide layer 124.

[0074] Please refer to Figure 2D , forming a gate G on the gate dielectric layer 130. Then, using the gate G as a mask, a doping process P is performed on the metal oxide layer OS' to form a source region sr, a drain region dr, and a channel region ch located between the source region sr and the drain region dr in the metal oxide layer OS'. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable processes.

[0075] In some embodiments, the hydrogen element in the silicon nitride layer 122 can maintain the hydrogen concentration of the drain region dr of the metal oxide layer OS, so that the hydrogen in the drain region dr is not easy to escape in the subsequent process. In addition, in some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the drain region dr, so that the hydrogen concentration of the drain region dr is greater than the hydrogen concentration of the source region sr. In addition, since part of the silicon nitride layer 122 is located between the gate G and the substrate 100, the metal oxide layer OS' / OS partially overlapping the gate G will also be doped with hydrogen elements, so that the metal oxide layer OS' / OS partially overlapping the gate G is transformed into the drain region dr, further reducing the hot carrier effect generated by the electric field at the edge of the gate G. In some embodiments, the drain region dr overlapping the gate G and the drain region dr not overlapping the gate G have different hydrogen concentrations, wherein the hydrogen concentration of the drain region dr not overlapping the gate G is greater than the hydrogen concentration of the drain region dr overlapping the gate G.

[0076] Please refer to Figure 2E , an interlayer dielectric layer 140 is formed on the gate dielectric layer 130. The interlayer dielectric layer 140 covers the gate G.

[0077] Next, one or more etching processes are performed to form a first contact hole V1 and a second contact hole V2 passing through the interlayer dielectric layer 140 and the gate dielectric layer 130. The first contact hole V1 and the second contact hole V2 overlap and expose the drain region dr and the source region sr of the metal oxide layer OS.

[0078] Finally, please return to FIG. 1 to form a drain D and a source S on the interlayer dielectric layer 140, and to form the drain D and the source S in the first contact hole V1 and the second contact hole V2. The drain D and the source S are respectively connected to the drain region dr and the source region sr of the metal oxide layer OS. At this point, the semiconductor device 10A is substantially completed.

[0079] Based on the above, the silicon nitride layer 122 in the insulating pattern 120 can improve the problem of hydrogen elements in the metal oxide layer OS escaping during the heating process, and can even provide additional hydrogen elements to the metal oxide layer OS. Therefore, the silicon nitride layer 122 in the insulating pattern 120 can prevent the resistivity of the drain region dr of the metal oxide layer OS from increasing due to hydrogen element escaping, thereby improving the hot carrier effect near the drain D.

[0080] Figure 3A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 3B yes Figure 3A It must be noted that, Figure 3A and Figure 3B The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0081] Figure 3A and Figure 3B The semiconductor device 10B and Figure 1A and Figure 1B The main difference between the semiconductor device 10A and the semiconductor device 10B is that the silicon nitride layer 122 of the insulating pattern 120 of the semiconductor device 10B does not extend below the gate G.

[0082] Please refer to Figure 3A and Figure 3B In this embodiment, the silicon nitride layer 122 does not overlap the gate G in the normal direction ND. The drain region dr of the metal oxide layer OS does not extend below the gate G.

[0083] In the present embodiment, the sidewall sw of the insulating pattern 120 includes only the second oxide layer 124 , and the metal oxide layer OS does not directly contact the silicon nitride layer 122 .

[0084] In addition, in the present embodiment, the silicon nitride layer 122 and the second oxide layer 124 of the insulating pattern 120 have different shapes. The silicon nitride layer 122 and the second oxide layer 124 are defined by different photolithography and etching processes.

[0085] Based on the above, the silicon nitride layer 122 in the insulating pattern 120 can improve the problem of hydrogen elements in the metal oxide layer OS escaping during the heating process, and can even provide additional hydrogen elements to the metal oxide layer OS. Therefore, the silicon nitride layer 122 in the insulating pattern 120 can prevent the resistivity of the drain region dr of the metal oxide layer OS from increasing due to hydrogen element escaping, thereby improving the hot carrier effect near the drain D.

[0086] Figure 4A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 4B yes Figure 4A Schematic cross-sectional view of line a-a'.

[0087] Please refer to Figure 4A and Figure 4B , the semiconductor device 10C includes a substrate 100, a drain D, an insulating pattern 120, a metal oxide layer OS, a gate dielectric layer 130, a gate G and a source S, wherein the insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In this embodiment, the semiconductor device 10C further includes a heat dissipation structure HDF, an interlayer dielectric layer 140 and a connecting electrode T. For convenience of description, Figure 4A The heat dissipation structure HDF, the drain electrode D, the metal oxide layer OS, the gate electrode G, the source electrode S, and the connection electrode T are shown, and other components are omitted.

[0088] The heat dissipation structure HDF is located on the substrate 100. In this embodiment, the heat dissipation structure HDF is directly formed on the substrate 100, but the present invention is not limited thereto. In other embodiments, other buffer layers are sandwiched between the heat dissipation structure HDF and the substrate 100, such as silicon oxide, silicon nitride, silicon oxynitride or other insulating materials. In some embodiments, the heat dissipation structure HDF is a thermally conductive insulating material, such as aluminum nitride, aluminum oxide or other materials. In some embodiments, the thermal conductivity of the heat dissipation structure HDF is greater than 2W·m -1 ℃ -1 The thickness of the heat dissipation structure HDF can be adjusted according to actual needs.

[0089] The drain electrode D is located on the substrate 100. In the present embodiment, the drain electrode D is directly formed on the heat dissipation structure HDF. The heat dissipation structure HDF is located between the drain electrode D and the substrate 100 and is thermally connected to the drain electrode D. The area of ​​the drain electrode D vertically projected on the substrate 100 is smaller than the area of ​​the heat dissipation structure HDF vertically projected on the substrate 100.

[0090] The insulating pattern 120 is located on the drain D. The insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In some embodiments, the silicon nitride layer 122 contains hydrogen. In some embodiments, the thickness t2 of the silicon nitride layer 122 is 30 nanometers to 300 nanometers. The second oxide layer 124 is located on the silicon nitride layer 122, and the silicon nitride layer 122 is located between the second oxide layer 124 and the substrate 100. The second oxide layer 124 includes silicon oxide, silicon oxynitride, aluminum oxide or other insulating materials. In some embodiments, the thickness t3 of the second oxide layer 124 is 50 nanometers to 200 nanometers.

[0091] The insulating pattern 120 has a first contact hole V1 and a second contact hole V2. The sidewalls sw1a and sw1b of the first contact hole V1 include a silicon nitride layer 122 and a second oxide layer 124. The sidewall sw2 of the second contact hole V2 includes a second oxide layer 124. The drain D is located below the first contact hole V1 and the second contact hole V2 of the insulating pattern 120. In the present embodiment, the second oxide layer 124 of the insulating pattern 120 has an opening OP, and the second contact hole V2 passes through the silicon nitride layer 122 at the bottom of the opening OP. In some embodiments, the width of the opening OP is greater than the width of the second contact hole V2.

[0092] The metal oxide layer OS is located on the insulating pattern 120 and fills the first contact hole V1. The metal oxide layer OS contacts the upper surface ts2 of the insulating pattern 120, the sidewalls sw1a and sw1b of the first contact hole V1 of the insulating pattern 120, and the drain D. In the present embodiment, the metal oxide layer OS contacts the silicon nitride layer 122 and the oxide layer 124.

[0093] The metal oxide layer OS includes a source region sr, a channel region ch, a hydrogen concentration gradient region h, and a drain region dr connected in sequence. The channel region ch is connected between the hydrogen concentration gradient region h and the source region sr. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The source region sr, the hydrogen concentration gradient region h, and the drain region dr are doped to have a resistivity lower than that of the channel region ch. In the present embodiment, the resistivity of the drain D is lower than the resistivity of the source region sr and the drain region dr, the resistivity of the source region sr and the drain region dr is lower than the resistivity of the hydrogen concentration gradient region h, and the resistivity of the hydrogen concentration gradient region h is lower than the resistivity of the channel region ch.

[0094] The source region sr contacts the upper surface ts2 of the second oxide layer 124. The channel region ch contacts the upper surface ts2 and the second oxide layer 124 at the side wall sw1a. The hydrogen concentration gradient region h contacts the silicon nitride layer 122 at the side wall sw1a and the upper surface of the drain D. The drain region dr is electrically connected to the drain D and contacts the upper surface of the drain D, the silicon nitride layer 122 at the side wall sw1b, and the second oxide layer 124 at the side wall sw1b. In the present embodiment, there is a height difference HD between the bottom surface of the drain region dr and the bottom surface of the source region sr, and the height difference HD is, for example, approximately equal to the depth of the first contact hole V1. In the present embodiment, a portion of the channel region ch extends along the side wall sw1a of the first contact hole V1.

[0095] In some embodiments, hydrogen elements in the silicon nitride layer 122 may diffuse into the hydrogen concentration gradient region h. In some embodiments, the drain region dr and the source region sr have a hydrogen concentration greater than that of the hydrogen concentration gradient region h through hydrogen plasma treatment. In some embodiments, since a portion of the drain region dr contacts the silicon nitride layer 122 at the sidewall sw1b, the hydrogen concentration of the drain region dr is greater than that of the source region sr.

[0096] In some embodiments, the material of the metal oxide layer OS includes quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or an oxide composed of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W).

[0097] The gate dielectric layer 130 is located on the metal oxide layer OS. The gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials. In some embodiments, the thickness t4 of the gate dielectric layer 130 is 50 nanometers to 200 nanometers. Part of the gate dielectric layer 130 is filled in the first contact hole V1 and the opening OP.

[0098] The gate G is located on the gate dielectric layer 130. A portion of the insulating pattern 120 is located between the gate G and the substrate 100. The drain D extends between the gate G and the substrate 100. In the present embodiment, in the normal direction ND of the top surface of the substrate, a portion of the gate G overlaps the insulating pattern 120, and another portion of the gate G does not overlap the insulating pattern 120. In the present embodiment, a portion of the gate G overlaps the hydrogen concentration gradient region h, and another portion overlaps the channel region ch. In the present embodiment, a portion of the gate G is filled in the first contact hole V1.

[0099] The interlayer dielectric layer 140 is disposed on the gate dielectric layer 130. The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials. A portion of the interlayer dielectric layer 140 fills the first contact hole V1 and the opening OP.

[0100] The connection electrode T and the source electrode S are disposed on the interlayer dielectric layer 140. The connection electrode T and the source electrode S are electrically connected to the drain electrode D and the source region sr of the metal oxide layer OS respectively through the second contact hole V2 in the interlayer dielectric layer 140, the gate dielectric layer 130 and the insulating pattern 120 and the third contact hole V3 in the interlayer dielectric layer 140 and the gate dielectric layer 130. In the present embodiment, the sidewall sw2 of the second contact hole V2 includes the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride layer 122, and the sidewall of the third contact hole V3 includes the interlayer dielectric layer 140 and the gate dielectric layer 130.

[0101] Figures 5A to 10A yes Figure 4A and Figure 4B A top view of a method for manufacturing a semiconductor device 10C. Figures 5B to 10B They are FIG. 5A to FIG. 10A Schematic cross-sectional view of line a-a'.

[0102] Please refer to FIG. 5A to FIG. 6A as well as FIG. 5B to FIG. 6B , forming a heat dissipation structure HDF and a drain electrode D on the substrate 100. Forming an insulating pattern 120 including a first contact hole V1 on the drain electrode D. The drain electrode D is located below the first contact hole V1 and is exposed by the first contact hole V1.

[0103] The method of forming the insulating pattern 120 including the first contact hole V1 includes: forming a silicon nitride layer 122 blanketing on the drain electrode D; forming a second oxide layer 124 blanketing on the silicon nitride layer 122; then, performing a first patterning process on the silicon nitride layer 122 and the second oxide layer 124 to form a first contact hole V1 and an opening OP, wherein the first contact hole V1 passes through the silicon nitride layer 122 and the second oxide layer 124, and the opening OP passes through the second oxide layer 124 and does not pass through the silicon nitride layer 122. The first contact hole V1 exposes the drain electrode D, and the opening OP exposes the silicon nitride layer 122.

[0104] For example, the first patterning process includes: forming a patterned photoresist layer PR on the second oxide layer 124, wherein the patterned photoresist layer PR includes portions with different thicknesses; then, etching the silicon nitride layer 122 and the second oxide layer 124 using the patterned photoresist layer PR as a mask. The portion with a thinner thickness in the patterned photoresist layer PR corresponds to the position of the opening OP, and the opening of the patterned photoresist layer PR corresponds to the position of the first contact hole V1. In the present embodiment, the first patterning process includes, for example, a half-tone mask process.

[0105] Please refer to Fig. 7A and Figure 7B Then, a metal oxide layer OS' is formed on the silicon nitride layer 122 and the oxide layer 124, and the metal oxide layer OS' fills the first contact hole V1 and contacts the upper surface ts2 of the oxide layer 124, the sidewalls sw1a and sw1b of the first contact hole V1, and the drain D.

[0106] In some embodiments, the method of forming the metal oxide layer OS' includes: first, forming a semiconductor material layer (not shown) blanketing the silicon nitride layer 122, the oxide layer 124 and the drain electrode D; then, forming a patterned photoresist layer on the semiconductor material layer (not shown); then, etching the semiconductor material layer (not shown) using the patterned photoresist layer as a mask to form the metal oxide layer OS'; finally, removing the patterned photoresist layer. In this embodiment, since the drain electrode D at the opening OP is covered by the silicon nitride layer 122, when the semiconductor material layer (not shown) is formed, the semiconductor material layer (not shown) will not directly contact the drain electrode D through the opening OP, thereby preventing the drain electrode D below the opening OP from being damaged when etching the semiconductor material layer (not shown).

[0107] Please refer to Fig. 8A and Figure 8B A gate dielectric layer 130 is formed on the metal oxide layer OS′. A gate G is formed on the gate dielectric layer 130 .

[0108] Using the gate G as a mask, a doping process P is performed on the metal oxide layer OS' to form a source region sr, a drain region dr, a hydrogen concentration gradient region h, and a channel region ch in the metal oxide layer OS'. The channel region ch is connected between the source region sr and the hydrogen concentration gradient region h. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The hydrogen concentration gradient region h and the channel region ch overlap the gate G. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable processes.

[0109] In some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the metal oxide layer OS' / OS. However, since the source region sr and the drain region dr are directly doped with hydrogen elements by the doping process P, the hydrogen concentration of the source region sr and the drain region dr is greater than the hydrogen concentration of the hydrogen concentration gradient region h. Therefore, the resistivity of the source region sr and the drain region dr is lower than the resistivity of the hydrogen concentration gradient region h, and the resistivity of the hydrogen concentration gradient region h is lower than the resistivity of the channel region ch. The hot carrier effect generated by the electric field at the edge of the gate G can be reduced by setting the hydrogen concentration gradient region h.

[0110] Please refer to Fig.9A and Fig. 9B , an interlayer dielectric layer 140 is formed on the gate dielectric layer 130. The interlayer dielectric layer 140 covers the gate G. In some embodiments, the interlayer dielectric layer 140 also contains hydrogen elements. In some embodiments, the hydrogen elements in the interlayer dielectric layer 140 diffuse into the source region sr and the drain region dr of the metal oxide layer OS, further increasing the hydrogen concentration of the source region sr and the drain region dr, and reducing the resistivity of the source region sr and the drain region dr. In some embodiments, the material of the gate G includes aluminum, and aluminum can serve as a hydrogen element barrier layer to prevent the hydrogen elements in the interlayer dielectric layer 140 from diffusing into the channel region ch and the hydrogen concentration gradient region h.

[0111] Please refer to Fig. 10A and Fig. 10B A second patterning process is performed on the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride material layer 122 to form a second contact hole V2 passing through the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride material layer 122 at the position of the opening OP, and at the same time, a third contact hole V3 passing through the interlayer dielectric layer 140 and the gate dielectric layer 130 is formed on the source region sr of the metal oxide layer OS.

[0112] Finally, please return Figure 4A and Figure 4B , forming a connection electrode T and a source electrode S on the interlayer dielectric layer 140, and forming the connection electrode T and the source electrode S in the second contact hole V2 and the third contact hole V3. The connection electrode T and the source electrode S are connected to the drain electrode D and the source region sr of the metal oxide layer OS, respectively. At this point, the semiconductor device 10C is substantially completed.

[0113] Fig.11A is a top view of a display device according to an embodiment of the present invention, wherein Fig.11A The substrate 100 and the heat dissipation structure DHF of the display device are shown, and other components are omitted. Fig. 11B yes Fig.11A A partial enlarged schematic diagram of .

[0114] Please refer to Fig.11A The display device includes a display area AA and a peripheral area BA. The heat dissipation structure DHF is located in the display area AA. In this embodiment, the heat dissipation structure DHF is mesh-shaped. Compared with the heat dissipation structure DHF of the entire surface, the mesh-shaped heat dissipation structure DHF has a better heat dissipation technical effect and can improve the problem that the stress of the heat dissipation structure DHF causes the substrate 100 to crack.

[0115] Please refer to Fig. 11B The display device includes a plurality of semiconductor devices 10C in an array. For a description of the semiconductor device 10C, reference may be made to Figure 4A and Figure 4B The relevant paragraphs of 10C are not repeated here. In the present embodiment, the drains D of the plurality of semiconductor devices 10C are electrically connected to each other through the multi-connection electrode T. The sources S of the plurality of semiconductor devices 10C are electrically connected to each other. The gates G of the plurality of semiconductor devices 10C are electrically connected to each other. By connecting the plurality of semiconductor devices 10C in parallel, the driving current of each semiconductor device 10C can be reduced, thereby increasing the reliability of the semiconductor device 10C.

[0116] In this embodiment, drains D of a plurality of semiconductor devices 10C are connected to the same mesh-shaped heat dissipation structure DHF. The semiconductor device 10C is electrically connected to an organic light emitting diode, a micro light emitting diode or other light emitting elements, for example.

Claims

1. A semiconductor device comprising: a substrate; a first oxide layer located on the substrate; an insulating pattern, located on the first oxide layer, and comprising: a silicon nitride layer; and a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; a metal oxide layer contacting an upper surface of the first oxide layer, a sidewall of the insulating pattern, and an upper surface of the insulating pattern; a gate dielectric layer located on the metal oxide layer; a gate disposed on the gate dielectric layer, wherein a portion of the insulating pattern is disposed between the gate and the substrate; and a source electrode and a drain electrode, electrically connected to the metal oxide layer, The metal oxide layer includes a source region, a drain region and a channel region located between the source region and the drain region, wherein the distance between the source region and the substrate is smaller than the distance between the drain region and the substrate, and the hydrogen concentration of the drain region is greater than the hydrogen concentration of the source region. 2 . The semiconductor device as claimed in claim 1 , wherein an oxygen concentration of the first oxide layer is greater than an oxygen concentration of the second oxide layer. The semiconductor device as claimed in claim 1 , wherein the silicon nitride layer contains hydrogen. The semiconductor device as claimed in claim 1 , wherein the drain overlaps the insulating pattern.

5. A method for manufacturing a semiconductor device, comprising: forming a first oxide layer on a substrate; An insulating pattern is formed on the first oxide layer, and the insulating pattern includes: a silicon nitride layer; and a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; forming a metal oxide layer on the upper surface of the first oxide layer, the sidewalls of the insulating pattern and the upper surface of the insulating pattern; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer, wherein a portion of the insulating pattern is located between the gate and the substrate; and forming a source electrode and a drain electrode electrically connected to the metal oxide layer, The hydrogen concentration in the drain region is greater than the hydrogen concentration in the source region.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising: Using the gate as a mask, a doping process is performed on the metal oxide layer to form the source region, the drain region and a channel region between the source region and the drain region in the metal oxide layer. 7 . The method for manufacturing a semiconductor device as claimed in claim 5 , further comprising performing an annealing process to diffuse oxygen in the first oxide layer into the metal oxide layer.

8. A semiconductor device comprising: a substrate; a drain electrode located on the substrate; an insulating pattern located on the drain electrode, and the drain electrode is located below a first contact hole of the insulating pattern; a metal oxide layer located on the insulating pattern and filled in the first contact hole, wherein the metal oxide layer contacts the upper surface of the insulating pattern, the sidewall of the first contact hole of the insulating pattern, and the drain; a gate dielectric layer located on the metal oxide layer; a gate, located on the gate dielectric layer; as well as a source electrode electrically connected to the metal oxide layer, The insulating pattern comprises: an oxide layer; and a silicon nitride layer located between the oxide layer and the substrate, wherein the sidewall of the first contact hole includes the silicon nitride layer and the oxide layer, and the metal oxide layer contacts the silicon nitride layer and the oxide layer, Wherein the metal oxide layer comprises: a source region electrically connected to the source; a drain region electrically connected to the drain; a channel region overlapping the gate and connected to the source region; and a hydrogen concentration gradient region, overlapping the gate and connected between the channel region and the drain region, wherein the hydrogen concentration gradient region contacts the silicon nitride layer, and the channel region contacts the oxide layer, The hydrogen concentration of the drain region is greater than the hydrogen concentration of the source region. 9 . The semiconductor device as claimed in claim 8 , wherein a portion of the insulating pattern is located between the gate and the substrate. 10 . The semiconductor device as claimed in claim 8 , wherein a hydrogen concentration in the hydrogen concentration gradient region is lower than a hydrogen concentration in the drain region. The semiconductor device as claimed in claim 8 , wherein the drain extends between the gate and the substrate.

12. The semiconductor device according to claim 8, further comprising: A connecting electrode, wherein the drain is located below a second contact hole of the insulating pattern, and the connecting electrode fills the second contact hole to electrically connect the drain.

13. The semiconductor device according to claim 8, further comprising: A heat dissipation structure is located between the drain and the substrate and is thermally connected to the drain.

14. A method for manufacturing a semiconductor device, comprising: forming a drain electrode on a substrate; forming a silicon nitride layer blanketing the drain electrode; forming an oxide layer blanketing the silicon nitride layer; Performing a first patterning process on the silicon nitride layer and the oxide layer to form a first contact hole and an opening, wherein the first contact hole passes through the oxide layer and the silicon nitride layer, and the opening passes through the oxide layer but does not pass through the silicon nitride layer; Forming a metal oxide layer on the silicon nitride layer and the oxide layer, wherein the metal oxide layer fills the first contact hole and contacts the upper surface of the oxide layer, the sidewall of the first contact hole and the drain; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer; as well as forming a source electrode electrically connected to the metal oxide layer, Using the gate as a mask, a doping process is performed on the metal oxide layer to form a source region, a drain region, a hydrogen concentration gradient region and a channel region in the metal oxide layer, wherein the channel region is connected between the source region and the hydrogen concentration gradient region, and the hydrogen concentration gradient region is connected between the channel region and the drain region, wherein the hydrogen concentration gradient region and the channel region overlap the gate, and wherein the hydrogen concentration of the drain region is greater than the hydrogen concentration of the source region.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: Performing a second patterning process on the silicon nitride layer to form a second contact hole passing through the silicon nitride layer at the position of the opening; as well as A connecting electrode is formed in the second contact hole to connect the drain.

16. The method for manufacturing a semiconductor device according to claim 14, further comprising: The hydrogen concentration of the hydrogen concentration gradient region is lower than the hydrogen concentration of the drain region.

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