A high-precision clock generation circuit with temperature compensation

Abstract

A high-precision, low-power over-temperature protection circuit includes a startup circuit, a PTAT (Proportional To Absolute Temperature) current source module, and a CTAT (Complementary To Absolute Temperature) current source module. The invention includes a current source module for temperature protection and an over-temperature protection core circuit. The startup circuit comprises a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2. The PATA current source module comprises a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a first resistor R1. The CTAT current source module comprises a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a second resistor R2. The over-temperature protection core circuit comprises a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a comparator COMP, a first inverter U1, and a second inverter U2. This invention achieves over-temperature protection by acquiring a temperature-independent voltage VREF and comparing it with a temperature-dependent voltage using a comparator.

Description

Technical Field

[0001] This invention relates to a clock generation circuit, and in particular to a high-precision clock generation circuit with temperature compensation. Clocks are a particularly important component in any hybrid analog-electronic circuit field. Background Technology

[0002] Currently, there are two common methods for generating clock signals: one is to use external crystal oscillators, ceramic oscillators, etc., which can output a constant frequency, but inevitably increase the area and cost of the entire system; the other is on-chip integrated oscillators, which can be further divided into hysteresis oscillators, LC oscillators and ring oscillators according to their structure. However, on-chip integrated oscillators have the problem of unstable output frequency due to external factors such as temperature. Summary of the Invention

[0003] To address the shortcomings of the aforementioned clock signal generation methods, this invention provides a clock generation circuit based on the principle of a ring oscillator. Compared to other on-chip integrated oscillators, the ring oscillator has the advantages of low power consumption and simple structure. It generates a temperature-self-calibrating compensation voltage by cascading a reference current source and a super-source follower, thereby solving the problem of its susceptibility to fluctuations in process parameters, temperature, and power supply, and thus controlling the ring oscillator to generate a stable oscillation frequency.

[0004] A high-precision clock generation circuit with temperature compensation is used to generate a stable clock signal. The clock generation circuit includes a temperature calibration module, which comprises a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, and a tenth PMOS transistor PM10. 10 Fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM 10 The first transistor Q1, the second transistor Q2, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the first capacitor C. M The gates of the second, fourth, sixth, seventh, and ninth PMOS transistors are connected, and their sources are connected to the power supply V. DDThe drains of the second and fourth PMOS transistors are connected to the sources of the third and fifth PMOS transistors, respectively. The gates of the third and fifth PMOS transistors are connected. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor through a first resistor. The gate of the fourth NMOS transistor is connected to the gate of the sixth NMOS transistor and then to the drain of the third PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the seventh NMOS transistor and then to the drain of the fourth NMOS transistor and connected to the output of the startup circuit. The source of the fifth NMOS transistor is connected to the emitter of the first transistor through a second resistor. The base and collector of the first transistor are grounded. The drain of the fifth PMOS transistor is connected to the gate of the second PMOS transistor and then to the drain of the sixth NMOS transistor through a third resistor. The drain of the sixth NMOS transistor is connected to the gate of the third PMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the emitter of the second transistor. The base and collector of the second transistor are grounded. The drain of the sixth PMOS transistor is connected to the gate and drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the eighth PMOS transistor is grounded through the fourth resistor. The drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor. The gate of the tenth PMOS transistor is connected to the drain of the eighth PMOS transistor. The drain of the tenth PMOS transistor is connected to both the drain of the ninth NMOS transistor and the gate of the tenth NMOS transistor. The gate of the ninth NMOS transistor is connected to the gate of the eighth NMOS transistor. The source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the tenth NMOS transistor is grounded. The first capacitor C... M One end is connected to the drain of the tenth NMOS transistor, and the other end is connected to the gate of the tenth NMOS transistor. The drain voltage of the tenth NMOS transistor serves as the output voltage V of the temperature calibration module. CTRL This provides the power supply voltage for the ring oscillator.

[0005] Specifically, the startup circuit includes a first PMOS transistor PM1, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, wherein the source of the first PMOS transistor is connected to the power supply V. DD The gate and drain of the first PMOS transistor are connected together and then connected to the gate and drain of the third NMOS transistor. The gate and drain of the first NMOS transistor are also connected together. The source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to the power supply V. DD The source of the third NMOS transistor serves as the output terminal of the startup circuit.

[0006] Specifically, the ring oscillator includes a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, and a fifth inverter U5. The output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, the output of the third inverter is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the first inverter. Simultaneously, the output of the fifth inverter also serves as the output f of the ring oscillator. CLK。

[0007] The beneficial effects of this invention are: without the need for a cumbersome compensation unit, the instability of the ring oscillator caused by external factors can be compensated by the temperature calibration module alone, thereby obtaining a high-precision oscillation frequency.

[0008] Figure 1 This is a circuit diagram of a high-precision clock generation circuit with temperature compensation according to the present invention. Detailed Implementation

[0009] This invention proposes a high-precision clock generation circuit with temperature compensation, comprising a startup circuit, a temperature calibration module, and a ring oscillator. The startup circuit, used to start the temperature calibration module, includes a first PMOS transistor PM1, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3. The source of the first PMOS transistor is connected to a power supply V. DD The gate and drain of the first PMOS transistor are connected together and then connected to the gate and drain of the third NMOS transistor. The gate and drain of the first NMOS transistor are also connected together. The source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to the power supply V. DD The source of the third NMOS transistor serves as the output terminal of the startup circuit.

[0010] This invention generates a temperature-correlated output voltage through a temperature calibration module, which serves as the power supply voltage for a ring oscillator. The oscillator comprises a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, and a tenth PMOS transistor PM10. 10 Fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM 10The first transistor Q1, the second transistor Q2, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the first capacitor C. M The gates of the second, fourth, sixth, seventh, and ninth PMOS transistors are connected, and their sources are connected to the power supply V. DD The drains of the second and fourth PMOS transistors are connected to the sources of the third and fifth PMOS transistors, respectively. The gates of the third and fifth PMOS transistors are connected. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor through a first resistor. The gate of the fourth NMOS transistor is connected to the gate of the sixth NMOS transistor and then to the drain of the third PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the seventh NMOS transistor and then to the drain of the fourth NMOS transistor and connected to the output of the startup circuit. The source of the fifth NMOS transistor is connected to the emitter of the first NMOS transistor through a second resistor. The base and collector of the first NMOS transistor are grounded. The drain of the fifth PMOS transistor is connected to the gate of the second PMOS transistor and then to the drain of the sixth NMOS transistor through a third resistor. The drain of the sixth NMOS transistor is connected to the gate of the third PMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the emitter of the second transistor. The base and collector of the second transistor are grounded. The drain of the sixth PMOS transistor is connected to the gate and drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the eighth PMOS transistor is grounded through the fourth resistor. The drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor. The gate of the tenth PMOS transistor is connected to the drain of the eighth PMOS transistor. The drain of the tenth PMOS transistor is connected to both the drain of the ninth NMOS transistor and the gate of the tenth NMOS transistor. The gate of the ninth NMOS transistor is connected to the gate of the eighth NMOS transistor. The source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the tenth NMOS transistor is grounded. The first capacitor C... M One end is connected to the drain of the tenth NMOS transistor, and the other end is connected to the gate of the tenth NMOS transistor. The drain voltage of the tenth NMOS transistor serves as the output voltage V of the temperature calibration module. CTRL This provides the power supply voltage for the ring oscillator.

[0011] This invention obtains the oscillation frequency of a clock generation circuit using a ring oscillator, comprising a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, and a fifth inverter U5. The output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, the output of the third inverter is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the first inverter. Simultaneously, the output of the fifth inverter also serves as the output frequency (f) of the ring oscillator. CLK .

[0012] In the temperature calibration module of this circuit, PM2, PM3, PM4, PM5, NM4, NM5, NM6, NM7, R1, and R3 constitute a self-biased low-voltage common-source cascode current source. By adding two resistors, R1 and R3, the power supply voltage required for the overall MOSFET to operate in the active region is reduced to a lower level, thus reducing power consumption. When affected by temperature, a current change of ∆I is generated in resistor R2, which is positively correlated with temperature. This change is copied to resistor R4 through a current mirror, so the voltage V generated in resistor R4 can be obtained. R4 It is a voltage that is positively correlated with temperature, and PM 10 and NM 10 The super-source follower is composed of V as input. R4 The output is V CTRL Its function is through NM 10 The negative feedback is used to reduce the output resistance of the source follower, enabling the temperature calibration module to have greater driving capability for subsequent stages. Due to the presence of negative feedback, a Miller compensation capacitor C is added. M To improve the stability of the loop.

[0013] It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0014] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This description is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other ways that can be understood by those skilled in the art.

Claims

1. A high-precision clock generation circuit with temperature compensation, the clock generation circuit including a temperature calibration module, characterized in that, The temperature calibration module includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, and a tenth PMOS transistor PM10. 10 Fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM 10 The first transistor Q1, the second transistor Q2, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the first capacitor C. M The gates of the second, fourth, sixth, seventh, and ninth PMOS transistors are connected, and their sources are connected to the power supply V. DD The drains of the second and fourth PMOS transistors are connected to the sources of the third and fifth PMOS transistors, respectively. The gates of the third and fifth PMOS transistors are connected. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor through a first resistor. The gate of the fourth NMOS transistor is connected to the gate of the sixth NMOS transistor and then to the drain of the third PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the seventh NMOS transistor and then to the drain of the fourth NMOS transistor, and is also connected to the output of the startup circuit. The source of the fifth NMOS transistor is connected to the emitter of the first transistor through a second resistor. The base and collector of the first transistor are grounded. The drain of the fifth PMOS transistor is connected to the gate of the second PMOS transistor and then to the drain of the sixth NMOS transistor through a third resistor. The drain of the sixth NMOS transistor is connected to the gate of the third PMOS transistor. The source of the OS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the emitter of the second transistor. The base and collector of the second transistor are grounded. The drain of the sixth PMOS transistor is connected to the gate and drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the eighth PMOS transistor is grounded through the fourth resistor. The drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor. The gate of the tenth PMOS transistor is connected to the drain of the eighth PMOS transistor. The drain of the tenth PMOS transistor is connected to both the drain of the ninth NMOS transistor and the gate of the tenth NMOS transistor. The gate of the ninth NMOS transistor is connected to the gate of the eighth NMOS transistor. The source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the tenth NMOS transistor is grounded. The first capacitor C... M One end is connected to the drain of the tenth NMOS transistor, and the other end is connected to the gate of the tenth NMOS transistor. The drain voltage of the tenth NMOS transistor serves as the output voltage V of the temperature calibration module. CTRL This provides the power supply voltage for the ring oscillator.

2. The high-precision clock generation circuit with temperature compensation according to claim 1, characterized in that, The startup circuit includes a first PMOS transistor PM1, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, wherein the source of the first PMOS transistor is connected to the power supply V. DD The gate and drain of the first PMOS transistor are connected together and then connected to the gate and drain of the third NMOS transistor. The gate and drain of the first NMOS transistor are also connected together. The source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is connected to the power supply V. DD The source of the third NMOS transistor serves as the output terminal of the startup circuit.

3. The high-precision clock generation circuit with temperature compensation according to claim 1, characterized in that, The ring oscillator includes a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, and a fifth inverter U5. The output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, the output of the third inverter is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the first inverter. The output of the fifth inverter also serves as the output f of the ring oscillator. CLK .

Images