A dynamic comparator and chip

Abstract

The embodiment of the present application provides a dynamic comparator and a chip, the dynamic comparator comprises: a pre-amplification stage, which is used for amplifying an input differential signal to obtain an amplified signal; a latch stage, which is connected with an output end of the pre-amplification stage and is used for latching the amplified signal to obtain a decision result; and a traction circuit, which is connected with the output end of the pre-amplification stage, and at least comprises a first capacitor, a second capacitor and a reverse clock, the reverse clock is arranged between the first capacitor and the second capacitor; when the reverse clock is at a rising edge, the charges of the first capacitor and the second capacitor remain unchanged, and the output end of the pre-amplification stage generates a pressure difference, so that the latch stage is opened. The dynamic comparator introduces the traction circuit, accelerates the speed of the pre-amplification stage, and improves the decision speed of the comparator.

Description

Technical Field

[0001] This invention relates to the field of circuits and chips, and more specifically to a dynamic comparator and chip. Background Technology

[0002] In recent years, with the development of 5G communication technology, the importance of basic communication chips has become increasingly prominent. Comparators, as an indispensable core module in communication chips, are widely used in analog-to-digital converters (ADCs), serial-to-parallel converters (SERDES), and power management chips. As a core module in ADCs, the comparator consumes the most processing time in the quantization stage after sampling, making its data processing speed a major factor affecting communication development.

[0003] To improve speed, most analog-to-digital converters (ADCs) employ dynamic comparators, where a single comparison consists of a reset phase and a comparison phase. During the reset phase, the comparator adjusts to its initial state. When the comparison phase arrives, the comparator quickly pre-amplifies the input differential signal, providing information to the positive feedback loop of the comparator's latch stage, thus obtaining the correct decision result. However, existing comparators are not fast enough, slowing down the entire ADC system and even producing incorrect decisions, severely limiting the overall system performance. Summary of the Invention

[0004] The purpose of this invention is to provide a dynamic comparator and chip, which introduces a traction capacitor to accelerate the pre-amplification stage and improve the comparator's decision speed.

[0005] This invention provides a dynamic comparator, characterized by comprising: a pre-amplification stage for amplifying an input differential signal to obtain an amplified signal; a latching stage connected to the output of the pre-amplification stage for latching the amplified signal to obtain a decision result; and a traction circuit connected to the output of the pre-amplification stage, the traction circuit including at least a first capacitor, a second capacitor, and an inverting clock, the inverting clock being located between the first capacitor and the second capacitor; when the inverting clock is at its rising edge, the charges of both the first capacitor and the second capacitor remain unchanged, a voltage difference is generated at the output of the pre-amplification stage, causing the latching stage to open.

[0006] Optionally, the pre-amplification stage has two output terminals, and the two ends of the traction circuit are respectively connected to the two output terminals of the pre-amplification stage.

[0007] Optionally, the latch stage includes a positive feedback loop for positive feedback of the amplified signal; the output of the pre-amplification stage is connected to the input of the positive feedback loop.

[0008] Optionally, when the clock of the dynamic comparator is at the falling edge, the inverted clock is at the rising edge; when the inverted clock is at the rising edge, the charges of the first capacitor and the second capacitor remain unchanged, and a voltage difference is generated at the output of the pre-amplification stage, which turns on the positive feedback loop of the latch stage.

[0009] Optionally, the traction strength of the traction circuit is inversely proportional to the capacitance values ​​of the first capacitor and the second capacitor.

[0010] Optionally, the reverse clock signal is the inverted clock signal of the dynamic comparator.

[0011] Optionally, both the first capacitor and the second capacitor are passive capacitors.

[0012] Optionally, the pre-amplification stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the drains of the first PMOS transistor and the first NMOS transistor are both connected to an inverting clock, and the gates of the first PMOS transistor and the first NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first PMOS transistor and the second PMOS transistor are both connected to the positive terminal of the power supply; the sources of the third PMOS transistor, the fourth PMOS transistor, and the drain of the second PMOS transistor are connected; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor; the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to the negative terminal of the power supply; and the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator.

[0013] Optionally, one end of the traction circuit is located between the drain of the third PMOS transistor and the drain of the second NMOS transistor; the other end of the traction circuit is located between the drain of the fourth PMOS transistor and the drain of the third NMOS transistor.

[0014] The present invention also provides a chip, characterized in that the chip includes at least the dynamic comparator described above.

[0015] The dynamic comparator of this invention includes: a pre-amplification stage for amplifying an input differential signal to obtain an amplified signal; a latching stage connected to the output of the pre-amplification stage for latching the amplified signal to obtain a decision result; and a traction circuit connected to the output of the pre-amplification stage. The traction circuit includes at least a first capacitor, a second capacitor, and an inverting clock, with the inverting clock positioned between the first and second capacitors. When the inverting clock is at its rising edge, the charges of both the first and second capacitors remain unchanged, generating a voltage difference at the output of the pre-amplification stage, thus enabling the latching stage. This invention, by introducing a traction circuit, accelerates the pre-amplification stage and saves the charging time of the MOS capacitors during the pre-amplification phase, thereby speeding up the pre-amplification process.

[0016] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 It is a classic two-stage dynamic comparator in existing technology;

[0019] Figure 2 This describes the working process of a dynamic comparator.

[0020] Figure 3 This is a schematic diagram of a dynamic comparator according to the present invention;

[0021] Figure 4 This is a timing diagram showing the operation of the comparator in this invention and the prior art. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0023] Currently, commonly used dynamic comparator structures employ a two-stage structure. The first stage is a pre-amplification stage, which initially amplifies the input differential signal. The second stage is a latching stage, which processes the pre-amplified differential signal through a positive feedback loop to obtain the final decision result.

[0024] Based on the comparator's operating state, it can be divided into a reset phase and a comparison phase. Figure 1 It is a classic two-stage dynamic comparator in existing technology, such as Figure 1As shown, clk is the comparator's clock signal, and clkb is the inverted version of the comparator's clock signal. When clk is high, MP2 (the second PMOS transistor) is off, MN2 (the second NMOS transistor) and MN3 (the third NMOS transistor) are on, Din and Dip are pulled to ground (Din and Dip are the two outputs of the preamplifier stage), MN4 (the fourth NMOS transistor) and MN5 (the fifth NMOS transistor) are off, and at the same time clkb is low, MP5 (the fifth PMOS transistor) and MP8 (the eighth PMOS transistor) are on. Op and On outputs are both high. This stage is the reset stage.

[0025] After the reset phase ends, when clk is at the falling edge, MP2 (the second PMOS transistor) will only start to conduct after the clk voltage drops by a threshold voltage. Current will flow from MP3 (the third PMOS transistor) and MP4 (the fourth PMOS transistor) to MN2 (the second NMOS transistor) and MN3 (the third NMOS transistor). Because MN2 and MN3 are in the conducting state, Din and Dip will remain at zero level until the clk voltage is lower than the threshold voltage of MN2 and MN3, at which point MN2 and MN3 will turn off.

[0026] At this point, MN2 and MN3 are equivalent to two capacitors, and the charge begins to accumulate gradually. The voltage at points Din and Dip gradually increases. However, due to the voltage difference between Vinp and Vinn, the conduction degree of MP3 and MP4 is different, and the voltage at Dip and Din will also be different.

[0027] When the Vinp voltage is higher than the Vinn voltage, the conduction level of MP4 is greater than that of MP3. When MN2 and MN3 are disconnected, the charge accumulated in MN3 will be greater than that in MN2, so the voltage at Dip point is greater than that at Din point. For the second stage, when the Dip voltage is greater than the Din voltage, the conduction level of MN5 is greater than that of MN4, and the discharge rate of MN5 will be greater than that of MN4, causing the voltage at Op point to be greater than that at On point. At this time, the positive feedback loop starts to work, the gate voltage of MN8 is greater than that of MN7, MN8 will quickly conduct, accelerating the discharge, and the voltage at On point will become lower and lower, while MP6 will gradually conduct and MP7 will gradually turn off. The voltage at Op point will continuously rise to VDD, and the voltage at On point will drop to VSS, thus obtaining the final decision result.

[0028] Similarly, when the Vinn voltage is higher than the Vinp voltage, the conduction degree of MP3 is greater than that of MP4. When MN2 and MN3 are disconnected, the charge accumulated in MN2 will be greater than that in MN3, so the voltage at point Din is greater than that at point Dip. For the second stage, when the Din voltage is greater than the Dip voltage, the conduction degree of MN4 is greater than that of MN5, and the discharge rate of MN4 will be greater than that of MN5, causing the voltage at point On to be greater than that at point Op. At this time, the positive feedback loop starts to work, the gate voltage of MN7 is greater than that of MN8, MN7 will quickly turn on, accelerating the discharge, and the voltage at point Op will become lower and lower, while MP7 will gradually turn on and MP6 will gradually turn off. The voltage at point On will continuously rise to VDD, and the voltage at point Op will drop to VSS, thus obtaining the final decision result.

[0029] Figure 2 This describes the working process of a dynamic comparator, such as... Figure 2 As shown, t1 is the reset stage of the comparator, t2 is the working time of the first stage (preamplification stage), and t3 is the working time of the second stage (latch stage). The total working time of the comparator is mainly determined by t2+t3, which is also the stage that occupies the most time.

[0030] The inventors discovered through research that in the conventional operation of a comparator, the second-stage latch stage only starts operating after the first-stage preamplifier stage has been operating for a certain period of time. Figure 1 As shown, the charge in MN2 and MN3 can only begin to accumulate after CLK drops below the threshold voltage of an NMOS transistor. Then, the second-stage latch can only detect the difference and begin positive feedback once a certain voltage difference appears between Din and Dip points. The time from CLK dropping below the threshold voltage of an NMOS transistor, and the charge accumulation process in MN2 and MN3, constitutes almost the entire comparator phase. This is one of the main factors limiting the comparator's speed.

[0031] Based on the above research, this invention proposes a dynamic comparator, comprising: a pre-amplification stage for amplifying an input differential signal to obtain an amplified signal, wherein the differential signal is a pair of signals with the same amplitude but opposite phase, which can suppress common-mode noise and improve the signal-to-noise ratio of the system. The pre-amplification stage has two output terminals, and the two ends of the traction circuit are respectively connected to the two output terminals of the pre-amplification stage. The dynamic comparator further comprises a latching stage, which is connected to the output terminal of the pre-amplification stage and is used to latch the amplified signal to obtain a decision result. The latching stage has a positive feedback loop for positive feedback of the signal. The dynamic comparator further comprises a traction circuit, which is connected to the output terminal of the pre-amplification stage. The traction circuit includes at least a first capacitor, a second capacitor, and an inverting clock. The first capacitor and the second capacitor are both passive capacitors. The traction circuit in the dynamic comparator can be one or more sets. The traction circuit is used to speed up the pre-amplification stage and save the charging time of the MOS capacitor in the pre-amplification stage.

[0032] Preferably, the reverse clock is located between the first capacitor and the second capacitor, and the signal of the reverse clock is the inverted clock signal of the dynamic comparator. When the reverse clock is at the rising edge (i.e., when the clock of the dynamic comparator is at the falling edge), at that instant, the charge of the first capacitor and the second capacitor remains unchanged. Since the charge cannot be transferred instantaneously, the charge of the capacitor does not have time to change at the instant the clock signal changes, and a voltage difference is generated at the output of the pre-amplification stage, which turns on the latch stage.

[0033] Figure 3 This is a schematic diagram of a dynamic comparator according to the present invention, comprising: a pre-amplification stage for amplifying an input differential signal to obtain an amplified signal; a latching stage connected to the output of the pre-amplification stage for latching the amplified signal to obtain a decision result; and a traction circuit connected to the output of the pre-amplification stage, the traction circuit including at least a first capacitor, a second capacitor, and an inverting clock, the inverting clock being positioned between the first capacitor and the second capacitor; when the inverting clock is at its rising edge, the charges of both the first capacitor and the second capacitor remain unchanged, a voltage difference is generated at the output of the pre-amplification stage, causing the latching stage to open. Figure 3 As shown, the left side of the dynamic comparator is a pre-amplification stage, used to amplify the input differential signal to obtain an amplified signal. Vinp and Vinn are the input terminals of the pre-amplification stage, where the input signal is the differential signal. Din and Dip are the output terminals of the pre-amplification stage, where the output signal is the amplified differential signal. The pre-amplification stage amplifies the differential signal, making the difference between the differential signals greater.

[0034] like Figure 3 As shown, the pre-amplification stage includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a third NMOS transistor (MN3). The drains of the first PMOS transistor and the first NMOS transistor are both connected to the reverse clock; the gates of the first PMOS transistor and the first NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first PMOS transistor and the second PMOS transistor are both connected to the positive terminal of the power supply; the sources of the third PMOS transistor, the fourth PMOS transistor, and the drain of the second PMOS transistor are connected; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor; the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to the negative terminal of the power supply; the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator.

[0035] The right side of the dynamic comparator is a latch stage, which is connected to the output of the pre-amplification stage and is used to latch the amplified signal to obtain the decision result. Figure 3 As shown, the output terminals Din and Dip of the pre-amplification stage of the dynamic comparator are connected to the input terminal of the latch stage. The latch stage includes a positive feedback loop for positive feedback of the amplified signal. The output terminals of the latch stage are Op and On.

[0036] like Figure 3As shown, the latch stage includes a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7), an eighth PMOS transistor (MP8), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), and a ninth NMOS transistor (MN9). The sources of the fifth, sixth, seventh, and eighth PMOS transistors are all connected to the positive terminal of the power supply. The drains of the fifth and sixth PMOS transistors are connected to the gate of the seventh PMOS transistor, serving as the output terminal Op of the latch stage. The gate of the sixth PMOS transistor, the drain of the seventh PMOS transistor, and the drain of the eighth PMOS transistor are connected, serving as the output terminal On of the latch stage. The gate of the fourth NMOS transistor is the input terminal Din of the latch stage. The source of the fourth NMOS transistor is connected to the drain of the sixth and seventh NMOS transistors. The drain of the fifth NMOS transistor and the gate of the seventh NMOS transistor are connected to the output terminal Op of the latch stage; the drain of the fifth NMOS transistor and the gate of the seventh NMOS transistor are connected to the output terminal On of the latch stage; the sources of the sixth, seventh, eighth, and ninth NMOS transistors are all connected to the negative terminal of the power supply; the gate of the eighth NMOS transistor is connected to the inverted clock of the dynamic comparator, and the gate of the ninth NMOS transistor is connected to the clock of the dynamic comparator; the gate of the fourth NMOS transistor is one input terminal Din of the latch stage, and the gate of the fifth NMOS transistor is the other input terminal Dip of the latch stage.

[0037] In another specific implementation, the PMOS transistors in the pre-amplification stage and the latching stage can be interchanged with the NMOS transistors. If they are interchanged, the entire circuit needs to be interchanged. For example, the pre-amplification stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor. The drains of the first NMOS transistor and the first PMOS transistor are both connected to the reverse clock; the gates of the first NMOS transistor and the first PMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first NMOS transistor and the second NMOS transistor are both connected to the positive terminal of the power supply; the sources of the third NMOS transistor, the fourth NMOS transistor, and the drain of the second NMOS transistor are connected; the drain of the third NMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the fourth NMOS transistor is connected to the drain of the third PMOS transistor; the gates of the second PMOS transistor and the third PMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the negative terminal of the power supply; the gates of the second PMOS transistor and the third PMOS transistor are both connected to the clock of the dynamic comparator. The corresponding MOS transistors in the latch stage are also replaced accordingly.

[0038] In this application, the dynamic comparator is preferably connected to a MOS transistor, and the MOS transistor can also be replaced by a bipolar transistor.

[0039] This invention adds a traction circuit to the two-stage dynamic comparator, the traction circuit being connected to the output of the pre-amplification stage, as shown below. Figure 3 As shown, one end of the traction circuit is located between the drain of the third PMOS transistor and the drain of the second NMOS transistor; the other end of the traction circuit is located between the drain of the fourth PMOS transistor and the drain of the third NMOS transistor, i.e. Figure 3 The pre-amplification stage has two output terminals, Din and Dip. The input signal of the pre-amplification circuit is a differential signal, the value range of which is 0 to VDD, where VDD is the input voltage of the dynamic comparator. The pre-amplification stage has two output terminals (Din and Dip are the two output terminals of the pre-amplification stage), and the two ends of the traction circuit are respectively connected to the two output terminals of the pre-amplification stage. The traction circuit includes at least a first capacitor, a second capacitor, and an inverting clock. The inverting clock signal is obtained by inverting the clock signal of the dynamic comparator. The clock of the dynamic comparator is a drive signal, and inverting the drive signal yields the inverting clock signal. Figure 3As shown, this invention adds two capacitors, C1 and C2, at positions Din and Dip, with a clock clkb (i.e., the inverted clock) added between them. clkb is the inverted version of clock clk. Din and Dip are the two output terminals of the pre-amplification stage. The first capacitor C1 and the second capacitor C2 are both passive capacitors, which avoids the influence of the power supply current from using active capacitors.

[0040] The dynamic comparator first performs a reset operation. When clk is high, MP2 (the second PMOS transistor) is off, MN2 (the second NMOS transistor) and MN3 (the third NMOS transistor) are on, Din and Dip are pulled to ground (Din and Dip are the two output terminals of the pre-amplifier stage), MN4 (the fourth NMOS transistor) and MN5 (the fifth NMOS transistor) are off, and at the same time clkb is low, MP5 (the fifth PMOS transistor) and MP8 (the eighth PMOS transistor) are on, and Op and On outputs are both high. This stage is the reset stage.

[0041] After the reset phase ends, the comparison process begins. The differential signal is amplified after passing through the pre-amplification stage, and the difference between the signals in the pre-amplification stage is also amplified. The dynamic comparator operates on the falling edge of clk, while clkb is on the rising edge. Due to the principle of charge conservation in capacitors, the charge in C1 and C2 does not have time to change during the instantaneous rise of clkb, which will drive the voltage increase at the two output terminals Din and Dip of the pre-amplification stage. This allows the two output terminals Dip and Din of the pre-amplification stage to obtain the difference value in advance, without having to wait for clk to drop below the threshold voltage of an NMOS. This process also successfully saves the charge accumulation time on MN2 and MN3.

[0042] The selection of passive component capacitors can be appropriately chosen based on the area size and traction strength. Within a certain range, the traction strength of the traction circuit is inversely proportional to the capacitance values ​​of the first and second capacitors. Within a certain range, when the capacitance values ​​of capacitors C1 and C2 are too large, the traction effect is not obvious. Only when capacitors C1 and C2 are small enough will the voltage traction effect be more obvious. The capacitance value range of capacitors C1 and C2 is preferably 0.5-2 times the parasitic capacitance of the Din and Dip nodes.

[0043] After adding the pull capacitor to the dynamic comparator of this application, the overall working process is as follows. When the voltage of Vinp is higher than that of Vinn, the conduction degree of MP4 is greater than that of MP3. Due to the pulling effect of clkb on the capacitor, without waiting for MN2 and MN3 to turn off, the voltage at the Dip point will be greater than that at the Din point. For the second stage (latch stage), when the Dip voltage is greater than the Din voltage, the conduction degree of MN5 is greater than that of MN4, and the discharge speed of MN5 will be greater than that of MN4, resulting in the voltage at the Op point being greater than that at the On point. At this time, the positive feedback loop starts to work, the gate voltage of MN8 is greater than that of MN7, MN8 will conduct rapidly, accelerating the discharge, the voltage at the On point will become lower and lower, while the MP6 transistor will gradually conduct, and the MP7 transistor will gradually turn off. The voltage at the Op point will continuously rise to VDD, and the voltage at the On point will drop to VSS. Thus, the final judgment result is obtained.

[0044] Similarly, when the voltage of Vinn is higher than that of Vinp, the conduction degree of MP3 is greater than that of MP4. Without waiting for the charge accumulated in MN2 to be more than that in MN3, due to the pulling effect of clkb on the capacitor, the voltage at the Din point is greater than that at the Dip point. For the second stage, when the Din voltage is greater than the Dip voltage, the conduction degree of MN4 is greater than that of MN5, and the discharge speed of MN4 will be greater than that of MN5, resulting in the voltage at the On point being greater than that at the Op point. At this time, the positive feedback loop starts to work, the gate voltage of MN7 is greater than that of MN8, MN7 will conduct rapidly, accelerating the discharge, the voltage at the Op point will become lower and lower, while the MP7 transistor will gradually conduct, and the MP6 transistor will gradually turn off. The voltage at the On point will continuously rise to VDD, and the voltage at the Op point will drop to VSS. Thus, the final judgment result is obtained.

[0045] The pull circuit can also be applied to other types of two-stage comparators, such as common double-tail comparators, etc. In addition, it can also be applied to circuits that require fast response, such as startup circuits.

[0046] Figure 4 is the timing diagram of the operation of the comparator of the present invention and the prior art, as Figure 4 shown, CLK is the clock signal of the dynamic comparator, VIP and VIN are the original differential input signals. Among them, the VIP is the positive terminal input signal of the dynamic comparator, and the VIN is the negative terminal input signal of the dynamic comparator. VOP is the output signal of the dynamic comparator in the prior art ( Figure 1 the dynamic comparator shown), and VOP_NEW is the comparator output result of the dynamic comparator of the present invention after passing through the pull circuit. When the falling edge of the comparator clock CLK arrives, the comparator starts to compare. In the case of the prior art, the time occupied by the comparison process is t1, and the time occupied by the comparison process of the present invention is t2, and t2 < t1. By comparison Figure 4As can be clearly seen from t1 and t2, the comparison process of the dynamic comparator of the present invention takes significantly less time than that of the existing dynamic comparator. Therefore, the present invention has a significant effect on improving the speed of the comparator.

[0047] The dynamic comparator of this invention includes: a pre-amplification stage for amplifying the input differential signal to obtain an amplified signal; a latching stage connected to the output of the pre-amplification stage for latching the amplified signal to obtain a decision result; and a traction circuit connected to the output of the pre-amplification stage. The traction circuit includes at least a first capacitor, a second capacitor, and an inverting clock, with the inverting clock positioned between the first and second capacitors. When the inverting clock is at its rising edge, the charges of both the first and second capacitors remain unchanged, generating a voltage difference at the output of the pre-amplification stage, thus enabling the latching stage. By introducing the traction circuit, the speed of the pre-amplification stage is accelerated, while saving the charging time of the MOS capacitors during the pre-amplification stage. Moreover, the hardware cost is low; the speed improvement can be achieved simply by adding two passive capacitors.

[0048] The present invention also proposes a chip, which includes at least the dynamic comparator of the present invention.

[0049] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.

[0050] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not describe the various possible combinations separately.

[0051] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0052] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A dynamic comparator, characterized in that, include: The pre-amplifier stage is used to amplify the input differential signal to obtain the amplified signal. The pre-amplifier stage has two output terminals. The pre-amplifier stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The drain of the first PMOS transistor and the drain of the first NMOS transistor are both connected to the reverse clock. A latching stage, which is connected to the output of the pre-amplification stage, is used to latch the amplified signal to obtain a decision result; A traction circuit is provided, with its two ends connected to the two output terminals of the pre-amplification stage, and including at least a first capacitor, a second capacitor, and an inverting clock. The inverting clock is located between the first capacitor and the second capacitor. One end of the traction circuit is located between the drain of the third PMOS transistor and the drain of the second NMOS transistor; the other end of the traction circuit is located between the drain of the fourth PMOS transistor and the drain of the third NMOS transistor. When the reverse clock is at its rising edge, the charges of the first and second capacitors remain unchanged, and a voltage difference is generated at the output of the pre-amplification stage, which turns on the latch stage.

2. The dynamic comparator according to claim 1, characterized in that, The pre-amplification stage has two output terminals, and the two ends of the traction circuit are respectively connected to the two output terminals of the pre-amplification stage.

3. The dynamic comparator according to claim 1, characterized in that, The latch stage includes a positive feedback loop for providing positive feedback to the amplified signal; The output of the pre-amplification stage is connected to the input of the positive feedback loop.

4. The dynamic comparator according to claim 3, characterized in that, When the clock of the dynamic comparator is at the falling edge, the reverse clock is at the rising edge; When the reverse clock is at its rising edge, the charges of the first and second capacitors remain unchanged, and a voltage difference is generated at the output of the pre-amplification stage, which turns on the positive feedback loop of the latch stage.

5. The dynamic comparator according to claim 1, characterized in that, The traction strength of the traction circuit is inversely proportional to the capacitance values ​​of the first capacitor and the second capacitor.

6. The dynamic comparator according to claim 1, characterized in that, The reverse clock signal is the inverted clock signal of the dynamic comparator.

7. The dynamic comparator according to claim 1, characterized in that, Both the first capacitor and the second capacitor are passive capacitors.

8. The dynamic comparator according to claim 1, characterized in that, The gates of the first PMOS transistor and the first NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first PMOS transistor and the second PMOS transistor are both connected to the positive terminal of the power supply; the sources of the third PMOS transistor, the fourth PMOS transistor, and the drain of the second PMOS transistor are connected; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor; the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to the negative terminal of the power supply; the gates of the second NMOS transistor and the third NMOS transistor are both connected to the clock of the dynamic comparator.

9. A chip, characterized in that, The chip includes at least the dynamic comparator as described in any one of claims 1-8.

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