A low leakage memory array

Abstract

A low leakage memory array (310) includes a read bit line (RBL), a connection ground (VSS) and a read bit line switch (M0) connected between the read bit line (RBL) and the connection ground (VSS), and a plurality of memory circuits, wherein each memory circuit includes a memory cell (420) for storing data and a read circuit (410) for reading the data in the memory cell (420). A data input of the read circuit (410) is connected to a data output of the memory cell (420) for reading the data in the memory circuit, and a data output of the read circuit (410) is connected to the read bit line (RBL) for outputting the read data to the read bit line (RBL). At least one PMOS transistor in a leakage path from a power supply (VDD) to the read bit line (RBL) in the read circuit (410) is provided to suppress the leakage current in the read circuit (410) and to improve the situation of data read error due to leakage in the memory array (310).

Description

Technical Field

[0001] This application relates to storage circuits, and more particularly to a low-leakage storage array. Background Technology

[0002] In the field of chip design, power consumption has gradually become a core technical indicator. In system-on-chip (SoC), compared to logic circuits, SRAM (Static Random Access Memory) occupies an increasingly larger area on the chip, and the leakage current it generates has become more severe.

[0003] like Figure 1 The diagram shows a schematic of an existing SRAM structure, including a read bitline (RBL), a read bitline switch (P0), and N memory cells connected to the read bitline: memory cell 0, memory cell 1, ..., and memory cell N-1. Each memory cell is electrically connected to the read bitline (RBL) via its corresponding MOSFETs N0 and N1. MOSFETs N0 and N1 are cascaded between the read bitline (RBL) and ground (VSS). The data output terminal (QB) of the memory cell is electrically connected to the gate of MOSFET N1, while the read word line (RWL) is electrically connected to the gate of MOSFET N0. When reading data, the read bitline switch (P0) is open, and the read word line (RWL) selects the memory cell to be read. For example, when reading memory cell 0, the read word line (RWL) corresponding to memory cell 0... <0> =1, the MOS transistor N0 corresponding to the memory cell is turned on, while the read word line RWL corresponding to other memory cells is 0. When the data output terminal QB of the memory cell is 0, N1 is turned off, and RBL remains high; when QB is 1, both N1 and N2 are turned on, and RBL is pulled down to low. The level on RBL represents the data read from the memory cell.

[0004] MOSFETs N0 and N1 introduce an additional leakage path, from RBL, through MOSFET N0 and N1 to VSS, increasing the SRAM's static power consumption. Furthermore, SRAM leakage limits the number of connected memory cells. When the data in one memory cell is opposite to the data in other cells, leakage in the other cells may prevent RBL from maintaining a high level, resulting in data read errors. Summary of the Invention

[0005] This application provides a low-leakage storage array that can effectively suppress leakage current in the storage array, thereby improving the situation where data reading errors are caused by leakage current in the storage array.

[0006] For ease of description, in the embodiments of this application, one of the drain or source terminals of a MOSFET is referred to as the first terminal, and the corresponding other terminal is referred to as the second terminal. For example, for MOSFET M1, if its first terminal is the drain, then its second terminal is the source; if its first terminal is the source, then its second terminal is the drain. Furthermore, the embodiments of this application describe any type of MOSFET as MOSFET M0, MOSFET M1, MOSFET M2, etc., such as a PMOS (P-channel Metal Oxide Semiconductor) or an NMOS (N-channel Metal Oxide Semiconductor). The embodiments of this application describe different NMOS transistors in the same circuit as MOSFET N1, MOSFET N2, MOSFET N3, etc., and different PMOS transistors in the same circuit as MOSFET P1, MOSFET P2, MOSFET P3, etc.

[0007] In a first aspect, embodiments of this application provide a storage array, including read bit lines, read bit line switches, and multiple storage circuits, wherein the read bit line switches are connected between ground and the read bit lines. The read bit line switches are open when data is being read, so that the level on the read bit lines can represent the level of the read data; the read bit line switches are open when no data is being read, so that the read bit lines remain at a low level. Each storage circuit includes a storage cell for storing data and a read circuit for reading data. The data input terminal of the read circuit is electrically connected to the data output terminal of the storage cell, and the data output terminal of the read circuit is electrically connected to the read bit line. The read circuit is also connected to a power supply and has a leakage path running from the power supply through the read circuit to the read bit line, with at least one PMOS transistor in this leakage path to suppress leakage current in the read circuit. Typically, each storage circuit has the same circuit structure to reduce the difficulty of circuit design and manufacturing. Each storage cell is used to store 1 bit of data; for example, a high level can represent 1, and a low level can represent 0.

[0008] When the leakage current in the read circuit is large, if the data in one memory cell is opposite to the data in other memory cells, the leakage current in the other memory cells will prevent the read bit line from maintaining the correct level, resulting in a data read error. The memory array provided in this application embodiment, because it has at least one PMOS transistor in the leakage path, and PMOS transistors have lower leakage current than NMOS transistors, can effectively suppress leakage current, allowing the read bit line to maintain the correct level even when other memory cells have leakage current, without affecting the correct data readout. Furthermore, the smaller leakage current allows more memory cells to be connected to the read bit line in the memory array, thereby increasing the storage density of the memory array and reducing area overhead.

[0009] In one possible implementation, each of the above-described memory circuits further includes a corresponding read word line. The read circuit includes MOSFETs M1 and M2 cascaded between the read bit line and the power supply. The gate (i.e., control terminal) of MOSFET M1 is the data input terminal of the read circuit, which can be turned on or off according to the data being read. The gate of MOSFET M2 is electrically connected to the read word line to receive control from the read word line to turn MOSFET M2 on or off. For memory circuits that do not require reading, the corresponding word line controls MOSFET M2 to turn off. The first terminal of MOSFET M2 is the output terminal of the read circuit, and the second terminal is electrically connected to the first terminal of MOSFET M1, while the second terminal of MOSFET M1 is electrically connected to the power supply. At least one of MOSFETs M1 and M2 includes a PMOS transistor. In the above memory circuit, MOSFET M1 is electrically connected to the power supply, changing the original leakage path to power supply - MOSFET M1 - MOSFET M2 - read bit line. Therefore, leakage current can be better suppressed when the data of the memory cell to be read is 1 while the data of other memory cells is 0.

[0010] In one possible implementation, the read line switch is an NMOS transistor. Compared to a PMOS transistor read line switch, the NMOS transistor has a lower on-state voltage and offers greater controllability.

[0011] In one possible implementation, MOSFET M1 is a PMOS transistor and MOSFET M2 is an NMOS transistor, or MOSFET M2 is a PMOS transistor and MOSFET M1 is an NMOS transistor. Maintaining that one of MOSFETs M1 and M2 is a PMOS transistor can help reduce leakage current.

[0012] In one possible implementation, both MOSFET M1 and MOSFET M2 are PMOS transistors. When both MOSFETs are PMOS transistors, leakage current can be reduced more effectively.

[0013] In one possible implementation, before reading data, the read bit line switch is turned on according to the received control signal, connecting the read bit line to ground to maintain a low level. When reading data, the read bit line switch is turned off, and MOSFET M1 is turned on or off according to the data read from the memory cell. For example, if MOSFET M1 is a PMOS transistor, it is turned on when 0 is read from the memory cell. MOSFET M2 is turned on and off according to the control of the read word line. The read word line can selectively turn on MOSFET M2 in the memory circuit that needs data to be read, while turning off MOSFET M2 in the memory circuit that does not need data to be read. This connection method allows data in each memory cell to be read by controlling the on / off state of the MOSFETs in the read circuit.

[0014] In one possible implementation, the aforementioned memory cell includes MOSFETs P1 and N1 cascaded between power supply and ground, MOSFETs P2 and N2 cascaded between power supply and ground, MOSFET N3 cascaded between power supply and ground, and MOSFET N4. The first terminals of MOSFETs P1 and N1 are electrically connected to the Q node, the first terminals of MOSFETs P2 and N2 are electrically connected to the QB node, the second terminals of MOSFETs P1 and P2 are electrically connected to the power supply, and the second terminals of MOSFETs N1 and N2 are electrically connected to ground. The QB node is the data output terminal of the memory cell and is the inverting node of the Q node. The first terminal of MOSFET N3 is electrically connected to the QB node, the second terminal of MOSFET N3 is electrically connected to the write bit line, and the gate of MOSFET N3 is electrically connected to the write word line. The first terminal of MOSFET N4 is electrically connected to the Q node, the second terminal of MOSFET N4 is electrically connected to the write bit line, and the gate of MOSFET N4 is electrically connected to the write word line. This circuit structure enables efficient writing, storage, and reading of data in the memory cell.

[0015] In one possible implementation, the memory cell includes MOSFETs P1 and N1 cascaded between power supply and ground, MOSFETs P2 and N2 cascaded between power supply and ground, MOSFET P3, MOSFET P4, MOSFET N5, and MOSFET N6. Specifically, the first terminals of MOSFET P1 and MOSFET N1 are electrically connected to the Q node; the first terminals of MOSFET P2 and MOSFET N2 are electrically connected to the QB node; the second terminals of MOSFETs P1 and P2 are electrically connected to the power supply; the QB node is the data output terminal of the memory cell and is the inverting node of the Q node; the first terminal of MOSFET P3 is electrically connected to the Q node; the second terminal of MOSFET P3 is electrically connected to the write bit line; the gate of MOSFET N3 is electrically connected to the write word line; the first terminal of MOSFET P4 is electrically connected to the QB node; the second terminal of MOSFET P4 is electrically connected to the write bit line; the gate of MOSFET P4 is electrically connected to the write word line; the first terminal of MOSFET N5 is electrically connected to the second terminal of MOSFET N1; the gate of MOSFET N5 is electrically connected to the write word line; the first terminal of MOSFET N6 is electrically connected to the second terminal of MOSFET N2; the gate of MOSFET N6 is electrically connected to the write word line; and the second terminals of MOSFETs N5 and N6 are electrically connected to ground. The circuit structure described above enables efficient writing, storage, and retrieval of data in the storage unit.

[0016] In one possible implementation, the aforementioned storage unit is a 6T storage unit.

[0017] In one possible implementation, the aforementioned memory array further includes a half-Schmitt inverter, the input of which is electrically connected to the read bit line, and the output of which outputs the signal from the inverted read bit line. The read bit line is inverted by the half-Schmitt inverter and then output. Because the half-Schmitt inverter has a lower switching threshold, the voltage on the read bit line that meets the flipping requirement is lower, thus improving the read performance of the entire memory array.

[0018] In one possible implementation, the aforementioned semi-Schmitt inverter includes MOSFETs P5, P6, and N7 cascaded between power supply and ground, and MOSFET P7. The gates of MOSFETs P5, P6, and N7 are electrically connected to the read bit lines. MOSFET P7 is electrically connected between a first node and ground, the first node being the connection point of MOSFETs P5 and P6. The output of the semi-Schmitt inverter is electrically connected to the gate of MOSFET P7 and a second node, the second node being the connection point of MOSFETs P6 and N7. Because the semi-Schmitt inverter has a lower switching threshold, the voltage on the read bit lines that meet the flipping requirements is lower, thus improving the read performance of the entire memory array.

[0019] In one possible implementation, the read circuit includes MOSFETs M1 and M2 cascaded between the read bit line and the power supply, wherein at least one of MOSFETs M1 and M2 is a P-type MOSFET. Since PMOS transistors have lower leakage current than NMOS transistors, leakage in the leakage path can be suppressed.

[0020] Secondly, embodiments of this application provide a memory including a decoder, an amplifier, and a memory array. The decoder decodes a received address and outputs the decoded result to the memory array. The decoded result includes an address for controlling a read line switch, allowing selection of the memory cell to be accessed within the memory array. The amplifier amplifies the data read from the memory array, which can be any of the memory arrays described in the first aspect. The amplifier can be a sense amplifier (SA).

[0021] When the leakage current in the read circuit is large, if the data in one memory cell is opposite to the data in other memory cells, the leakage current in the other memory cells will prevent the read bit line from maintaining the correct level, resulting in a data read error. The memory array provided in this application embodiment, because it has at least one PMOS transistor in the leakage path, and PMOS transistors have lower leakage current than NMOS transistors, can effectively suppress leakage current, allowing the read bit line to maintain the correct level even when other memory cells have leakage current, without affecting the correct data readout. Furthermore, the smaller leakage current allows more memory cells to be connected to the read bit line in the memory array, thereby increasing the storage density of the memory array and reducing area overhead. In one possible implementation, the memory further includes a word line driver, a timing controller, and an input / output driver. The word line driver controls the levels of word lines and bit lines based on the decoding results generated by the decoder, thereby enabling access to a specified memory cell. The timing controller controls the timing of the sensitive amplifier and controls the word line driver to drive the word lines in the memory array. The input / output driver drives transmission signals, such as driven received data signals and driven data signals to be transmitted, enabling data signals to be transmitted over long distances. The aforementioned word line driver, timing controller, and input / output driver can improve the efficiency of data access in the memory.

[0022] Thirdly, embodiments of this application provide a processor including logic circuitry and a memory electrically connected to the logic circuitry, wherein the memory is the memory described in the second aspect of the embodiment.

[0023] Fourthly, embodiments of this application provide an electronic device including a processor, a bus, and a RAM bus for implementing communication between the RAM and the processor, wherein the processor is the processor in the third aspect of the embodiment. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an SRAM in the prior art.

[0025] Figure 2 This is a schematic diagram of the structure of an electronic device.

[0026] Figure 3 This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0027] Figure 4 A storage array is provided as an embodiment of this application.

[0028] Figure 5 This diagram illustrates leakage current under different PVT conditions.

[0029] Figure 6 The simulation results show the voltage levels under different leakage current scenarios.

[0030] Figure 7 This is a circuit diagram of a specific memory array provided in an embodiment of this application.

[0031] Figure 8 This is a circuit diagram of another specific memory array provided in an embodiment of this application.

[0032] Figure 9 This is a circuit diagram of another memory array provided in an embodiment of this application.

[0033] Figure 10 The VTC curves are for two types of inverters. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0035] In this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the term "electrical connection" should be interpreted broadly; for example, "electrical connection" can refer to a direct physical connection or an electrical connection achieved through an intermediate medium, such as a connection achieved through a resistor, inductor, or other electronic device.

[0036] For ease of description, this application uses MOS transistors M0, M1, M2, etc., to describe any type of MOS transistor, such as a PMOS (P-channel Metal Oxide Semiconductor) or an NMOS (N-channel Metal Oxide Semiconductor). This application uses MOS transistors N1, N2, N3, etc., to describe different NMOS transistors, and MOS transistors P1, P2, P3, etc., to describe different PMOS transistors. This application also refers to one of the drain or source terminals of the MOS transistor as the first terminal, and the other terminal as the second terminal.

[0037] like Figure 2The diagram illustrates the structure of an electronic device 200. The electronic device 200 may include a bus 210, and a processor 220, a ROM (Read Only Memory) 230, and a RAM (Random Access Memory) 240 electrically connected to the bus 210. The bus 210 is used to implement data transmission and control (communication) between the processor 220, ROM 230, and RAM 240. The bus 210 may be a bus using the AXI (Advanced eXtensible Interface) bus protocol, PCIE (Peripheral Component Interface Express), or other bus protocols. The processor 220 is used to perform data processing, such as calculation, compression and decompression, encoding and decoding, etc. The processor 220 may be a CPU (Central Processing Unit), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), or a microprocessor, etc. The processor 220 can be integrated into a SoC (System on a Chip) or ASIC (Application Specific Integrated Circuit), or it can be a separate semiconductor chip. ROM 230 is used to store fixed programs or data. ROM 230 can be PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), flash memory, etc. RAM 240 is used to store temporary data for the running program. RAM 240 can be SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), etc. In one embodiment, the processor 220 may also include RAM for storing temporary data and enabling higher-speed read / write operations. The aforementioned electronic device 200 can be a PC (personal computer), server, workstation, or a terminal product such as a mobile phone, laptop, or smartwatch.

[0038] This application provides a memory, which can be used for… Figure 2The RAM 240 shown can also be the RAM in the processor 220, or RAM and cache in other application scenarios. In one possible implementation, the processor 220 may include SRAM and logic circuitry for implementing data computation and scheduling. The memory can be used as SRAM as the main cache or level 2 cache in the processor 220. In another possible implementation, the memory can also be used as a register in a register file, or as a cache in an ASIC or FPGA (field-programmable gate array).

[0039] like Figure 3The diagram shows a schematic of a memory 300 according to an embodiment of this application. The memory 300 includes a memory array 310, a decoder 320, a word line driver 330, a timing controller 340, a sensor amplifier (SA) 350, and an input / output driver 360. The memory array 310 includes multiple memory cells, each of which stores 1 bit of data. Each memory cell is electrically connected to a corresponding word line (WL) and bit line (BL), where WL and BL are used to select a unique memory cell and perform read or write operations on that cell. Specifically, WL may include a read word line (RWL) and a write word line (WWL). Correspondingly, BL may include a read bit line (RBL) and a write bit line (WBL). The read word line RWL and read bit line RBL are used to select the corresponding memory cell when reading data; the write word line WWL and write bit line WBL are used to select the corresponding memory cell when writing data. Decoder 320 is used to decode the address of a memory cell. Decoder 320 decodes the received address to determine the memory cell to be accessed. Word line driver 330 controls the levels of word line WL and bit line BL based on the decoding result generated by decoder 320, thereby enabling access to the specified memory cell. Sensitive amplifier 350 amplifies the read data signal. Timing controller 330 controls the timing of sensitive amplifier 350 and controls word line driver 330 to drive word line WL in memory array 310. Input / output driver 360 drives transmission signals, such as the received data signal and the data signal to be transmitted, enabling long-distance transmission of data signals. The memory array 310, decoder 320, word line driver 330, timing controller 340, sensitive amplifier 350, and input / output driver 360 can be integrated into a single chip or integrated into multiple chips.

[0040] Figure 4 This application provides one implementation of a storage array 310. The storage array 310 includes a read bit line RBL, a read bit line switch M0 electrically connected between the read bit line RBL and ground VSS, and multiple storage circuits connected to the read bit line RBL. Each storage circuit includes a read circuit 410 and a storage cell 420. These read circuits 410 can employ the same circuit structure or different circuit structures. Similarly, the storage cells 420 can also employ the same or different circuit structures. Figure 4In the storage array 310 shown, the read circuit 410 and the storage cell 420 adopt the same circuit structure. The number of read circuits 410 and storage cells 420 connected to the read bit line RBL is the same, for example, it can be 32, 64, 128, etc. In this embodiment, 32 read circuits 410 and 32 storage cells 420 are used as an example. The storage array 310 may also include multiple read bit lines RBL, which are all electrically connected to ground VSS through read bit line switch M0. The storage cell 420 is used to store data, and the read circuit 410 is used to read the data stored in the storage cell 420 and output the data to the read bit line RBL. The read circuit 410 has a data input terminal and a data output terminal. Its data input terminal is electrically connected to the data output terminal of the storage cell 420, and its data output terminal is electrically connected to the read bit line RBL. The read circuit 410 is also electrically connected to the power supply VDD. The read circuit 410 has a leakage path from the power supply VDD to the read bit line RBL, and this leakage path has at least one PMOS transistor. In one embodiment, each memory circuit includes a corresponding read word line RWL, and the read circuit 410 can be implemented in various ways. For example... Figure 4 In the storage array 310 shown, the read circuit 410 includes MOSFETs M1 and M2 cascaded between the read bit line RBL and the power supply VDD. The gate of MOSFET M1 serves as the data input terminal of the read circuit 410 and is electrically connected to the data output terminal of the storage cell 420, turning on or off according to the data signal at the data output terminal of the storage cell 420. The drain and source of MOSFET M1 are electrically connected to the power supply VDD and MOSFET M2, respectively. For example, the drain of MOSFET M1 can be connected to the power supply VDD, and the source to MOSFET M2; alternatively, the source of MOSFET M1 can be connected to the power supply VDD, and the drain to MOSFET M2. The gate of MOSFET M2 is electrically connected to the read word line RWL and turns on or off according to the level of the read word line RWL. One end of MOSFET M2 serves as the data output terminal of the read circuit 410 and is electrically connected to the read bit line RBL. Specifically, the drain and source of MOSFET M2 are electrically connected to MOSFET M1 and read line RBL, respectively. For example, the drain of MOSFET M2 can be electrically connected to read line RBL, and the source to MOSFET M1; alternatively, the source of MOSFET M2 can be electrically connected to read line RBL, and the drain to MOSFET M1. Figure 4 In the reading circuit shown, the read line switch M0 is an NMOS transistor, while MOS transistors M1 and M2 are both PMOS transistors. Figure 4 The reading circuit 410 shown is only an example, and the specific circuit structure of the reading circuit 410 is not limited in the embodiments of this application.

[0041] The aforementioned read bit line switch M0 can be turned on or off by address control after being decoded by decoder 320. Read bit line switch M0 is used to control the level of read bit line RBL, thereby controlling data reading. Before reading data, read bit line switch M0 remains on according to the control signal, and all read word lines RWL are at an invalid level (1). At this time, MOS transistor M2 is off, and read bit line RBL and ground VSS are connected through read bit line switch M0 and are in a low-level state. When reading data, for example from the first memory cell 420 (read bit line RWL... <0> When the corresponding storage unit 420 reads data, the read bit line switch M0 is opened according to the control signal, and the read word line RWL is opened. <0> The voltage level on the line becomes active (0) to activate the corresponding read circuit 410, while the other 31 read word lines RWL <1> ~RWL <31> The level remains invalid (1). The read circuit 410 reads data from the data output terminal QB of the first memory cell 420. When QB=1, MOS transistor M1 is off, and the read bit line RBL remains low to indicate that the read data Q=0; when QB=0, both MOS transistors M1 and M2 are on, and the read bit line RBL is pulled high by the power supply VDD to indicate that the read data Q=1. Since the read word lines RWL of the other 31 read circuits are also low, the read bit line RBL remains low to indicate that the read data Q=1. <1> ~RWL <31> All are invalid levels, therefore the level on the read bit line RBL represents the level on the read word line RWL. <0> The selected reading circuit 410 reads the data in the corresponding storage unit 420.

[0042] Each memory circuit in memory array 310 still has a leakage path. The leakage paths in memory array 310 are as follows: Figure 4 As shown in Ioff. For each read circuit 410, its leakage path is from the power supply VDD, MOSFET M1, MOSFET M2 to the read bit line RBL. Since the channel type of PMOS transistors is P-type and that of NMOS transistors is N-type, the mobility of hole carriers in the P-type channel is lower than that of electron carriers in the N-type channel. Therefore, PMOS transistors have lower leakage current than NMOS transistors, thus effectively suppressing leakage current in the read data path.

[0043] For example Figure 1 The leakage current of the SRAM is described to illustrate the leakage suppression effect of the storage array 310. In the case of... Figure 1 In the SRAM shown, when reading data from memory cell 0, and the data QB of memory cell 0 is 0 while the data QB of other memory cells 1 to N-1 is 1, the MOS transistor N1 corresponding to memory cell 0 is turned off, and MOS transistor N0 is turned on. Under normal circumstances, the read bit line RBL should be at a high level (1). However, leakage current occurs between MOS transistors N0 and N1 between other memory cells 1 to N-1 and the read bit line RBL, preventing the read bit line RBL from maintaining a high level. The leakage current Ioff flows from... Figure 1 The read bit line RBL shown flows to ground VSS through MOSFETs N0 and N1. The more memory cells connected to the read bit line RBL, the greater the leakage current Ioff generated by these memory cells. This causes the read bit line RBL to fail to maintain a high level under the above conditions, resulting in errors in the data read from the read bit line.

[0044] In the embodiments provided in this application, such as Figure 4 In the storage array 310 shown, when reading the first storage cell 420 (read word line RWL)... <0> When the data in the corresponding memory cell 420 is read, and the data QB of the first memory cell is 1 while the data QB of the other memory cells is 0, the MOS transistor M1 corresponding to the first memory cell is turned off, and the MOS transistor M2 is turned on. Under normal circumstances, the read bit line RBL should be at a low level held before reading. Due to the presence of MOS transistors M1 and M2, the data in other memory cells (read word line RBL) is read... <1> ~RWL <31> In the read circuit 410 corresponding to the memory cell 420, although there is still a leakage current Ioff across the power supply VDD-MOS transistor M1-MOS transistor M2-read bit line RBL, the leakage effect between other memory cells and the read bit line RBL is suppressed by the PMOS transistor with lower leakage current. This allows the read bit line RBL to remain at a low level under the aforementioned conditions, preventing it from failing to maintain its level due to the leakage current Ioff and thus avoiding data read errors. Furthermore, the smaller leakage current Ioff allows more memory cells to be connected to the read bit line RBL in the memory array 310, thereby increasing the storage density of the memory array 310 and reducing area overhead.

[0045] like Figure 5 The diagram illustrates leakage current at different PVT (process voltage temperature). The horizontal axis represents different temperatures, and the vertical axis represents the leakage current under different PVT conditions. Figure 1 The normalized leakage current in the SRAM shown represents the relative leakage current of the memory array 310. Figure 5 It can be seen that, regardless of whether it is the FF (fast fast), TT (typical typical), or SS (slow slow) process corner, the leakage current suppression effect of the memory array 310 is significantly improved compared to existing technologies under any of these processes. The FF process corner exhibits the best leakage current suppression effect, approximately 20%. Furthermore, the leakage current suppression effect gradually improves with increasing temperature. Even after exceeding 85°C, the leakage current suppression decreases somewhat, but it is still superior to the leakage current in existing technologies (less than 1%).

[0046] like Figure 6 The image shown is for Figure 1 The simulation results of the read bit line (RBL) in the SRAM (existing technology) and the read bit line RBL in the memory array 310 provided in this application embodiment under leakage current scenario are shown. The leakage current scenario refers to the situation where, for the existing technology RBL, when reading data from memory cell 0, and the data QB of memory cell 0 is 0 while the data QB of other memory cells is 1, the read bit line RBL cannot maintain a high level, resulting in a data reading error. For this application embodiment, the leakage current scenario refers to the situation where, when reading data from the first memory cell, and the data QB of the first memory cell is 1 while the data QB of other memory cells is 0, the read bit line RBL can maintain a low level normally because the two cascaded low-leakage PMOS transistors do not affect the correct reading of data. Figure 6 As can be seen, during the data reading process, the level of the read bit line RBL in the prior art drops rapidly to Vdd / 2 at time t0 due to the leakage current of the NMOS transistor, and finally drops to a level far below Vdd / 2, causing the subsequent inverter to flip and resulting in data reading errors. In the memory array 310 provided in this application embodiment, the read bit line RBL, due to the low leakage current characteristics of the cascaded PMOS transistor, only rises to 0.03*Vdd at time t0, and then slowly rises to a level below Vdd / 2 after the same amount of time. Since the level of the read bit line RBL in the memory array 310 ultimately does not exceed Vdd / 2, it will not cause the subsequent inverter to flip, and therefore will not affect the correct reading of data.

[0047] In one implementation, Figure 4 In this embodiment, the read line switch M0 is an NMOS switch. In another implementation, the read line switch M0 can also be a PMOS switch. Compared to a PMOS read line switch, an NMOS transistor has a lower on-state voltage and offers greater controllability.

[0048] In one embodiment, one of the PMOS transistors M1 and M2 in the read circuit 410 can be replaced by an NMOS transistor. For example, if MOS transistor M1 is replaced with an NMOS transistor, the N-type MOS transistor M1 and the P-type MOS transistor M2 are cascaded. Since a PMOS transistor still exists in the leakage path, the read circuit 410 can still suppress the leakage current Ioff. Alternatively, if MOS transistor M2 is replaced with an NMOS transistor, the N-type MOS transistor M2 and the P-type MOS transistor M1 are cascaded. Since a PMOS transistor still exists in the leakage path, the read circuit 410 can still suppress the leakage current Ioff. Therefore, as long as there is at least one PMOS transistor in the read circuit 410, the leakage current Ioff can be suppressed.

[0049] This application does not limit the specific structure of the memory cell 420. The memory cell 420 can be a common 6T (transistor) structure, a structure that is further improved on the 6T structure, or a memory cell with other structures in the prior art. Figure 7 The present application provides a specific circuit structure diagram of a storage array 310, which includes 6T storage cells 420. Figure 7 The read circuit 410 in the illustrated memory array 310 still uses two cascaded PMOS transistors, and the read bit line switch M0 is an NMOS transistor. Alternatively, the read circuit and read bit line switch M0 in the memory array 310 can also adopt the implementation methods described above.

[0050] For ease of description, the source or drain of a MOSFET will be represented by "first terminal" and "second terminal". For example, the first terminal of a MOSFET may be the source and the second terminal the drain, or vice versa. Figure 7 In the illustrated memory array 310, memory cell 420 includes MOSFETs P1, N1, P2, N2, N3, and N4. MOSFETs P1 and N1 are cascaded, and the first terminals of MOSFETs P1 and N1 are electrically connected to a Q node, where the voltage level of the Q node represents the data stored in memory cell 420. Correspondingly, MOSFETs P2 and N2 are cascaded, and the first terminals of MOSFETs P2 and N2 are electrically connected to a QB node, where the inverted voltage level of the QB node represents the data stored in memory cell 420. The gates of MOSFETs P1 and N1 are both electrically connected to the QB node, and the gates of MOSFETs P2 and N2 are both electrically connected to the Q node. The second terminals of MOSFETs P1 and P2 are pulled up to the power supply voltage, and the second terminals of MOSFETs N1 and N2 are pulled down to ground. Furthermore, the first terminal of MOSFET N3 is electrically connected to the QB node, the second terminal is electrically connected to the write bit line WBL, and the gate is electrically connected to the write word line WWL. The first terminal of MOSFET N4 is electrically connected to the Q node, the second terminal is electrically connected to the write bit line WBL, and the gate is electrically connected to the write word line WWL. In one embodiment, the aforementioned QB node is the data output terminal of the memory cell 420 and is electrically connected to the input terminal of the read circuit 410, i.e., the gate of MOSFET M1.

[0051] The write word line WWL is used to select the corresponding word when writing data to the memory cell 410, while the write bit line WBL is used to write specific data to the memory cell 410. When the write word line WWL is at an active level (1), both MOSFETs N3 and N4 are turned on, and the level on the write bit line WBL is written to the memory cell 410. When the write word line WWL is at an inactive level (0), both MOSFETs N3 and N4 are turned off, and the memory cell 410 is in a locked state. The level on the write bit line WBL will not affect the levels of the Q node and the QB node.

[0052] Figure 8 The circuit diagram of another specific storage array 800 provided in this application embodiment includes 8T storage cells 820. Figure 8 The read circuit 810 in the illustrated memory array 800 is cascaded with a P-type MOS transistor M1 and an N-type MOS transistor M2, and the read bit line switch M0 is an NMOS transistor. Alternatively, the read circuit and read bit line switch M0 in the memory array 800 can each adopt any of the embodiments described above.

[0053] Figure 8 The storage cell 820 shown is Figure 7 The circuit structure of memory cell 420 shown is similar, and the identical parts will not be described again. The difference is that memory cell 820 also includes MOSFETs P3, P4, N5, and N6. The first terminal of MOSFET P3 is electrically connected to the Q node, the second terminal of MOSFET P3 is electrically connected to the second terminal of MOSFET P4, and the first terminal of MOSFET P4 is electrically connected to the QB node. The gate of MOSFET P3 is electrically connected to the write word line WWL and is also electrically connected to the gate of MOSFET N5. The gate of MOSFET P4 is electrically connected to the write word line WWL and is also electrically connected to the gate of MOSFET N6. The first terminal of MOSFET N5 is electrically connected to the second terminal of MOSFET N1, and the first terminal of MOSFET N6 is electrically connected to the second terminal of MOSFET N2. The second terminals of both MOSFETs N5 and N6 are pulled down to ground. The operating principle of memory cell 820 is similar to that of memory cell 420 and will not be described again here.

[0054] In the read circuit 410, MOSFET M2 is replaced with an N-type MOSFET. Since the P-type MOSFET M1 is still present in the leakage path VDD-M1-M2-RBL, the leakage effect can be effectively suppressed.

[0055] To further improve the read performance of the memory array, this application also provides a memory array including a half-Schmitt inverter. The circuit structure of this half-Schmitt inverter can employ half of any Schmitt inverter structure. The half-Schmitt inverter takes the read bit line RBL as input and outputs the inverted data signal. For example... Figure 9 The diagram shown is a circuit structure diagram of another memory array 900 provided in this application embodiment. The memory array 900 is similar to the memory array 310, and the similarities will not be repeated. The difference is that the memory array 900 also includes a half-Schmitt inverter 930. This half-Schmitt inverter 930 includes MOSFETs P5, P6, N7, and P7, wherein MOSFETs P5, P6, and N7 are cascaded between power supply VDD and ground VSS, and the gates of MOSFETs P5, P6, and N7 are all electrically connected to the read bit line RBL. The first terminal of MOSFET P7 is electrically connected to the connection point of MOSFETs P5 and P6, and the second terminal of MOSFET P7 is electrically connected to ground VSS. The gate of MOSFET P7 is connected to the connection point of MOSFETs P6 and N7, and this connection point is the output point OUT of the half-Schmitt inverter 930.

[0056] The semi-Schmidt inverter 930 can optimize the read performance of the memory array 900. For example... Figure 10 The diagram shows the VTC (voltage-transfer characteristic) curves of two types of inverters. The horizontal axis represents the input voltage Vin of the inverter, and the vertical axis represents the output voltage Vout. The solid curve represents the VTC curve of an inverter electrically connected to the read line RBL in the prior art, while the dashed curve represents the VTC curve of the half-Schmitt inverter 930 in the memory array 900. Figure 10 As the input voltage Vin increases, the dashed curve reaches a low level faster than the real curve during the decrease of the output voltage Vout. This means that the switching threshold of the half-Schmitt inverter 930 is more biased towards a low level than that of inverters in the prior art. The lower switching threshold of the half-Schmitt inverter 930 results in a lower voltage on the read bit line RBL that meets the flipping requirements, thus improving the read performance of the memory array 900.

[0057] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: Read lines; A read position line switch, wherein the read position line switch is electrically connected between ground and the read position line; A half-Schmitt inverter, wherein the input terminal of the half-Schmitt inverter is electrically connected to the read line, and the output terminal of the half-Schmitt inverter is used to output the signal in the read line after inversion; Multiple storage circuits, each of the multiple storage circuits comprising: Storage unit, the storage unit being used to store data; The read circuit has its data input terminal electrically connected to the data output terminal of the storage cell, and its data output terminal electrically connected to the read bit line. The read circuit is also electrically connected to a power supply. In the read circuit, at least one PMOS transistor is present in the leakage path from the power supply to the read bit line. The half-Schmitt inverter includes: MOSFETs P5, P6, and N7 are cascaded between the power supply and the ground, wherein the gates of MOSFETs P5, P6, and N7 are electrically connected to the read bit line, respectively. MOS transistor P7 is electrically connected between a first node and ground. The first node is the connection point of MOS transistors P5 and P6. The output terminal of the half-Schmitt inverter is electrically connected to the gate of MOS transistor P7 and a second node, which is the connection point of MOS transistors P6 and N7.

2. The storage array as described in claim 1, characterized in that, Each storage circuit further includes a corresponding read word line, and the read circuit includes MOSFETs M1 and M2 cascaded between the read bit line and the power supply. The gate of the MOS transistor M1 is the data input terminal of the read circuit, the gate of the MOS transistor M2 is electrically connected to the read word line, the first terminal of the MOS transistor M2 is the data output terminal of the read circuit, the second terminal of the MOS transistor M2 is electrically connected to the first terminal of the MOS transistor M1, the second terminal of the MOS transistor M1 is electrically connected to the power supply, and the MOS transistors M1 and M2 include at least one PMOS transistor.

3. The storage array as described in claim 1 or 2, characterized in that, The read line switch is an NMOS transistor.

4. The storage array as described in claim 2, characterized in that, The MOS transistor M1 is a PMOS transistor, and the MOS transistor M2 is a PMOS transistor.

5. The storage array as described in claim 2, characterized in that, The read line switch is used to: turn on before reading data and turn off when reading data from the storage unit; The MOS transistor M1 is used to: turn on or off according to the data read from the memory cell; The MOS transistor M2 is used to: conduct when reading data from the memory cell according to the read word line.

6. The storage array as described in claim 1 or 2, characterized in that, The storage unit includes: MOSFETs P1 and N1 are cascaded between the power supply and ground, with the first terminal of MOSFET P1 and the first terminal of MOSFET N1 electrically connected to the Q node; MOSFETs P2 and N2 are cascaded between the power supply and ground. The first terminal of MOSFET P2 and the first terminal of MOSFET N2 are electrically connected to the QB node. The second terminals of MOSFETs P1 and P2 are respectively electrically connected to the power supply. The second terminals of MOSFETs N1 and N2 are respectively electrically connected to the ground. The QB node is the data output terminal of the memory cell and is the inverting node of the Q node. MOS transistor N3, the first terminal of which is electrically connected to the QB node, the second terminal of which is electrically connected to the write bit line, and the gate of which is electrically connected to the write word line; MOS transistor N4, the first terminal of which is electrically connected to the Q node, the second terminal of which is electrically connected to the write bit line, and the gate of which is electrically connected to the write word line.

7. The storage array as described in claim 1 or 2, characterized in that, The storage unit includes: MOSFETs P1 and N1 are cascaded between the power supply and ground, with the first terminal of MOSFET P1 and the first terminal of MOSFET N1 electrically connected to the Q node; MOSFETs P2 and N2 are cascaded between the power supply and ground. The first terminals of MOSFET P2 and N2 are electrically connected to the QB node. The second terminals of MOSFETs P1 and P2 are respectively electrically connected to the power supply. The QB node is the data output terminal of the memory cell and is the inverting node of the Q node. MOS transistor P3, the first terminal of which is electrically connected to the Q node, the second terminal of which is electrically connected to the write bit line, and the gate of MOS transistor N3 is electrically connected to the write word line; MOS transistor P4, the first terminal of which is electrically connected to the QB node, the second terminal of which is electrically connected to the write bit line, and the gate of which is electrically connected to the write word line; MOS transistor N5, the first terminal of which is electrically connected to the second terminal of MOS transistor N1, and the gate of MOS transistor N5 is electrically connected to the write line; MOS transistor N6, the first terminal of which is electrically connected to the second terminal of MOS transistor N2, the gate of which is electrically connected to the write line, and the second terminals of MOS transistors N5 and N6 are respectively electrically connected to ground.

8. A memory, characterized in that, The device includes a decoder, an amplifier, and a storage array as described in any one of claims 1 to 7, wherein the decoder is configured to decode a received address and output it to the storage array, and the amplifier is configured to amplify data read from the read bit line, wherein the decoded address includes an address for controlling the read bit line switch.

9. A processor, characterized in that, It includes logic circuitry and a memory electrically connected to the logic circuitry, wherein the memory is the memory as described in claim 8.

10. An electronic device, characterized in that, It includes a processor, a bus, and RAM, wherein the bus is used to enable communication between the RAM and the processor, and the processor is the processor as described in claim 9.

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