Capacitance detection device, detection method, and electronic device

Abstract

A kind of capacitance detection device, detection method and electronic equipment, circuit includes state machine module and capacitance detection module;State machine module is used to read channel configuration parameter according to preset reading rule and output to capacitance detection module;Capacitance detection module includes control unit and capacitance detection unit, control unit is used to configure corresponding channel based on channel configuration parameter and output switch control signal to capacitance detection unit;Capacitance detection unit is used to realize the capacitance detection of corresponding channel based on switch control signal.This application provides a kind of capacitance detection device, by using state machine module hardware circuit to read channel configuration parameter to carry out channel configuration, when the number of capacitance channel to be detected is more, the area of capacitance detection device is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to a capacitance detection device, detection method, and electronic equipment. Background Technology

[0002] A capacitive sensor is a device that converts a measured physical or mechanical quantity into an electrical signal. Due to its simple structure, stable performance, and high sensitivity, capacitive sensors are widely used in industrial and consumer electronics fields, such as for measuring pressure, displacement, acceleration, thickness, and liquid level. A capacitive sensor converts changes in capacitance into an electrical signal output through a capacitance detection device, and then determines the magnitude of the measured quantity by measuring the magnitude of the electrical signal.

[0003] In the prior art, in order to realize multi-channel capacitance measurement, a configuration register needs to be set for each channel to configure the channel parameters. When there are many channels, the configuration registers of each channel will occupy a large area of ​​the chip. Summary of the Invention

[0004] In view of this, this application provides a capacitance detection device, detection method and electronic device to solve the problem that the configuration registers of each channel occupy a large area of ​​the chip when performing multi-channel capacitance measurement in existing capacitance detection devices.

[0005] This application provides a capacitance detection device, including a state machine module and a capacitance detection module; the state machine module is used to read channel configuration parameters according to preset reading rules and output them to the capacitance detection module; the capacitance detection module includes a control unit and a capacitance detection unit, the control unit is used to configure the corresponding channel based on the channel configuration parameters and output a switch control signal to the capacitance detection unit; the capacitance detection unit is used to realize capacitance detection of the corresponding channel based on the switch control signal.

[0006] Optionally, the state machine module includes a drive state machine unit and a read / write state machine unit; the drive state machine unit is used to start working based on a trigger signal and output a memory control signal to the read / write state machine unit; the read / write state machine unit is used to read the channel configuration parameters according to the preset reading rules based on the memory control signal and write them to the control unit.

[0007] Optionally, the control unit includes at least one channel configuration register; the read / write state machine unit is used to write the channel configuration parameters into the channel configuration register, and the channel configuration register is used to configure the parameters of the corresponding channel according to the channel configuration parameters.

[0008] Optionally, the preset reading rules include: a preset step size, a preset base address, and the starting address of each logical channel calculated based on the preset step size and the preset base address.

[0009] Optionally, the capacitance detection module is further configured to output the acquired capacitance detection data of the corresponding channel to the read / write state machine unit; the read / write state machine unit is further configured to write the capacitance detection data to the memory.

[0010] Optionally, it also includes a memory; the state machine module is connected to the memory via a memory bus, and the state machine module is used to read the channel configuration parameters stored in the memory according to a preset reading rule, and the channel configuration parameters are stored in the memory according to a preset configuration rule.

[0011] Optionally, the preset configuration rules include: forming configuration information based on the initial address of each logical channel, channel configuration parameters, and capacitance detection data of the corresponding channel; the magnitude of the channel configuration parameters is a first value, and the magnitude of the capacitance detection data is a second value.

[0012] Optionally, the memory is provided with an arbitration module, and the state machine module is connected to the memory through the arbitration module. The arbitration module is used to perform read control according to a preset priority when the state machine module and the controller read the memory at the same time.

[0013] This application also provides a capacitance detection method, comprising: reading channel configuration parameters according to preset reading rules; configuring a corresponding channel based on the channel configuration parameters and outputting a switch control signal to realize capacitance detection of the corresponding channel.

[0014] Optionally, before the step of reading the channel configuration parameters, the method further includes: obtaining the channel selection signals and / or scan cycles of all channels; sequentially determining whether the channel selection signal of the current channel is valid, and / or sequentially determining whether the scan cycle of the current channel is a preset cycle value; generating a trigger signal when the channel selection signal is valid, and / or when the scan cycle is a preset cycle value; and reading the channel configuration parameters of the current channel according to the preset reading rules based on the trigger signal.

[0015] Optionally, the step of reading the channel configuration parameters specifically includes: generating an arbitration signal according to a preset priority; and reading the channel configuration parameters of the current channel according to the arbitration signal.

[0016] Optionally, after completing the capacitance detection, the capacitance detection method further includes: acquiring an end signal; acquiring capacitance detection data of the current channel based on the end signal, and writing the capacitance detection data into a memory.

[0017] Optionally, the step of reading the channel configuration parameters according to the preset reading rules includes: calculating the starting address of each logical channel using a preset step size and a preset base address; and reading the channel configuration parameters according to the starting address.

[0018] Optionally, the starting address of each logical channel satisfies the following formula:

[0019] ssx_base_addr=x*step+base_addr

[0020] Wherein, ssx_base_addr is the starting address of the channel number x, x is the number of channels, step is the preset step size, and base_addr is the preset base address.

[0021] Optionally, after writing the capacitance detection data to the memory, the capacitance detection method further includes: outputting a detection completion interrupt signal after all valid channels have completed detection.

[0022] This application also provides an electronic device, including the aforementioned capacitance detection device.

[0023] This application provides a capacitance detection device that uses a state machine module hardware circuit to read channel configuration parameters for channel configuration. When there are many capacitance channels to be detected, the area of ​​the capacitance detection device is reduced. In addition, since the circuit of the state machine module is simple, its power consumption is lower than that of the controller. Using the state machine module instead of the controller to configure the parameters of each channel avoids the power loss caused by the controller and reduces the power consumption of the capacitance detection device.

[0024] Furthermore, the capacitance detection device also includes a memory. The state machine module is connected to an external memory via a memory bus and directly reads the channel configuration parameters via DMA (Direct Memory Access). The state machine module hardware circuit reads the channel configuration parameters to configure the channel, thereby improving the detection speed of the capacitance detection device.

[0025] Furthermore, the preset read rules include: a preset step size, a preset base address, and a start address for each logical channel calculated based on the preset step size and the preset base address. The start address for each logical channel is calculated using the preset step size and the preset base address, enabling automatic read / write operations to the memory. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an existing capacitance detection device;

[0028] Figure 2 This is a schematic diagram of the structure of a capacitance detection device according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of a capacitance detection unit according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of a capacitance detection device according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the actual storage space of the channel configuration parameters of each channel in SRAM according to the SRAM preset configuration rules in Table 1, according to an embodiment of the present invention.

[0032] Figure 6 The calculation of the write address of each channel of the SRAM according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic flowchart of a capacitance detection method according to an embodiment of the present invention;

[0034] Figure 8 This is a flowchart illustrating the application of a capacitance detection method according to an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0036] Please see Figure 1 A schematic diagram of the structure of an existing capacitance detection device.

[0037] Figure 1In existing capacitance detection devices, an analog front-end and a controller are included. The analog front-end can perform capacitance detection on multiple channels (CH0, CH1 to CHn). The controller includes configuration registers corresponding to each channel. Since the area and parasitic capacitance of each channel are different, channel parameter configuration is required when performing multi-channel capacitance measurements. Specifically, channel parameter configuration is achieved by configuring the configuration registers of the corresponding channels in the controller.

[0038] When there are many channels, each channel requires a corresponding configuration register, which will occupy a large chip area.

[0039] To address the aforementioned problems, this application provides a capacitance detection device. This device includes only one configuration register. By executing firmware code to retrieve channel configuration parameters from SRAM (Static Random Access Memory) and write them to the configuration register, channel parameter configuration can be achieved. Since only one configuration register is needed to realize multi-channel capacitance detection, the chip area occupied by the capacitance detection device can be significantly reduced.

[0040] However, when the number of channels is large, the firmware becomes very large, which reduces the capacitance detection speed through the controller. Additionally, since the controller needs to be involved throughout the process, its power consumption is also high, resulting in relatively high power consumption for the capacitance detection device.

[0041] To further improve the speed of capacitance detection and reduce the power consumption of the capacitance detection device, this application provides a capacitance detection device that reads channel configuration parameters through a state machine module. Since the circuit of the state machine module is simple and its power consumption is lower than that of the controller, using the state machine module instead of the controller to configure the parameters of each channel avoids the power loss caused by the controller and reduces the power consumption of the capacitance detection device.

[0042] Please see Figure 2 A schematic diagram of the structure of a capacitance detection device according to an embodiment of the present invention.

[0043] The capacitance detection device in this embodiment includes a state machine module 1 and a capacitance detection module 2.

[0044] State machine module 1 is used to read the channel configuration parameter cfg_data according to the preset reading rules and output it to the capacitance detection module 2.

[0045] The capacitance detection module 2 includes a control unit 21 and a capacitance detection unit 22.

[0046] The control unit 21 is used to configure the corresponding channel based on the channel configuration parameter cfg_data and output a switch control signal to the capacitor detection unit 22.

[0047] The capacitance detection unit 22 is used to detect the capacitance of the corresponding channel among channels CH0 to CHn based on the switch control signal.

[0048] The capacitance detection device in this embodiment uses a state machine module hardware circuit to read channel configuration parameters for channel configuration. When there are many capacitance channels to be detected, the area of ​​the capacitance detection device is reduced. In addition, since the circuit of the state machine module is simple and has lower power consumption compared to the controller, using the state machine module instead of the controller to configure the parameters of each channel avoids the power loss caused by the controller and reduces the power consumption of the capacitance detection device.

[0049] Optionally, the capacitance detection device further includes a memory. The state machine module is connected to the memory via a memory bus. The state machine module is used to read channel configuration parameters stored in the memory according to preset reading rules. The channel configuration parameters are stored in the memory according to preset configuration rules. Specifically, the state machine module is used to automatically read the channel configuration parameter cfg_data and output it to the capacitance detection module 2. The channel configuration parameters are stored in the memory according to preset rules. The memory can be located outside or inside the capacitance detection device. The state machine module 1 consists of a state register and combinational logic circuits. It can perform state transitions according to preset states based on control signals, coordinate related signal actions, and complete specific operations. The state machine module 1 includes a finite state machine. The state machine module 1 and the capacitance detection module 2 can be integrated into the same chip or separated into two different chips.

[0050] The control unit 21 includes triggers, latches, counters, shift registers, and memory. The control unit 21 also includes registers for configuring channel parameters. In other optional embodiments, the registers in the control unit 21 can be located externally to the control unit 21.

[0051] The capacitance detection unit 22 uses an amplifier and an integrating capacitor to realize capacitance detection. During the capacitance sampling stage, the capacitor to be detected is connected to the power supply voltage for charging. After charging is completed, the output terminal of the capacitor to be detected is connected to any one of the channels CH0 to CHn of the capacitance detection device through a switch to realize the capacitance measurement of the corresponding channel.

[0052] Please see Figure 3 A schematic diagram of the structure of a capacitance detection unit according to an embodiment of the present invention.

[0053] Figure 3The capacitance detection unit 22 therein includes switches K1, K2, K3, capacitor Cmod, resistor RB, a comparator, a latch, and a counter. The capacitor Cx to be detected is connected to the power supply voltage VDD through one end of switch K1 and grounded through the other end. When switch K1 is closed, the capacitor Cx to be detected is charged. Switches K1 and K2 are opened alternately by non-overlapping switch control signals. During the alternating closing of switches K1 and K2, the capacitor Cx to be detected injects charge into capacitor Cmod. At the same time, the comparator compares the magnitudes of voltage VX and the reference voltage VREF, and outputs the comparison result to the subsequent latch. The latch works synchronously through the clock CLK. When VX < VREF, the comparator outputs 0 and switch K3 is disconnected; when VX > VREF, the comparator outputs 1 and switch K3 is closed. At this time, the voltage VX discharges charge to the ground through resistor RB. Eventually, the charge injected by the capacitor Cx to be detected into capacitor Cmod reaches dynamic equilibrium with the amount of charge discharged by capacitor Cmod through resistor RB, and the value of voltage VX stabilizes near the reference voltage VREF. The counter calculates the number of times the latch outputs 0 or 1 within a certain period of time to determine the capacitance change of the capacitor Cx to be detected. For example, when there is no pressing on the capacitor Cx to be detected, switches K1 and K2 conduct alternately, and the charge on the capacitor Cx to be detected is injected into capacitor Cmod. When VX > VREF, charge is discharged through resistor RB to reduce VX, so that the number of times VX > VREF is limited. For example, within one minute, the number of times VX > VREF is 50 times. At this time, the value counted by the counter within one minute should be the standard 50 times. When there is a pressing on the capacitor Cx to be detected, it will cause the value of the capacitor Cx to be detected to increase, and the sampled charge will also increase. Within one minute, the number of times VX > VREF will exceed 50 times, such as reaching 100 times. At this time, the value counted by the counter within one minute should be 100 times. Connecting Figure 3 the capacitance detection unit 22 therein to different capacitors Cx to be detected can achieve capacitance detection for multiple channels CH0 to CHn. Figure 3 The counting result of the counter therein is the capacitance detection data of the corresponding channel obtained by the capacitance detection unit 22.

[0054] The capacitance detection device of this embodiment uses a capacitance detection unit to perform multi-channel capacitance detection, which improves the detection speed of the capacitance detection device when the number of capacitance channels to be detected is relatively large.

[0055] Please refer to Figure 4 , the structural schematic diagram of the capacitance detection device according to an embodiment of the present invention.

[0056] In this embodiment of the capacitance detection device, the state machine module 1 includes a drive state machine unit 11 and a read / write state machine unit 12. Preferably, the state machine module 1 is connected to the memory via a memory bus SRAM_bus, and the memory includes SRAM, RAM (random access memory), DRAM (dynamic random access memory), etc. When the memory is SRAM, by connecting a hardwired connection between the state machine module 1 and the external memory, the state machine module 1 can directly read the data on the memory, realizing DMA transfer mode read / write to the memory.

[0057] DMA (Direct Memory Access) refers to copying data from one address space to another. It is usually controlled by the CPU (Central Processing Unit), meaning the CPU accesses SRAM via DMA. Ordinary peripherals generally cannot directly access SRAM.

[0058] The capacitance detection device in this embodiment is designed in an unconventional way. It connects the state machine module 1 and the external memory with a hardwire, namely the memory bus SRAM_bus. Through this hardwire, the state machine module 1 can directly read the data on the memory, realizing DMA transfer mode for reading and writing the memory. This can greatly improve the capacitance detection speed in multi-channel capacitance detection.

[0059] The drive state machine unit 11 is used to start operation based on a trigger signal and output a memory control signal to the read / write state machine unit 12. The memory control signal includes a read memory signal.

[0060] The trigger signal includes a trigger signal Time_trig directly sent by an external controller. The Time_trig trigger signal allows the external controller to control the startup of the drive state machine unit 11 for convenient control. In other optional embodiments, the trigger signal can also be configured by setting the startup bit of the startup register to 1 to achieve automatic state machine startup of the drive state machine unit 11. In other optional embodiments, the scan period is set by configuring the TIMER0_LOAD register, and the counter timer is started to generate the Time_trig signal. The scan channel valid register is configured to set the valid on / off state cs_en to 1. If it is determined that cs_en = 1 and the scan period meets the requirements, an afe_ready level signal is generated internally. This afe_ready level signal serves as the trigger signal. When the drive state machine unit 11 receives the afe_ready signal as 1, it starts working and outputs a memory control signal to the read / write state machine unit 12 to start the read / write state machine unit 12. The drive state machine unit 11 consists of a state register and combinational logic circuits, and is a finite state machine.

[0061] The read / write state machine unit 12 is used to read the channel configuration parameter cfg_data through the memory bus SRAM_bus based on the memory control signal and write it into the capacitance detection module 2.

[0062] After the read / write state machine unit 12 is started, it generates the signals required for reading the memory, mainly generating the address information corresponding to the memory, and reading the channel configuration parameter cfg_data stored in the memory according to the address information.

[0063] The configuration information of the SRAM is automatically read and written by the read / write state machine unit 12, which consists of a state register and combinational logic circuits. If the SRAM information is too complex, the hardware circuit may encounter read / write errors or even fail to read / write. To enable the read / write state machine unit 12 to automatically read and write the SRAM, the channel configuration parameters need to be stored in the SRAM according to preset configuration rules.

[0064] The preset configuration rules include: forming configuration information based on the initial address of each logical channel, channel configuration parameters, and corresponding capacitance detection data; the size of the channel configuration parameters is a first value, and the size of the capacitance detection data is a second value. The first value can be set to 4 bytes, 8 bytes, etc., depending on the actual situation. The second value can also be set to 1 byte or 2 bytes, depending on the actual situation. Logical channels SS0 to SSn are arranged sequentially, but the actual physical channels CH0 to CHn can be arbitrarily mapped to logical channels, allowing for flexible configuration. The preset configuration rules include register configuration tables and other forms of configuration information.

[0065] Please refer to Table 1 below, which is an SRAM register configuration table of an embodiment of the present invention.

[0066]

[0067] Table 1

[0068] In Table 1 above, each channel configuration parameter is fixed at 4 words. Taking logic channel SS0 as an example, the 4 words are cfg0_ss0, cfg1_ss0, cfg2_ss0, and cfg3_ss0 parameters. Before capacitance detection, a scan is required to obtain the original data of the circuit. After the scan is completed, the original data is stored in the 5th word of the current channel. In Table 1 above, 31:0 indicates a bit width of 32 bits, RW indicates that the corresponding parameter is readable and writable, RO indicates that the corresponding parameter is readable but not writable, b00 is binary, and h00 is hexadecimal. The original data of logic channel SS0 AFE and logic channel SS1 AFE refer to the original data after the scan is completed. In the SRAM of this embodiment, the initial address of each channel can be configured by writing registers to the host computer, and the space occupied by each channel, i.e., the scan cycle, can also be configured by writing registers to the host computer. The SRAM allocation is very flexible and can be set according to the actual usage. The host computer includes the CPU and the host connected to the capacitance detection device. Table 1 only shows the case with two channels as an example. When there are multiple channels, more channels can be set according to the actual situation.

[0069] Please see Figure 5 The diagram shows the actual storage space in SRAM according to the channel configuration parameters of each channel in the SRAM register configuration table in Table 1.

[0070] Since the initial address portion of the SRAM may already store other data, to flexibly configure the channel configuration parameters for each channel in the SRAM's segmented storage, register configuration items for the preset step size (`step`) and preset base address (`base_addr`) can be set. The preset base address (`base_addr`) sets the starting address in the SRAM address space where channel configuration parameters begin to be stored, and the preset step size (`step`) sets the amount of storage space occupied by each logical channel. Both the preset step size (`step`) and the preset base address (`base_addr`) can be configured via a host computer.

[0071] For example, if we set base_addr = 0, then Figure 5 In this context, the initial address A1 of logical channel SS0 is 0x0000, and address A1 is also the starting address of the channel configuration parameters for logical channel SS0. The configuration parameters for logical channel SS0 are written starting from address 0 of the SRAM. If base_addr = 0x400, then... Figure 5 In this context, the initial address A1 of logical channel SS0 is 0x400, and the configuration parameters of logical channel SS0 are written starting from address 0x400 in the SRAM. When stpe = 0x40, Figure 5The storage space size of middle segment 0 and segment 1 is 0x40, indicating that logical channels SS0 and SS1 each occupy 64 bytes. When stpe = 0x80, Figure 5 The storage space size of middle segment 0 and segment 1 is 0x80, indicating that logical channel SS0 and logical channel SS1 each occupy 128 bytes.

[0072] The state machine module 1 reads the channel configuration parameters in the register according to the preset reading rules, which include: preset step size, preset base address, and the starting address of each logical channel calculated based on the preset step size and the preset base address.

[0073] The starting address of each logical channel satisfies the following formula:

[0074] ssx_base_addr=x*step+base_addr;

[0075] Where ssx_base_addr is the starting address of channel x, x is the number of channels, step is the preset step size, and base_addr is the preset base address.

[0076] Assume base_addr = 0x0 and step = 0x40 (where 0x represents hexadecimal).

[0077] at this time, Figure 5 middle

[0078] A1 = 0 * 0x40 = 0x0;

[0079] A2=A1+4word=0x0+4*4=0x10;

[0080] B1 = 1 * 0x40 = 0x40;

[0081] B2=B1+4word=0x40+4*4=0x50;

[0082] C1 = 2 * 0x40 = 0x80;

[0083] C2 = C1 + 4word = 0x90

[0084] Assume base_addr = 0x400 and step = 0x40 (where 0x represents hexadecimal).

[0085] at this time, Figure 5 middle

[0086] A1 = 0 * 0x40 + 0x400 = 0x400;

[0087] A2=A1+4word=0x400+4*4=0x410;

[0088] B1 = 1 * 0x40 + 0x400 = 0x440;

[0089] B2=B1+4word=0x440+4*4=0x450;

[0090] C1 = 2 * 0x40 + 0x400 = 0x480;

[0091] C2 = C1 + 4word = 0x490

[0092] Therefore, when the state machine module 1 reads data from the memory, it can calculate the starting address of each logical channel using a preset step size and a preset base address, and automatically read the channel configuration parameters of the corresponding channel based on the starting address of each logical channel.

[0093] Figure 5 In the configuration, the default base address base_addr is set to 0x0, the initial address A1 of logic channel SS0 is 0x0000, and address A2 is the starting storage address of the capacitance detection data of logic channel SS0, with A2 being 0x0010.

[0094] The initial address B1 of logic channel SS1 is 0x0040. Address B1 is also the starting address of the channel configuration parameters of logic channel SS1. Address B2 is the starting storage address of the capacitance detection data of logic channel SS1, and B2 is 0x0050.

[0095] The address space between addresses A1 and A2 is the first value of the channel configuration parameters for logical channel SS0, which is 4 words. The address space between addresses A1 and B1 is the space of segment 0, equal to the preset step size, which also determines the storage space occupied by logical channel SS0. The address space of address A2 is the second value of the capacitance detection data for logical channel SS0, which is 1 word. The address spaces between addresses A1 and A2, and between addresses A1 and B1, can also be changed according to the actual situation, as shown in Table 1.

[0096] Please refer to Table 2 below for the calculation of the read addresses of each logical channel of the SRAM in an embodiment of the present invention.

[0097]

[0098] Table 2

[0099] In Table 2, when the preset step size is 0x80, the preset base address is 0, the starting address of logical channel SS0 is 0x000, the address read by the read / write state machine unit is 0x000, the starting address of logical channel SS1 is 0x080, the address read by the read / write state machine unit is 0x080, the starting address of logical channel SS2 is 0x100, and the address read by the read / write state machine unit is 0x100.

[0100] When the preset step size is 0x40, the preset base address is 0x400, the starting address of logical channel SS0 is 0x000, the address read by the read / write state machine unit is 0x400, the starting address of logical channel SS1 is 0x040, the address read by the read / write state machine unit is 0x440, the starting address of logical channel SS2 is 0x080, and the address read by the read / write state machine unit is 0x480.

[0101] When the state machine module 1 reads data from the memory, it can automatically read the channel configuration parameters of the corresponding channel according to the starting address of each channel in Table 2.

[0102] After the read / write state machine unit 12 finishes reading the channel configuration parameters, it enters the start_gen state, generates a start signal start, and outputs the start signal start to the control unit 21. The control unit 21 is also used to output the switch control signal timing to the capacitor detection unit 22 based on the start signal start for capacitor detection. The switch control signal timing is used to control... Figure 3 The time-sharing on / off of switches K1 and K2.

[0103] The control unit 21 includes at least one channel configuration register; the read / write state machine unit 12 is used to write the channel configuration parameter cfg_data into the channel configuration register, and the channel configuration register is used to configure the parameters of the corresponding channel according to the channel configuration parameter.

[0104] When the control unit 21 includes one channel configuration register, the read / write state machine unit 12 writes the channel configuration parameter cfg_data into the channel configuration register according to the effective channel order to perform channel capacitance detection. A single channel configuration register reduces the occupied area. When the control unit 21 includes two or more channel configuration registers, the read / write state machine unit 12 can write the channel configuration parameter cfg_data into two or more channel configuration registers according to the number of effective channels to perform two or more capacitance detections, thus balancing area considerations and capacitance detection speed.

[0105] In an optional embodiment, the capacitance detection module is further configured to output the acquired capacitance detection data of the corresponding channel to the read / write state machine unit; the read / write state machine unit is further configured to write the capacitance detection data to an external memory. Optionally, the capacitance detection unit directly outputs the acquired capacitance detection data of the corresponding channel to the read / write state machine unit; the read / write state machine unit is further configured to write the capacitance detection data to an external memory. Or, as... Figure 4 As shown, the capacitance detection unit 22 transmits the acquired capacitance detection data raw_data of the corresponding channel to the control unit 21. The control unit 21 reads and writes the capacitance detection data raw_data to the state machine unit 12. The state machine unit 12 then writes the capacitance detection data raw_data to the external memory via the SRAM_bus. By writing the capacitance detection data raw_data to the memory, real-time storage of the capacitance detection data raw_data can be achieved.

[0106] Please see Figure 6 The calculation of the write address of each channel of the SRAM in one embodiment of the present invention. Figure 6In this configuration, with a preset step size of 0x80 and a preset base address of 0, the starting address of logical channel SS0 (ssx_base_addr) is 0x000, and the address read by the read / write state machine unit (load_addr) is 0x000. Similarly, the starting address of logical channel SS1 (ssx_base_addr) is 0x080, and the address read by the read / write state machine unit (load_addr) is 0x080. The starting address of logical channel SS2 (ssx_base_addr) is 0x100, and the address read by the read / write state machine unit (load_addr) is 0x100. When calculating the write address for each channel, the 5th word of each channel can be used as the first write address based on the external firmware register table. A maximum of 8 write operations are supported, with the address incremented by one word for each write operation. For example, for channel SS0, the address for the first write is 0x10, the address for the second write is 0x14, the address for the third write is 0x18, and the address for the fourth write is 0x1c; for channel SS1, the address for the first write is 0x90, the address for the second write is 0x94, the address for the third write is 0x98, and the address for the fourth write is 0x9c.

[0107] From Table 2, Figure 5 and Figure 6 As can be seen, by setting the preset step size `step` and preset base address `base_addr` in the register, the hardware state machine module can calculate the read and write addresses of each channel. By agreeing on the addresses of the memory and the read / write state machine unit, the read / write state machine unit can automatically read and write to the memory. That is, through this agreement, the hardware can automatically obtain the configuration parameter information of each channel and complete the automatic scanning.

[0108] Furthermore, as shown in the table above, the SRAM registers store the channel configuration parameters for each channel, and the read / write state machine unit 12 can directly read the channel configuration parameters for each channel. Compared to setting configuration registers for each channel in the capacitance detection module to store the channel configuration parameters, this application places the channel configuration parameters in SRAM and directly reads the parameter information in SRAM via DMA, thereby reducing a large number of configuration registers and significantly saving chip area.

[0109] In alternative embodiments, an arbitration module is provided in the memory. The state machine module is connected to the memory through the arbitration module. The arbitration module is used to control the read operation according to a preset priority when the state machine module and the controller read the memory simultaneously. For example, the priority of the state machine module is set to be higher than that of the controller. When the state machine module and the controller read the memory simultaneously, the arbitration module ensures that the state machine module reads the memory first, avoiding errors caused by data read conflicts.

[0110] In alternative embodiments, the scheme of using SRAM to store channel configuration parameters and setting a configuration register in the capacitance detection module to store channel configuration parameters can be combined. Parameters for specific functions are placed in the configuration register in the capacitance detection module, while parameters for other functions are placed in SRAM to improve the ease of application.

[0111] In other optional embodiments, after the capacitance detection unit 22 completes the detection, the control unit 21 outputs a done signal to the state machine module 1. Upon detecting the done signal, the state machine module 1 writes the capacitance detection data raw_data into the SRAM for SRAM update. Optionally, the control unit 21 outputs the done signal after a fixed time, such as 30 seconds, or it can output the done signal immediately upon receiving the capacitance detection data raw_data.

[0112] In alternative embodiments, the control unit 21 may also output a reset signal rst to the capacitance detection unit 22 to control the capacitance detection unit 22 to reset. The control unit 21 may also output a clock signal CLK to the capacitance detection unit 22 to provide a clock signal. The control unit 21 may also output other control signals as needed.

[0113] After completing the capacitance detection of one channel, the state machine module will proceed to the capacitance scan and judgment of the next channel, and perform capacitance detection on the next channel. When all valid channels have been detected, the state machine module will generate a detection completion interrupt signal to report to the controller. The capacitance scan is now complete, and the capacitance detection device will automatically enter sleep mode, waiting for the next trigger to wake up, in order to reduce power consumption.

[0114] This application also provides a capacitance detection method.

[0115] Please see Figure 7 A schematic flowchart of a capacitance detection method according to an embodiment of the present invention.

[0116] The capacitance detection method in this embodiment includes the following steps:

[0117] Step S1: Read the channel configuration parameters according to the preset reading rules.

[0118] Step S2: Configure the corresponding channel based on the channel configuration parameters and output a switch control signal to realize the capacitance detection of the corresponding channel.

[0119] The capacitance detection method in this embodiment uses a state machine module to read channel configuration parameters via DMA through hardware circuitry, eliminating the need for a controller to configure parameters for each channel. This avoids power loss caused by the controller and reduces the power consumption of the capacitance detection device. Furthermore, when there are many capacitance channels to be detected, using the state machine module hardware circuitry to read channel configuration parameters improves the detection speed of the capacitance detection device.

[0120] In one optional implementation, step S1 specifically includes: providing a capacitance detection device, the capacitance detection device including a state machine module. The state machine module consists of a state register and combinational logic circuits, capable of state transitions according to a pre-set state based on control signals, and able to coordinate related signal actions to complete specific operations. The state machine module includes a finite state machine. For example, the capacitance detection device is as follows: Figure 2 As shown, the capacitance detection device includes a state machine module 1 and a capacitance detection module 2. The state machine module 1 reads the channel configuration parameters from the external memory via the SRAM_bus based on the memory control signal and writes them into the capacitance detection module. The connection relationship and working principle of the state machine module 1 and the capacitance detection module 2 have been described above and will not be repeated here.

[0121] Channel configuration parameters are read by a capacitance detection device according to preset reading rules, and these parameters are stored in memory according to the same preset rules. For example, a state machine module can be used to obtain channel configuration parameters from internal or external registers via DMA, or from internal or external SRAM. The preset configuration rules include: based on the initial address of each logical channel, the channel configuration parameters, and the corresponding capacitance detection data; the size of the channel configuration parameters is a first value, and the size of the capacitance detection data is a second value. The first value can be set to 4 bytes, 8 bytes, etc., depending on the actual situation. The second value can also be set to 1 byte or 2 bytes, depending on the actual situation. Logical channels SS0 to SSn are arranged sequentially, but the actual physical channels CH0 to CHn can be arbitrarily mapped to logical channels, allowing for flexible configuration. See Table 1 for details. Figure 5 According to the SRAM preset configuration rules in Table 1, the actual storage space of the channel configuration parameters in SRAM is shown in the diagram. The specific content is similar to that described above and will not be repeated here.

[0122] In one optional embodiment, step S1 specifically includes: calculating the starting address of each logical channel based on a preset step size and a preset base address; and reading the channel configuration parameters based on the starting address of each logical channel.

[0123] The starting address of each logical channel satisfies the following formula:

[0124] ssx_base_addr=x*step+base_addr

[0125] Wherein, ssx_base_addr is the starting address of the channel number x, x is the number of channels, step is the preset step size, and base_addr is the preset base address.

[0126] The specific values ​​of ssx_base_addr, step, and base_addr are... Figure 5 The calculation process for the starting address of each logical channel and the contents of Table 2 have been described above and will not be repeated here.

[0127] Step S2 specifically includes: after determining the valid channel based on the channel configuration parameters, generating a switch control signal for the corresponding channel to control the channel to perform capacitance detection.

[0128] In an optional embodiment, after reading the channel configuration parameters from the external memory, the capacitance detection method further includes: generating a start signal using the drive state machine unit; and generating the switch control signal based on the start signal. For example, after the drive state machine unit finishes reading the channel configuration parameters, it enters the start_gen state, generates a start signal start, and outputs the start signal start to the control unit; the control unit outputs the switch control signal timing to the capacitance detection unit based on the start signal start to perform capacitance detection. In other optional embodiments, the drive state machine unit can also generate a start signal based on an external control signal to generate the switch control signal. Using an external signal to control the generation of the start signal facilitates external control of the start of capacitance detection.

[0129] In an optional embodiment, step S1 specifically includes: acquiring the channel selection signals of all channels, and / or the scan period; sequentially determining whether the channel selection signal of the current channel is valid, and / or sequentially determining whether the scan period of the current channel is a preset period value; when the channel selection signal is valid, and / or when the scan period is a preset period value, using the drive state machine unit to receive the trigger signal.

[0130] Specifically, after the controller detects the status of each channel, it acquires the raw channel data for each channel and writes it into SRAM. The SRAM configuration format is shown in Table 1. In Table 1, the raw channel data is also the standard data corresponding to when the capacitors of each channel are not pressed. In the subsequent capacitor detection process, the capacitor detection data detected by the capacitor detection device is compared with this standard data to determine whether the capacitor under test has been pressed. The controller then configures the TIMER0_LOAD register (to set the scan period) and starts the timer to generate the Time_trig signal, configures the scan channel valid register to set the valid on / off state cs_en to 1; it determines that cs_en = 1 and the scan period meets the requirements, and internally generates an afe_ready level signal. This afe_ready level signal serves as a trigger signal, driving the state machine unit to receive the afe_ready signal as 1, start working, and output memory control signals to the read / write state machine unit to start the read / write state machine unit.

[0131] In an optional embodiment, step S1 further includes: generating an arbitration signal according to a preset priority; and reading the channel configuration parameters of the current channel according to the arbitration signal. For example, the priority of the state machine module is set higher than that of the controller. When the state machine module and the controller read the memory simultaneously, the arbitration module generates an arbitration signal according to the preset priority, so that the state machine module reads the channel configuration parameters of the current channel first according to the arbitration signal, avoiding errors caused by data reading conflicts.

[0132] In an optional embodiment, after the capacitance detection device completes capacitance detection, the capacitance detection method further includes: acquiring an end signal; acquiring capacitance detection data of the current channel based on the end signal, and writing the capacitance detection data into a memory.

[0133] Optionally, an end signal can be output after a fixed time, such as 30 seconds, while simultaneously acquiring the capacitance detection data of the current channel. Alternatively, an end signal can be output after receiving the capacitance detection data, and the capacitance detection data can be written to the memory for real-time data storage. Acquiring the capacitance detection data of the current channel only after receiving the end signal and writing it to the memory prevents data acquisition errors that might occur if data acquisition is performed before the capacitance detection process is complete.

[0134] In an optional embodiment, the memory includes channel configuration parameters for each channel and capacitance detection data for the corresponding channel. The address of the channel configuration parameters is a first address, and the address of the capacitance detection data is a second address. The first address and the second address can be configured via registers. The step of writing the capacitance detection data into the memory includes: writing the capacitance detection data into the second address of the memory.

[0135] Specifically, as shown in Table 1, the SRAM memory includes channel configuration parameters cfg0_ss0, cfg1_ss0, cfg2_ss0, cfg3_ss0, cfg0_ss1, cfg1_ss1, cfg2_ss1, and cfg3_ss1 for logic channels SS0 and SS1. The fifth word contains the capacitance detection data for the corresponding channel. The address of the channel configuration parameters is the first address, which is the address of the first four words of the initial address in Table 1. The address of the capacitance detection data is the second address, which is the address of the fifth word in the initial address. The first and second addresses can be configured via registers, and the space occupied by each channel can also be configured via registers. The SRAM allocation is very flexible and can be set according to actual usage.

[0136] For example: see Figure 6 When calculating the write address for each channel, the fifth word of each channel can be used as the first storage address based on the external firmware register table, supporting up to eight write operations, with the address incremented by one word for each write operation. The read / write state machine unit writes the capacitance detection data to the second address in the external memory via the bus, corresponding to the address of the fifth word. By writing the capacitance detection data to memory, real-time storage of the capacitance detection data can be achieved. Furthermore, by setting the preset step size `step` and preset base address `base_addr` in the registers, the hardware state machine module can calculate the read and write addresses for each channel. Through this convention, the hardware can automatically acquire the configuration parameter information of each channel and complete automatic scanning. This application places the channel configuration parameters in SRAM and directly reads the parameter information from SRAM via DMA, thereby reducing the number of configuration registers and significantly saving chip area.

[0137] In other alternative embodiments, the scheme of using SRAM to store channel configuration parameters and setting a configuration register in the capacitance detection module to store channel configuration parameters can be combined. Parameters for specific functions are placed in the configuration register in the capacitance detection module, while parameters for other functions are placed in SRAM to improve the ease of application.

[0138] In an optional embodiment, after the step of writing the capacitance detection data to the memory, the capacitance detection method further includes: after all valid channels have completed detection, outputting a detection completion interrupt signal.

[0139] Once all valid channels have completed detection, the state machine module outputs an interrupt signal to the controller, enabling the controller to manage the capacitance detection status. At this time, the CPU can directly send a wake-up signal to the capacitance detection device to control it to enter sleep mode to save power. The capacitance detection device can also enter sleep mode on its own to save power and wait for the next trigger to wake it up.

[0140] Please see Figure 8 The following is a flowchart illustrating the application of a capacitance detection method according to an embodiment of the present invention.

[0141] The capacitance detection method of this embodiment is applied to a chip, which includes the above-mentioned state machine module. The state machine module includes a driver state machine and a read / write state machine. In the initial stage, step S11, power-on initialization Start, is executed. After initialization is completed, the CPU enters sleep mode and outputs an initialization completion interrupt signal CPU_cmd.

[0142] Step S12: The host computer connected to the chip determines whether an interrupt signal CPU_cmd has occurred. After detecting the interrupt signal CPU_cmd, the host computer connected to the chip configures the channel configuration parameters in the SRAM through the I2C bus (a bidirectional two-wire synchronous serial bus) interface. The specific configuration format is shown in Table 1. The purpose of configuring the SRAM is to acquire the status of each channel before capacitance detection and then write it into the SRAM as initial values, such as the original data of channel 0AFE in Table 1. The original data of channel 0AFE serves as a standard value. The capacitance detection data detected in the subsequent capacitance detection device will be compared with this standard value to determine the change of the capacitor to be detected. Specifically, when the capacitance detection data is greater than the original data of channel 0AFE, it indicates that the capacitor to be detected has been pressed; otherwise, no pressing has occurred.

[0143] Simultaneously, the host computer connected to the chip configures the TIMER0_LOAD register to set the scan cycle to scan_prd, configures the scan channel valid register to select which channels are valid (specifically, by setting the channel enable signal cs_en of the corresponding channel in the channel register to 1), and starts the timer, which outputs a trigger signal Timer_trig after a certain period to control the state machine module to start, and / or configures the start register to 1 to automatically start the state machine module.

[0144] If an initialization completion interrupt signal CPU_cmd appears, proceed to step S13; if no initialization completion interrupt signal CPU_cmd appears, proceed to step S22.

[0145] Step S13: Obtain the trigger signal Timer_trig.

[0146] Step S14: Determine whether cs_en = 1 & Cnt = scan_prd is true, that is, whether the current channel is valid and whether the current scan cycle meets the requirements;

[0147] If step S14 is true, it indicates that the current channel is valid and the current scan cycle meets the requirements. Capacitance detection of the current channel is performed, and step S15 is executed. If step S14 is false, it indicates that the current channel is invalid or the current scan cycle does not meet the requirements. Capacitance detection of the current channel is not performed, and step S16 is executed.

[0148] Step S15: Generate a level signal afe_ready, and output the level signal afe_ready to the driving state machine DRV_FSM. The driving state machine DRV_FSM is the state machine module in the above embodiment.

[0149] Step S16: Increment the channel pointer by 1, i.e., Csx = Csx + 1, and continue to determine whether the next channel is valid.

[0150] Step S17: Start the driver state machine DRV_FSM. The driver state machine DRV_FSM receives the afe_ready signal as 1 and starts working.

[0151] Step S18: Start the read / write state machine load_store. The read / write state machine load_store generates the signals required to read the SRAM, mainly the corresponding address signals. Specific SRAM configuration information is shown in Table 1 above and will not be repeated here. The read / write state machine load_store is the read / write state machine unit in the above embodiment.

[0152] After the read / write state machine load_store completes the channel configuration parameters in the SRAM, it enters the start_gen state and generates a start signal to control the control unit to generate the timing switch control signal required by the capacitor detection unit.

[0153] Step S19: Wait for the control unit AFE_CTRL to complete its work. Upon detecting the "done" signal, update the SRAM by storing the raw_data data collected by the control unit AFE_CTRL into the SRAM. The control unit AFE_CTRL is the control unit in the above embodiment.

[0154] Enter the capacitance scan judgment of the next channel, and repeat the above steps S14 to S18.

[0155] Step S20: Determine whether all channels have been detected. If yes, proceed to step S21; otherwise, proceed to step S22.

[0156] Step S21: After all capacitor scans are completed, an interrupt signal is generated to report to the CPU.

[0157] Step S22: Enter sleep mode and wait for the next trigger.

[0158] This invention provides a capacitance detection method that directly obtains the configuration information required by the capacitance detection device from SRAM via DMA, eliminating the need to add configuration registers for each channel to the capacitance detection device. This saves a significant amount of chip area. Furthermore, the controller does not need to be constantly involved in the operation. The entire automated electrical testing solution simplifies the firmware program and reduces chip power consumption.

[0159] This application also provides an electronic device that includes the aforementioned capacitance detection device. The electronic device includes a capacitance sensor, a chip, and various capacitance detection devices. By using the aforementioned capacitance detection device, the electronic device can reduce power consumption and decrease device size.

[0160] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A capacitance detection device, characterized in that, Includes a state machine module, a memory, and a capacitance detection module; The state machine module is connected to the memory via a memory bus and is used to read the channel configuration parameters stored in the memory according to a preset reading rule and output them to the capacitance detection module. The preset reading rules include: a preset step size, a preset base address, and the starting address of each logical channel calculated based on the preset step size and the preset base address; The channel configuration parameters are stored in the memory according to preset configuration rules; The capacitance detection module includes a control unit and a capacitance detection unit. The control unit is used to configure the corresponding channel based on the channel configuration parameters and output a switch control signal to the capacitance detection unit. The capacitance detection unit is used to detect the capacitance of the corresponding channel based on the switch control signal.

2. The capacitance detection device as described in claim 1, characterized in that, The state machine module includes a driving state machine unit and a read / write state machine unit; The drive state machine unit is used to start working based on the trigger signal and output memory control signals to the read / write state machine unit; The read / write state machine unit is used to read the channel configuration parameters according to the preset read rules based on the memory control signal, and write them to the control unit.

3. The capacitance detection device as described in claim 2, characterized in that, The control unit includes at least one channel configuration register; The read / write state machine unit is used to write the channel configuration parameters into the channel configuration register, and the channel configuration register is used to configure the parameters of the corresponding channel according to the channel configuration parameters.

4. The capacitance detection device as described in claim 1, characterized in that, The preset configuration rules include: forming configuration information based on the initial address of each logical channel, channel configuration parameters, and capacitance detection data of the corresponding channel; The channel configuration parameter is a first value, and the capacitance detection data is a second value.

5. The capacitance detection device as described in claim 1, characterized in that, The memory is equipped with an arbitration module, and the state machine module is connected to the memory through the arbitration module. The arbitration module is used to control the reading according to a preset priority when the state machine module and the controller read the memory at the same time.

6. The capacitance detection device as described in claim 2, characterized in that, The capacitance detection module is also used to output the acquired capacitance detection data of the corresponding channel to the read / write state machine unit. The read / write state machine unit is also used to write the capacitance detection data to the memory.

7. A capacitance detection method, characterized in that, The capacitance detection method is implemented using the capacitance detection device according to any one of claims 1 to 6, including: Read the channel configuration parameters according to the preset reading rules; Configure the corresponding channel based on the channel configuration parameters and output a switch control signal to realize the capacitance detection of the corresponding channel; The step of reading channel configuration parameters according to preset reading rules includes: calculating the starting address of each logical channel using a preset step size and a preset base address; and reading the channel configuration parameters according to the starting address.

8. The capacitance detection method as described in claim 7, characterized in that, Prior to the step of reading the channel configuration parameters, the following is also included: Obtain the channel selection signal for all channels, and / or the scan period; Sequentially determine whether the channel selection signal of the current channel is valid, and / or sequentially determine whether the scanning period of the current channel is the preset period value; A trigger signal is generated when the channel selection signal is valid, and / or when the scan period is a preset period value; According to the trigger signal, the channel configuration parameters of the current channel are read according to the preset reading rules.

9. The capacitance detection method as described in claim 7, characterized in that, The steps for reading the channel configuration parameters specifically include: Arbitration signals are generated according to preset priorities; The channel configuration parameters of the current channel are read based on the arbitration signal.

10. The capacitance detection method as described in claim 7, characterized in that, After completing the capacitance detection, the capacitance detection method further includes... Obtain the end signal; The capacitance detection data of the current channel is obtained based on the termination signal, and the capacitance detection data is written to the memory.

11. The capacitance detection method as described in claim 7, characterized in that, The starting address of each logical channel satisfies the following formula: ssx_base_addr=x*step+base_addr Wherein, ssx_base_addr is the starting address of the channel number x, x is the number of channels, step is the preset step size, and base_addr is the preset base address.

12. The capacitance detection method as described in claim 10, characterized in that, After the step of writing the capacitance detection data to the memory, the capacitance detection method further includes: After all valid channels have completed the detection, an interrupt signal is output to indicate that the detection is complete.

13. An electronic device, characterized in that, Includes the capacitance detection device according to any one of claims 1-6.

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