Driving control circuit and driving control method, gate driving circuit, display panel

Abstract

The application provides a driving control circuit and method, a gate driving circuit and a display panel. The driving control circuit comprises a gear selection circuit and an output end which are electrically connected. The gear selection circuit comprises a plurality of first selection branches in parallel. The control end, the first end and the third end of each first selection branch are electrically connected with the corresponding control signal end, the first level signal end and the output end, respectively. The plurality of first selection branches are configured to: when the control signal end receives the control signal provided by the first selection branches in a first specified number, the first selection branches in the first specified number are turned on. The first specified number is greater than 0 and less than or equal to the total number of the first selection branches in the gear selection circuit. The technical solution of the application can flexibly adjust the driving signal output by the output end, and further flexibly adjust the driving force and power consumption of the driven shift register.

Description

Technical Field

[0001] This application relates to display driving technology, and more particularly to a driving control circuit and driving control method, a gate driving circuit, and a display panel. Background Technology

[0002] When the DDIC (Display Driver Integrated Circuit) in the display panel drives the display module, the source drive circuit and the gate drive circuit consume most of the power in the DDIC. In the traditional GOA (Gate Driver On Array) circuit, the driving force (which can be characterized by the rise time Tr and fall time Tf of the driving signal) is not adjustable, which causes the same driving force to be maintained under any display conditions, resulting in a waste of power in the driving force of the GOA circuit. Summary of the Invention

[0003] This application provides a driving control circuit and driving control method, a gate driving circuit, and a display panel to solve the problems existing in related technologies. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a drive control circuit, including: a gear selection circuit and an output terminal that are electrically connected;

[0005] The gear selection circuit includes multiple first selection branches connected in parallel. The control terminal, first terminal, and third terminal of each first selection branch are electrically connected to the corresponding control signal terminal, first level signal terminal, and output terminal, respectively.

[0006] Multiple first selection branches are configured such that when a control signal is received from the control signal terminal for a first specified number of first selection branches, the first specified number of first selection branches are turned on;

[0007] The first specified quantity is greater than 0 and less than or equal to the total number of the first selection branches in the gear selection circuit.

[0008] Secondly, embodiments of this application provide a gate driving circuit, including: a plurality of cascaded shift registers, and a driving control circuit for driving the plurality of shift registers;

[0009] The drive control circuit is the shift register drive control circuit provided in any embodiment of this application.

[0010] Thirdly, embodiments of this application provide a display panel, including: a gate driving circuit provided in any embodiment of this application.

[0011] Fourthly, embodiments of this application provide a drive control method, including:

[0012] A control signal is provided to a first selected branch of a first specified number in the drive control circuit to turn on the first selected branch and output a corresponding drive signal; the drive control circuit is the drive control circuit of the shift register provided in any embodiment of this application.

[0013] The advantages or beneficial effects of the above technical solutions include at least the following:

[0014] The drive control circuit includes a gear selection circuit with multiple first selection branches. Under the control of the control signal, a specified number of first selection branches can be turned on, so that the output terminal outputs a specified drive signal. The specified number is greater than 0 and less than or equal to the total number of first selection branches in the gear selection circuit. Thus, the number of first selection branches turned on can be flexibly adjusted within a certain range, the drive signal output at the output terminal can be flexibly adjusted, and the driving force and power consumption of the driven shift register can be flexibly adjusted.

[0015] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0017] Figure 1 This is a schematic diagram of the structural framework of a drive control circuit provided in an embodiment of this application;

[0018] Figure 2 A schematic diagram of the gear selection circuit provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram of another gear selection circuit provided in an embodiment of this application;

[0020] Figure 4 A schematic diagram of the circuit principle of another gear selection circuit provided in the embodiments of this application;

[0021] Figure 5 A schematic diagram of the circuit principle of another gear selection circuit provided in the embodiments of this application;

[0022] Figure 6 This is a schematic diagram of the structural framework of another drive control circuit provided in an embodiment of this application. Detailed Implementation

[0023] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0024] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0025] The inventors of this application discovered in their research that as terminal devices such as mobile phones, wearable devices, and laptops become more portable and lightweight, display modules are also developing in the same direction. As the core component driving the display module, the DDIC also has requirements for larger resolution and smaller size. At the same time, due to the portability requirements of terminal devices, the battery capacity is reduced under the same conditions, which also places corresponding requirements on the power consumption of the DDIC.

[0026] When a DDIC drives a display module, the source and gate drive circuits consume most of the DDIC's power. In traditional GOA (Gate Driver On Array) circuits, the driving force (Tr and Tf) is not adjustable, resulting in the same driving force being maintained under all display conditions, which wastes the power of the GOA circuit's driving force. Furthermore, the input terminals of the GOA circuit cannot be individually configured; it can only support a fixed input terminal configuration scheme.

[0027] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0028] This application provides a drive control circuit that can be used to drive a shift register (i.e., a GOA circuit), such as... Figure 1 As shown, the drive control circuit includes: a gear selection circuit 100 electrically connected to an output terminal OUT.

[0029] The gear selection circuit 100 includes multiple first selection branches 101 connected in parallel. The control terminal, first terminal, and third terminal of each first selection branch 101 are electrically connected to a corresponding control signal terminal, a first level signal terminal, and the output terminal OUT, respectively. The multiple first selection branches 101 are configured such that when a control signal is received from the control signal terminal corresponding to the multiple first selection branches 101 for a first specified number of first selection branches 101, the first specified number of first selection branches 101 is turned on; the first specified number is greater than 0 and less than or equal to the total number of first selection branches 101 in the gear selection circuit 100.

[0030] The output terminal OUT can be electrically connected to the input terminal of the shift register. The shift register may include multiple input terminals, such as the STV (Start of Frame) signal input terminal and the clock signal input terminal. According to actual needs, in this embodiment of the application, the output terminal OUT of the drive control circuit can be electrically connected to any one of the input terminals of the shift register.

[0031] The drive control circuit provided in this application embodiment includes a gear selection circuit comprising multiple first selection branches 101. Under the control of a control signal, a specified number of first selection branches 101 can be turned on, causing the output terminal OUT to output a specified drive signal. The specified number is greater than 0 and less than or equal to the total number of first selection branches 101 in the gear selection circuit. Therefore, the number of turned-on first selection branches 101 can be flexibly adjusted within a certain range, thereby flexibly adjusting the drive signal output at the output terminal OUT, and consequently flexibly adjusting the driving force and power consumption of the driven shift register. In the gear selection circuit, the number of first selection branches 101 can be set according to actual needs.

[0032] Optional, such as Figure 2 As shown, the first selection branch 101 includes: a first transistor T1i (i is any value among 0, 1, 2, and 3); the gate, first terminal, and second terminal of the first transistor are electrically connected to the first control signal terminal, the first level signal terminal, and the output terminal OUT, respectively.

[0033] Reference Figure 2 The first transistors T10 to T13 can be turned on or off under the control of the control signals IN_P0 to IN_P3 provided by the first control signal terminal. When turned on, the signal of the first level signal terminal is transmitted to the output terminal OUT, and the corresponding drive voltage and drive current are output by the output terminal OUT, thereby realizing the regulation of the output of the drive control circuit by the first selection branch 101.

[0034] The first transistor can be a P-type transistor, such as a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, or an N-type transistor, such as an NMOS (Negative Channel Metal Oxide Semiconductor) transistor. The first level signal terminal can be a high-level signal terminal, used to provide a high-level signal VGH, or a low-level signal terminal, used to provide a low-level signal VGL.

[0035] Figure 2 Only a configuration where the first transistor is a P-type transistor and the first level signal terminal is a high-level signal terminal VGH is shown as an example. Figure 3 In the example, when the control signal IN_Pi (i is any value among 0, 1, 2, and 3) is high, the corresponding first transistor T1i is turned on, transmitting the high-level signal VGH to the output terminal OUT. When the control signal IN_Pi is low, the corresponding first transistor T1i is turned off. In other examples, other configurations are also possible.

[0036] By configuring different control signals IN_Pi, the first transistor T1i in different first selection branches 101 can be controlled to conduct in parallel, thereby achieving different OUT outputs.

[0037] Optional, such as Figure 3 As shown, the first selection branch 101 further includes: a second transistor T2i; the gate, first terminal, and second terminal of the second transistor are electrically connected to the second control signal terminal, the second level signal terminal, and the output terminal OUT, respectively.

[0038] Reference Figure 3 The second transistors T20 to T23 can be turned on or off under the control of the control signals IN_N0 to IN_N3 provided by the second control signal terminal. When turned on, the second level signal terminal is transmitted to the output terminal OUT, and the corresponding drive voltage and drive current are output by the output terminal OUT, thereby further realizing the regulation function of the first selection branch 101 on the output of the drive control circuit.

[0039] The channel type of the second transistor T2i can be different from that of the first transistor T1i. When the first transistor T1i is a P-type transistor, the second transistor T2i can be an N-type transistor; conversely, when the first transistor T1i is an N-type transistor, the second transistor T2i can be a P-type transistor. The signal provided by the second level signal terminal can be different from the signal provided by the first level signal terminal. When the first level signal terminal is a high-level signal terminal, the second level signal terminal can be a low-level signal terminal to provide a low-level signal VGL; conversely, when the first level signal terminal is a low-level signal terminal, the first level signal terminal can be a high-level signal terminal to provide a high-level signal VGH.

[0040] Figure 3 Only a configuration is shown as an example, where the first transistor T1i is a P-type transistor, the second transistor T2i is an N-type transistor, the first level signal terminal is a high-level signal terminal, and the second level signal terminal is a low-level signal terminal. Figure 3 In the example, when the control signal IN_Pi (i can be any value among 0, 1, 2, and 3) is high, the corresponding first transistor T1i is turned on, transmitting the high-level signal VGH to the output terminal OUT. When the control signal IN_Pi is low, the corresponding first transistor T1i is turned off. When the control signal IN_Ni (i can be any value among 0, 1, 2, and 3) is high, the corresponding second transistor T2i is turned on, transmitting the low-level signal VGL to the output terminal OUT. When the control signal IN_Ni is low, the corresponding second transistor T2i is turned off. Other configurations are possible in other examples.

[0041] Reference Figure 3 Each first selection branch 101 may include a first transistor T1i and a second transistor T2i. By configuring different control signals IN_Pi and IN_Ni, the first transistor and the second transistor in different first selection branches 101 can be turned on to achieve different Gout outputs.

[0042] In one alternative implementation, the drive current multiples of the transistors in at least a portion of the first selection branch 101 are different. In one example, when the first selection branch 101 includes a first transistor, for example... Figure 2 In the case shown, the drive current multiple of the transistor in the first selection branch 101 refers to the drive current multiple of the first transistor. When the first selection branch 101 includes both a first transistor and a second transistor, for example... Figure 3 As shown, the drive current multiple of the first transistor and the drive current multiple of the second transistor can be the same, and the drive current multiple of the transistor in the first selection branch 101 can refer to the same drive current multiple of the first transistor and the second transistor.

[0043] Setting different drive current multiples allows for the combination of multiple drive current multiples in the drive control circuit when different first selection branches 101 are turned on to form a parallel structure, resulting in multiple selectable gears. This increases the flexibility of adjustment. At the same time, by combining fewer first selection branches 101 with different drive current multiples, more selectable gears can be obtained with a smaller number of first selection branches 101. This reduces the number of first selection branches 101 and the size of the drive circuit while meeting the gear selection requirements, which is beneficial for achieving a thinner and lighter device.

[0044] Reference Figure 3 For example, in a gear selection circuit 100 comprising four first selection branches 101, and each first selection branch 101 comprising a first transistor T1i and a second transistor T2i, in a left-to-right order (or a right-to-left order, but here we take a left-to-right order as an example), the driving current multiple of the two transistors (i.e., T10 and T20) in the first first selection branch 101 is 1, the driving current multiple of the two transistors (i.e., T11 and T21) in the second first selection branch 101 is 1, the driving current multiple of the two transistors (i.e., T12 and T22) in the third first selection branch 101 is 2, and the driving current multiple of the two transistors (i.e., T13 and T23) in the fourth first selection branch 101 is 4.

[0045] Based on this drive current multiple configuration, by controlling Figure 3 The conduction states of the four first selection branches 101 shown can yield eight gear positions as shown in Table 1.

[0046] Table 1

[0047]

[0048]

[0049] Reference Figure 3Following the example in Table 1, if two transistors (T10 and T20) in the first first selection branch 101 are turned on, and the transistors in the remaining first selection branches 101 are turned off, the first gear position, gear 000, can be formed. In this gear position, the drive current multiple of the drive control circuit is: 1×1 + 1×0 + 2×0 + 4×0 = 1, which means the drive current is 1 times the rated current. If four transistors (T10, T20, T11, and T21) in both the first and second first selection branches 101 are turned on, and the transistors in the remaining first selection branches 101 are turned off, the second gear position, gear 001, can be formed. In this gear position, the drive current multiple of the drive control circuit is: 1×1 + 1×1 + 2×0 + 4×0 = 2, which means the drive current is 2 times the rated current. If the first first... When all four transistors (T10, T20, T12, and T22) in the first selection branch 101 and the third first selection branch 101 are turned on, and the transistors in the remaining first selection branches 101 are turned off, a third gear position, gear 010, can be formed. In this gear position, the drive current multiple of the drive control circuit is: 1×1 + 1×0 + 2×1 + 4×0 = 3, which means the drive current is 3 times the rated current. If all six transistors (T10, T20, T11, T21, T12, and T22) in the first to third first selection branches 101 are turned on, and the transistors in the fourth first selection branch 101 are turned off, a fourth gear position, gear 011, can be formed. In this gear position, the drive current multiple of the drive control circuit is: 1×1 + 1×1 + 2×1 + 4×0 = 4, which means the drive current is 4 times the rated current.

[0050] Continue to refer to Figure 3Following the example in Table 1, if all four transistors (T10, T20, T13, and T23) in the first and fourth first selection branches 101 are turned on, and the transistors in the remaining first selection branches 101 are turned off, a fifth gear, gear 100, can be formed. In this gear, the drive current multiple of the drive control circuit is: 1×1 + 1×0 + 2×0 + 4×1 = 5, which means it can output a 5 times drive current. If the transistors (T10, T20, T11, T21, T13, and T23) in the first, second, and fourth first selection branches 101 are turned on, and the transistor in the third first selection branch 101 is turned off, a fifth gear, gear 100, can be formed. The sixth gear, gear 101, is configured such that the drive current multiplier of the drive control circuit is 1×1 + 1×1 + 2×0 + 4×1 = 6, resulting in a 6-fold drive current output. If the transistors (T10, T20, T12, T22, T13, and T23) in the first, third, and fourth first selection branches 101 are all turned on, and the transistor in the second first selection branch 101 is turned off, the seventh gear, gear 110, is configured such that the drive current multiplier of the drive control circuit is 1×1 + 1×0 + 2×1 + 4×1 = 7, resulting in a 7-fold drive current output. If all the transistors (T10, T20, T12, T22, T13, and T23) in the first, third, and fourth first selection branches 101 are turned on, the seventh gear, gear 110, is configured such that the drive current multiplier of the drive control circuit is 1×1 + 1×0 + 2×1 + 4×1 = 7, resulting in a 7-fold drive current output. Figure 4 All transistors in the circuit are turned on, forming the eighth gear, gear 111. In this gear, the driving current multiple of the drive control circuit is: 1×1+1×1+2×1+4×1=8, which means that the driving current is 8 times the output.

[0051] Based on the drive current multiples of each gear shown in Table 1, it can be seen that by configuring different control signals, different first selection branches 101 can be turned on in parallel, thereby enabling different drive currents to be output. The more first selection branches 101 are connected in parallel, the larger the drive current output at the output terminal OUT, and the stronger the drive capability. Under the condition of ensuring normal display, the appropriate drive current output can be selected by selecting the gear. When the drive control circuit is integrated into the DDIC, the power consumption of the DDIC can be effectively reduced.

[0052] The implementation methods of each gear shown in Table 1 are only examples. The implementation methods of each gear are not limited to those in Table 1. For example, in order to obtain the driving current of gear 001, the transistors (i.e., T12 and T22) in the third first selection branch 101 can be turned on, and the transistors in the other first selection branches 101 can be turned off. In this case, the driving current multiple of the driving control circuit is: 1×0+1×0+2×1+4×0=2. As another example, in order to obtain the driving current of gear 101, the transistors (T12, T22, T13 and T23) in the third and fourth first selection branches 101 can be turned on, and the transistors in the other first selection branches 101 can be turned off. In this case, the driving current multiple of the driving control circuit is: 1×0+1×0+2×1+4×1=6.

[0053] In the same first selection branch 101, the first transistor T1i and the second transistor T2i can be turned on at different times, thereby combining more drive current multiples, obtaining more range selections, and making more precise adjustments to the output of the output terminal OUT.

[0054] In another alternative implementation, the drive current multiples of the transistors in each of the first selection branches 101 can be the same. In one example, when the first selection branch 101 includes a first transistor, for example... Figure 3 In the case shown, the drive current multiple of the transistor in the first selection branch 101 refers to the drive current multiple of the first transistor. When the first selection branch 101 includes both a first transistor and a second transistor, for example... Figure 4 As shown, the drive current multiple of the first transistor and the drive current multiple of the second transistor can be the same, and the drive current multiple of the transistor in the first selection branch 101 can refer to the same drive current multiple of the first transistor and the second transistor.

[0055] Setting the same drive current multiple also allows for the combination of multiple drive current multiples when different first selection branches 101 are turned on to form a parallel structure, resulting in multiple selectable levels, thereby increasing the flexibility of adjustment.

[0056] When the driving current multiple of the transistors in each of the first selection branches 101 is the same, the driving current multiple can be any value, which can be configured according to actual needs. The number of first selection branches 101 can also be configured according to actual needs. In one example, if you want to configure 8 levels, you can make the driving current multiple of the transistors in each of the first selection branches 101 1 times and set 8 first selection branches 101 at the same time, or make the driving current multiple of the transistors in each of the first selection branches 101 2 times and set 4 first selection branches 101 at the same time.

[0057] Optional, such as Figure 4 and Figure 5 As shown, the gear selection circuit 100 further includes a second selection branch 102. The control terminal, first terminal, and second terminal of the second selection branch 102 are electrically connected to their respective control signal terminal, ground terminal, and output terminal OUT. The second selection branch 102 is configured to conduct when it receives a control signal from its corresponding control signal terminal. The grounding state of the output terminal OUT can be adjusted.

[0058] In one alternative implementation, such as Figure 4 As shown, the second selection branch 102 includes a third transistor T3; the gate, first terminal, and second terminal of the third transistor are electrically connected to the third control signal terminal, the ground terminal, and the output terminal OUT, respectively. When the control signal EQ provided by the third control signal terminal is high, the third transistor T3 is turned on, and the output terminal OUT can output the ground signal AVSS (which can also be represented as GND). When the control signal EQ provided by the third control signal terminal is low, the third transistor T3 is turned off, and the output terminal OUT is floating.

[0059] The third transistor can be a P-type transistor or an N-type transistor. Figure 5 Only the case where the third transistor is an N-type transistor is shown as an example.

[0060] In another alternative implementation, such as Figure 5 As shown, based on the third transistor T3, the second selection branch 102 may further include a fourth transistor T4; the gate, first terminal, and second terminal of the fourth transistor are electrically connected to the fourth control signal terminal, the ground terminal, and the output terminal OUT, respectively. The fourth transistor is configured to conduct simultaneously with the third transistor under the control of the control signal provided by the fourth control signal terminal.

[0061] The channel type of the fourth transistor T4 can be different from that of the third transistor T3. For example, when the third transistor T3 is a P-type transistor, the fourth transistor T4 can be an N-type transistor, and when the third transistor T3 is an N-type transistor, the fourth transistor T4 can be a P-type transistor.

[0062] At the same time, the control signal EQ provided by the third control signal terminal is at the first level, and the control signal EQB provided by the fourth control signal terminal is at the second level, or the control signal EQ provided by the third control signal terminal is at the second level, and the control signal EQB provided by the fourth control signal terminal is at the first level; the first level is higher than the second level, that is, the first level is high level and the second level is low level.

[0063] When the control signal EQ provided by the third control signal terminal is high, the control signal EQB provided by the fourth control signal terminal is low. Both the third transistor T3 and the fourth transistor T4 are turned on, forming a parallel path. This not only grounds the output terminal OUT, but also releases static electricity through the parallel path, preventing static electricity from affecting the GOA circuit. When the control signal EQB provided by the third control signal terminal is low, the control signal EQ provided by the fourth control signal terminal is high, and both the third transistor T3 and the fourth transistor T4 are turned off.

[0064] Optional, such as Figure 6 As shown in the embodiment of this application, the shift register further includes: a plurality of gating circuits 200. The control terminal and the first terminal of each gating circuit 200 are electrically connected to the corresponding control signal terminal and the output terminal OUT, respectively, and the second terminal of each gating circuit 200 is electrically connected to the corresponding input terminal of the plurality of shift registers to be driven;

[0065] The multiple gating circuits 200 are configured such that when a control signal is received from the control signal terminal corresponding to the multiple gating circuits 200 for a second specified number of gating circuits 200, the second specified number of gating circuits 200 is turned on; the second specified number is greater than 0 and less than or equal to the total number of shift registers to be driven.

[0066] By setting multiple gating circuits 200, the same output terminal OUT can be connected to different shift registers. According to actual needs, at least one appropriate gating circuit 200 can be turned on to connect the output terminal OUT to the appropriate shift register, so as to output the drive signal used to drive the shift register.

[0067] In one example, each gating circuit 200 may include a fifth transistor (not shown in the figure), the gate, first terminal, and second terminal of the fifth transistor being electrically connected to the corresponding control signal terminal, output terminal OUT, and a corresponding shift register, respectively.

[0068] In another example, multiple gating circuits 200 and multiple shift registers to be driven can be connected one-to-one. In the same gating circuit 200, multiple parallel gating branches (not shown in the figure) can be set. Each gating branch can include a fifth transistor. The gate (which can be used as the control terminal of the gating branch), the first terminal (which can be used as the first terminal of the gating branch), and the second terminal (which can be used as the second terminal of the gating branch) of the fifth transistor are respectively connected to the corresponding control signal terminal, the output terminal OUT, and an input terminal of a shift register. Multiple gating branches in the same gating circuit 200 can be connected one-to-one with multiple input terminals in the same shift register.

[0069] When integrating the drive control circuit onto the DDIC, based on the above method, the DDIC can be mapped to different GOA circuits to achieve the output of the gate drive signal.

[0070] Based on the same inventive concept, embodiments of this application provide a drive control method, including:

[0071] A control signal is provided to a first specified number of first selection branches in the drive control circuit to turn on the first specified number of first selection branches and output a corresponding drive signal. The drive control circuit can be any of the drive control circuits provided in any embodiment of this application, and the control signals can be provided through the control signal terminals corresponding to the first specified number of first selection branches.

[0072] In one example, a high-level control signal can be provided to the first transistor in the first selected branch of the first specified number of transistors through the first control signal terminal to turn on the first transistor. A high-level signal can be provided to the second transistor in the first selected branch of the first specified number of transistors through the second control signal terminal to turn on the second transistor. The specific principle can be referred to the relevant content above, and will not be repeated here.

[0073] In an optional implementation, the drive control method provided in this application further includes: providing a control signal to a second selection branch in the drive control circuit to turn on the second selection branch and output a ground signal.

[0074] In one example, a high-level or low-level control signal can be provided to the third transistor in the second selection branch through the third control signal terminal to turn on the third transistor. Similarly, a high-level or low-level control signal can be provided to the fourth transistor in the second selection branch through the fourth control signal terminal to turn on the fourth transistor. The specific principle can be found in the previous related content, and will not be repeated here.

[0075] In an optional implementation, the drive control method provided in this application further includes: providing control signals to a second specified number of gating circuits in the drive control circuit, causing the second specified number of gating circuits to conduct, thereby connecting the drive control circuit with the input terminal of the corresponding shift register. This method allows for flexible configuration of the connection state between the output terminal OUT of the drive control circuit and the input terminal of the shift register. Each shift register input terminal can be configured individually, so that the output terminal OUT of the drive control circuit is not limited to driving a fixed shift register; it can select which shift register to drive, achieving multiple output schemes and providing good compatibility.

[0076] In one optional implementation, the drive control method provided in this application embodiment can be executed in any of a variety of drive modes, with different drive modes having different refresh rate ranges. The specific drive mode can be selected according to actual needs.

[0077] In one example, multiple drive modes can include the following four modes: AOD (Always On Display) mode, with a refresh rate typically below 30 Hz; Normal mode, with a refresh rate typically less than 120 Hz, such as 60 Hz or 90 Hz; HFR (High Frame Rate) mode, with a refresh rate typically above 120 Hz; and Max mode, with a refresh rate typically above 144 Hz. Each mode in this example can support a 16-set (cascaded 16 shift registers) configuration for the gate drive circuitry.

[0078] Based on the same inventive concept, embodiments of this application also provide a gate driving circuit, including: a plurality of cascaded shift registers, and a driving control circuit for driving the plurality of shift registers; the driving control circuit may be the driving control circuit provided in any embodiment of this application.

[0079] This application does not limit the number of cascaded shift registers in its embodiments; in one example, 16 shift registers can be cascaded. The gate driving circuit can be located on one side of the display panel or on both sides of the display panel, and the gate driving circuit on each side can include multiple cascaded shift registers.

[0080] In a gate drive circuit, there can be one or more drive control circuits. When the number of drive control circuits is less than the number of shift registers, some drive control circuits can drive multiple shift registers simultaneously.

[0081] Based on the same inventive concept, embodiments of this application also provide a display panel, including: the gate driving circuit provided in any embodiment of this application.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0084] The terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” “counterclockwise,” “axial,” “radial,” and “circumferential” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0085] In this specification, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top of" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. The first feature is in...

[0086] The second feature “below,” “under,” and “below” include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a lower horizontal height than the second feature.

[0087] It should be understood that when we say a component is "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be an intermediate component. Furthermore, the term "connected" or "coupled" as used here can include wireless connections or wireless coupling.

[0088] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0089] It should be further understood that the term "comprising" as used in the specification of this application means the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" as used herein includes all or any unit and all combination of one or more associated listed items.

[0090] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A drive control circuit, characterized in that, include: Electrically connected gear selection circuit and output terminal; The gear selection circuit includes multiple first selection branches connected in parallel. The control terminal, first terminal, and third terminal of each first selection branch are electrically connected to the corresponding control signal terminal, first level signal terminal, and output terminal, respectively. The plurality of first selection branches are configured such that when a control signal is received from the control signal terminal for a first specified number of first selection branches, the first specified number of first selection branches are turned on. The first specified quantity is greater than 0 and less than or equal to the total number of the first selection branches in the gear selection circuit; The gear selection circuit further includes: a second selection branch; the control terminal, first terminal, and second terminal of the second selection branch are electrically connected to the corresponding control signal terminal, ground terminal, and output terminal, respectively; the second selection branch is configured to be turned on when a control signal is received from the control signal terminal corresponding to the second selection branch. The second selection branch includes a third transistor and a fourth transistor; the gate, first electrode, and second electrode of the third transistor are electrically connected to the third control signal terminal, the ground terminal, and the output terminal, respectively; the gate, first electrode, and second electrode of the fourth transistor are electrically connected to the fourth control signal terminal, the ground terminal, and the output terminal, respectively; the fourth transistor is configured to conduct simultaneously with the third transistor under the control of the control signal provided by the fourth control signal terminal. The first selection branch includes: a first transistor and a second transistor; the gate, first electrode, and second electrode of the first transistor are electrically connected to a first control signal terminal, a first level signal terminal, and the output terminal, respectively; the gate, first electrode, and second electrode of the second transistor are electrically connected to a second control signal terminal, a second level signal terminal, and the output terminal, respectively. The drive control circuit further includes: multiple gating circuits; the control terminal and first terminal of each gating circuit are electrically connected to the corresponding control signal terminal and the output terminal, respectively, and the second terminal of each gating circuit is electrically connected to the corresponding input terminal of the multiple shift registers to be driven; the multiple gating circuits are configured such that when a control signal is received from the control signal terminal corresponding to the multiple gating circuits for a second specified number of gating circuits, the second specified number of gating circuits is turned on; the second specified number is greater than 0 and less than or equal to the total number of shift registers to be driven.

2. The drive control circuit according to claim 1, characterized in that, In at least some of the first selection branches, the drive current multiples of the transistors in different first selection branches are different.

3. A gate driving circuit, characterized in that, include: A cascaded array of shift registers, and a drive control circuit for driving the multiple shift registers; The drive control circuit is the drive control circuit as described in any one of claims 1-2.

4. A display panel, characterized in that, include: The gate drive circuit as described in claim 3.

5. A drive control method, characterized in that, include: A control signal is provided to a first selected branch of a first specified number in the drive control circuit to turn on the first selected branch and output a corresponding drive signal; the drive control circuit is the drive control circuit as described in any one of claims 1-2.

6. The drive control method according to claim 5, characterized in that, Also includes: A control signal is provided to the second selection branch in the drive control circuit to turn on the second selection branch and output a ground signal.

7. The drive control method according to claim 5 or 6, characterized in that, Also includes: A control signal is provided to a second specified number of gating circuits in the drive control circuit to turn on the second specified number of gating circuits and connect the output terminal of the drive control circuit to the input terminal of the corresponding shift register.

8. The drive control method according to claim 5 or 6, characterized in that, The drive control method is executed in any of the multiple drive modes, and the different drive modes have different refresh rate ranges.

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