Memory and method for decoupling thereof

Abstract

The present application provides a memory with calibration function. By setting the phase difference of clock signals applied to a plurality of comparators included in the memory, so that the comparator has the rising edge of the inverted data clock signal of another comparator to eliminate coupling noise, i.e. decoupling, whenever the calibration is started according to the falling edge of the data clock signal applied to the comparator. Thus, not only the misadjustment calibration can be performed, but also the adverse effects of coupling noise on the reference voltage during the calibration process can be eliminated, the comparison accuracy of the comparator is improved, and the performance of the memory is improved.

Description

Technical Field

[0001] This invention relates to a memory with calibration function, and more particularly to a memory capable of removing noise generated by coupling during calibration. Background Technology

[0002] Based on read / write capabilities, memory can be divided into Read-Only Memory (ROM) and Random Access Memory (RAM). The content stored in ROM is fixed and can only be read, not written. Random Access Memory, on the other hand, can be both read from and written to. Furthermore, Random Access Memory can be further divided into SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0003] DRAM stores data by measuring the amount of charge stored in capacitors. It requires periodic refresh circuitry to overcome capacitor leakage issues and is commonly used in large-capacity main memory, such as in computers, smartphones, and server memory. DRAM can be further divided into SDRAM, DDR SDRAM, and RDRAM.

[0004] SDRAM (Synchronous DRAM) is a clock-synchronous memory that operates based on the clock signal issued by the processor. Command signals defining actions and address signals specifying memory cells are sent in parallel and synchronized with the rising edge of the clock signal. DDR SDRAM (double data rate SDRAM) is a memory with double the data transfer rate, capable of data transfer on both the rising and falling edges of the clock signal; its data transfer speed is twice the clock frequency. Due to this increased speed, its transmission performance is superior to traditional SDRAM.

[0005] DDR SDRAM (hereinafter referred to as DDR) uses the DQ Strobe (DQS) signal as the source synchronization clock to select the data signal DQ and transmit data through the DQ bus. Command and address signals are synchronized only to the rising edge of the DQS clock signal, while data signals are synchronized to both the rising and falling edges of DQS. The clock, command, and address signals are unidirectionally input to the DDR from the processor, while DQS and DQ are bidirectional, input to the DDR during writing and output from the DDR during reading.

[0006] DDR receiver circuits typically have multiple (e.g., four) comparators connected in parallel. Each comparator determines whether to select the data signal by comparing the input data signal with a reference voltage signal. For example, as described below... Figure 1In the comparator COMP_A of the DDR receiver circuit, the voltage of the data signal DQ is compared with the reference voltage VREFDQ to obtain an output signal OUTA, which is either 0 or 1, output from the output terminal OUT. This output signal OUTA, via the subsequent circuit, feeds back a control signal to the comparator's control terminal CNT to calibrate the comparator's offset caused by circuit component mismatch, and thereby controls the clock signal DQSAb applied to the clock signal terminal CKb of the comparator COMP_A.

[0007] When a signal edge of the clock signal DQSAb triggers the aforementioned offset calibration, if the input data signal DQ is near the reference voltage VREFDQ, noise will be further coupled due to inherent signal noise and circuit component mismatch, leading to a decrease in comparator accuracy. Furthermore, to save power, a weaker voltage (lower voltage value) is typically used for the reference voltage VREFDQ during normal read / write operations. Therefore, the aforementioned coupling noise will significantly impact the reference voltage VREFDQ, thereby affecting the comparator and even the overall performance of the DDR. Summary of the Invention

[0008] This invention addresses the aforementioned problems by providing a memory with a calibration function that eliminates noise generated by coupling during calibration. By setting the phase difference of the clock signals applied to the multiple comparators included in the memory, each time a comparator begins calibration based on the falling edge of its data clock signal, the rising edge of another comparator's data clock signal is present to eliminate coupling noise, i.e., decoupling. This eliminates the adverse effects of coupling noise on the reference voltage through calibration, improving the comparator's comparison accuracy and enhancing memory performance.

[0009] The first aspect of the present invention relates to a memory with calibration function that can eliminate noise generated by coupling during calibration, comprising an input receiving unit, a calibration unit, and a storage unit.

[0010] The input receiving unit includes an interface for converting serial input to parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface. A frequency-divided first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal are respectively input to the clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator. A reference voltage signal is respectively input to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator. A data signal is respectively input to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator. The reference voltage signal and the data signal are compared, and a comparison result is output.

[0011] The calibration unit includes a calibration control unit, which generates control signals based on the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator, and applies these signals to the control terminals of each comparator to perform calibration.

[0012] The storage unit stores the data signal that has been selected after calibration by the calibration unit.

[0013] When the first comparator, the second comparator, the third comparator, and the fourth comparator each begin the calibration according to the control signal, the phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal are set to 0°, 90°, 180°, and 270°, respectively.

[0014] Preferably, the second aspect of the present invention is contained in the memory with calibration function as described in the first aspect of the present invention.

[0015] At the first falling edge of the first data clock signal, the control signal causes the first comparator to begin the calibration, while simultaneously using the first rising edge of the third data clock signal, which is inverted by the first data clock signal, to eliminate noise caused by coupling.

[0016] At the first falling edge of the second data clock signal, the first rising edge of the fourth data clock signal, which is inversely phase to the second data clock signal, is used to eliminate noise generated by coupling during the offset cancellation calibration.

[0017] Preferably, the third aspect of the present invention is contained in the memory with calibration function as described in the second aspect of the present invention.

[0018] After the first falling edge of the first data clock signal, each signal edge of the first data clock signal is out of phase with each signal edge of the third data clock signal.

[0019] After the first falling edge of the second data clock signal, each signal edge of the second data clock signal is out of phase with each signal edge of the fourth data clock signal.

[0020] Preferably, the fourth aspect of the present invention is in the memory with calibration function involved in any of the first to third aspects of the present invention.

[0021] The calibration control unit generates the control signal based on the control code from an external source, including:

[0022] A counter is used to count the control codes; and

[0023] The locking unit locks the control code when the comparator corresponding to the control code completes the calibration, triggering the data signal determined by the control code.

[0024] Preferably, the fifth aspect of the present invention is based on the memory with calibration function described in the fourth aspect of the present invention.

[0025] The start timing of the counter corresponding to the third data clock signal is set within a specified time after the first falling edge of the third data clock signal and before the first falling edge of the first data clock signal, so as to release the lock of the control code caused by the first falling edge of the third data clock signal.

[0026] Preferably, the sixth aspect of the present invention is in the memory with calibration function according to the fourth aspect of the present invention.

[0027] The start timing of the counter corresponding to the fourth data clock signal is set within a specified time after the first falling edge of the fourth data clock signal and before the first falling edge of the first data clock signal, so as to release the lock of the control code caused by the first falling edge of the fourth data clock signal.

[0028] Preferably, the seventh aspect of the present invention is a memory with calibration function as described in any of the first to fourth aspects of the present invention.

[0029] The memory is DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

[0030] An eighth aspect of the present invention provides a decoupling method for eliminating noise generated by coupling during calibration in a memory having a calibration function, wherein the memory includes:

[0031] An input receiving unit includes an interface for converting serial input to parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface. The unit inputs a frequency-divided first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal to the clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. It also inputs a reference voltage signal to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and inputs a data signal to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. The unit compares the reference voltage signal and the data signal and outputs a comparison result.

[0032] A calibration control unit, which generates control signals based on the comparison results of the first, second, third, and fourth comparators and applies them to the control terminals of the first, second, third, and fourth comparators to perform calibration; and

[0033] The storage unit stores at least the data signal selected by comparison by the first comparator, the second comparator, the third comparator, and the fourth comparator, as well as the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator.

[0034] When the first comparator, the second comparator, the third comparator, and the fourth comparator each begin the calibration according to the control signal, the phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal are set to 0°, 90°, 180°, and 270°, respectively.

[0035] Invention Effects

[0036] According to the present invention, a memory with a calibration function, by setting the phase difference of the clock signals applied to the plurality of comparators included in the memory, ensures that whenever a comparator begins calibration based on the falling edge of the data clock signal applied to that comparator, there is an inverted rising edge of the data clock signal of another comparator to eliminate coupling noise, i.e., decoupling. Thus, not only can offset calibration be performed, but the adverse effects of coupling noise on the reference voltage during calibration can also be eliminated, improving the comparator's comparison accuracy and enhancing the memory's performance. Attached Figure Description

[0037] Figure 1This is a block diagram illustrating the basic structure of a memory with calibration function according to Embodiment 1 of the present invention.

[0038] Figure 2 This is a circuit diagram illustrating the specific structure of the comparator in the memory according to Embodiment 1 of the present invention.

[0039] Figure 3 This is a timing diagram of signals in a memory according to Embodiment 1 of the present invention.

[0040] Figure 4 This is a timing diagram showing the control signals and clock signals of the memory according to Embodiment 1 of the present invention.

[0041] Figure 5 This is a schematic diagram of a circuit in a memory used to eliminate coupling noise according to Embodiment 1 of the present invention.

[0042] Figure 6 This is a timing diagram showing the signal for unlocking the control code in a memory with calibration function according to Embodiment 2 of the present invention.

[0043] Figure 7 This is a schematic diagram of the circuit for unlocking the control code in the memory according to Embodiment 2 of the present invention.

[0044] Figure 8 This is a timing diagram illustrating the unlocking of the control code in the memory according to Embodiment 2 of the present invention. Detailed Implementation

[0045] The invention is described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention may be practiced in different ways and should not be limited to the embodiments set forth herein. The dimensions and relative dimensions of layers and regions may be enlarged in the drawings for clarity.

[0046] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatial relative terms are intended to include different orientations of the device used or operated in addition to those shown in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features.

[0047] Unless otherwise specified, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms should be understood to have the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formalized manner, unless explicitly stated otherwise herein.

[0048] <Implementation Method 1>

[0049] The memory of this invention includes an input receiving unit, a storage unit, and a calibration unit. Below, an example of a DDR memory will be described, but its type is not particularly limited, as long as it possesses the calibration function described in this application.

[0050] Figure 1 This is a block diagram illustrating the basic structure of a DDR memory 100 with calibration function according to Embodiment 1 of the present invention.

[0051] like Figure 1 As shown, the input receiving unit 10 of the DDR memory 100 includes an interface (not shown) for converting serial input to parallel output, and a first comparator COMP_A, a second comparator COMP_B, a third comparator COMP_C, and a fourth comparator COMP_D connected in parallel to the interface. The reference voltage input terminals of the first comparator COMP_A, the second comparator COMP_B, the third comparator COMP_C, and the fourth comparator COMP_D are connected to each other and are respectively subjected to a reference voltage signal VREFDQ. The data signal input terminal DQ_IN of these comparators COMP_A, COMP_B, COMP_C, and COMP_D accepts the input of the data signal DQ to be stored.

[0052] In the input receiving unit 10, a single serial data clock signal DQS is divided into four parallel data clock signals—a first data clock signal DQSAb, a second data clock signal DQSBb, a third data clock signal DQSCb, and a fourth data clock signal DQSDb—through its interface. These signals are then input to the respective clock signal input terminals CKb of the four comparators. Specifically, the first data clock signal DQSAb is input to the clock signal input terminal CKb of the first comparator COMP_A, the second data clock signal DQSBb is input to the clock signal input terminal CKb of the second comparator COMP_B, the third data clock signal DQSCb is input to the clock signal input terminal CKb of the third comparator COMP_C, and the fourth data clock signal DQSDb is input to the clock signal input terminal CKb of the fourth comparator COMP_D.

[0053] In each comparator COMP_A, COMP_B, COMP_C, and COMP_D, the reference voltage signal VREFDQ and the data signal DQ are compared respectively, and digital output signals OUTA, OUTB, OUTC, and OUTD (0 or 1) are output from their respective output terminals OUT based on the comparison results.

[0054] Each digital output signal OUTA, OUTB, OUTC, and OUTD is input to the subsequent calibration unit 20. Figure 1 An example of the calibration unit 20 is shown. Specifically, each comparator is followed by a calibration control unit consisting of a driver, pulse generator, locking mechanism, etc. This calibration control unit generates a control signal based on the comparison result of its connected comparator and applies it to the comparator's control terminal CNT, controlling the comparator to perform calibrations to eliminate misalignments caused by circuit component mismatches. Its specific structure will be described later.

[0055] The DDR memory 100 also has a storage cell (not shown) for storing the data signal DQ selected after the above-mentioned offset calibration, as well as the above-mentioned output signals OUTA, OUTB, OUTC, OUTD, etc.

[0056] Figure 2 This is a circuit diagram illustrating the specific structure of the comparator in the memory according to Embodiment 1 of the present invention. Figure 1 An example of the structure of a DDR memory 100 with four comparators CMP_A, COMP_B, COMP_C, and COMP_D is shown. Figure 2 In this paper, these comparators are no longer distinguished, but a general exemplary structure of the comparator CMP is shown.

[0057] like Figure 2 As shown, the basic structure of the comparator COMP includes nine transistors P1 to P9. In this embodiment, transistors P1 to P5 are PMOS, and transistors P6 to P9 are NMOS. The gates of transistors P1, P6, and P7 are connected to the clock signal input terminal CKb of the comparator, the gate of transistor P2 is connected to the reference voltage input terminal VREFDQ, and the gate of transistor P3 is connected to the data signal input terminal DQ_IN. Furthermore, VSS and OUT in the figure represent the source voltage and the output terminal of the comparator COMP, respectively.

[0058] Figure 2In the diagram, three PMOS transistors P23, P24, and P25 are shown to the left of the reference voltage input terminal VREFDQ, and three PMOS transistors P28, P29, and P30 are shown to the right of the data signal input terminal DQ_IN. The gates of these transistors are connected to the comparator's control terminal CNT, through which the control signal CNT<5:0>, i.e., the control code CNT, is input. <0> CNT <1> CNT <2> CNT <3> CNT <4> CNT <5> . Figure 2 The "3.2 / 0.2", "1.6 / 0.2", and "0.8 / 0.2" markings above each control code correspond to the operating parameters of each transistor. The three transistors on each of the left and right sides act as tuning units, compensating for circuit component mismatches based on the control signals—that is, performing misalignment calibration—until the comparator's output signal OUT changes to "H" and locks onto the control code CNT<5:0>, thus completing the comparator's misalignment calibration. Specific details regarding "calibration" and "locking" will be explained later.

[0059] Figure 3 This is a timing diagram illustrating the signal in the memory according to Embodiment 1 of the present invention. In the diagram, the data signal DQ is 16 bits of data: 0, 1, ..., 9, a, b, ..., f. The clock signals DQS_t and DQS_c are inverted signals and, after frequency division, generate clock signals DQSAb, DQSBb, DQSCb, and DQSDb, respectively, which are input to the four comparators CMP_A, CMP_B, CMP_C, and CMP_D. Each comparator is triggered on the signal edge of its respective clock signal (falling edge in this embodiment), compares the reference voltage signal VREFDQ with the data signal DQ, and outputs its respective output signals OUTA, OUT, OUTC, and OUTD based on the comparison result.

[0060] As mentioned above, there is a possibility of circuit element mismatch in the comparator, and the input signal is inevitably distorted. Therefore, when the data signal DQ is close to the reference voltage signal VREFDQ or within a certain range of the reference voltage signal VREFDQ, the comparator will become unbalanced due to circuit element mismatch. Furthermore, the noise generated by coupling during calibration will affect the smaller reference voltage signal VREFDQ, resulting in a decrease in the performance and accuracy of the comparator.

[0061] In this regard, in Embodiment 1 of the present invention, the phases of the first data clock signal DQSAb, the second data clock signal DQSBb, the third data clock signal DQSCb, and the fourth data clock signal DQSDb input to the four comparators are set to 0°, 90°, 180°, and 270°, respectively. For example... Figure 3As shown, for the first bit "0" of the data signal DQ, its trigger timing corresponds to the falling edge of the first data clock signal DQSAb. Therefore, the comparison result for this data "0" is output from the output terminal OUTA of the first comparator CMP_A. It is important to note that, in addition to the falling edge of the first data clock signal DQSAb, the rising edge of the third data clock signal DQSCb is also set for the trigger timing of this data "0". That is, the trigger edge of the first bit "0" corresponds to both the falling edge of the first data clock signal DQSAb and the rising edge of the third data clock signal DQSCb. Similarly, the trigger edge of the second bit "1" corresponds to both the falling edge of the second data clock signal DQSBb and the rising edge of the fourth data clock signal DQSDb. The trigger edge of the third bit "2" corresponds to both the falling edge of the third data clock signal DQSCb and the rising edge of the first data clock signal DQSAb. The trigger edge of the fourth data bit "3" corresponds simultaneously to the falling edge of the fourth data clock signal DQSDb and the rising edge of the second data clock signal DQSBb. The trigger edges of the subsequent data bits 5 through 16 follow the same pattern.

[0062] Figure 4 This is a timing diagram illustrating the control signals and clock signals of the memory according to Embodiment 1 of the present invention. Figure 3 A diagram for further explanation.

[0063] exist Figure 4 In the example shown, the control signal CNT<5:0> and Figure 1 , Figure 2 The control signals shown are the same, so they will not be described again. Figure 4 In this clock signal, DQSAb, DQSBb, DQSCb, and DQSDb are initially high. Furthermore, the falling edge of DQSAb is aligned with the rising edge of DQSCb, the falling edge of DQSBb is aligned with the rising edge of DQSDb, the falling edge of DQSCb is aligned with the rising edge of DQSAb, and the falling edge of DQSDb is aligned with the rising edge of DQSBb. That is, the phases of DQSAb, DQSBb, DQSCb, and DQSDb are 0°, 90°, 180°, and 270°, respectively. Therefore, at the falling edge of any clock signal, there is always a rising edge of another clock signal that is inversely phase.

[0064] In this embodiment, when the falling edge of any clock signal triggers data and calibrates the comparator offset caused by circuit component mismatch, noise is generated due to coupling. To address this, this embodiment employs methods such as... Figure 4The phase of each clock signal is set as shown, meaning that when DQSAb triggers data on the falling edge, DQSCb has a corresponding rising edge to eliminate coupling noise. Similarly, when DQSBb, DQSCb, and DQSDb trigger data on the falling edge, DQSDb, DQSAb, and DQSBb each have a corresponding rising edge to eliminate coupling noise.

[0065] In particular, the aforementioned misalignment calibration begins when the control code CNT<5:0> is ready. To suppress or eliminate coupling noise, the first rising edge of the corresponding inverted DQSCb (180° phase) is set at the first falling edge of DQSAb (0° phase). These two inverted signal edges are used to eliminate the coupling noise generated by the first falling edge of DQSAb. Next, the first rising edge of the corresponding inverted DQSDb (270° phase) is set at the first falling edge of DQSBb (90° phase). These two inverted signal edges are used to eliminate the coupling noise generated by the first falling edge of DQSBb. Then, the first rising edge of the corresponding inverted DQSAb (180° phase) is set at the second falling edge of DQSCb (360° phase). These two inverted signal edges are used to eliminate the coupling noise generated by the second falling edge of DQSCb. At the second falling edge of DQSDb (with a phase of 90°), the first rising edge of the corresponding inverted DQSBb (with a phase of 270°) is set. These two inverted signal edges are used to eliminate the coupling noise generated by the second falling edge of DQSCb.

[0066] The principle of eliminating coupling noise in this embodiment will be explained below. Figure 5 This is a schematic diagram of a circuit in the memory involved in this embodiment that uses the first falling edge of the first data clock signal DQSAb and the first rising edge of the third data clock signal DQSCb to eliminate coupling noise.

[0067] Figure 5The diagram illustrates the structure of the first comparator COMP_A and the third comparator COMP_C, along with examples of the waveforms of their clock signals DQSAb and DQSCb. When the first falling edge of DQSAb is input to the gate of transistor P1 of the first comparator COMP_A (i.e., the clock signal input terminal), a pull-down effect is created on the voltage of transistor P1. Meanwhile, the coupling capacitance between transistor P1 and transistor P2 (the gate of transistor P2, i.e., the reference voltage input terminal VREFDQ) causes the voltage at transistor P6 to rise, equivalent to a rise in the reference voltage VREFDQ. At this time, by simultaneously inputting the first rising edge of DQSCb to the gate of transistor P1 in the third comparator COMP_C, i.e. the clock signal input terminal, the voltage of transistor P1 will be pulled up. The coupling capacitance generated between transistor P1 and transistor P2 in the third comparator COMP_C causes the increased reference voltage VREFDQ to discharge through transistor P6, i.e., the reference voltage VREFDQ decreases. Thus, the first falling edge of DQSAb and the first rising edge of DQSCb are out of phase, so that the rise and fall of the reference voltage VREFDQ cancel each other out, thereby eliminating the adverse effects caused by coupling noise.

[0068] Figure 5 The diagram also shows waveform examples of the second data clock signal DQSBb and the fourth data clock signal DQSDb, which are similar to those of DQSAb and DQSCb, and will not be described again.

[0069] As described above, in this embodiment, the data clock signals of each comparator connected in parallel in the memory are staggered by 90°. Specifically, when the first comparator, the second comparator, the third comparator, and the fourth comparator begin offset calibration, the phases of their respective data clock signals are 0°, 90°, 180°, and 270°, respectively. Thus, when data is triggered by the falling edge of any data clock signal, there is a corresponding rising edge of another inverted data clock signal to eliminate coupling noise. Therefore, not only can offset calibration be performed, but the adverse effects of coupling noise on the reference voltage during calibration can also be eliminated, improving the comparison accuracy of the comparators and improving the performance of the memory.

[0070] <Implementation Method 2>

[0071] In implementation method 1, coupling noise is eliminated by synchronizing the rising edge of another inverted data clock signal with the falling edge of the data clock signal when data is triggered. For example... Figure 4As shown, after the control signal CNT<5:0> is ready, the data clock signals DQSAb and DQSCb, DQSBb and DQSDb, DQSAb and DQSCb, DQSBb and DQSDb, DQSDb and DQSCb, DQSBb and DQSDb, DQSDb and DQSDb, DQSBb and DQSDb, DQSDb and DQSCb, DQSBb and DQSDb, DQSDb and DQSDb, DQSDb and DQSDb, DQSDb and DQSDb, DQSDb and DQSCb, DQSDb and DQSDb, DQSDb and DQSDb, DQSDb and DQSCb, DQSDb and DQSDb, DQSDb and DQSDb, DQSDb and DQSCb, DQSDb and DQSDb, DQSCb and DQSDb, DQSDb and DQSDb, DQSCb and DQSDb, DQSDb and DQSCb, DQSDb and DQSDb, DQSCb and DQSDb, ... If a falling edge of the data clock signal occurs before the control code CNT<5:0> is ready, the data determined by the error code will be triggered before calibration (before the counter starts and the control code is locked, which will be explained later), resulting in an incorrect calibration result.

[0072] In this embodiment 2, the error triggering and locking caused by the first falling edge of the data clock signals DQSCb and DQSDb that occur before calibration control are released, thereby eliminating the coupling noise that may be generated therefrom.

[0073] Figure 6 This is a timing diagram showing the signal for unlocking the control code in a memory with calibration function according to Embodiment 2 of the present invention. Figure 6 In the diagram, the waveforms of control signal CNT<5:0>, data clock signals DQSAb, DQSBb, DQSCb, and DQSDb are similar to... Figure 2 , Figure 3 The same applies as shown, so I will not repeat the explanation. However, Figure 6 The first falling edge of the data clock signals DQSCb and DQSDb is specifically marked. Furthermore, the structures used to eliminate the effects of the first falling edge of DQSCb and DQSDb are identical. Figure 6 The diagram shown is only an example of the corresponding signal waveform to eliminate the effect of the first falling edge of DQSDb.

[0074] On the first falling edge of DQSDb, since the counter of the control signal CNT<5:0> has not yet started, it will trigger data determined by the wrong control code, resulting in an incorrect calibration result. Figure 6LCK_CNT in the code is a waveform signal obtained by counting the locks of the control code using a counter. For example... Figure 6 As shown, the first falling edge of DQSDb causes the output OUTD of comparator CMP_D to change from 0 to 1, that is, from low level to high level. At this time, the control code is locked, thereby generating a pulse in LCK_CNT. The data determined by the locked control code at this time has not been calibrated, so it will affect the reliability of the comparator's comparison result. It is necessary to release the locked control code at this time. Therefore, in this embodiment 2, the control code input enable signal CODE_INPUT_EN is used to make the calibration of comparator COMP_D start before the first falling edge of DQSDb (calibration enabled, CODE_INPUT_EN becomes H level). Afterwards, the first falling edge of DQSDb arrives. At this time, the control code input enable signal CODE_INPUT_EN is changed to L level by the first falling edge of DQSDb. That is, the control code lock corresponding to the rising edge of the LCK_CNT pulse is registered at the falling edge of CODE_INPUT_EN. Subsequently, when the counter of control signal CNT<5:0> starts (i.e., the counter start signal CNT_START becomes H), CODE_INPUT_EN becomes H, and the registered lock is released, meaning the locked error control code is released. At this point, the counter of control signal CNT<5:0> has started, meaning the comparator's offset calibration is performed according to each subsequent falling edge of the clock signal. Finally, as... Figure 6 As shown, after a calibration is completed, at the third falling edge of the clock signal DQSDb, the output signal OUTD of the comparator COMP_D changes to H level again, and the signal CODE_INPUT_EN changes to L level. The correct control code for completing the calibration is locked, thereby triggering the correct data.

[0075] Figure 7 This is a schematic diagram showing the circuit used to unlock the control code in the memory according to Embodiment 2. Figure 7 As shown, the lock count signal LCK_CNT and the counter start signal CNT_START are respectively processed by a logic circuit composed of NOT gates, latches, etc. to generate the control code input enable signal CODE_INPUT_EN, thereby realizing... Figure 6 The signal waveform diagram shown here. Figure 7 This is just an example circuit structure; as long as it can be generated... Figure 6 The signal shown can be any logic circuit.

[0076] Combination Figure 1 The structure of the calibration unit 20 shown, for example, the calibration control unit in the memory of this embodiment generates a control signal based on a control code from an external source, and may include: a counter that counts the control code to obtain... Figure 1 The control code signal Counter_CNT<5:0> shown is used; and when the comparator completes calibration, the control code is locked and the locking unit of the data signal determined by the control code is triggered. The start timing of the counter corresponding to the third data clock signal DQSCb is set within a specified time after the first falling edge of DQSCb and before the first falling edge of DQSAb, so as to release the lock of the control code caused by the first falling edge of DQSCb, and the start timing of the counter corresponding to the fourth data clock signal DQSDb is set within a specified time after the first falling edge of DQSDb and before the first falling edge of DQSAb, so as to release the lock of the control code caused by the first falling edge of DQSDb.

[0077] Figure 8 This illustrates the use of memory in Embodiment 2 of the present invention. Figure 7 The diagram shows the timing sequence of the circuit performing the calibration operation. In the diagram, CNT_CODE<5:0> corresponds to... Figure 1 The control codes CNT<5:0> and CTR3b<5:0> (CNT_REG) shown are the count values ​​of the shift register, indicating the count value when the control code is locked. Figure 8 In this example, the third data clock signal DQSCb and its corresponding comparator COMP_C are used as examples. Therefore, the output signal OUTC of the comparator COMP_C is shown in the figure for illustration. Figure 8 The waveforms of each clock signal, DQS, DQSAb, DQSBb, DQSCb, and DQSDb, are also shown in the diagram.

[0078] like Figure 8 As shown, the four consecutive signal edges of the clock signal DQS serve as the falling edges of DQS, DQSAb, DQSBb, DQSCb, and DQSDb, respectively. That is, the data clock signals of each comparator are staggered by 90° phase. Specifically, when the first, second, third, and fourth comparators begin offset calibration, the phases of their respective data clock signals are 0°, 90°, 180°, and 270°, respectively. Thus, when data is triggered by the falling edge of any data clock signal, there is a corresponding rising edge of another inverted data clock signal to eliminate coupling noise. Therefore, not only can offset calibration be performed, but the adverse effects of coupling noise on the reference voltage during calibration can also be eliminated, improving the comparator's comparison accuracy and enhancing memory performance.

[0079] Moreover, for example Figure 6As shown, the first falling edge of DQSCb and DQSDb, controlled by CODE_LCK, CODE_INPUT_EN, and CNT_START, unlocks the erroneous control code. Then, the counter for control signal CNT<5:0> is started, and the correct control code for calibration is locked, triggering the correct data. This eliminates the influence of coupling noise during calibration, improves the comparator's accuracy, and enhances memory performance.

[0080] This invention has been described in detail, but the above embodiments are merely examples of all embodiments, and this invention is not limited thereto. Within the scope of this invention, embodiments can be freely combined, any constituent elements of each embodiment can be modified, or any constituent elements of each embodiment can be omitted.

[0081] Industrial practicality

[0082] The calibration-functional memory of the present invention can be applied to various types of memory, including SRAM such as SDR SRAM, DDR SRAM, QDR SRAM, and ZBT SRAM; DRAM such as SDRAM, DDR DRAM, and RDRAM; and ROM.

Claims

1. A memory with calibration function, capable of eliminating noise generated by coupling during calibration, characterized in that... ,include: An input receiving unit includes an interface for converting serial input to parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface. The unit inputs a frequency-divided first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal to the clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. It also inputs a reference voltage signal to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and inputs a data signal to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. The unit compares the reference voltage signal and the data signal and outputs a comparison result. A calibration control unit generates control signals based on the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator, and applies them to the control terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator to perform calibration. as well as The storage unit stores at least the data signal selected by comparison by the first comparator, the second comparator, the third comparator, and the fourth comparator, as well as the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator. When the first comparator, the second comparator, the third comparator, and the fourth comparator each begin the calibration according to the control signal, the phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal are fixed at 0°, 90°, 180°, and 270°, respectively. At the first falling edge of the first data clock signal, the control signal causes the first comparator to begin the calibration, while simultaneously using the first rising edge of the third data clock signal, which is inverted by the first data clock signal, to eliminate noise caused by coupling. At the first falling edge of the second data clock signal, the first rising edge of the fourth data clock signal, which is inversely phase to the second data clock signal, is used to eliminate noise generated by coupling during the calibration.

2. The memory as claimed in claim 1, characterized in that, After the first falling edge of the first data clock signal, each signal edge of the first data clock signal is out of phase with each signal edge of the third data clock signal. After the first falling edge of the second data clock signal, each signal edge of the second data clock signal is out of phase with each signal edge of the fourth data clock signal.

3. The memory as described in claim 1 or 2, characterized in that, The calibration control unit generates the control signal based on control codes from an external source, including: A counter is used to count the control codes; and The locking unit locks the control code when the comparator corresponding to the control code completes the calibration, triggering the data signal determined by the control code.

4. The memory as described in claim 3, characterized in that, The start timing of the counter corresponding to the third data clock signal is set within a specified time after the first falling edge of the third data clock signal and before the first falling edge of the first data clock signal, so as to release the lock of the control code caused by the first falling edge of the third data clock signal.

5. The memory as described in claim 3, characterized in that, The start timing of the counter corresponding to the fourth data clock signal is set within a specified time after the first falling edge of the fourth data clock signal and before the first falling edge of the first data clock signal, so as to release the lock of the control code caused by the first falling edge of the fourth data clock signal.

6. The memory as claimed in claim 1 or 2, characterized in that, The memory is DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

7. A decoupling method for eliminating noise generated by coupling during calibration in a memory with calibration function, characterized in that... , The memory includes: An input receiving unit includes an interface for converting serial input to parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface. The unit inputs a frequency-divided first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal to the clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. It also inputs a reference voltage signal to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and inputs a data signal to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. The unit compares the reference voltage signal and the data signal and outputs a comparison result. A calibration control unit generates control signals based on the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator, and applies them to the control terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator to perform calibration. as well as The storage unit stores at least the data signal selected by comparison by the first comparator, the second comparator, the third comparator, and the fourth comparator, as well as the comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator. When the first comparator, the second comparator, the third comparator, and the fourth comparator each begin the calibration according to the control signal, the phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal are fixed at 0°, 90°, 180°, and 270°, respectively. At the first falling edge of the first data clock signal, the control signal causes the first comparator to begin the calibration, while simultaneously using the first rising edge of the third data clock signal, which is inverted by the first data clock signal, to eliminate noise caused by coupling. At the first falling edge of the second data clock signal, the first rising edge of the fourth data clock signal, which is inversely phase to the second data clock signal, is used to eliminate noise generated by coupling during the calibration.

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