Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The method comprises: alternately stacking insulating layers and gate layers on one side of a substrate to form a stack structure, the stack structure comprising a storage region and a step region comprising a plurality of steps, wherein the gate layers cover the insulating layers and are exposed in each step; performing ion implantation on the exposed gate layers to form a gate sacrificial layer, wherein the gate sacrificial layer has a different etching selectivity ratio from the gate layers; and forming a gate line gap extending through the stack structure and to the substrate, and replacing at least the gate sacrificial layer with a metal layer via the gate line gap.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] Three-dimensional memory devices, with their high storage density and large capacity, have seen continuous development and widespread application in recent years. A 3D NAND structure comprises multiple layers of gate and insulating layers stacked vertically and alternately. The gate layers are typically made of polysilicon or conductive metal.

[0003] When polysilicon is used as the gate layer material, its conductivity is poor. Although doping can improve its conductivity, the improvement is limited, resulting in a high gate layer resistance and significant RC delay. This severely limits the signal transmission speed of the memory and affects its performance. The higher the storage density of a 3D memory, the more alternating gate and insulating layers are stacked. When a conductive metal is used for the gate layer, the sacrificial layers in the stacked structure need to be completely replaced with metal layers, which is complex and costly. Therefore, reducing the gate layer resistance, lowering the cost of the memory, and further reducing the RC delay are urgent problems to be solved. Summary of the Invention

[0004] Some embodiments of this application provide a three-dimensional memory and a method for its fabrication that can at least partially solve the problems existing in the prior art.

[0005] According to one aspect of this application, a method for fabricating a three-dimensional memory is provided, the method comprising: alternately stacking an insulating layer and a gate layer on a substrate side to form a stacked structure, the stacked structure including a storage region and a step region including a plurality of steps, wherein the gate layer covers the insulating layer and is exposed in each step; performing ion implantation on the exposed gate layer to form a gate sacrificial layer, wherein the gate sacrificial layer has a different etching selectivity than the gate layer; and forming a gate line slot penetrating the stacked structure and extending to the substrate, and replacing the gate sacrificial layer with at least a metal layer via the gate line slot.

[0006] In one embodiment of this application, the material of the gate layer may include polycrystalline silicon doped with a first ion.

[0007] In one embodiment of this application, ion implantation of the exposed gate layer may include: performing a second ion implantation on the gate layer doped with a first ion exposed at each step, wherein the second ion is different from the first ion.

[0008] In one embodiment of this application, ion implantation of the exposed gate layer may include: further implanting the first ion into the gate layer doped with the first ion exposed at each step.

[0009] In one embodiment of this application, the first ion may include a pentavalent ion.

[0010] In one embodiment of this application, the second ion may include a trivalent ion.

[0011] In one embodiment of this application, the etching selectivity ratio of the gate sacrificial layer to the gate layer may be greater than or equal to 10:1.

[0012] In one embodiment of this application, the ratio of the length of the metal layer to the length of the gate layer in the step region can be in the range of 1:5 to 1:10.

[0013] In one embodiment of this application, before forming the gate line slots that penetrate the stacked structure and extend to the substrate, the method may further include: forming a fill layer covering the stacked structure.

[0014] This application also provides a semiconductor device, which may include: a stacked structure, the stacked structure including an insulating layer and a sub-gate layer and a metal layer located between adjacent insulating layers; wherein the stacked structure includes a storage region and a step region in its extension direction, the step region including a plurality of steps, in which the metal layer covers the insulating layer.

[0015] In one embodiment of this application, the semiconductor device further includes a gate line slot structure that extends through the stacked structure, and the metal layer is also located between adjacent insulating layers of the storage region and close to the gate line slot structure.

[0016] In one embodiment of this application, the material of the sub-gate layer includes polycrystalline silicon doped with a first ion.

[0017] In one embodiment of this application, the ratio of the length of the metal layer to the length of the sub-gate layer in the step region in the direction extending along the stacked structure ranges from 1:5 to 1:10.

[0018] In one embodiment of this application, the first ion includes a pentavalent ion.

[0019] In one embodiment of this application, the semiconductor device further includes a fill layer covering the stacked structure and conductive contacts penetrating the fill layer of the storage region, wherein the conductive contacts are electrically connected to the metal layer.

[0020] This application also provides a three-dimensional memory, which includes any of the semiconductor devices described above.

[0021] In another aspect, this application provides a storage system that may include any of the three-dimensional memories described above; and a controller coupled to the three-dimensional memory and controlling the three-dimensional memory to store data.

[0022] According to an exemplary embodiment of this application, by replacing the gate sacrificial layer with a metal layer and using a metal material to replace polysilicon or polysilicon-doped material, the resistance Rwl of the gate layer in the storage region and the resistance Rc of the conductive contact connected to the gate layer can be reduced, further reducing the RC delay of the memory, improving the performance of the memory to a certain extent, and reducing the cost of the memory to a certain extent. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0024] Figure 1 This is a partial cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment;

[0025] Figure 2 A flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0026] Figure 3 This is a schematic cross-sectional view of the YZ plane after forming a stacked structure on a substrate according to an exemplary embodiment of this application;

[0027] Figure 4 This is a schematic cross-sectional view of the XY plane of a three-dimensional memory according to an exemplary embodiment of this application;

[0028] Figure 5 This is a cross-sectional view of the stepped structure formed according to an exemplary embodiment of this application;

[0029] Figure 6 This is a schematic cross-sectional view after ion implantation according to an exemplary embodiment of this application;

[0030] Figure 7 This is a cross-sectional view of the filling layer after it has been formed according to an exemplary embodiment of this application;

[0031] Figure 8A This is a schematic diagram of the etched step region YZ plane according to an exemplary embodiment of this application;

[0032] Figure 8B This is a schematic diagram of the etched YZ plane of the storage region according to an exemplary embodiment of this application;

[0033] Figure 8C This is a schematic diagram of the XY plane of the etched gate layer according to an exemplary embodiment of this application;

[0034] Figure 9 This is a schematic diagram of the XY plane after forming a metal layer according to an exemplary embodiment of this application;

[0035] Figure 10 This is a composite cross-sectional view of a semiconductor device according to an exemplary embodiment of this application, showing cross-sectional views along dashed line BB' and dashed line AA'; and

[0036] Figure 11A and Figure 11B This is a schematic diagram of a memory system according to an exemplary embodiment of this application. Detailed Implementation

[0037] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, the order in which the steps are described in this application does not necessarily indicate the order in which these steps occur in actual operation, unless otherwise expressly defined or deduced from the context.

[0039] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0040] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0041] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] Figure 1 This is a partial cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment, such as... Figure 1 As shown, the three-dimensional memory step region includes a substrate 110, a stacked structure 120, a fill layer 130, and conductive contacts 140. The stacked structure 120 may include an insulating layer 121 and a gate layer 122, with each step consisting of an insulating layer 121 and its corresponding gate layer 122. The conductive contacts 140 penetrate the fill layer 130, with one end contacting the gate layer 122 to form an electrical connection, and the other end connecting to the memory's peripheral circuitry. This allows the memory to control the gate layer via the peripheral circuitry, further transmitting control information to the memory region to achieve read and write operations.

[0043] The insulating layer 121 may be made of, for example, silicon oxide, and the gate layer 122 may be made of, for example, polysilicon. Since polysilicon has poor conductivity, the polysilicon in the gate layer 122 is often doped with other ions to improve its conductivity and reduce its resistance, for example, by doping polysilicon with ions of group III or group V elements. However, although the conductivity of the gate layer 122 can be improved by doping, the improvement is limited, resulting in a high gate layer resistance and a large RC delay, which greatly limits the transmission speed of memory signals and affects memory performance.

[0044] Figure 2 This is a flowchart illustrating the fabrication method of a three-dimensional memory 1000 according to an embodiment of this application. Figure 2 As shown, the method 1000 for fabricating a three-dimensional memory may include:

[0045] Step S100: Alternately stack insulating layers and gate layers on one side of the substrate to form a stacked structure, the stacked structure including a storage region and a step region including multiple steps, wherein the gate layer covers the insulating layer and is exposed in each step;

[0046] Step S200: Ion implantation is performed on the exposed gate layer to form a gate sacrificial layer, wherein the gate sacrificial layer and the gate layer have different etch selectivity ratios; and

[0047] Step S300: Form a gate line gap that extends through the stacked structure and into the substrate, and replace the gate sacrificial layer with a metal layer at least through the gate line gap.

[0048] The following will combine Figures 3 to 9 The specific processes for each step of the above preparation method 1000 are described in detail.

[0049] Step S100

[0050] First, according to some embodiments of this application, the method 1000 for fabricating a three-dimensional memory starts from step S100, in which an insulating layer 121 and a gate layer 122 are alternately stacked on one side of a substrate 110 to form a stacked structure 120, the stacked structure including a storage region and a step region. Figure 3 This is a schematic cross-sectional view of the YZ plane after forming a multilayer structure on a substrate according to an exemplary embodiment of this application. The substrate of the memory can be a single-layer substrate or a multilayer composite substrate; this application uses a single-layer substrate as an example. The substrate can be any suitable semiconductor material, as mentioned above, such as group III-V compounds like single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), or germanium-on-insulator (GOI). It is worth noting that the substrate 110 of this application can also be prepared using at least one of other semiconductor materials known in the art.

[0051] The stacked structure 120 includes alternately stacked insulating layers 121 and gate layers 122. The thicknesses of the multiple gate layers 122 may be the same or different, and the thicknesses of the multiple insulating layers 121 may also be the same or different. The thicknesses of the insulating layers 121 and gate layers 122 can be set according to specific process requirements. Furthermore, the stacked structure 120 may include multiple pairs of alternately stacked insulating layers 121 and gate layers 122. For example, the stacked structure 120 may include 32 pairs, 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 121 and gate layers 122. Although a specific number of pairs of insulating layers 121 and gate layers 122 has been exemplified here, other numbers of pairs of insulating layers 121 and gate layers 122 may be used in other embodiments, and this application does not limit this.

[0052] In an exemplary embodiment of this application, the material of the insulating layer 121 may include, for example, silicon oxide, and the material of the gate layer 122 may include, for example, doped polysilicon. Polysilicon has poor conductivity, which can be improved by doping it with other ions. The polysilicon may be doped with a first ion, which may include pentavalent ions, such as phosphorus ions or arsenic ions. The more insulating layers 121 and gate layers 122 in the stacked structure 120, the higher the integration density and the more memory cells formed. The number of stacked layers and the stacking height of the stacked structure 120 can be designed according to actual memory requirements; this application does not impose specific limitations on this. According to an exemplary embodiment of this application, by directly forming the insulating layer and gate layer on the substrate, the process is simple and the cost is low.

[0053] A schematic cross-sectional view of the three-dimensional memory in an exemplary embodiment of this application is shown in the figure below. Figure 4 As shown, the three-dimensional memory includes a storage region 10 and a stepped region 20. The three-dimensional memory also includes a channel structure 210 and a gate wire slot structure 220 that penetrate the stacked structure. To better illustrate the fabrication method of the three-dimensional memory according to the exemplary embodiment of this application, a cross-sectional view of the storage region 10 along the dashed line BB' and / or a cross-sectional view of the stepped region 20 along the dashed line AA' will be described in conjunction with the process flow.

[0054] In an exemplary embodiment of this application, after forming the stacked structure 120, a channel hole (not shown in the figure) can be formed through the stacked structure 120 and extending to the substrate 110, and a functional layer and a channel layer are sequentially formed on the inner wall of the channel hole, and an insulating material is filled in the channel hole to form a channel structure (not shown in the figure).

[0055] Figure 5 This is a cross-sectional view of the stepped structure formed according to an exemplary embodiment of this application. In an exemplary embodiment of this application, multiple trimming-etching cycles can be performed on the edge portions of the insulating layer 121 and gate layer 122 in the stacked structure 120 to give the stacked structure 120 one or more inclined edges, wherein the length of the insulating layer 121 and gate layer 122 pair on the side away from the substrate 110 is less than the length of the insulating layer 121 and gate layer 122 pair on the side closer to the substrate 110. In the stepped region 20, each pair of insulating layers 121 and the gate layer 122 covering its insulating layer 121 forms a step, such as... Figure 5As shown in the dashed box, multiple insulating layers 121 and gate layers 122 form a stepped structure. The stacked structure 120 may include a storage region 10 and a stepped region 20, wherein the storage region 10 is used for storing information, and the stepped region 20 is used for transmitting control information to the storage region 10 to realize operations such as reading, writing, and erasing of the storage region 10. The stepped region 20 may be located between adjacent storage regions 10, and two storage regions 10 may share a single stepped region 20 for information transmission. Alternatively, the storage region 10 may be located between adjacent stepped regions 20, and the storage region 10 may transmit information through two adjacent stepped regions 20.

[0056] Step S200

[0057] Then, a surface treatment process, such as ion implantation (IMP), can be used to process the gate layer 122 exposed in the step to form a gate sacrificial layer 122-2 that is partially connected to the gate layer 122 located in the memory region 10. Figure 6 This is a cross-sectional schematic diagram after ion implantation according to an exemplary embodiment of this application.

[0058] In an exemplary embodiment of this application, a first ion is further implanted into the gate layer exposed in the step region 20 to form a gate sacrificial layer 122-2. The first ion may include pentavalent ions, such as phosphorus ions or arsenic ions. That is, the ions implanted in the gate sacrificial layer 122-2 may have the same valence as the ions implanted in the gate layer 122-1 of the storage region, or they may be the same ions implanted in the gate layer 122-1 of the storage region. Since the ion concentrations in the gate layer 122-1 and the gate sacrificial layer 122-2 of the storage region are different, the gate layer 122-1 and the gate sacrificial layer 122-2 located in the storage region 10 may have different etching selectivity ratios. For example, the etching selectivity ratio of the gate sacrificial layer 122-2 and the gate layer 122-1 of the storage region may be greater than or equal to 10:1.

[0059] In another exemplary embodiment of this application, a second ion is implanted into the gate layer exposed in the step region 20 to form a gate sacrificial layer 122-2, wherein the second ion is different from the first ion. The first ion may include pentavalent ions, such as phosphorus ions and arsenic ions, and the second ion may include trivalent ions, such as boron ions and gallium ions. Since the valences of the implanted ions in the gate layer 122-1 and the gate sacrificial layer 122-2 of the storage region are different, N-type doped semiconductors and P-type doped semiconductors can be formed respectively. Therefore, the gate layer 122-1 and the gate sacrificial layer 122-2 located in the storage region 10 can have different etching selectivity ratios. For example, the etching selectivity ratio of the gate sacrificial layer 122-2 and the gate layer 122-1 of the storage region can be greater than or equal to 10:1.

[0060] Figure 7 This is a cross-sectional view showing the filling layer after it has been formed according to an exemplary embodiment of this application. Figure 7 As shown, after forming the stepped structure, a filler layer 130 covering the stacked structure 120 can be further formed. In an exemplary embodiment of this application, the filler layer 130 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The filler layer 130 can be an oxide or silicon oxide-based material, such as TEOS-based silicon oxide (TESO-based SiO2). Alternatively, the filler layer 130 can also be a multilayer structure. The surface of the filler layer 130 can be further planarized using processes such as chemical mechanical polishing, so that the filler layer 130 provides a substantially flat surface for the subsequently generated word line contact holes.

[0061] Step S300

[0062] In an exemplary embodiment of this application, a gate line slot 221 penetrating the stacked structure can be formed using, for example, a dry or wet etching process. The gate line slot 221 can be spaced apart from the channel structure in a direction parallel to the substrate 110, and penetrates the stacked structure 120 and extends into the substrate 110. Then, a dry or wet etching process can be used to etch the stacked structure through the gate line slot 221. The gate sacrificial layer 122-2 and the gate layer 122-1 of the memory region have different etching selectivity ratios, and the etching rate of the gate sacrificial layer 122-2 is greater than the etching rate of the gate layer 122-1 of the memory region. Figure 8A This is a schematic diagram of the etched step region YZ plane according to an exemplary embodiment of this application. Figure 8A As shown, the gate sacrificial layer in the stepped region has a faster etching rate and can be completely etched to form voids 123-2. Figure 8B This is a schematic diagram of the etched YZ plane of the storage region according to an exemplary embodiment of this application. Figure 8B As shown, the gate layer 122-1 of the memory region is etched at a slower rate, allowing for partial etching to form the groove 123-1 and the sub-gate layer 122-3. For a more intuitive representation, Figure 8C This is a schematic diagram of the etched XY plane of the gate layer according to an exemplary embodiment of this application. Figure 8C As shown, the gate sacrificial layer in the stepped region is completely etched to form a void 123-2, and the portion of the gate layer in the storage region near the gate line gap 221 is etched to form a groove 123-1 and a sub-gate layer 122-3. However, those skilled in the art will understand that while the gate sacrificial layer in the exemplary embodiment of this application is completely etched to form a void, it is also possible to etch only the portion of the gate sacrificial layer near the gate line gap, and this application does not limit this.

[0063] In an exemplary embodiment of this application, metal material can be deposited in the grooves 123-1, voids 123-2, and gate line slots 221 using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. By controlling the isotropic etching time, the metal material located inside the gate line slots 221 is removed, thereby forming a metal layer from the metal material located in the grooves 123-1 and voids 123-2. The material of the metal layer may include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof. Figure 9 This is a schematic diagram of the XY plane after forming a metal layer according to an exemplary embodiment of this application. Figure 9 As shown, the sub-gate layer 122-3 and the metal layer 124 together form a new gate layer. In the direction extending along the substrate, i.e., the Y direction, the ratio of the length of the metal layer 124 in the step region to the length of the metal layer 124 in the storage region can range from 1:5 to 1:10. For example, the ratio of the length of the metal layer 124 in the step region to the length of the metal layer 124 in the storage region is 1:7, and the ratio is 1:9. After forming the new gate layer, conductive contacts (not shown) penetrating the fill layer can be formed. One end of the conductive contact contacts the metal layer in the step region to form an electrical connection, and the other end connects to the peripheral circuitry of the memory, allowing the memory to control the new gate layer through the peripheral circuitry and further transmit control information to the storage region to achieve operations such as reading and writing to the storage region. In an exemplary embodiment of this application, the gate line gaps 221 can also be filled to form a gate line gap structure, wherein the filling material may include insulating materials such as silicon carbide and silicon oxide.

[0064] According to an exemplary embodiment of this application, a combination of a sub-gate layer and a metal layer is used as a new gate layer. For the step region, replacing polysilicon or polysilicon-doped material with metal material can reduce the resistance Rc of the connection between the conductive contact and the gate layer to a certain extent, further reducing the RC delay of the memory and improving the performance of the memory to a certain extent. For the storage region, replacing part of the polysilicon or polysilicon-doped material with metal material can reduce the resistance Rwl of the gate layer in the storage region.

[0065] This application also provides a semiconductor device, such as Figures 8A-8C and Figure 9 As shown, the semiconductor device may include a stacked structure 120. Figure 8BExemplarily, the semiconductor device may further include a substrate 110 and a gate line gap structure (not shown). The stacked structure 120 is located on one side of the substrate 110 and includes an insulating layer 121, sub-gate layers 122-3 and a metal layer 124 located between adjacent insulating layers, with the gate line gap structure extending through the stacked structure. The stacked structure 120 includes a storage region and a step region, and the metal layer 124 includes a portion of the storage region adjacent to the gate line gap structure and a portion of the step region covering the insulating layer.

[0066] In the exemplary embodiments of this application, the substrate 110 of the semiconductor device can be a single-layer substrate or a multi-layer composite substrate. This application uses a single-layer substrate as an example for illustration. The substrate can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), or germanium-on-insulator (GOI) and other group III-V compounds. It is worth noting that the substrate 110 of this application can also be prepared using at least one of other semiconductor materials known in the art. In the exemplary embodiments of this application, during the formation of the semiconductor device, part or all of the substrate can be removed; that is, the final semiconductor device may not include a substrate. The semiconductor device in this application is illustrative, but the structure of the semiconductor is not limited thereto.

[0067] like Figures 8A-8C and Figure 9 As shown, the stacked structure 120 includes an insulating layer 121 and sub-gate layers 122-3 and a metal layer 124 located between adjacent insulating layers 121. Figure 9 The gate line gap 221 penetrates the stacked structure. A top view of the sub-gate layer 122-3 and the metal layer 124 located between adjacent insulating layers 121 is shown below. Figure 9 As shown. In an exemplary embodiment of this application, the material of the insulating layer 121 may include, for example, silicon oxide, and the material of the sub-gate layer 122-3 may include, for example, doped polysilicon. Polysilicon has poor conductivity, which can be improved by doping it with other ions. The polysilicon may be doped with a first ion, which may include pentavalent ions, such as phosphorus ions or arsenic ions. The material of the metal layer 124 may include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. The sub-gate layer 122-3 and the metal layer 124 together form a new gate layer, wherein, in the direction extending along the substrate, i.e., the Y direction, the ratio of the length of the metal layer 124 in the step region to the length of the metal layer 124 in the storage region may range from 1:5 to 1:10. For example, the ratio of the length of the metal layer 124 in the step region to the length of the metal layer 124 in the storage region is 1:7, and the ratio of the length of the metal layer 124 in the step region to the length of the metal layer 124 in the storage region is 1:9.

[0068] Figure 10 This is a composite cross-sectional view of a semiconductor device according to an exemplary embodiment of this application, showing cross-sectional views along dashed lines BB' and AA'. In the exemplary embodiments of this application, as... Figure 10 As shown, the semiconductor device may further include a channel structure 150 extending through the stacked structure 120 and to the substrate 110, wherein the channel structure 150 includes a channel filling layer, a channel layer, and a functional layer in sequence from the core outwards. The semiconductor device may also include a gate line gap structure 220, which may include a filling material located inside the gate line gap, wherein the filling material may include insulating materials such as silicon carbide or silicon oxide. The semiconductor device may also include a filling layer 130 covering the stacked structure. The filling layer 130 may be an oxide or silicon oxide-based material, such as TEOS-based silicon oxide (TESO-based SiO2). Alternatively, the filling layer 130 may also be a multilayer structure. The semiconductor device may also include a conductive contact 140 extending through the filling layer 130, one end of which contacts the metal layer of the step region to form an electrical connection, and the other end is connected to the peripheral circuitry of the semiconductor device, allowing the semiconductor device to control the new gate layer through the peripheral circuitry, further transmitting control information to the memory region to achieve operations such as reading and writing to the memory region. This application may also provide a three-dimensional memory, wherein the unit memory may include the aforementioned semiconductor device. Although this application uses a floating gate (FG) semiconductor device as an example for description, those skilled in the art will understand that the sub-gate layer and metal layer of this application can also be applied as new gate layers to semiconductor devices or memories with other structures, and this application does not limit this application.

[0069] According to an exemplary embodiment of this application, a combination of polysilicon and a metal layer is used as a new gate layer. For the step region, replacing polysilicon or polysilicon-doped material with metal material can reduce the resistance Rc of the connection between the conductive contact and the gate layer to a certain extent, further reducing the RC delay of the memory and improving the performance of the memory to a certain extent. For the storage region, replacing part of the polysilicon or polysilicon-doped material with metal material can reduce the resistance Rwl of the gate layer in the storage region.

[0070] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the semiconductor structure described here, related or similar content will not be repeated.

[0071] The memory system of an exemplary embodiment of this application is as follows: Figure 11AAs shown, the controller 41 and a single memory 42 can be integrated into the memory system 400a. The controller 41 can control the memory 42 via, for example, a channel (not shown), and the memory 42 can perform operations based on the control of the controller 41. The memory 42 can receive commands and addresses from the controller 41 via the channel and access regions selected from the memory array in response to the address. More specifically, the controller 41 can send commands and addresses via the channel to perform the programming operation method 1000 described in any of the embodiments above, causing the memory 42 to perform the programming operation method.

[0072] In some exemplary embodiments, the controller 41 and one or more memories 42 can be integrated into various types of storage systems; in other words, memory systems 400a, 400b can be implemented and packaged into different types of final electronic products. Figure 11A In one example shown, controller 41 and memory 42 may be integrated into a memory card-based memory system 400a. The memory card may include PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash memory cards (UFS), etc. The memory card-based memory system 400a may also include a memory card connector 43 that couples it to a host (not shown).

[0073] The memory system of an exemplary embodiment of this application is as follows: Figure 11B As shown, controller 41 and multiple memories 42 can be integrated into memory system 400b. Controller 41 and multiple memories 42 can also be integrated into memory system 400b formed by a solid-state drive (SSD). The SSD may further include an SSD connector 43 that couples it to the host. In some embodiments, the storage capacity and / or operating speed of the SSD may be higher than that of a memory card.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: An insulating layer and a gate layer are alternately stacked on one side of a substrate to form a stacked structure, the stacked structure including a storage region and a step region including multiple steps, wherein the gate layer covers the insulating layer and is exposed in each step; Ion implantation is performed on the exposed gate layer to form a gate sacrificial layer; and A gate line slot is formed that penetrates the stacked structure and extends to the substrate; The gate sacrificial layer is removed by etching through the gate line gap to form a void. A portion of the gate layer in the memory region is removed by etching through the gate line gap to form a groove. The remaining gate layer forms a sub-gate layer. The etching rate of the gate sacrificial layer is greater than the etching rate of the gate layer in the memory region. The size of the groove in a first direction is smaller than the size of the void in a second direction. The first direction is from the sub-gate layer to the gate line gap, and the second direction is from the memory region to the step region. A metal layer is formed in the groove and the gap via the grid line slots.

2. The method according to claim 1, wherein, The material of the gate layer includes polycrystalline silicon doped with a first ion.

3. The method according to claim 2, wherein, Ion implantation of the exposed gate layer includes: A second ion implantation is performed on the gate layer doped with the first ion exposed at each step, wherein the second ion is different from the first ion.

4. The method according to claim 2, wherein, Ion implantation of the exposed gate layer includes: The first ion is further implanted into the gate layer, which is doped with the first ion and exposed at each step.

5. The method according to claim 2, wherein, The first ion includes pentavalent ions.

6. The method according to claim 3, wherein, The second ion includes trivalent ions.

7. The method according to claim 1, wherein, The etching selectivity ratio of the gate sacrificial layer to the gate layer is greater than or equal to 10:

1.

8. The method according to claim 1, wherein, In the direction extending along the substrate, the ratio of the length of the metal layer to the length of the gate layer in the stepped region ranges from 1:5 to 1:

10.

9. The method according to any one of claims 1 to 8, wherein, Before forming the gate line slots that penetrate the stacked structure and extend to the substrate, the method further includes: A filling layer is formed to cover the stacked structure.

10. A semiconductor device, characterized in that, include: A stacked structure and a gate line gap structure are disclosed, wherein the gate line gap structure extends through the stacked structure. The stacked structure includes an insulating layer and a sub-gate layer and a metal layer located between adjacent insulating layers. The stacked structure includes a storage region and a step region. The step region includes multiple steps, and in each step, the metal layer covers the insulating layer. The metal layer includes a first portion and a second portion. The first portion is located between the storage region and adjacent insulating layers of the step region, and between the sub-gate layer and the gate line gap structure. The second portion is located at the step position. Wherein, the size of the first part in the first direction is smaller than the size of the second part in the second direction, the first direction being the direction from the sub-gate layer to the gate line gap structure, and the second direction being the direction from the memory region to the step region.

11. The semiconductor device according to claim 10, wherein, The material of the sub-gate layer includes polycrystalline silicon doped with a first ion.

12. The semiconductor device according to claim 10, wherein, In the direction extending along the stacked structure, the ratio of the length of the metal layer to the length of the sub-gate layer in the stepped region ranges from 1:5 to 1:

10.

13. The semiconductor device according to claim 11, wherein, The first ion includes pentavalent ions.

14. The semiconductor device according to claim 10, wherein, The semiconductor device further includes: The filling layer covering the stacked structure, and A conductive contact penetrating a fill layer located in the storage area, wherein the conductive contact is electrically connected to the metal layer.

15. A three-dimensional memory, characterized in that, The three-dimensional memory includes a semiconductor device as claimed in any one of claims 10 to 14.

16. A storage system, characterized in that, include: The three-dimensional memory as described in claim 15; as well as The controller is coupled to the three-dimensional memory and controls the three-dimensional memory to store data.

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