Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure manufacturing method and a semiconductor structure, which comprises the following steps: providing a substrate, forming a plurality of bit lines spaced from each other on the substrate, a plurality of insulation structures corresponding to the plurality of bit lines and a barrier layer, forming a first filling hole between adjacent insulation structures, and covering the first filling hole and the insulation structures with the barrier layer; removing the barrier layer covered by a part of the insulation structures, forming a filling structure on the exposed insulation structures and the first filling hole, forming a second filling hole between adjacent filling structures, and the second filling hole is communicated with the first filling hole; and forming a capacitor contact structure in the first filling hole and the second filling hole. The application can solve the problem of short circuit between capacitor connection pads caused by residual metal.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] DRAM (Dynamic Random Access Memory) consists of multiple memory cells, each including a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor. The switching on and off of the transistor is controlled by the voltage signal on the word line, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] In this design, the capacitor is connected to a landing pad via its lower electrode to form an access path through the transistor and bit line. In existing technology, a metal material is first laid down, and then patterned to form multiple spaced-apart landing pads.

[0004] However, as the feature size of semiconductor integrated circuit devices continues to shrink, residual metal materials can cause short circuits between capacitor pads, reducing the yield of semiconductor structures. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure to address the problem of short circuits between capacitor connection pads caused by residual metal in the prior art.

[0006] To achieve the above objectives, in one aspect, the present invention provides a method for fabricating a semiconductor structure, comprising:

[0007] A substrate is provided, on which a plurality of spaced bit lines, a plurality of insulating structures corresponding to and covering the plurality of bit lines, and a barrier layer are formed, wherein a first filling hole is formed between adjacent insulating structures, and the barrier layer covers the first filling hole and the insulating structure;

[0008] Remove the barrier layer covering a portion of the insulating structure, and form a filling structure on the exposed insulating structure and the first filling hole, with a second filling hole communicating with the first filling hole formed between adjacent filling structures;

[0009] Capacitive contact structures are formed within the first filling hole and the second filling.

[0010] In one embodiment, the orthographic projection of the first filling hole on the substrate partially coincides with the orthographic projection of the second filling hole on the substrate;

[0011] Removing the barrier layer covering a portion of the insulating structure and forming a filling structure on the exposed insulating structure and the first filling hole includes:

[0012] A sacrificial layer is formed within the first filling hole, and the barrier layer covering a portion of the insulating structure is removed;

[0013] A filling structure is formed in a portion of the sacrificial layer and on the exposed insulating structure;

[0014] Remove the sacrificial layer.

[0015] In one embodiment, a sacrificial layer is formed within the first filling hole, and a barrier layer covering a portion of the insulating structure is removed, including:

[0016] A sacrificial layer is formed on the barrier layer;

[0017] The barrier layer covering a portion of the sacrificial layer and the insulating structure is etched back so that the top surface of the sacrificial layer is lower than the opening of the first filling hole.

[0018] In one embodiment, the distance between the top surface of the sacrificial layer and the opening of the first filling hole is 10 nm to 30 nm.

[0019] In one embodiment, the sacrificial layer is made of spin-coated dielectric layer or borosilicate glass.

[0020] In one embodiment, a fill structure is formed on a portion of the sacrificial layer and the exposed insulating structure, including:

[0021] A filler layer is formed on the insulating structure and the sacrificial layer;

[0022] The filling structure is formed by etching the filling layer using a mask, wherein the orthogonal projection of the mask onto the substrate partially coincides with the orthogonal projection of the first filling hole onto the substrate.

[0023] In one embodiment, the etching selectivity ratio of the filling layer to the insulating structure is greater than 3:1.

[0024] In one embodiment, the insulating structure is made of SiN, and the filling layer is made of SiBN or SiCN.

[0025] In one embodiment, a fill layer is formed on the insulating structure and the sacrificial layer, including:

[0026] SiBN is deposited on the insulating structure and the sacrificial layer using a furnace tube process to form the filling layer; or,

[0027] SiCN is deposited on the insulating structure and the sacrificial layer using a thin-film fabrication process to form the filling layer.

[0028] In one embodiment, the filling structure is formed by etching the filling layer using a mask, including:

[0029] A mask is formed on the filling layer;

[0030] Etching gas is introduced into the reaction chamber to etch the filling layer and form a filling structure;

[0031] Remove the mask.

[0032] In one embodiment, the etching gas includes C4F8 gas and C4F6 gas.

[0033] In one embodiment, the flow rate of C4F8 gas is 10 sccm to 50 sccm, and the flow rate of C4F6 gas is 15 sccm to 60 sccm.

[0034] In one embodiment, the pressure in the reaction chamber is 10 mtorr to 30 mtorr.

[0035] In one embodiment, a capacitive contact structure is formed within the first filling hole and the second filling, including:

[0036] A contact layer is formed on the filling structure and within the first filling hole and the second filling.

[0037] The contact layer on the filling structure is removed by a planarization process, and the first filling hole and the contact layer in the second filling form the capacitor contact structure.

[0038] In one embodiment, it further includes:

[0039] Multiple bit lines spaced apart from each other are formed on the substrate;

[0040] An insulating structure is formed one-to-one on the multiple bit lines using photolithography, and a first filling hole is formed between adjacent insulating structures.

[0041] A barrier layer is formed within the first filling hole and on the insulating structure.

[0042] The present invention also provides a semiconductor structure, which is prepared by the fabrication method provided in the above embodiments.

[0043] The method for fabricating the semiconductor structure and the semiconductor structure of the present invention have the following beneficial effects:

[0044] Multiple spaced bit lines, multiple insulating structures corresponding to and covering the bit lines, and a barrier layer are formed on the substrate. A first filling hole is formed between adjacent insulating structures. The barrier layer covers the first filling hole and the insulating structure. First, the barrier layer covering a portion of the insulating structure is removed, and a filling structure is formed on the exposed insulating structure and in the first filling hole. A second filling hole communicating with the first filling hole is formed between adjacent filling structures. Then, a capacitor contact structure is formed in the first and second filling holes. The capacitor contact structures are separated by the insulating structure and the filling structure, which can effectively prevent short circuits between the capacitor contact structures and improve the yield of the semiconductor structure. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic cross-sectional view of the structure obtained in the first step of a semiconductor structure fabrication method provided in related technologies;

[0047] Figure 2 A schematic cross-sectional view of the structure obtained in the second step of the semiconductor structure fabrication method provided in the related technology;

[0048] Figure 3 A schematic cross-sectional view of the structure obtained in the third step of the semiconductor structure fabrication method provided in the related technology;

[0049] Figure 4 A schematic cross-sectional view of the structure obtained in the fourth step of the semiconductor structure fabrication method provided in the related technology;

[0050] Figure 5 A flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0051] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S502 of the semiconductor structure fabrication method provided in one embodiment.

[0052] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S504 of the semiconductor structure fabrication method provided in one embodiment.

[0053] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S506 of the semiconductor structure fabrication method provided in one embodiment.

[0054] Figure 9 This is a flowchart of step S504 in a method for fabricating a semiconductor structure provided in one embodiment;

[0055] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S902 of the semiconductor structure fabrication method provided in one embodiment.

[0056] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S904 of the semiconductor structure fabrication method provided in one embodiment.

[0057] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S906 of the semiconductor structure fabrication method provided in one embodiment.

[0058] Figure 13 This is a flowchart of step S902 in a method for fabricating a semiconductor structure provided in one embodiment;

[0059] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S1302 of the semiconductor structure fabrication method provided in one embodiment.

[0060] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S1304 of the semiconductor structure fabrication method provided in one embodiment.

[0061] Figure 16 This is a flowchart of step S904 in a method for fabricating a semiconductor structure provided in one embodiment;

[0062] Figure 17 This is a schematic cross-sectional view of the structure obtained in step S1602 of the semiconductor structure fabrication method provided in one embodiment.

[0063] Figure 18 This is a schematic cross-sectional view of the structure obtained in step S1604 of the semiconductor structure fabrication method provided in one embodiment.

[0064] Figure 19 This is a flowchart of step S1604 in a method for fabricating a semiconductor structure provided in one embodiment;

[0065] Figure 20 This is a flowchart of step S506 in a method for fabricating a semiconductor structure provided in one embodiment;

[0066] Figure 21 This is a schematic cross-sectional view of the structure obtained in step S2002 of the semiconductor structure fabrication method provided in one embodiment.

[0067] Figure 22This is a schematic cross-sectional view of the structure obtained in step S2204 of the semiconductor structure fabrication method provided in one embodiment.

[0068] Figure 23 A flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0069] Figure 24 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment.

[0070] Explanation of reference numerals in the attached figures:

[0071] 1. Substrate; 2. Bit line; 3. First dielectric layer; 4. Via; 5. Barrier layer; 6. Capacitor contact layer; 7. Capacitor connection pad; 8. Second dielectric layer;

[0072] 10. Substrate; 20. Bit line; 30. Insulating structure; 31. First filling via; 40. Barrier layer; 50. Filling structure; 51. Second filling via; 52. Filling layer; 60. Capacitive contact structure; 61. Contact layer; 70. Sacrificial layer; 80. Mask. Detailed Implementation

[0073] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0075] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0076] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0079] As the feature size of semiconductor integrated circuit devices continues to shrink, the projected area of ​​capacitors on the substrate gradually decreases. To obtain larger capacitance, stacked layers can be fabricated on the substrate, and deep trenches can be formed within these stacked layers to expose capacitor connection pads. The sidewalls of these trenches provide the main plate area corresponding to the capacitor connection pads. Currently, the contact resistance at the capacitor connection pads is relatively high; this can be improved by increasing the area of ​​the capacitor connection pads.

[0080] In related technologies, after forming multiple spaced bit lines and multiple first dielectric layers corresponding to and covering the bit lines on a substrate, a via is formed between adjacent first dielectric layers, and a barrier layer is first deposited in the via and on the first dielectric layer. For example... Figure 1 As shown, the substrate 1 has multiple bit lines 2, each bit line 2 is covered with a first dielectric layer 3, and a connecting hole 4 is formed between adjacent first dielectric layers 3. A barrier layer 5 is deposited in the connecting hole 4 and on the first dielectric layer 3.

[0081] Then, a capacitor contact layer is laid on top of the barrier layer. For example... Figure 2 As shown, a capacitor contact layer 6 is laid inside the connecting hole 4 and on the barrier layer 5 on the first dielectric layer 3, and the capacitor contact layer 6 fills the connecting hole 4.

[0082] Then, the capacitor contact layer and barrier layer are patterned and etched to form multiple spaced capacitor connection pads located within the vias and on the adjacent first dielectric layer. For example... Figure 3 As shown, the capacitor contact layer 6 and the barrier layer 5 are patterned and etched into multiple capacitor connection pads 7 spaced apart from each other. Each capacitor connection pad 7 corresponds to a connecting hole 4. The capacitor connection pad 7 is located in the corresponding connecting hole 4 and on the first region of the first dielectric layer 3 adjacent to the connecting hole 4. The capacitor connection pads 7 are separated by a second region of the first dielectric layer 3. The second region is the region of the first dielectric layer 3 other than the first region.

[0083] Finally, a second dielectric layer is filled between the capacitor connection pads and inside the vias. For example... Figure 4 As shown, a second dielectric layer 8 is provided on the second region of the first dielectric layer 3 and on the capacitor connection pad 7 in the connecting hole 4. The second dielectric layer 8 on the capacitor connection pad 7 in the connecting hole 4 is connected to the second dielectric layer 8 on the second region of the first dielectric layer 3 adjacent to the connecting hole 4, and the second dielectric layer 8 on the second region of the first dielectric layer 3 is connected to the first dielectric layer 3.

[0084] In this design, the first dielectric layer 3 and the second dielectric layer 8 are SiN layers, the barrier layer 5 is a TiN layer, and the capacitor contact layer 6 is a W layer. The capacitor connection pads 7 extend from inside the through-hole 4 to the first region of the first dielectric layer 3 outside the through-hole 4, increasing the contact area and decreasing the contact resistance. Furthermore, the second dielectric layer 8 is provided between the capacitor connection pads 7, serving both insulating and supporting functions.

[0085] However, due to limitations in photolithography, as the feature size of semiconductor integrated circuit devices continues to shrink, residual capacitor contact layers and barrier layers are prone to appear in the patterned etching process. Residual capacitor contact layers and / or barrier layers can cause short circuits between capacitor connection pads, reducing the yield of semiconductor structures.

[0086] Based on the above reasons, the present invention provides a method for fabricating a semiconductor structure and a semiconductor structure. By changing the order in which the capacitor contact layer and the dielectric layer are formed, a dielectric layer with a specific pattern is formed first, and then the capacitor contact layer is filled between the dielectric layers. This can effectively avoid short circuits caused by residual capacitor contact layers during the patterning process, thereby improving the yield of the semiconductor structure.

[0087] Please see Figure 5 The present invention provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0088] Step S502: A substrate is provided, on which multiple bit lines spaced apart from each other, multiple insulating structures corresponding to and covering the multiple bit lines, and a barrier layer are formed. A first filling hole is formed between adjacent insulating structures, and the barrier layer covers the first filling hole and the insulating structure.

[0089] Figure 6 This is a cross-sectional view of the semiconductor structure after step S502 is performed in one embodiment. See also... Figure 6 The substrate 10 has multiple spaced bit lines 20, each bit line 20 is covered with an insulating structure 30, and a first filling hole 31 is formed between adjacent insulating structures 30. A barrier layer 40 is covered inside the first filling hole 31 and on the insulating structure 30.

[0090] Step S504: Remove the barrier layer covering a portion of the insulating structure, and form a filling structure on the exposed insulating structure and the first filling hole, and form a second filling hole communicating with the first filling hole between adjacent filling structures.

[0091] Figure 7 This is a cross-sectional view of the semiconductor structure after step S504 is performed in one embodiment. See also... Figure 7 The barrier layer 40 covering a portion of the insulating structure 30 has been removed and replaced with a filling structure 50. The filling structure 50 not only covers the exposed insulating structure 40, but also extends laterally to a portion of the first filling hole 31. A second filling hole 51 is formed between adjacent filling structures 50, and the second filling hole 51 communicates with the first filling hole 31.

[0092] Step S506: A capacitor contact structure is formed in the first filling hole and the second filling hole.

[0093] Figure 8 This is a cross-sectional view of the semiconductor structure after step S506 is performed in one embodiment. See also... Figure 8 The first filling hole 31 and the second filling hole 51 are filled with capacitor contact structures 60. The capacitor contact structures 60 extend from inside the first filling hole 31 to a part of the insulating structure 30 outside the first filling hole 31. The other part of the insulating structure 30 is provided with filling structures 50 to separate adjacent capacitor contact structures 60.

[0094] The above-described semiconductor structure fabrication method involves forming multiple spaced bit lines, multiple insulating structures corresponding to and covering the bit lines, and a barrier layer on a substrate. A first filling hole is formed between adjacent insulating structures. The barrier layer covers the first filling hole and the insulating structure. First, the barrier layer covering a portion of the insulating structure is removed, and a filling structure is formed on the exposed insulating structure and within the first filling hole. A second filling hole communicating with the first filling hole is formed between adjacent filling structures. Then, a capacitor contact structure is formed within the first and second filling holes. The capacitor contact structures are separated by the insulating structure and the filling structure, which can effectively prevent short circuits between the capacitor contact structures and improve the yield of the semiconductor structure.

[0095] In some embodiments, such as Figure 7As shown, the orthographic projection of the first filling hole 31 on the substrate 10 partially coincides with the orthographic projection of the second filling hole 51 on the substrate 10. That is, a portion of the orthographic projection of the first filling hole 31 on the substrate 10 coincides with a portion of the orthographic projection of the second filling hole 51 on the substrate 10, and another portion of the orthographic projection of the first filling hole 31 on the substrate 10 does not coincide with another portion of the orthographic projection of the second filling hole 51 on the substrate 10. For example, the non-coincident regions of the first filling hole 31 and the second filling hole 51 are located on opposite sides of the coincident regions.

[0096] In the above embodiments, the orthographic projection of the first filling hole on the substrate and the orthographic projection of the second filling hole on the substrate partially coincide. On the one hand, the second filling hole can communicate with the first filling hole, and on the other hand, the orthographic projection of the second filling hole on the substrate can also coincide with the orthographic projection of the insulating structure on the substrate. In this way, the capacitive contact structure formed in the first filling hole and the second filling hole can extend from inside the first filling hole to a part of the insulating structure outside the first filling hole. The contact area of ​​the capacitive contact structure is large and the contact resistance is small.

[0097] Accordingly, please refer to Figure 9 Step S504 includes:

[0098] In step S902, a sacrificial layer is formed in the first filling hole, and the barrier layer covering a portion of the insulating structure is removed.

[0099] Figure 10 This is a cross-sectional view of the semiconductor structure after step S902 is performed in one embodiment. See also... Figure 10 A sacrificial layer 70 is formed in the first filling hole 31. The sacrificial layer 70 covers a portion of the barrier layer 40. The portion of the barrier layer 40 that does not cover the sacrificial layer 70 has been removed. The barrier layer 40 only covers a portion of the insulating structure 30.

[0100] Step S904: A filling structure is formed on a portion of the sacrificial layer and the exposed insulating structure.

[0101] Figure 11 This is a cross-sectional view of the semiconductor structure after step S904 is performed in one embodiment. See also... Figure 11 A filling structure 50 is formed on a portion of the exposed insulating structure 30 and the sacrificial layer 70. A second filling hole 51 is formed between the filling structures 50. A portion of the second filling hole 51 extends to the exposed insulating structure 30, and another portion extends to the sacrificial layer 70 within the first filling hole 31.

[0102] Step S906: Remove the sacrificial layer.

[0103] Figure 12This is a cross-sectional view of the semiconductor structure after step S906 is performed in one embodiment. See also... Figure 12 The sacrificial layer 70 in the first filling hole 31 has been removed, and the second filling hole 51 can extend to the barrier layer 40 in the first filling hole 31.

[0104] In the above embodiments, a sacrificial layer is first formed within the first filling hole. This sacrificial layer occupies the space within the first filling hole, allowing the filling structure to be formed on the first filling hole. Simultaneously, the barrier layer covering a portion of the insulating structure is removed. The subsequently formed filling structure can then be integrated with the insulating structure, separating adjacent capacitor contact structures. Next, a filling structure is formed on a portion of the sacrificial layer and the exposed insulating structure. A second filling hole is formed between these filling structures. A portion of the second filling hole extends onto the exposed insulating structure, and another portion extends onto the sacrificial layer within the first filling hole. Finally, the sacrificial layer is removed, exposing the barrier layer within the first filling hole. The second filling hole and the capacitor contact structure formed within the first filling hole can extend from the barrier layer within the first filling hole to the insulating structure outside the first filling hole. The capacitor contact structure has a large contact area and low contact resistance.

[0105] In some embodiments, please refer to Figure 13 Step S902 includes:

[0106] Step S1302: A sacrificial layer is formed on the barrier layer.

[0107] Figure 14 This is a cross-sectional view of the semiconductor structure after step S1302 is performed in one embodiment. See also... Figure 14 Both the insulating structure 30 and the barrier layer 40 inside the first filling hole 31 are covered with a sacrificial layer 70, and the sacrificial layer 70 inside the first filling hole 31 fills the first filling hole 31.

[0108] Step S1304: Etch back the barrier layer covering a portion of the sacrificial layer and insulating structure so that the top surface of the sacrificial layer is lower than the opening of the first filling hole.

[0109] Figure 15 This is a cross-sectional view of the semiconductor structure after step S1304 is performed in one embodiment. See also... Figure 15 The portion of the sacrificial layer 70 above the opening of the first filling hole 31 is removed, and the portion of the barrier layer 40 not covering the sacrificial layer 70 is also removed, exposing a portion of the insulating structure 30.

[0110] In the above embodiments, a sacrificial layer is first formed on the barrier layer, and then the sacrificial layer and the barrier layer covering a portion of the insulating structure are etched back, so that the top surface of the sacrificial layer is lower than the opening of the first filling hole. Thus, while the sacrificial layer is formed in the first filling hole, the barrier layer covering a portion of the insulating structure is removed, achieving two goals at once, reducing process steps, improving production efficiency, and reducing implementation costs.

[0111] For example, such as Figure 15 As shown, the distance between the top surface of the sacrificial layer 70 and the opening of the first filling hole 31 is 10nm to 30nm, such as 10nm, 15nm, 20nm, 25nm, 30nm, etc.

[0112] In the above embodiments, the distance between the top surface of the sacrificial layer and the opening of the first filling hole is 10nm to 30nm, which effectively removes the barrier layer outside the first filling hole on the one hand, and retains the barrier layer inside the first filling hole on the other hand.

[0113] For example, the material of the sacrificial layer is SOD (Spin-on Dielectric) or BPSG (Boro-phospho-silicate Glass).

[0114] In the above embodiments, the sacrificial layer is made of SOD or BPSG, which can achieve the function of a sacrificial layer and has a low cost.

[0115] In some embodiments, please refer to Figure 16 Step S904 includes:

[0116] Step S1602: A filler layer is formed on the insulating structure and the sacrificial layer.

[0117] Figure 17 This is a cross-sectional view of the semiconductor structure after step S1602 is performed in one embodiment. See also... Figure 17 A filling layer 52 is formed on the insulating structure 30 outside the first filling hole 31 and on the barrier layer 40 inside the first filling hole 31, and the filling layer 52 fills the first filling hole 31.

[0118] Step S1604: A filling structure is formed by etching the filling layer through a mask, and the orthogonal projection of the mask on the substrate coincides with the orthogonal projection of the first filling hole on the substrate.

[0119] Figure 18 This is a cross-sectional view of the semiconductor structure after step S1604 is performed in one embodiment. See also... Figure 18A patterned mask 80 is formed on the filling layer 52, turning the filling layer 52 into a patterned filling structure 50. A second filling hole 51 is formed between the filling structures 50. A portion of the second filling hole 51 extends onto the insulating structure 30, and another portion extends into the first filling hole 31.

[0120] In the above embodiments, a filling layer is first formed on the insulating structure and the sacrificial layer to cover the entire surface. Then, the filling layer is etched by a mask to form a filling structure. The orthogonal projection of the mask on the substrate partially coincides with the orthogonal projection of the first filling hole on the substrate, so that a part of the area of ​​the second filling hole between the filling structures extends to the insulating structure and another part extends into the first filling hole. The capacitive contact structure formed in the second filling hole and the first filling hole can extend from the barrier layer inside the first filling hole to the insulating structure outside the first filling hole. The contact area of ​​the capacitive contact structure is large and the contact resistance is small.

[0121] For example, the etching selectivity ratio of the filler layer to the insulating structure is greater than 3:1, such as 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc.

[0122] In the above embodiments, the etching selectivity ratio of the filling layer to the insulating structure is greater than 3:1. When the filling layer is etched to form the filling structure, the insulating structure is etched less and remains essentially unchanged. This allows the orthogonal projection of the second filling hole on the substrate to partially overlap with the orthogonal projection of the first filling hole on the substrate. Consequently, the capacitive contact structure formed in the second filling hole and the first filling hole can extend from the barrier layer inside the first filling hole to the insulating structure outside the first filling hole.

[0123] For example, the insulating structure is made of SiN, and the filling layer is made of SiBN or SiCN.

[0124] In the above embodiments, the insulating structure is made of SiN, and the filling layer is made of SiBN or SiCN. On the one hand, the filling layer material is similar to the insulating structure material, which can be well integrated; on the other hand, the etching selectivity ratio of the filling layer to the insulating structure can be greater than 3:1.

[0125] Furthermore, the material of the capacitor contact structure is W, and the material of the barrier layer is TiN.

[0126] In the above embodiments, the material of the capacitor contact structure is W, and the material of the barrier layer is TiN. The barrier layer can form a transition between the filling structure, the insulating structure and the capacitor contact structure, which is beneficial for fixing the capacitor structure on the filling structure and the insulating structure. At the same time, the barrier layer can prevent the capacitor contact structure from penetrating into the filling structure and the insulating structure.

[0127] In other embodiments, the material of the capacitive contact structure may include, but is not limited to, metallic materials such as Co, Ni, Ti, Cu, and Al, and the material of the barrier layer may include, but is not limited to, at least one of cobalt layer, platinum layer, and titanium-tungsten layer.

[0128] In one implementation, step S1602 includes: depositing SiBN on the insulating structure and the sacrificial layer using a furnace tube process to form a filler layer.

[0129] In another implementation, step S1602 includes: depositing SiCN on the insulating structure and the sacrificial layer using a thin film fabrication process to form a filling layer.

[0130] In the above embodiments, when the filler layer material is SiBN, the filler layer is deposited using a furnace tube process; when the filler layer material is SiCN, the filler layer is deposited using a thin film process. Selecting the corresponding process for depositing the filler layer according to different materials is beneficial to improving the quality of the filler layer.

[0131] In some embodiments, please refer to Figure 19 Step S1604 includes:

[0132] Step S1902: A mask is formed on the filler layer, and the orthographic projection of the mask on the substrate partially coincides with the orthographic projection of the first filler hole on the substrate.

[0133] Specifically, step S1902 includes: laying photoresist on the filler layer; and patterning the photoresist using a photolithography process to form a mask.

[0134] Step S1904: Etching gas is introduced into the reaction chamber to etch the filling layer and form a filling structure.

[0135] Step S1906: Remove the mask.

[0136] In the above embodiments, a mask is first formed on the filling layer, and the orthographic projection of the mask on the substrate partially coincides with the orthographic projection of the first filling hole on the substrate. Then, etching gas is introduced into the reaction chamber to etch the filling layer to form a filling structure. The etching gas works with the mask to remove only the filling layer that does not cover the mask, so that the filling structure is located in both the first filling hole and a part of the insulating structure. The second filling hole between the filling structures extends to both the insulating structure and the first filling hole. The capacitive contact structure formed in the second filling hole and the first filling hole can extend from the barrier layer in the first filling hole to the insulating structure outside the first filling hole.

[0137] For example, the etching gas includes C4F8 gas and C4F6 gas.

[0138] In the above embodiments, the etching gases include C4F8 gas and C4F6 gas, which can etch the filling layer while preserving the insulating structure.

[0139] For example, the flow rate of C4F8 gas is 10 sccm to 50 sccm, and the flow rate of C4F6 gas is 15 sccm to 60 sccm. For instance, the flow rate of C4F8 gas is 10 sccm and the flow rate of C4F6 gas is 15 sccm; or, the flow rate of C4F8 gas is 30 sccm and the flow rate of C4F6 gas is 40 sccm; or, the flow rate of C4F8 gas is 50 sccm and the flow rate of C4F6 gas is 60 sccm; or, the flow rate of C4F8 gas is 50 sccm and the flow rate of C4F6 gas is 15 sccm; or, the flow rate of C4F8 gas is 10 sccm and the flow rate of C4F6 gas is 60 sccm, etc.

[0140] In the above embodiments, the flow rate of C4F8 gas is 10 sccm to 50 sccm, and the flow rate of C4F6 gas is 15 sccm to 60 sccm, resulting in a better etching morphology.

[0141] For example, the pressure in the reaction chamber is 10 mtorr to 30 mtorr, such as 10 mtorr, 15 mtorr, 20 mtorr, 25 mtorr, 30 mtorr, etc.

[0142] In the above embodiments, the pressure in the reaction chamber is 10 mtorr to 30 mtorr, resulting in a better etching morphology.

[0143] In one implementation, step S906 includes: removing the sacrificial layer using a wet etching technique.

[0144] In another implementation, step S906 includes removing the sacrificial layer using a vapor etching technique.

[0145] In the above embodiments, wet etching or steam etching is used to remove the sacrificial layer, which can effectively remove the sacrificial layer.

[0146] In some embodiments, please refer to Figure 20 Step S506 includes:

[0147] Step S2002: A contact layer is formed on the filling structure and inside the first filling hole and the second filling hole.

[0148] Figure 21 This is a cross-sectional view of the semiconductor structure after step S2002 is performed in one embodiment. See also... Figure 21A contact layer 61 is formed on the filling structure 50 and inside the first filling hole 31 and the second filling hole 51, and the contact layer 61 fills the first filling hole 31 and the second filling hole 51.

[0149] In step S2004, a planarization process is used to remove the contact layer on the filling structure, and the contact layers in the first filling hole and the second filling hole form a capacitor contact structure.

[0150] Specifically, step S2004 includes: grinding the contact layer using CMP (Chemical Mechanical Polishing) technology until the filling structure is exposed.

[0151] Figure 22 This is a cross-sectional view of the semiconductor structure after step S2004 is performed in one embodiment. See also... Figure 22 The contact layer 61 is ground until the filling structure 50 is exposed, and the contact layer 61 becomes a plurality of capacitor contact structures 60 spaced apart from each other, with the filling structure 50 located between the capacitor contact structures 60.

[0152] In the above embodiments, a contact layer is first formed on the filling structure and inside the first filling hole and the second filling hole. Then, a planarization process is used to remove the contact layer on the filling structure, leaving the contact layer inside the first filling hole and the second filling hole to form a capacitor contact structure, thus achieving low cost.

[0153] In some embodiments, please refer to Figure 23 The manufacturing method also includes:

[0154] Step S2302: Form multiple bit lines spaced apart from each other on the substrate.

[0155] In step S2304, an insulating structure is formed one-to-one on multiple bit lines using photolithography, and a first filling hole is formed between adjacent insulating structures.

[0156] Step S2306: A barrier layer is formed on the first filling hole and the second insulating structure.

[0157] In the above embodiments, multiple bit lines spaced apart from each other are first formed on the substrate, and then an insulating structure is formed one-to-one on the multiple bit lines using photolithography. A first filling hole is formed between adjacent insulating structures, and finally a barrier layer is formed on the first filling hole and the second insulating structure, thus providing the required substrate.

[0158] Please see Figure 24 A method for fabricating a semiconductor structure is provided, comprising the following steps:

[0159] Step S2402: A substrate is provided, on which multiple spaced bit lines, multiple insulating structures corresponding to and covering the multiple bit lines, and a barrier layer are formed. A first filling hole is formed between adjacent insulating structures, and the barrier layer covers the first filling hole and the insulating structure, as shown below. Figure 6 As shown.

[0160] Step S2404: A sacrificial layer is formed on the barrier layer, such as... Figure 14 As shown.

[0161] Step S2406: Etch back the barrier layer covering a portion of the sacrificial layer and insulating structure, such that the top surface of the sacrificial layer is lower than the opening of the first filling hole, as shown. Figure 15 As shown.

[0162] Step S2408: A fill layer is formed on the insulating structure and the sacrificial layer, such as... Figure 17 As shown.

[0163] Step S2410: A filling structure is formed by etching the filling layer using a mask, wherein the orthogonal projection of the mask on the substrate partially coincides with the orthogonal projection of the first filling hole on the substrate, such as... Figure 18 As shown.

[0164] Step S2412, remove the sacrificial layer, as follows Figure 12 As shown.

[0165] Step S2414: A contact layer is formed on the filling structure and inside the first filling hole and the second filling hole, such as... Figure 21 As shown.

[0166] Step S2416: A planarization process is used to remove the contact layer on the filling structure. The contact layer in the first and second filling holes forms a capacitor contact structure, such as... Figure 22 As shown.

[0167] Specifically, the substrate can be made of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0168] Shallow trench isolation (STI) structures can be formed within the substrate, which can isolate several spaced-apart active areas (AA) within the substrate.

[0169] In embodiments where the substrate includes a P-type substrate, the source region can be formed by implanting N-type ions; conversely, in embodiments where the substrate includes an N-type substrate, the source region can be formed by implanting P-type ions.

[0170] The active region can be either a P-type active region or an N-type active region. A P-type active region can be used to form an NMOS device, and an N-type active region can be used to form a PMOS device.

[0171] Chemical mechanical polishing (CMP) is used to planarize the upper surface of the substrate, thereby optimizing the device's performance and reliability. A sidewall protective material layer can be set as a stop layer during CMP. By setting an overpolishing time, a predetermined thickness of sidewall protective material layer is retained on the upper surface of the substrate, preventing damage to the substrate's upper surface from the CMP process. Furthermore, the retained predetermined thickness of sidewall protective material layer can prevent damage to the substrate's upper surface from subsequent etching processes.

[0172] The deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0173] It should be understood that, although Figure 5 , Figure 9 , Figure 13 , Figure 16 , Figure 19 , Figure 20 , Figure 23 and Figure 24 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 , Figure 9 , Figure 13 , Figure 16 , Figure 19 , Figure 20 , Figure 23 and Figure 24 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0174] The present invention also provides a semiconductor structure (not shown), which is prepared by the fabrication method provided in the above embodiments.

[0175] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a plurality of spaced bit lines, a plurality of insulating structures corresponding to and covering the plurality of bit lines, and a barrier layer are formed, wherein a first filling hole is formed between adjacent insulating structures, and the barrier layer covers the first filling hole and the insulating structure; Remove the barrier layer covering a portion of the insulating structure, and form a filling structure on the exposed insulating structure and the first filling hole, with a second filling hole communicating with the first filling hole formed between adjacent filling structures; Capacitive contact structures are formed within the first filling hole and the second filling.

2. The manufacturing method according to claim 1, characterized in that, The orthographic projection of the first filling hole on the substrate and the orthographic projection of the second filling hole on the substrate partially coincide; Removing the barrier layer covering a portion of the insulating structure and forming a filling structure on the exposed insulating structure and the first filling hole includes: A sacrificial layer is formed within the first filling hole, and the barrier layer covering a portion of the insulating structure is removed; A filling structure is formed in a portion of the sacrificial layer and on the exposed insulating structure; Remove the sacrificial layer.

3. The manufacturing method according to claim 2, characterized in that, Forming a sacrificial layer within the first filling hole and removing the barrier layer covering a portion of the insulating structure, including: A sacrificial layer is formed on the barrier layer; The barrier layer covering a portion of the sacrificial layer and the insulating structure is etched back so that the top surface of the sacrificial layer is lower than the opening of the first filling hole.

4. The manufacturing method according to claim 3, characterized in that, The distance between the top surface of the sacrificial layer and the opening of the first filling hole is 10 nm to 30 nm.

5. The manufacturing method according to claim 3, characterized in that, The sacrificial layer is made of spin-coated dielectric layer or borosilicate glass.

6. The manufacturing method according to claim 2, characterized in that, A filling structure is formed in a portion of the sacrificial layer and on the exposed insulating structure, comprising: A filler layer is formed on the insulating structure and the sacrificial layer; The filling structure is formed by etching the filling layer using a mask, wherein the orthogonal projection of the mask onto the substrate partially coincides with the orthogonal projection of the first filling hole onto the substrate.

7. The manufacturing method according to claim 6, characterized in that, The etching selectivity ratio between the filling layer and the insulating structure is greater than 3:

1.

8. The manufacturing method according to claim 7, characterized in that, The insulating structure is made of SiN, and the filling layer is made of SiBN or SiCN.

9. The manufacturing method according to claim 8, characterized in that, A fill layer is formed on the insulating structure and the sacrificial layer, comprising: SiBN is deposited on the insulating structure and the sacrificial layer using a furnace tube process to form the filling layer; or, SiCN is deposited on the insulating structure and the sacrificial layer using a thin-film fabrication process to form the filling layer.

10. The manufacturing method according to claim 6, characterized in that, The filling structure is formed by etching the filling layer using a mask, including: A mask is formed on the filling layer; Etching gas is introduced into the reaction chamber to etch the filling layer and form a filling structure; Remove the mask.

11. The manufacturing method according to claim 10, characterized in that, The etching gases include C4F8 gas and C4F6 gas.

12. The manufacturing method according to claim 10, characterized in that, The flow rate of C4F8 gas is 10 sccm to 50 sccm, and the flow rate of C4F6 gas is 15 sccm to 60 sccm.

13. The manufacturing method according to claim 10, characterized in that, The pressure in the reaction chamber is 10 mtorr to 30 mtorr.

14. The manufacturing method according to any one of claims 1 to 13, characterized in that, A capacitive contact structure is formed within the first filling hole and the second filling, comprising: A contact layer is formed on the filling structure and within the first filling hole and the second filling. The contact layer on the filling structure is removed by a planarization process, and the first filling hole and the contact layer in the second filling form the capacitor contact structure.

15. The manufacturing method according to any one of claims 1 to 13, characterized in that, Also includes: Multiple bit lines spaced apart from each other are formed on the substrate; An insulating structure is formed one-to-one on the multiple bit lines using photolithography, and a first filling hole is formed between adjacent insulating structures. A barrier layer is formed within the first filling hole and on the insulating structure.

16. A semiconductor structure, characterized in that, It is prepared by the manufacturing method described in any one of claims 1 to 15.

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