Semiconductor structure and method of fabrication

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a preparation method, and a preparation method of the semiconductor structure, which comprises the following steps: providing a substrate, forming an active pillar, a bit line, a word line and a storage structure, and the process steps for forming the storage structure comprise that: the word line and the storage structure have an isolation layer, a first conductive layer, a dielectric film and a second conductive layer are formed in sequence and continuously on the side surface of the isolation layer and the surface of the active pillar; the first conductive layer on the side surface of the isolation layer is etched and removed, the side surface of the dielectric film is exposed, the remaining first conductive layer serves as a first electrode plate, the remaining dielectric film serves as a first dielectric layer, and the second conductive layer serves as a second electrode plate. The semiconductor structure and the preparation method provided by the embodiment of the present disclosure can at least reduce the device line width and improve the storage density of the semiconductor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration density of integrated circuits while increasing the operating speed of memory and reducing its power consumption, the feature size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices is constantly shrinking. MOSFET devices face a series of challenges. For example, in order to reduce the linewidth of the device, semiconductor structures have begun to evolve from buried word line structures to Gate-All-Around (GAA) structures. However, the integration density of memory devices is mainly determined by the area occupied by a unit memory cell, meaning that the storage capacity is also limited by size.

[0003] How to reduce device linewidth and further increase storage density has become an important problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and fabrication method that at least helps to reduce device linewidth and increase storage density.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming active pillars and bit lines extending along a first direction, the bit lines being located on the surface of the substrate, the active pillars being spaced apart along a direction perpendicular to the surface of the substrate, each active pillar including a source region, a channel region, a drain region, and a support region, the bit lines being connected to one of the active pillars in the source region or the drain region; forming word lines extending along a second direction, the word lines being located between adjacent active pillars and surrounding the active pillars in the channel region; forming a plurality of memory structures, the memory structures being vertically stacked on the substrate, the memory structures being connected to the source region or the drain region. The active pillar of the polar region is connected to the other side. The memory structure surrounds the active pillar of the support region. The memory structure includes a first electrode plate, a first dielectric layer, and a second electrode plate stacked sequentially on the surface of the active pillar of the support region. The process steps for forming the memory structure include: an isolation layer between the word line and the memory structure; forming a continuous and sequentially stacked first conductive layer, dielectric film, and second conductive layer on the side of the isolation layer and the surface of the active pillar; etching away the first conductive layer located on the side of the isolation layer to expose the side of the dielectric film; the remaining first conductive layer serves as the first electrode plate; the remaining dielectric film serves as the first dielectric layer; and the second conductive layer serves as the second electrode plate.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate having bit lines extending along a first direction on its surface; a plurality of active pillars spaced apart along a direction perpendicular to the substrate surface, each active pillar including a source region, a channel region, a drain region, and a support region, the bit lines being connected to one of the active pillars in the source or drain region; word lines extending along a second direction, the word lines being located between adjacent active pillars and surrounding the active pillars in the channel region; and a plurality of memory structures vertically stacked on the substrate, each memory structure being connected to the other of the active pillars in the source or drain region, the memory structures surrounding the active pillars in the support region, each memory structure including a first electrode plate, a first dielectric layer, and a second electrode plate sequentially stacked on the surface of the active pillars in the support region, and an isolation layer being provided between the word lines and the memory structures.

[0007] The technical solutions provided in this disclosure have at least the following advantages:

[0008] This embodiment of the disclosure forms a memory structure stacked on a substrate surface, with the support region of the active pillars serving as the support layer for the memory structure. This allows for the improvement of the integration density of the 3D memory structure by stacking transistors and capacitor structures in a three-dimensional manner on the substrate surface, thereby increasing the storage density of the semiconductor structure. Furthermore, by changing the memory structure's extension from a direction perpendicular to the substrate to a direction parallel to the substrate, the linewidth in the vertical direction can be reduced. In addition, by forming a continuous and sequentially stacked first conductive layer, dielectric film, and second conductive layer on the side of the isolation layer and the surface of the active pillars, the first conductive layers on different active pillar surfaces are continuous, meaning they are connected. After forming the first conductive layer, dielectric film, and second conductive layer, this solution etches away the first conductive layer on the surface of the isolation layer, separating the first conductive layers on different active pillar surfaces. This avoids the problem of memory structure failure caused by interconnection between the first plates corresponding to different transistor structures. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with corresponding accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the accompanying drawings are not to be limited in scale. To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figures 1 to 17 A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of this disclosure;

[0011] Figures 18-34 A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to another embodiment of this disclosure;

[0012] Figure 35 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0013] Figure 36 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure;

[0014] Figure 37 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure;

[0015] Figure 38 A schematic cross-sectional view of a semiconductor structure along a C-C' section, provided in an embodiment of this disclosure;

[0016] Figure 39 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure;

[0017] Figure 40 A schematic cross-sectional view of a semiconductor structure along section A-A' provided in another embodiment of this disclosure;

[0018] Figure 41 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure;

[0019] Figure 42 This is a schematic cross-sectional view of a semiconductor structure along the C-C' section, provided as an embodiment of the present disclosure. Detailed Implementation

[0020] This disclosure provides a method for fabricating a semiconductor structure, forming a memory structure. The memory structure surrounds an active pillar in a support region, allowing the memory structure to be formed on a substrate surface in a 3D stacked manner and perpendicularly stacked on the substrate. This reduces the linewidth of the semiconductor structure while increasing the storage density within a limited cell area. Furthermore, in the step of forming the memory structure, etching removes the first conductive layer located on the side of the isolation layer, exposing the side of the dielectric film. The remaining first conductive layer serves as the first electrode, the remaining dielectric film serves as the first dielectric layer, and the second conductive layer serves as the second electrode. This avoids electrical connections between the first electrodes connected to different transistors along a direction perpendicular to the substrate surface, which could lead to memory structure failure and improve the stability of the semiconductor structure.

[0021] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0022] Figures 1 to 17 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor structure provided in an embodiment of this disclosure. Wherein, Figures 1 to 11 A cross-section along A-A' provided for an embodiment of this disclosure (reference) Figure 35 The schematic diagrams of each step in the preparation method of the semiconductor structure are shown below. Figures 12-17 A B-B' section (reference) provided for an embodiment of this disclosure Figure 35 The schematic diagrams of each step in the preparation method of the semiconductor structure are shown.

[0023] refer to Figure 1 or Figure 12 A substrate 100 is provided, and a first sacrificial film 101 and a semiconductor layer 102 are sequentially formed on the surface of the substrate 100 at intervals.

[0024] The substrate 100 may also be an initial substrate. In some embodiments, the material of the substrate 100 may be a semiconductor material. Specifically, the semiconductor material may be any one of silicon, germanium, silicon germanium, or silicon carbide.

[0025] In some embodiments, the semiconductor layer 102 is used to subsequently form active pillars. The material of the first sacrificial film 101 can be an oxide or germanium-silicon, and the oxide can include silicon oxide, aluminum oxide, or titanium oxide. The material of the semiconductor layer 102 can be silicon, germanium, doped polycrystalline silicon, undoped polycrystalline silicon, or amorphous silicon. The doped element can be an N-type element or a P-type element. The N-type element can be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type element can be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0026] refer to Figures 2 to 11 as well as Figures 13-17 Active pillars 110 and bit lines 130 extending along a first direction are formed. The bit lines 130 are located on the surface of the substrate 100. The active pillars 110 are spaced apart along a direction perpendicular to the surface of the substrate 100. Each active pillar 110 includes a source region 111, a channel region 112, a drain region 113, and a support region 114. The bit lines 130 are connected to one of the active pillars 110 in the source region 111 or the drain region 113. Word lines 120 extending along a second direction are formed. The word lines 120 are located on adjacent active pillars 110. The active pillars 110 of the channel region 112 are arranged between and surrounded by word lines; forming a plurality of memory structures 140, which are vertically stacked on the substrate 100. The memory structure 140 is connected to the other active pillar 110 of the source region 111 or the drain region 113. The memory structure 140 surrounds the active pillar 110 of the support region 114. The memory structure 140 includes a first electrode plate 141, a first dielectric layer 142 and a second electrode plate 143 stacked sequentially on the surface of the active pillar 110 of the support region 114.

[0027] In some embodiments, the first direction is Figure 2 The first direction is the Z direction, which is perpendicular to the surface of the substrate 100; the second direction is the Y direction, which is parallel to the surface of the substrate 100 (reference). Figure 13 The bit line 120 and word line 130 can be formed before the memory structure 140 is formed. In other embodiments, the first direction is the Y direction parallel to the surface of the substrate 100 (see reference). Figure 13 The second direction is Figure 2 In the Z direction perpendicular to the surface of the substrate 100, the memory structure can be formed first, followed by the bit lines and word lines.

[0028] In some embodiments, Figure 2 The semiconductor layer 102 shown is used to form the active pillar 110 (reference). Figure 11Bit line 130 is connected to the source region 111 of active pillar 110, and memory structure 140 is connected to the drain region 113 of active pillar 110. In other embodiments, bit line 130 is connected to the drain region 113 of active pillar 110, and memory structure 140 is connected to the source region 111 of active pillar 110.

[0029] In some embodiments, bit line 130 is a metallic bit line, and the material of bit line 130 can be metals such as tungsten, copper, molybdenum, and silver. Metals have low resistance, which is beneficial for improving the conductivity between bit line 130 and active pillar 110. In other embodiments, bit line 130 can be a semiconductor bit line, and the material of semiconductor bit line can be silicon, germanium, germanium-silicon, silicon carbide, or polycrystalline silicon. Furthermore, the semiconductor bit line is doped with the same type of dopant element as the semiconductor layer 102. The dopant element can act as a charge carrier, which can improve the migration and diffusion of charge carriers between bit line 130 and active pillar 110, thus improving the conductivity between bit line 130 and active pillar 110.

[0030] In some embodiments, word line 120 and channel region 112 of active pillar 110, and active pillar 110 of source region 111 and drain region 113 located at both ends of channel region 112 constitute a transistor structure; at least two transistor structures are provided along the direction from source region 111 to drain region 113, and the two transistor structures are electrically connected to the same bit line 130, so that the two transistor structures share bit line 130 and form a direction X parallel to substrate 100. The memory structure 140 located at the other end of the transistor structure can share a bit line 130, so that the embodiments of this disclosure can reduce the size of key devices and improve the performance of semiconductor devices and the stability of semiconductor structures while realizing three-dimensional stacking.

[0031] In some embodiments, word line 120 serves as the gate of a semiconductor structure. Word line 120 surrounds the channel region 112 of active pillar 110, i.e., the semiconductor structure is a GAA structure. The GAA structure can realize that the gate surrounds the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size. It also reduces the area occupied by word line 120 in the vertical direction, which is beneficial to enhance gate control performance and improve the integration of semiconductor structure.

[0032] In some embodiments, the word line 120 is made of any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride, forming a metal gate line. In other embodiments, the word line is made of doped polysilicon. Since the band gap of polysilicon is similar to that of the active pillar material serving as the channel, and the work function of polysilicon can be changed by controlling the doping concentration, it is beneficial to reduce the threshold voltage between the gate and the active pillar in the channel region. The doping element type of the doped polysilicon may be the same as or different from the doping element type of the active pillar in the channel region.

[0033] In some embodiments, the storage structure 140 can be a capacitor structure, and the support region 114 of the active pillar 110 can serve as a support layer for the capacitor structure. The semiconductor structure can form one transistor corresponding to one capacitor structure (1T-1C). Maximizing the area occupied by the storage structure within a limited device unit area is beneficial for improving storage density. The first electrode 141 serves as the lower electrode of the capacitor structure, and the second electrode 143 serves as the upper electrode of the capacitor structure. The second electrode 143 can be a common electrode for multiple capacitor structures. The storage structure 140 can be used as a storage element for storing data.

[0034] Specifically, refer to Figure 2 A bit line 130 extending along a first direction is formed, the bit line 130 being located on the surface of the substrate 100; a word line 120 extending along a second direction is formed, the word line 120 being located between adjacent semiconductor layers 102 and surrounding a portion of the semiconductor layer 102; an isolation layer 103 is formed, the isolation layer 103 being located between adjacent semiconductor layers 102, between the bit line 130 and the word line 120, and between the word line and the first sacrificial film 101.

[0035] In some embodiments, the semiconductor layer 102 surrounding the word line 120 is used to form the active pillar of the channel region. The isolation layer 103 serves as an insulating layer, and the material of the isolation layer 103 can be silicon nitride, silicon oxide, or other materials with a high dielectric constant K. Materials with a high dielectric constant K can include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0036] In some embodiments, reference Figure 2 The method for fabricating the semiconductor structure further includes: forming a gate dielectric layer 121, which is located between the word line 120 and the semiconductor layer 102, and between the word line 120 and the isolation layer 103. The gate dielectric layer 121 is formed before the word line 120. The material of the gate dielectric layer 121 can be silicon oxide, silicon carbide, silicon nitride, or other materials with high dielectric constant, used to suppress short-channel effects, thereby suppressing tunneling leakage current and other issues.

[0037] In some embodiments, reference Figure 2The step of forming word lines 120 includes: forming a conductive film surrounding the semiconductor layer 102; etching the conductive film to form spaced word lines 120; and forming a second isolation layer 122 located between adjacent word lines 120 along a direction Z perpendicular to the surface of the substrate 100, for isolating adjacent word lines 120 to prevent electrical connection between adjacent word lines 120 and short circuits. The material of the second isolation layer 122 can be silicon oxide, silicon carbide, or silicon nitride.

[0038] refer to Figure 3 as well as Figure 13 The first sacrificial film 101 and semiconductor layer 102 in the patterned portion form the first groove 104 (see reference). Figure 13 The bottom of the first groove 104 exposes the substrate 100; the first sacrificial film 101 exposed by the first groove 104 is removed by etching along the second direction, exposing the surface of the semiconductor layer 102.

[0039] It is worth noting that the side of the first groove 104 does not expose the side of the isolation layer 103, so that part of the first sacrificial membrane 101 is located in the first groove 104 (see reference). Figure 13 Between the first electrode and the isolation layer 103, a continuous first conductive layer is subsequently exposed through the first sacrificial film 101, so that the first conductive layer located in the isolation layer can be completely etched to form the first electrode. This ensures that there is no electrical connection between the first conductive layers corresponding to different transistors, i.e., an open circuit relationship, which can avoid the problem of memory structure failure.

[0040] It is understood that in other embodiments, a first groove may be formed to expose the side of the isolation layer, and the first conductive layer located in the isolation layer may be exposed by etching a portion of the width of the isolation layer.

[0041] refer to Figure 4 Along a third direction (parallel to the X direction of the substrate surface), the ends of the first sacrificial film 101 and the semiconductor layer 102 are patterned to expose the substrate 100. The first sacrificial film 101 and the semiconductor layer 102 are patterned to form a third groove 105, which is located between adjacent first grooves 104. The first sacrificial film 101 exposed by the third groove 105 is etched away along a second direction to expose the surface of the semiconductor layer 102. The third groove 105 is used to form an isolation structure between two adjacent rows of memory structures along the arrangement direction of the source and drain regions.

[0042] In other embodiments, three first grooves arranged sequentially along the X direction are first formed, and then a third groove is formed by etching the semiconductor layers on both sides of the middle first groove and the first sacrificial film, that is, increasing the width of one of the middle first grooves.

[0043] refer to Figure 5 as well as Figure 14 The first sacrificial film 101 and the semiconductor layer 102 are patterned to form the spaced semiconductor layers 102, which are used to form active pillars in the future.

[0044] refer to Figure 6 In the third groove 105 (reference) Figure 5 A second sacrificial film 107 is formed within the substrate 101; a first isolation layer 106 is formed on the surface of the substrate 100, the first isolation layer 106 also being located on the side of the first sacrificial film 101 and the side of the semiconductor layer 102. The material of the second sacrificial film 107 includes silicon nitride, titanium nitride, aluminum nitride, gallium nitride, or indium nitride, and the material of the first isolation layer 106 includes any one or more of silicon oxide, silicon nitride, and high dielectric constant materials, the high dielectric constant materials including hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0045] refer to Figure 7 Along the first groove 104 (reference) Figure 5 The first sacrificial film 101 is etched along the X direction, retaining a portion of the width of the first sacrificial film 101 located on the side of the isolation layer 103, the side of the second sacrificial film 107, and the side of the first isolation layer 106. The remaining first sacrificial film 101 can serve as a protective layer, preventing etching damage to the isolation layer 103 and the second isolation layer 106, and facilitating the exposure of the side of the first conductive layer by etching the remaining first sacrificial film 101, thereby facilitating the re-etching of the first conductive layer. In other embodiments, all of the first sacrificial film can be etched away, exposing the isolation layer, the second sacrificial film, and the side of the first isolation layer.

[0046] refer to Figure 8 as well as Figure 15 A first conductive layer 108, a dielectric film 109, and a second conductive layer 115 are formed continuously and sequentially on the side of the isolation layer 103 and the surface of the active pillar 110.

[0047] Specifically, a first conductive layer 108, a dielectric film 109, a metal film 116, and a semiconductor film 117 are continuously and sequentially stacked on the side of the first sacrificial film 101 and the side of the active pillar 110. The metal film 116 and the semiconductor film 117 together constitute the second conductive layer 115.

[0048] In some embodiments, the material of the first conductive layer 108 includes tungsten, tantalum, and molybdenum. The material of the dielectric film 109 may include silicon oxide, silicon nitride, and one or more high-dielectric-constant materials. The high-dielectric-constant materials may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. The metal film 116 serves as a metal barrier layer, and the material of the metal film 116 may be titanium nitride or tantalum nitride. The material of the semiconductor film 117 may be doped polycrystalline silicon or undoped polycrystalline silicon.

[0049] refer to Figure 9 The first sacrificial membrane 101 in the graphical portion of the region (reference) Figure 13 ) and semiconductor layer 102 (reference) Figure 13 A second groove 118 is formed, with the bottom of the second groove 118 exposing the substrate 100. The first sacrificial film 101 is removed, exposing the side surface of the first conductive layer 108. The second sacrificial film 107 is removed simultaneously with the removal of the first sacrificial film 101.

[0050] refer to Figure 10 as well as Figure 16 The first conductive layer 108 located on the side of the isolation layer 103 (reference) is etched away. Figure 9 ), exposing dielectric film 109 (reference) Figure 9 On the side of the first conductive layer 108 (reference) Figure 9 As the first electrode 141, the remaining dielectric film 109 (reference) Figure 9 ) as the first dielectric layer 142, the second conductive layer 115 (reference) Figure 9 ) as the second electrode plate 143.

[0051] In some embodiments, etching removes the first conductive layer 108 located on the side of the isolation layer 103 (see reference). Figure 9 Simultaneously, along the arrangement direction of the source region 111 and drain region 113 of the active pillar 110, a portion of the dielectric film 109 is thinned (refer to...). Figure 9 The reduced thickness of the dielectric film 109 ensures complete disconnection between continuous first conductive layers, preventing memory structure failure caused by connections between the first conductive layers corresponding to different transistors.

[0052] refer to Figure 11 as well as Figure 17 A dielectric layer 119 is formed, filling the space between the memory structure 140 and the isolation layer 103, as well as between the parallel-arranged memory structures 140. The dielectric layer 119 is also located on the surface of the second electrode 143. The material of the dielectric layer 119 may include silicon oxide, silicon nitride, or silicon oxide nitride. For example, silicon oxide may specifically be silicon oxide, silicon nitride may specifically be silicon nitride, and silicon oxide nitride may specifically be silicon carbonitride.

[0053] A second dielectric layer 123 is formed. Along a direction perpendicular to the surface of the substrate 100, the second dielectric layer 123 is located between the active pillars 110 of adjacent support regions 114. The second dielectric layer 123 is also located on the side of the first dielectric layer 142. The thickness of the first dielectric layer 142 located on the surface of the first electrode plate 141 is greater than or equal to the thickness of the first dielectric layer 142 located on the side of the second dielectric layer 123. In this way, it can be ensured that the continuous first conductive layers are completely disconnected, and the connection between the first conductive layers corresponding to different transistors is avoided, which would cause the memory structure to fail.

[0054] In some other embodiments, the material of the dielectric layer 119 is the same as that of the second dielectric layer 123, and the second dielectric layer 123 can be formed at the same time as the dielectric layer 119. This simplifies the process of preparing the dielectric layer 119 and the second dielectric layer 123, thereby simplifying the semiconductor structure preparation process and saving costs.

[0055] This embodiment of the present disclosure forms a memory structure 140 stacked on the surface of a substrate 100, with the support region 114 of the active pillar 110 serving as a support layer for the memory structure 140. In this way, the integration density of the 3D memory structure can be improved by stacking transistors and capacitor structures in a three-dimensional manner on the surface of the substrate 100, thereby increasing the storage density of the semiconductor structure. Moreover, the memory structure 140 is changed from extending in a direction perpendicular to the substrate 100 to extending in a direction parallel to the substrate 100, which can reduce the linewidth in the vertical direction. Furthermore, by forming a continuous and sequentially stacked first conductive layer 108, dielectric film 109, and second conductive layer 115 on the side of the isolation layer 103 and the surface of the active pillar 110, the first conductive layer 108 located on different active pillar 110 surfaces is continuous, that is, the active pillars 110 are connected. In this solution, after forming the first conductive layer 108, dielectric film 109, and second conductive layer 115, the first conductive layer 108 is etched back, specifically the first conductive layer 108 located on the surface of the isolation layer 103 is etched away, so that the first conductive layer 108 located on different active pillar 110 surfaces can be separated, avoiding the problem of memory structure 140 failure caused by the connection between the first plates 141 corresponding to different transistor structures.

[0056] This disclosure also provides a method for fabricating a semiconductor structure. Figures 18-34 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor structure provided in another embodiment of this disclosure. Wherein, Figures 18-26 A cross-section along A-A' provided for an embodiment of this disclosure (reference) Figure 39 The schematic diagrams of each step in the preparation method of the semiconductor structure are shown below. Figures 27-34 A B-B' section (reference) provided for an embodiment of this disclosure Figure 39The diagram shows the structural schematics corresponding to each step in the fabrication method of the semiconductor structure. Parts that are the same as or corresponding to those in the above embodiments will not be described in detail below.

[0057] refer to Figure 18 as well as Figure 27 A substrate 200 is provided, and a first sacrificial film 201 and a semiconductor layer 202 are sequentially formed on the surface of the substrate 200 at intervals.

[0058] refer to Figures 19-11 as well as Figures 28-17 Active pillars 210 and bit lines 230 extending along a first direction are formed. The bit lines 230 are located on the surface of the substrate 200. The active pillars 210 are spaced apart along a direction perpendicular to the surface of the substrate 200. Each active pillar 210 includes a source region 211, a channel region 212, a drain region 213, and a support region 214. The bit lines 230 are connected to one of the active pillars 210 in the source region 211 or the drain region 213. Word lines 220 extending along a second direction are formed. The word lines 220 are located on adjacent active pillars 210. The active pillars 210 of the channel region 212 are arranged between and surrounded by word lines; forming multiple memory structures 240, which are vertically stacked on the substrate 200. Each memory structure 240 is connected to the other of the active pillars 210 of the source region 211 or the drain region 213. The memory structure 240 surrounds the active pillars 210 of the support region 214. Each memory structure 240 includes a first electrode plate 241, a first dielectric layer 242, and a second electrode plate 243, which are sequentially stacked on the surface of the active pillars 210 of the support region 214. Along the X direction, the sides of the first electrode plate 241, the first dielectric layer 242, and the second electrode plate 243 are flush.

[0059] Specifically, refer to Figure 19 A bit line 230 extending along a first direction is formed, the bit line 230 being located on the surface of the substrate 200; a word line 220 extending along a second direction is formed, the word line 220 being located between adjacent semiconductor layers 202 and surrounding a portion of the semiconductor layer 202; an isolation layer 203 is formed, the isolation layer 203 being located between adjacent semiconductor layers 202, between the bit line 230 and the word line 220, and between the word line and the first sacrificial film 201.

[0060] refer to Figure 20 Along a third direction (the X direction parallel to the substrate surface), the ends of the first sacrificial film 201 and the semiconductor layer 202 are patterned to expose the substrate 200.

[0061] refer to Figure 21 A first isolation layer 206 is formed on the surface of the substrate 200. The first isolation layer 206 is also located on the side of the first sacrificial film 201 and the side of the semiconductor layer 202.

[0062] refer to Figure 28The first sacrificial film 201 and the semiconductor layer 202 are patterned to form the fifth groove 207.

[0063] In some embodiments, the fifth groove 207 is formed on the one hand for etching away the first sacrificial film, and on the other hand for forming a spaced semiconductor layer 202. The position of the semiconductor layer 202 corresponds to the semiconductor layer 202 surrounded by the word line 220, that is, forming a spaced active pillar.

[0064] refer to Figure 22 and Figure 29 The first sacrificial film 201 exposed by the fifth groove 207 is removed by etching along the second direction, exposing the surface of the semiconductor layer 202.

[0065] refer to Figure 23 and Figure 30 On the surface of the substrate 200, a first conductive layer 208, a dielectric film 209, a metal film 216, and a semiconductor film 217 are formed continuously and sequentially stacked on the side of the isolation layer 203, the side of the first isolation layer 206, and the side of the active pillar 210. The metal film 216 and the semiconductor film 217 together constitute the second conductive layer 215.

[0066] refer to Figure 31 The patterned semiconductor film 217 forms a fourth groove 218, which is arranged along the second direction and exposes the surface of the metal film 216.

[0067] refer to Figure 24 and Figure 32 The semiconductor film 217 is etched along the first direction until the side of the metal film 216 is exposed. At the same time, the semiconductor film 217 is etched along the arrangement direction of the source region 211 and the drain region 213 of the active pillar 210.

[0068] refer to Figure 25 as well as Figure 33 Along the arrangement direction of the source region 211 and the drain region 113 of the active pillar 210, a portion of the width of the metal film 216, the dielectric film 209 and the first conductive layer 208 are sequentially etched away until the side of the isolation layer 203 and the surface of the active pillar 210 are exposed.

[0069] refer to Figure 26 as well as Figure 34 A second dielectric layer 223 is formed. Along a direction perpendicular to the surface of the substrate 200, the second dielectric layer 223 is located between the active pillars 210 of the adjacent support region 214. The second dielectric layer 223 is also located on the side of the flush first electrode plate 241, the first dielectric layer 242 and the second electrode plate 243.

[0070] Accordingly, another embodiment of this disclosure provides a semiconductor structure prepared by the semiconductor structure preparation method described in the above embodiments. Figure 35 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 36 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure; Figure 37 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure; Figure 38 This is a schematic cross-sectional view of a semiconductor structure along the C-C' section, provided as an embodiment of the present disclosure.

[0071] refer to Figures 35-38 The semiconductor structure includes: a substrate 100, the surface of which has a bit line 130 extending along a first direction (a Z-direction perpendicular to the surface of the substrate 100); a plurality of active pillars 110, the active pillars 110 being spaced apart along a Z-direction perpendicular to the surface of the substrate 100, each active pillar 110 including a source region 111, a channel region 112, a drain region 113, and a support region 114, the bit line 130 being connected to the active pillars 110 of the source region 111; and a word line 120, the word line 120 extending along a second direction (a Y-direction parallel to the surface of the substrate 100), the word line 120 being bit... The active pillars 110 are located between adjacent active pillars 110 and the word line 120 surrounds the active pillars 110 of the channel region 112; a plurality of memory structures 140 are vertically stacked on the substrate 100, the memory structures 114 are connected to the active pillars 110 of the drain region 113, the memory structures 140 surround the active pillars 110 of the support region 114, and the memory structure 140 includes a first electrode plate 141, a first dielectric layer 142 and a second electrode plate 143 stacked sequentially on the surface of the active pillars 110 of the support region 114, and an isolation layer 103 is provided between the word line 120 and the memory structure 140.

[0072] In some embodiments, the substrate 100 can be made of a semiconductor material. Specifically, the semiconductor material can be any one of silicon, germanium, silicon germanium, or silicon carbide. The bit line 130 can be a metal bit line or a semiconductor bit line. The word line 120, the channel region 112 of the active pillar 110, and the active pillars 110 of the source region 111 and drain region 113 located at both ends of the channel region 112 constitute a transistor structure; at least two transistor structures are present along the direction from the source region 111 to the drain region 113, and the two transistor structures are electrically connected to the same bit line 130. Similarly, the memory structure 140 located at the other end of the transistor structure can share a bit line 130, enabling the present disclosure embodiments to achieve three-dimensional stacking while reducing the size of key devices by sharing the bit line 130, thereby improving the performance of the semiconductor device and the stability of the semiconductor structure. In other embodiments, the bit line 130 is connected to the active pillar 110 of the drain region 113, and in other embodiments, the memory structure 114 is connected to the active pillar 110 of the source region 111.

[0073] In some embodiments, at least two columns of memory structures 140 are included along the arrangement direction of the source region 111 and the drain region 113 of the active pillar 110; a dielectric layer 119 is provided between adjacent memory structures 140. The dielectric layer 119 is located between the first dielectric layer 142 of any memory structure 140 and the first dielectric layer 142 of the adjacent memory structure 140.

[0074] In some embodiments, along a direction perpendicular to the surface of the substrate 100, the thickness of the first dielectric layer 142 located on the surface of the first electrode 141 is greater than or equal to the thickness of the first dielectric layer 142 located on the side of the dielectric layer 119. The thickness of the first dielectric layer 142 located on the side of the dielectric layer 119 ranges from 5 nm to 100 nm, specifically 15 nm, 28 nm, 58 nm, or 89 nm, ensuring complete disconnection between the first electrode 141 electrically connected to different transistors, and preventing the memory structure 140 from failing due to connections between the first electrode 141 corresponding to different transistors. Similarly, the semiconductor structure also includes a second dielectric layer 123, located between the active pillars 110 of adjacent support regions 114 along a direction perpendicular to the surface of the substrate 100, and also located on the side of the first dielectric layer 142; the thickness of the first dielectric layer 142 located on the surface of the first electrode 141 is greater than or equal to the thickness of the first dielectric layer 142 located on the side of the second dielectric layer 123. The thickness of the first dielectric layer 142 located on the side of the second dielectric layer 123 ranges from 5nm to 100nm, specifically 19nm, 33nm, 65nm or 93nm.

[0075] In some embodiments, the semiconductor structure further includes: a gate dielectric layer 121 located between the word line 120 and the semiconductor layer 102 and between the word line 120 and the isolation layer 103; and a second isolation layer 122 located between adjacent word lines 120 along a direction Z perpendicular to the surface of the substrate 100, for isolating adjacent word lines 120 to prevent electrical connection between adjacent word lines 120 and short circuit.

[0076] The above embodiments are described using a semiconductor structure prepared by etching only the first conductive layer. Another embodiment of this disclosure also provides a semiconductor structure. The semiconductor structure provided in this other embodiment is substantially the same as the semiconductor structure provided in the foregoing embodiments. The main difference is that the sides of the first electrode plate, the first dielectric layer and the second electrode plate are flush along the arrangement direction of the source and drain regions of the active pillar. Figure 39 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure; Figure 40 A schematic cross-sectional view of a semiconductor structure along section A-A' provided in another embodiment of this disclosure; Figure 41 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure; Figure 42 This is a schematic cross-sectional view of a semiconductor structure along the C-C' section, provided as an embodiment of the present disclosure.

[0077] refer to Figures 39-42 The semiconductor structure includes: a substrate 200, the surface of which has a bit line 230 extending along a first direction (a Z-direction perpendicular to the surface of the substrate 200); a plurality of active pillars 210, the active pillars 210 being spaced apart along a Z-direction perpendicular to the surface of the substrate 200, each active pillar 210 including a source region 211, a channel region 212, a drain region 213, and a support region 214, the bit line 230 being connected to the active pillars 210 of the source region 211; and a word line 220, the word line 220 extending along a second direction (a Y-direction parallel to the surface of the substrate 200), the word line 220 being bit... The active pillars 210 are located between adjacent active pillars 210 and the word line 220 surrounds the channel region 212; a plurality of memory structures 240 are vertically stacked on the substrate 200, the memory structure 214 is connected to the active pillar 210 of the drain region 213, the memory structure 240 surrounds the active pillar 210 of the support region 214, and the memory structure 240 includes a first electrode plate 241, a first dielectric layer 242 and a second electrode plate 243 stacked sequentially on the surface of the active pillar 210 of the support region 214, and an isolation layer 203 is provided between the word line 220 and the memory structure 240.

[0078] In some embodiments, along the arrangement direction of the source region 211 and drain region 213 of the active pillar 210, the sides of the first electrode 241, the first dielectric layer 242, and the second electrode 243 are flush. The semiconductor structure further includes a second dielectric layer 223, which is located between the active pillars 210 of adjacent support regions 214 along a direction perpendicular to the surface of the substrate 200. The second dielectric layer 224 is also located on the flush sides of the first electrode 241, the first dielectric layer 242, and the second electrode 243.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; An active pillar and a bit line extending along a first direction are formed, the bit line being located on the substrate surface, the active pillars being spaced apart along a direction perpendicular to the substrate surface, the active pillars including a source region, a channel region, a drain region, and a support region, and the bit line being connected to one of the active pillars of the source region or the drain region. A word line is formed extending in a second direction, the word line being located between adjacent active posts and the word line surrounding the active posts of the channel region; Multiple memory structures are formed and vertically stacked on the substrate. Each memory structure is connected to another active pillar of the source or drain region. The memory structure surrounds the active pillar of the support region. Each memory structure includes a first electrode plate, a first dielectric layer, and a second electrode plate stacked sequentially on the surface of the active pillar of the support region. The process steps for forming the memory structure include: An isolation layer is provided between the word line and the storage structure, and a first conductive layer, a dielectric film and a second conductive layer are formed continuously and sequentially stacked on the side of the isolation layer and the surface of the active pillar. The first conductive layer located on the side of the isolation layer is etched away to expose the side of the dielectric film. The remaining first conductive layer serves as the first electrode, the remaining dielectric film serves as the first dielectric layer, and the second conductive layer serves as the second electrode.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the storage structure, the following are included: An initial substrate is provided, and a first sacrificial film and a semiconductor layer are sequentially formed on the surface of the initial substrate at intervals. The first sacrificial film and semiconductor layer in a patterned portion of the region are used to form a first groove, the bottom of which exposes the initial substrate. The first sacrificial film is etched away to expose the surface of the semiconductor layer; A first conductive layer, a dielectric film, and a second conductive layer are sequentially formed on the surface of the semiconductor layer, the surface of the initial substrate, and the side surface of the first sacrificial film, with the semiconductor layer serving as the active pillar.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before etching away the first conductive layer located on the side of the isolation layer, the process includes: patterning a portion of the first sacrificial film and semiconductor layer to form a second groove, the bottom of the second groove exposing the initial substrate, removing the first sacrificial film, and exposing the side of the first conductive layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After forming the first groove, the process further includes: patterning the first sacrificial film and the semiconductor layer to form a third groove, the third groove being located between adjacent first grooves, and forming a second sacrificial film within the third groove; removing the first sacrificial film while simultaneously removing the second sacrificial film.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, While etching away the first conductive layer located on the side of the isolation layer, the dielectric film with a portion of its thickness is thinned along the arrangement direction of the source region and the drain region of the active pillar.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second conductive layer includes a metal film and a semiconductor film; Before etching away the first conductive layer located on the side of the isolation layer, the process includes: patterning the semiconductor film to form a fourth groove, the fourth groove being arranged along the second direction, the fourth groove exposing the surface of the metal film; Along the arrangement direction of the source region and the drain region of the active pillar, a portion of the width of the metal film, dielectric film and the first conductive layer are sequentially etched away until the side of the isolation layer and the surface of the active pillar are exposed.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, Before sequentially etching away a portion of the width of the metal film, dielectric film, and first conductive layer, the process includes etching the semiconductor film along the arrangement direction of the source region and the drain region of the active pillar.

8. A semiconductor structure prepared by the method of preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, include: A substrate, the surface of which has bit lines extending along a first direction; Multiple active pillars are spaced apart along a direction perpendicular to the surface of the substrate. Each active pillar includes a source region, a channel region, a drain region, and a support region. The bit line is connected to one of the active pillars in the source region or the drain region. The word line extends along a second direction, the word line is located between adjacent active posts and the word line surrounds the active posts of the channel region; Multiple memory structures are vertically stacked on the substrate. Each memory structure is connected to another active pillar of the source or drain region. The memory structure surrounds the active pillar of the support region. Each memory structure includes a first electrode plate, a first dielectric layer, and a second electrode plate stacked sequentially on the surface of the active pillar of the support region. An isolation layer is provided between the word line and the memory structure.

9. The semiconductor structure according to claim 8, characterized in that, Along the arrangement direction of the source and drain regions of the active pillar, at least two columns of the memory structures are included; a dielectric layer is provided between adjacent memory structures.

10. The semiconductor structure according to claim 9, characterized in that, The dielectric layer is located between the first dielectric layer of any of the memory structures and the first dielectric layer of the adjacent memory structures.

11. The semiconductor structure according to claim 10, characterized in that, Along a direction perpendicular to the surface of the substrate, the thickness of the first dielectric layer located on the surface of the first electrode is greater than or equal to the thickness of the first dielectric layer located on the side of the dielectric layer.

12. The semiconductor structure according to claim 11, characterized in that, The thickness of the first dielectric layer located on the side of the dielectric layer ranges from 5 nm to 100 nm.

13. The semiconductor structure according to claim 8, characterized in that, Along the first direction, there is a second dielectric layer between the active columns of adjacent support areas, and the second dielectric layer is also located on the side of the first dielectric layer; the thickness of the first dielectric layer located on the surface of the first electrode plate is greater than or equal to the thickness of the first dielectric layer located on the side of the second dielectric layer.

14. The semiconductor structure according to claim 13, characterized in that, The thickness of the first dielectric layer located on the side of the second dielectric layer ranges from 5 nm to 100 nm.

15. The semiconductor structure according to claim 8, characterized in that, Along the arrangement direction of the source region and the drain region of the active pillar, the sides of the first electrode plate, the first dielectric layer and the second electrode plate are flush.

Images