Method for manufacturing a semiconductor structure and structure thereof

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a manufacturing method of a semiconductor structure and a structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprising semiconductor channels arranged in a matrix along a first direction and a second direction, and a part of the substrate exposed between adjacent semiconductor channels; forming a metal layer, the metal layer being located on the sidewall of the semiconductor channel and also on the surface of the exposed substrate between adjacent semiconductor channels; and converting part of the semiconductor channels and the exposed substrate between adjacent semiconductor channels into bit lines by a metal silicide process, the bit lines penetrating the semiconductor channels along the first direction, so that the difficulty of forming the bit lines can be reduced at least.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the structure thereof. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitance. The word line of the memory cell can control the opening or closing of the transistor's channel region, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0004] However, there is currently a problem that it is difficult to form a line connecting the position lines. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and the structure thereof, which at least helps to reduce the process difficulty of forming interconnected bit lines.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure and the structure thereof, comprising: providing a substrate, the substrate including semiconductor channels arranged in an array along a first direction and a second direction, with a portion of the substrate exposed between adjacent semiconductor channels; forming a metal layer, the metal layer being located on the sidewalls of the semiconductor channels and also on the surface of the substrate exposed between adjacent semiconductor channels, the angle between the top surface of the metal layer and the sidewalls of the semiconductor channels being less than or equal to 90°; and using a metal silicide process to convert a portion of the semiconductor channels and the substrate exposed between adjacent semiconductor channels into bit lines, the bit lines penetrating the semiconductor channels along the first direction.

[0007] In some embodiments, the step of forming the metal layer includes: forming a groove located on the surface of the substrate exposed between adjacent semiconductor channels; and forming the metal layer located on the sidewalls and bottom surface of the groove.

[0008] In some embodiments, the step of forming the groove includes: forming a sacrificial layer located on the surface of the substrate exposed between adjacent semiconductor channels spaced apart along the first direction; forming a sidewall layer located on the sidewall of the semiconductor channel and a portion of the top surface of the sacrificial layer; and etching the sacrificial layer to form the groove.

[0009] In some embodiments, the method of forming the sacrificial layer includes forming the sacrificial layer on the surface of the substrate exposed between adjacent semiconductor channels using reverse selective deposition.

[0010] In some embodiments, the method of forming the sidewall layer includes: thermally oxidizing the semiconductor channel sidewall or forming the sidewall layer spaced along the first direction on the sidewall of the semiconductor channel by atomic layer deposition.

[0011] In some embodiments, the step of forming the metal layer includes: forming an initial metal layer that covers the entire sidewall of the semiconductor channel and also covers the surface of the substrate exposed between adjacent semiconductor channels; and etching back the initial metal layer to remove a portion of the initial metal layer from the sidewall of the semiconductor channel, leaving the remaining initial metal layer as the metal layer.

[0012] In some embodiments, after forming the metal layer, the method further includes forming a sidewall layer that covers the sidewalls of the semiconductor channel exposed by the metal layer.

[0013] In some embodiments, after forming the metal layer and before forming the sidewall layer, the method further includes: forming a diffusion barrier layer, the diffusion barrier layer covering the top surface and sidewalls of the metal layer, and the top surface of the diffusion barrier layer being higher than or flush with the top surface of the metal layer.

[0014] In some embodiments, the bit line includes a metal semiconductor compound layer and a bit line metal layer. The step of forming the bit line includes: using a metal silicide process to diffuse ions from the metal layer into the semiconductor channel to form the metal semiconductor compound layer; and forming the bit line metal layer, wherein the bit line metal layer covers the surface and sidewalls of the metal layer.

[0015] In some embodiments, the metal silicide process includes: using a thermal annealing process to diffuse metal ions from the metal layer into the semiconductor channel to form the metal semiconductor compound layer, wherein the process temperature of the thermal annealing process is 400°C to 1000°C.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, including: a substrate, the substrate including semiconductor channels arranged in an array along a first direction and a second direction; bit lines, the bit lines penetrating the semiconductor channels along the first direction, and a portion of the surface of the bit lines is exposed between adjacent semiconductor channels.

[0017] In some embodiments, the bit line includes: a metal-semiconductor compound layer that penetrates the semiconductor channel along a first direction, and a portion of the metal-semiconductor compound layer is exposed between adjacent semiconductor channels; and a bit line metal layer that is located between the semiconductor channels spaced apart along the first direction and is electrically connected to the adjacent semiconductor channels.

[0018] In some embodiments, the bit line further includes: a metal layer covering the sidewalls opposite to the semiconductor channels spaced along a first direction, and also covering the top surface of the metal-semiconductor compound layer; and a diffusion barrier layer located on the surface of the metal layer and between the metal layer and the bit line metal layer.

[0019] In some embodiments, the thickness of the metal-semiconductor compound layer exposed by the semiconductor channel is 6–20 nm in a direction perpendicular to the substrate surface.

[0020] In some embodiments, the angle between the top surface of the metal layer and the sidewall of the semiconductor channel is less than or equal to 90°.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by forming a metal layer between adjacent semiconductor channels and by using a metal silicide process to convert part of the semiconductor channel and the exposed substrate between adjacent semiconductor channels into bit lines, the resistance of the bit lines can be reduced, and the process difficulty of forming bit lines can also be reduced. By forming a metal layer between semiconductor channels, it is easier to convert semiconductor channels into bit lines, thereby making it easier to form bit lines connected along the first direction. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 8 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0024] Figures 9 to 14 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0025] As can be seen from the background technology, there are currently two common methods for forming bit lines using semiconductor silicide processes: Method 1: By forming a metal layer between semiconductor channels, the substrate exposed by the semiconductor channel and the substrate at the bottom of the semiconductor channel are converted into bit lines using metal silicide; Method 2: By forming a bowl-shaped groove between semiconductor channels that is recessed into the substrate, and by forming a metal layer in the bowl-shaped groove, the substrate at the bottom of the semiconductor channel is converted into bit lines using a metal silicide process.

[0026] However, the distance required for metal ion diffusion in Method 1 is too large, making it difficult to form continuous bit lines; Method 2 makes it difficult to fill the bowl-shaped groove with metal, resulting in gaps that affect the subsequent formation of bit lines.

[0027] The embodiments disclosed herein form a metal layer on the substrate surface exposed by the semiconductor channel, and convert a portion of the semiconductor channel and a portion of the substrate exposed by the adjacent semiconductor channel into bit lines. This facilitates the formation of bit lines that penetrate the semiconductor channel along the first direction and also makes it easier to fill metal to form a metal layer, thereby reducing the process difficulty of the semiconductor structure fabrication method.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] Figures 1 to 8 This is a schematic diagram of the fabrication steps of the semiconductor structure provided in the embodiments of this disclosure.

[0030] refer to Figures 1 to 3 The method for fabricating a semiconductor structure includes: providing a substrate 100, the substrate 100 including semiconductor channels 110 arranged in an array along a first direction X and a second direction Y, and exposing portions of the substrate 100 between adjacent semiconductor channels 110.

[0031] For details, please refer to Figure 1A substrate 100 is provided, and the substrate 100 is patterned to form initial semiconductor channels 111 spaced along the second direction Y.

[0032] In some embodiments, the material of the substrate 100 may be silicon, germanium, or silicon germanide, and the material of the substrate 100 may also be doped. Taking silicon as an example, a trace amount of trivalent elements, such as boron, indium, gallium, or aluminum, may be doped into the substrate 100 to form a P-type substrate. Similarly, a trace amount of pentavalent elements, such as phosphorus, antimony, or arsenic, may be doped into the substrate 100 to form an N-type substrate. The selection of doping elements for the substrate 100 may be based on actual needs and product performance, etc. This disclosure does not limit the material of the substrate 100 or the doped elements.

[0033] In some embodiments, the initial semiconductor channel 111 can be formed using a self-aligned double patterning (SADP) process. In other embodiments, the initial semiconductor channel 111 can also be formed using a self-aligned quadruple patterning (SAQP) process. SADP or SAQP techniques can result in a more precise pattern of the formed initial semiconductor channel 111.

[0034] refer to Figure 2 An isolation structure 120 is formed, which fills the gap between adjacent initial semiconductor channels 111. The isolation structure 120 is used to isolate adjacent initial semiconductor channels 111.

[0035] In some embodiments, the method of forming the isolation structure 120 may include: filling the space between adjacent initial semiconductor channels 111 with material of the isolation structure 120 until the top surface of the isolation structure 120 is flush with the top surface of the initial semiconductor channels 111. In other embodiments, when filling the material of the isolation structure 120, the formed isolation structure 120 also covers a portion of the top surface of the initial semiconductor channels 111, and a portion of the isolation structure 120 is removed by planarization until the top surface of the isolation structure 120 is flush with the top surface of the initial semiconductor channels 111.

[0036] refer to Figure 3 The initial semiconductor channel 111 is patterned to form the semiconductor channel 110. The isolation structure 120 separates adjacent semiconductor channels 110, thereby avoiding mutual interference between adjacent semiconductor channels 110 and thus improving the reliability of the semiconductor structure.

[0037] refer to Figures 4 to 8A metal layer 130 is formed, which is located on the sidewall of the semiconductor channel 110 and also on the surface of the substrate 100 exposed between adjacent semiconductor channels 110. The angle between the top surface of the metal layer 130 and the sidewall of the semiconductor channel 110 is less than or equal to 90°. A metal silicide process is used to convert part of the semiconductor channel 110 and the substrate 100 exposed between adjacent semiconductor channels 110 into a bit line 140. The bit line 140 penetrates the semiconductor channel 110 along the first direction X.

[0038] For details, please refer to Figure 4 A sacrificial layer 150 is formed. The sacrificial layer 150 is located on the surface of the substrate 100 exposed between adjacent semiconductor channels 110 arranged at intervals along the first direction X. The formation of the sacrificial layer 150 provides a process basis for the subsequent formation of the groove and for the subsequent formation of the metal layer. The thickness of the subsequently formed metal layer 130 can be controlled by controlling the thickness of the sacrificial layer 150 in the direction perpendicular to the surface of the substrate 100.

[0039] In some embodiments, the material of the sacrificial layer 150 may be an insulating material such as silicon nitride or silicon oxide. The material of the sacrificial layer 150 may be different from the material of the isolation structure 120, thereby avoiding the removal of part of the isolation structure 120 when the sacrificial layer 150 is subsequently etched away.

[0040] In some embodiments, the method of forming the sacrificial layer 150 may include: forming the sacrificial layer 150 on the surface of the substrate 100 exposed between adjacent semiconductor channels 110 using reverse topology selectivity (RTS); in other embodiments, the method of forming the sacrificial layer 150 may also include: forming an initial sacrificial layer, the top surface of which is flush with the top surface of the semiconductor channel; etching the initial sacrificial layer, with the remaining initial sacrificial layer serving as the sacrificial layer 150. Reverse selective deposition allows control over the deposition of the sacrificial layer material on the bottom surface of the recess formed by the substrate 100 and the semiconductor channel 110, without depositing it on the sidewalls of the recess. This avoids the material of the sacrificial layer 150 adhering to the sidewalls of the semiconductor channel 110, preventing damage to the semiconductor channel 110 during subsequent etching. Forming the sacrificial layer 150 by forming an initial sacrificial layer followed by etching, located between adjacent semiconductor channels 110 at intervals along the first direction X, allows for better control of the thickness of the sacrificial layer 150.

[0041] refer to Figure 5A sidewall layer 160 is formed, which is located on the sidewall of the semiconductor channel 110 and the top surface of part of the sacrificial layer 150. By forming the sidewall layer 160, the semiconductor channel 110 can be prevented from being over-converted in the subsequent metal silicide process. By forming the sidewall layer 160, part of the semiconductor channel 110 can be protected, thereby preventing the covered part of the semiconductor channel 110 from being converted into a bit line.

[0042] In some embodiments, the method of forming the sidewall layer 160 may include: thermally oxidizing the sidewall of the semiconductor channel 110 or forming the sidewall layer 160 spaced along the first direction X on the sidewall of the semiconductor channel 110 by atomic layer deposition. The method of thermally oxidizing the sidewall of the semiconductor channel 110 can form a relatively dense oxide layer, and the sidewall layer 160 can also serve as the gate dielectric layer of the semiconductor structure; the atomic layer deposition method can better control the width of the sidewall layer 160 along the first direction X, and the formed sidewall layer 160 has good uniformity.

[0043] In some embodiments, the sidewall layer 160 is also located on the top surface of the semiconductor channel 110. By forming the sidewall layer 160 on the top surface of the semiconductor channel 110, the semiconductor channel 110 can be protected, thereby preventing the semiconductor channel 110 from being affected in subsequent process steps and thus improving the reliability of the semiconductor structure.

[0044] refer to Figure 6 Etching the sacrificial layer to 150 (reference) Figure 5 A groove 170 is formed on the surface of the substrate 100 exposed between adjacent semiconductor channels 110. Forming a groove 170 on the surface of the substrate 100 facilitates the subsequent formation of a metal layer. Furthermore, the top surface of the groove 170 forms an angle with the sidewall of the semiconductor channel 110, making it easier to fill the metal layer during the subsequent formation process. This eliminates the need to specifically search for a metal material with good gap-filling capabilities, thereby reducing the difficulty of forming the metal layer.

[0045] In some embodiments, the angle between the top surface of the groove 170 and the sidewall of the semiconductor channel 110 is less than or equal to 90°. It is understood that the groove 170 is formed by etching the sacrificial layer 150. Therefore, provided the sacrificial layer 150 is completely etched away, the angle between the top surface of the groove 170 and the sidewall of the semiconductor channel 110 is equal to the angle between the top surface of the sacrificial layer 150 and the sidewall of the semiconductor channel 110. By controlling the top surface of the sacrificial layer 150 and the etching process, the angle between the top surface of the groove 170 and the semiconductor channel 110 can be controlled. By controlling the angle between the top surface of the groove 170 and the sidewall of the semiconductor channel 110 to be less than or equal to 90°, it is easier to fill the groove 170 with metal during the subsequent formation of the metal layer, thus improving the gap problem between the metal layer and the semiconductor channel 110.

[0046] refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 A magnified schematic diagram of the structure inside the ellipse.

[0047] A metal layer 130 is formed, which is located on the sidewall and bottom surface of the groove 170. The formation of the metal layer 130 provides a basis for the subsequent formation of the metal semiconductor compound layer 141. The metal semiconductor compound layer 141 is formed by diffusing metal ions of the metal layer 130 into the semiconductor channel 110.

[0048] In some embodiments, the angle between the top surface of the metal layer 130 and the sidewall of the semiconductor channel 110 is less than or equal to 90°. By controlling the angle between the top surface of the metal layer 130 and the sidewall of the semiconductor channel 110 to be less than or equal to 90°, the gap between the metal layer 130 and the semiconductor channel 110 can be reduced, thereby facilitating the diffusion of metal ions during subsequent metal silicide processes.

[0049] After forming the metal layer 130, bit lines 140 are formed. In some embodiments, bit lines 140 include a metal-semiconductor compound layer 141 and a bit line metal layer 142. The step of forming bit lines 140 may include: using a metal silicide process to diffuse ions from the metal layer 130 into the semiconductor channel 110 to form the metal-semiconductor compound layer 141; and forming the bit line metal layer 142, which covers the surface and sidewalls of the metal layer 130. In other embodiments, the bit line may only include the metal-semiconductor compound layer 141. The metal silicide process can reduce the contact resistance between the formed bit line 140 and the semiconductor channel 110, and the formation of the bit line metal layer 142 allows the bit line 140 to conduct through the surface of the substrate 100, thereby improving the reliability of the bit line 140's conduction. Furthermore, the bit line metal layer 142 can reduce the resistance of the bit line 140 and increase its conduction speed.

[0050] In some embodiments, the metal silicide process includes: employing a thermal annealing process to diffuse metal ions from the metal layer 130 into the semiconductor channel 110 to form a metal-semiconductor compound layer 141. The process temperature of the thermal annealing process is 400°C to 1000°C. It is understood that when the process temperature of the thermal annealing process is below 400°C, the diffusion of metal ions into the semiconductor channel is ineffective; when the process temperature of the thermal annealing process is above 1000°C, the formed metal-semiconductor compound layer 141 is unstable, causing some of the metal-semiconductor compound layer 141 to revert to semiconductor material, which may affect the reliability of the formed bit line 140.

[0051] In some embodiments, before forming the bit line metal layer 142, a diffusion barrier layer 180 is formed. The diffusion barrier layer 180 is located on the sidewall and top surface of the metal layer 130. By forming the diffusion barrier layer 180, metal ions of the bit line metal layer 142 are prevented from diffusing into the semiconductor channel 110, thereby preventing contamination of the semiconductor channel 110.

[0052] In some embodiments, the diffusion barrier layer 180 and the bit line metal layer 142 are formed in the same step as the metal layer 130. The diffusion barrier layer 180, the bit line metal layer 142, and the metal layer 130 can be formed before the metal silicide process, and then the metal semiconductor compound layer 141 can be formed using the metal silicide process. In other embodiments, the metal layer can be formed first, and then the metal semiconductor compound layer can be formed using the metal silicide process. After the metal semiconductor compound layer is formed, the diffusion barrier layer and the bit line metal layer are formed. In still other embodiments, the metal layer can be formed first, and then the metal semiconductor compound layer can be formed using the metal silicide process. After the metal semiconductor compound layer is formed, the metal layer is removed, and the bit line metal layer is formed.

[0053] In some embodiments, retaining the metal layer 130 after the metal silicide process can improve the tightness of the connection between the semiconductor channel 110 and the bit line metal layer 142. The metal layer 130 can serve as a contact bonding layer, thereby improving the reliability of the semiconductor structure.

[0054] In some embodiments, the sidewall layer 160 also covers a portion of the diffusion barrier layer 180. The limiting space formed by the sidewall layer 160, the diffusion barrier layer 180, and the substrate 100 covering the portion of the diffusion barrier layer 180 can prevent the metal layer 130 from flowing during the formation of the metal semiconductor compound layer 141, thereby improving the reliability of the formed metal semiconductor compound layer 141.

[0055] In other embodiments, the projection of the sidewall layer on the substrate surface is spaced apart from the projection of the diffusion barrier layer on the substrate surface, or the sidewall of the sidewall layer facing the diffusion barrier layer is flush with the sidewall of the diffusion barrier layer facing the sidewall layer, or the projection of the sidewall layer on the substrate surface partially coincides with the projection of the bit line metal layer on the substrate surface.

[0056] In some embodiments, the bit line metal layer 142 is wrapped by the metal semiconductor compound layer 141, thereby increasing the contact area between the bit line metal layer 142 and the metal semiconductor compound layer 141, thereby reducing the contact resistance between the bit line metal layer 142 and the metal semiconductor compound layer 141.

[0057] In some embodiments, the material of the metal layer 130 may be a metal such as molybdenum, tungsten, nickel, cobalt, titanium, or platinum. Taking titanium as an example and silicon as an example of a semiconductor channel, the material of the metal-semiconductor compound layer is titanium silicide. Titanium silicide has a low Schottky barrier and lower contact resistance, and only requires one annealing, which can reduce process time and save costs.

[0058] In some embodiments, the diffusion barrier layer 180 may be made of titanium nitride or tantalum nitride, etc. The diffusion barrier layer 180 can also prevent the metal layer 130 from flowing during the annealing process.

[0059] In some embodiments, the material of the bit line metal layer 142 may be tungsten metal or copper metal, etc.

[0060] The metal semiconductor compound layer 141 formed in this embodiment is thinner than the metal semiconductor compound layer 141 formed in the first embodiment described above. By forming a thinner metal semiconductor compound layer 141, the thermal stability of the metal semiconductor compound layer 141 can be improved, thereby improving the reliability of the semiconductor structure.

[0061] In this embodiment, a sacrificial layer 150 is first formed, and the space occupied by the sacrificial layer 150 is used as the space for the subsequent formation of the metal layer 130. By forming the sacrificial layer 150, it is easy to control the thickness of the metal layer 130 in the direction perpendicular to the surface of the substrate 100. Then, the metal ions of the metal layer 130 are diffused into the semiconductor channel 110 and the substrate 100 through the metal silicide process to form the bit line 140. This makes the distance that the metal ions need to diffuse equal to the width of the semiconductor channel 110 in the first direction X, reducing the difficulty of connecting the bit lines 140 and avoiding the filling gaps when forming the metal layer 130.

[0062] Another embodiment of this disclosure also provides a method for fabricating another semiconductor structure, which is largely the same as the aforementioned embodiment, with the main difference being that the embodiment of this disclosure does not form a sacrificial layer. The method for fabricating the semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the aforementioned embodiments can be referred to the corresponding descriptions of the aforementioned embodiments, and will not be repeated hereafter.

[0063] refer to Figure 9 A substrate 200 is provided, the substrate including semiconductor channels 210 arranged in an array along a first direction X and a second direction Y, and a portion of the substrate 200 is exposed between adjacent semiconductor channels 210.

[0064] In some embodiments, the method further includes: forming an isolation structure 220 that is spaced apart along a first direction X and filled between adjacent semiconductor channels 210 along a second direction Y.

[0065] refer to Figure 10 A metal layer 230 is formed, located on the sidewall of the semiconductor channel 210 and also on the surface of the substrate 200 exposed between adjacent semiconductor channels 210. In some embodiments, the step of forming the metal layer 230 includes: forming an initial metal layer that covers the entire sidewall of the semiconductor channel 210 and also covers the surface of the substrate 200 exposed between adjacent semiconductor channels 210; and etching back the initial metal layer to remove a portion of the initial metal layer on the sidewall of the semiconductor channel, leaving the remaining initial metal layer as the metal layer 230. By directly forming the metal layer 230 on the sidewall of the semiconductor channel 210, compared to the embodiment described above which forms a sacrificial layer, the number of process steps in the semiconductor structure fabrication method can be reduced, thereby reducing the overall process time of the semiconductor structure fabrication method.

[0066] refer to Figure 11 , Figure 11 for Figure 10 A magnified view of the area within the dashed box.

[0067] In some embodiments, after forming the metal layer 230, a diffusion barrier layer 280 is further formed. The diffusion barrier layer 280 covers the top surface and sidewalls of the metal layer 230, and the top surface of the diffusion barrier layer 280 is higher than or flush with the top surface of the metal layer 230. By forming the diffusion barrier layer 280, metal ions from the bit line metal layer can be prevented from diffusing into the semiconductor channel 210 during the subsequent metal silicide process, thereby improving the reliability of the formed semiconductor structure.

[0068] In some embodiments, after forming the diffusion barrier layer 280, the method further includes forming a bit line metal layer 242, which covers the sidewall of the diffusion barrier layer 280, and the top surface of the bit line metal layer 242 is flush with the top surface of the diffusion barrier layer 280 or the top surface of the bit line metal layer 242 is lower than the top surface of the diffusion barrier layer 280.

[0069] It should be noted that the above-mentioned flushing can refer to the top surface of the bit line metal layer 242 being completely flush with the top surface of the diffusion barrier layer 280, or the height difference between the top surface of the bit line metal layer 242 and the top surface of the diffusion barrier layer 280 being within the allowable error range can also be regarded as the top surface of the bit line metal layer 242 being flush with the top surface of the diffusion barrier layer 280.

[0070] refer to Figure 12 After forming the metal layer 230, the process may further include forming a sidewall layer 260, which covers the sidewalls of the semiconductor channel 210 exposed by the metal layer 230. Forming the sidewall layer 260 prevents the metal layer 230 from flowing at high temperatures during subsequent metal silicide processes, thus avoiding the conversion of excessive semiconductor channels 210 into bit lines 240. Forming the sidewall layer 260 also prevents metal ions from the bit line metal layer 242 from diffusing into the semiconductor channel 210.

[0071] refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 A magnified view of the area within the dashed circle.

[0072] Specifically, the metal silicide process converts a portion of the semiconductor channel 210 and the exposed substrate 200 between adjacent semiconductor channels 210 into bit lines 240, which penetrate the semiconductor channel 210 along a first direction X. In some embodiments, the bit line 240 includes a metal semiconductor compound layer 241 and a bit line metal layer 242. The step of forming the bit line 240 may include: using a metal silicide process to diffuse ions from the metal layer 230 into the semiconductor channel 210 to form the metal semiconductor compound layer 241; and forming the bit line metal layer 242, which covers the surface and sidewalls of the metal layer 230. The metal silicide process can reduce the contact resistance between the formed bit line 240 and the semiconductor channel 210, and the formation of the bit line metal layer 242 allows the bit line 240 to conduct through the surface of the substrate 200, thereby improving the reliability of the bit line 240's conduction. Furthermore, the bit line metal layer 242 can reduce the resistance of the bit line 240 and increase its conduction speed.

[0073] In other embodiments, the bit line may consist only of a metal-semiconductor compound layer. Therefore, after using a metal silicide process to diffuse ions from the metal layer into the semiconductor channel to form the metal-semiconductor compound layer, the process further includes: removing the metal layer.

[0074] In some embodiments, the bit line metal layer 242 may be formed simultaneously with the formation of the metal layer 230; in other embodiments, the bit line metal layer may be formed after the formation of the metal semiconductor compound layer.

[0075] In some embodiments, the metal silicide process includes: employing a thermal annealing process to diffuse metal ions from the metal layer 230 into the semiconductor channel 210 to form a metal-semiconductor compound layer 241. The process temperature of the thermal annealing process is 400°C to 1000°C. It is understood that when the process temperature of the thermal annealing process is below 400°C, the diffusion of metal ions into the semiconductor channel is ineffective; when the process temperature of the thermal annealing process is above 1000°C, the formed metal-semiconductor compound layer 241 is unstable, causing some of the metal-semiconductor compound layer to be reduced to semiconductor material, which may affect the reliability of the formed bit line 240.

[0076] This embodiment controls the thickness of the metal layer 230 in the direction perpendicular to the surface of the substrate 200 by first forming a metal layer 230 between semiconductor channels 210 and etching the metal layer 230, and then forming bit lines 240 by metal silicide process. By directly forming the metal layer 230, the process steps of forming the sacrificial layer can be reduced, thereby reducing the process time of the entire semiconductor structure fabrication method.

[0077] Another embodiment of this disclosure also provides a semiconductor structure, which can be formed by adopting some or all of the above-described semiconductor structure fabrication methods. The semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0078] refer to Figure 7 and Figure 8 The semiconductor structure includes: a substrate 100, the substrate 100 including semiconductor channels 110 arranged in an array along a first direction X and a second direction Y; and bit lines 140, the bit lines 140 passing through the semiconductor channels 110 along the first direction X, and a portion of the surface of the bit lines 140 is exposed between adjacent semiconductor channels 110.

[0079] By forming a bit line 140 that runs through the semiconductor channel 110 along the first direction X, the bit lines 140 connected along the first direction X can be formed, thereby ensuring the signal transmission capability of the bit lines 140.

[0080] In some embodiments, the bit line 140 includes: a metal-semiconductor compound layer 141, which penetrates the semiconductor channel 110 along a first direction X, and a portion of the metal-semiconductor compound layer 141 is exposed between adjacent semiconductor channels 110; and a bit line metal layer 142, which is located between the semiconductor channels 110 spaced apart along the first direction X and is electrically connected to adjacent semiconductor channels 110. By forming the metal-semiconductor compound layer 141, the contact resistance between the bit line 140 and the substrate 100 can be reduced, and by forming the bit line metal layer 142, the resistance of the bit line 140 itself can be reduced, thereby increasing the signal transmission speed of the bit line 140.

[0081] In some embodiments, the semiconductor structure further includes: a metal layer 130 covering the sidewalls opposite to the semiconductor channels 110 spaced along a first direction X, and also covering the top surface of the metal-semiconductor compound layer 141; and a diffusion barrier layer 180 located on the surface of the metal layer 130 and between the metal layer 130 and the bit line metal layer 142. The metal layer 130 can be used to improve the tightness of the connection between the bit line metal layer 142 and the metal-semiconductor compound layer 141, and the diffusion barrier layer 180 is used to prevent metal ions from the bit line metal layer 142 from diffusing into the metal-semiconductor compound layer 141. By providing the metal layer 130 and the diffusion barrier layer 180, the reliability of the semiconductor structure can be improved.

[0082] In some embodiments, the angle between the top surface of the metal layer 130 and the sidewall of the semiconductor channel 110 is less than or equal to 90°. By setting the angle between the top surface of the metal layer 130 and the sidewall of the semiconductor channel 110 to be less than or equal to 90°, the gap between the metal layer 130 and the metal semiconductor compound layer 141 can be reduced, thereby improving the reliability of the connection between the metal layer 130 and the metal semiconductor compound layer 141.

[0083] In some embodiments, the thickness of the metal-semiconductor compound layer 141 exposed by the semiconductor channel 110 in a direction perpendicular to the surface of the substrate 100 is 6–20 nm. The thermal stability of the metal-semiconductor compound layer 141 can be improved by providing a thin metal-semiconductor compound layer 141.

[0084] In some embodiments, in the first direction X, the width of the metal-semiconductor compound layer 141 is greater than or equal to the width of the semiconductor channel 110, and a bit line 140 through the semiconductor channel 110 is formed by the width of the metal-semiconductor compound layer 141 being greater than or equal to the width of the semiconductor channel 110.

[0085] It is understood that ion diffusion is reciprocal. During the formation of the metal-semiconductor compound layer 141, metal ions diffuse into the semiconductor channel 110, and some semiconductor ions in the semiconductor channel 110 diffuse into the metal layer 130. Therefore, the width of the metal-semiconductor compound layer 141 is greater than the width of the semiconductor channel 110. However, in some embodiments, the semiconductor ions diffused into the metal layer 130 are much smaller than the metal ions diffused into the semiconductor channel 110. This portion of semiconductor ions diffused into the metal layer 130 is negligible. Therefore, the width of the metal-semiconductor compound layer 141 can be considered equal to the width of the semiconductor channel 110.

[0086] In some embodiments, the semiconductor structure further includes an isolation structure 120, which fills the spaces between adjacent semiconductor channels 110 along a second direction Y, and the isolation structures 120 are also spaced apart along a first direction X. The isolation structure 120 is used to isolate adjacent semiconductor channels 110.

[0087] In some embodiments, the semiconductor structure further includes a sidewall layer 160, which covers the sidewall of the semiconductor channel 110, and the bottom surface of the sidewall layer 160 contacts the top surface of the metal layer 130. The sidewall layer 160 can serve as a gate dielectric layer.

[0088] This disclosure provides a semiconductor structure including: a substrate 100 and an array of semiconductor channels 110; bit lines 140 penetrating the semiconductor channels 110, and bit lines 140 connected in a first direction X can be formed by forming bit lines 140 penetrating the semiconductor channels 110.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including semiconductor channels arranged in an array along a first direction and a second direction, with portions of the substrate exposed between adjacent semiconductor channels; A metal layer is formed, the metal layer being located on the sidewall of the semiconductor channel and also on the surface of the substrate exposed between adjacent semiconductor channels, the angle between the top surface of the metal layer and the sidewall of the semiconductor channel being less than or equal to 90°; A metal silicide process is used to convert a portion of the semiconductor channel and the exposed substrate between adjacent semiconductor channels into bit lines, which penetrate the semiconductor channel along the first direction.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of forming the metal layer includes: forming a groove located on the surface of the substrate exposed between adjacent semiconductor channels; The metal layer is formed on the sidewalls and bottom surface of the groove.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The step of forming the groove includes: forming a sacrificial layer located on the surface of the substrate exposed between adjacent semiconductor channels spaced apart along the first direction; A sidewall layer is formed, the sidewall layer being located on the sidewall of the semiconductor channel and on the top surface of a portion of the sacrificial layer; The sacrificial layer is etched to form the groove.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method of forming the sacrificial layer includes forming the sacrificial layer on the surface of the substrate exposed between adjacent semiconductor channels using reverse selective deposition.

5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method of forming the sidewall layer includes: thermally oxidizing the sidewall of the semiconductor channel or forming the sidewall layer spaced along the first direction on the sidewall of the semiconductor channel by atomic layer deposition.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of forming the metal layer includes: forming an initial metal layer that covers the entire sidewall of the semiconductor channel and also covers the surface of the substrate exposed between adjacent semiconductor channels; The initial metal layer is etched back, and a portion of the initial metal layer on the sidewall of the semiconductor channel is removed, leaving the remaining initial metal layer as the metal layer.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, After forming the metal layer, the process further includes: A sidewall layer is formed, which covers the sidewall of the semiconductor channel exposed by the metal layer.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The process further includes forming a diffusion barrier layer after the metal layer is formed and before the sidewall layer is formed. The diffusion barrier layer covers the top surface and sidewall of the metal layer, and the top surface of the diffusion barrier layer is higher than or flush with the top surface of the metal layer.

9. The method for fabricating a semiconductor structure according to claim 2 or 6, characterized in that, The bit line includes: a metal-semiconductor compound layer and a bit line metal layer, and the step of forming the bit line includes: The metal layer is diffused into the semiconductor channel using a metal silicide process to form the metal semiconductor compound layer; A bitline metal layer is formed, which covers the surface and sidewalls of the metal layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The metal silicide process includes: using a thermal annealing process to diffuse metal ions from the metal layer into the semiconductor channel to form the metal semiconductor compound layer, wherein the process temperature of the thermal annealing process is 400℃~1000℃.

11. A semiconductor structure, said semiconductor structure being fabricated using the method described in any one of claims 1-10, characterized in that, include: A substrate, the substrate comprising semiconductor channels arranged in an array along a first direction and a second direction; Bit lines that penetrate the semiconductor channel along a first direction, with a portion of the surface of the bit lines exposed between adjacent semiconductor channels.

12. The semiconductor structure according to claim 11, characterized in that, The bit line includes: a metal-semiconductor compound layer, which penetrates the semiconductor channel along a first direction, and a portion of the metal-semiconductor compound layer is exposed between adjacent semiconductor channels; Bit line metal layers are located between the semiconductor channels spaced apart along a first direction and are electrically connected to the adjacent semiconductor channels.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure further includes: a metal layer that covers the sidewalls opposite to the semiconductor channels spaced along a first direction, and also covers the top surface of the metal semiconductor compound layer; A diffusion barrier layer is located on the surface of the metal layer and between the metal layer and the bit line metal layer.

14. The semiconductor structure according to claim 13, characterized in that, In a direction perpendicular to the substrate surface, the thickness of the metal-semiconductor compound layer exposed by the semiconductor channel is 6–20 nm.

15. The semiconductor structure according to claim 13, characterized in that, The angle between the top surface of the metal layer and the sidewall of the semiconductor channel is less than or equal to 90°.

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