Semiconductor structure, memory structure and method of manufacturing thereof

Abstract

The application relates to a semiconductor structure, a storage structure and a preparation method thereof. The semiconductor structure comprises a substrate, an isolation layer on the substrate, and a bit line structure in the isolation layer; the bit line structure is at least partially exposed to the isolation layer; an active region structure comprises an active pillar and a stress layer, the active pillar is located on the bit line structure, and the stress layer covers the exposed surface of the active pillar; the active region structure comprises a first connecting end, a second connecting end and a channel region between the first connecting end and the second connecting end, and the first connecting end is electrically connected with the bit line structure; and a word line structure is arranged on the periphery of the channel region. By arranging the stress layer covering the active pillar on the periphery of the active pillar, the electron mobility of the active pillar can be greatly increased by introducing stress, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a memory structure, and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor technology, three-dimensional storage structures have attracted widespread market attention due to their higher storage density per unit area compared to two-dimensional storage structures, and users are constantly increasing their performance requirements for three-dimensional storage structures.

[0003] In three-dimensional memory structures, the VGAA (Vertical Gate-all-around) has a significant impact on the overall performance of the structure. However, existing VGAAs typically use silicon pillars as active pillars, forming gate word lines around the channel region of the active pillars; but the electron mobility within the active pillars of existing VGAAs is low, resulting in poor device performance. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure, a memory structure, and a method for fabricating the same, addressing the problems of excessive electron accumulation in the bit line structure and low electron mobility due to poor contact between the drain and the bit line in the existing technology.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor structure comprising:

[0006] A substrate having an isolation layer thereon, the isolation layer having a bit line structure therein; the bit line structure being at least partially exposed to the isolation layer.

[0007] An active region structure includes an active pillar and a stress layer. The active pillar is located on the bit line structure, and the stress layer covers the exposed surface of the active pillar. The active region structure includes a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end. The first connection end is electrically connected to the bit line structure.

[0008] A character line structure, wherein the character line structure covers the periphery of the channel region.

[0009] In one embodiment, the active post is embedded within the bit line structure.

[0010] In one embodiment, the active region structure is arranged in multiple rows and columns, and the isolation layer has multiple bit line structures. The multiple bit line structures are arranged in parallel and spaced apart, and extend along the row direction of the active region structure. The number of word line structures is multiple. The multiple word line structures are arranged in parallel and spaced apart, and extend along the column direction of the active region structure. Each word line structure covers the channel region of the active region structure located in the same column.

[0011] In one embodiment, the semiconductor structure further includes an insulating dielectric layer located between adjacent word line structures and filling the gaps between the active region structures.

[0012] In one embodiment, the insulating dielectric layer includes:

[0013] A connection end dielectric layer covers the periphery of the first connection end and the periphery of the second connection end;

[0014] A filling dielectric layer is located around the connection end dielectric layer and around the word line structure.

[0015] In one embodiment, the active pillar comprises a germanium-silicon pillar, and the stress layer comprises a silicon layer.

[0016] Secondly, the present invention also provides a method for preparing a semiconductor structure, comprising:

[0017] Provide substrate;

[0018] An isolation layer is formed on the surface of the substrate;

[0019] A bitline structure is formed within the isolation layer;

[0020] An active region structure is formed on the bit line structure. The active region structure includes an active post and a stress layer. The active post is located on the bit line structure, and the stress layer covers the exposed surface of the active post. The active region structure includes a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end. The first connection end is electrically connected to the bit line structure.

[0021] A character line structure is formed around the periphery of the channel area.

[0022] In one embodiment, forming a bit line structure within the isolation layer includes:

[0023] Bit line trenches are formed within the isolation layer;

[0024] The bit line structure is formed within the bit line trench.

[0025] In one embodiment, forming an active region structure on the bit line structure includes:

[0026] A surface-bonded sacrificial substrate having the bit line structure formed on the isolation layer;

[0027] An active region via is formed within the sacrificial substrate, and the active region via exposes the bit line structure;

[0028] The active pillar is formed within the through hole of the active region;

[0029] Remove the sacrificial substrate;

[0030] The stress layer is formed on the exposed surface of the active pillar, and the stress layer and the active pillar together constitute the active region structure.

[0031] In one embodiment, the active region via penetrates the sacrificial substrate along the thickness direction and extends into the bit line structure; the active pillar is embedded in the bit line structure.

[0032] In one embodiment, a germanium-silicon pillar is formed within the via of the active region as the active pillar, and a silicon layer is formed on the exposed surface of the active pillar as the stress layer.

[0033] In one embodiment, a plurality of active region vias are formed in the sacrificial substrate, and the active region vias are arranged in multiple rows and columns; an active pillar is formed in each of the active region vias; after the stress layer is formed, a plurality of active region structures are obtained, and the active region structures are arranged in multiple rows and columns; a plurality of bit line structures are formed in the isolation layer, and the plurality of bit line structures are arranged in parallel and spaced apart, and extend along the row direction of the active region structures.

[0034] In one embodiment, while forming a word line structure around the channel region, a connector dielectric layer is also formed around the first connector and the second connector; the forming of the word line structure around the channel region and the forming of the connector dielectric layer around the first connector and the second connector include:

[0035] A first dielectric material layer is formed on the surface of the isolation layer where the bit line structure is formed, and the first dielectric material layer fills the gap between adjacent first connection ends;

[0036] A word line material layer is formed on the surface of the first dielectric material layer, and the word line material layer fills the gap between adjacent channel regions;

[0037] A second dielectric material layer is formed on the surface of the word line material layer, and the second dielectric material layer fills the gap between adjacent second connection ends;

[0038] The second dielectric material layer, the word line material layer, and the first dielectric material layer are etched to form isolation trenches extending along the column direction of the active region structures between adjacent columns of the active region structures, so as to obtain the connection end dielectric layer and multiple word line structures extending along the column direction of the active region structures, each word line structure covering the channel region of the active region structure located in the same column.

[0039] In one embodiment, after forming the isolation groove, the method further includes:

[0040] A filling medium layer is formed inside the isolation groove, and the filling medium layer fills the isolation groove.

[0041] Thirdly, the present invention provides a storage structure, comprising:

[0042] The semiconductor structure described in any of the above solutions;

[0043] The storage node structure is located on the surface of the active region structure away from the substrate;

[0044] A capacitor is located on the surface of the storage node structure away from the active region structure.

[0045] In one embodiment, there are multiple active region structures, multiple storage node structures, and multiple capacitors; each storage node structure is configured in a one-to-one correspondence with an active region structure; and each capacitor is configured in a one-to-one correspondence with a storage node structure.

[0046] Fourthly, the present invention provides a method for preparing a storage structure, comprising:

[0047] The semiconductor structure is prepared using the semiconductor structure preparation method described in any of the above schemes;

[0048] A memory node structure is formed on the surface of the active region structure away from the substrate;

[0049] A capacitor is formed on the surface of the storage node structure that is away from the active region structure.

[0050] In one embodiment, there are multiple active region structures, multiple storage node structures, and multiple capacitors; each storage node structure is configured in a one-to-one correspondence with an active region structure; and each capacitor is configured in a one-to-one correspondence with a storage node structure.

[0051] The semiconductor structure and its preparation method of the present invention have the following beneficial effects:

[0052] The semiconductor structure of the present invention includes a substrate, an isolation layer, an active region structure, and a word line structure. The isolation layer has a bit line structure, and the active region structure includes an active pillar and a stress layer. The active pillar is located on the bit line structure, and the stress layer covers the exposed surface of the active pillar. By providing a stress layer covering the active pillar around its periphery, the electron mobility of the active pillar can be greatly increased by introducing stress, thereby improving the performance of the semiconductor structure.

[0053] The semiconductor structure fabrication method of the present invention, by forming a stress layer covering the active pillar around the active pillar, can greatly increase the electron mobility of the active pillar by introducing stress, thereby improving the performance of the semiconductor structure.

[0054] The semiconductor structure in the memory structure of the present invention, by providing a stress layer covering the active pillars around the active pillars, can greatly increase the electron mobility of the active pillars by introducing stress, thereby improving the performance of the memory structure.

[0055] The semiconductor structure in the method for fabricating the memory structure of the present invention, by forming a stress layer around the active pillar and introducing stress, can greatly increase the electron mobility of the active pillar, thereby improving the performance of the memory structure. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0058] Figure 2 This is a three-dimensional structural diagram of the structure obtained in step S11 of the semiconductor structure fabrication method provided in one embodiment;

[0059] Figure 3 This is a three-dimensional structural diagram of the structure obtained in step S12 of the semiconductor structure fabrication method provided in one embodiment;

[0060] Figure 4 This is a flowchart of step S13, forming a bit line structure in a substrate, in a semiconductor structure fabrication method provided in one embodiment.

[0061] Figure 5 This is a three-dimensional structural diagram of the structure obtained in step S131 of the semiconductor structure fabrication method provided in one embodiment;

[0062] Figure 6 This is a three-dimensional structural diagram of the structure obtained in step S132 of the semiconductor structure fabrication method provided in one embodiment;

[0063] Figure 7 This is a flowchart of step S14, forming an active region structure on a bit line structure, in a semiconductor structure fabrication method provided in one embodiment.

[0064] Figure 8 This is a three-dimensional structural diagram of the structure obtained in step S141 of the semiconductor structure fabrication method provided in one embodiment;

[0065] Figure 9 This is a three-dimensional structural diagram of the structure obtained in step S142 of the semiconductor structure fabrication method provided in one embodiment;

[0066] Figure 10 This is a three-dimensional structural diagram of the structure obtained in step S143 of the semiconductor structure fabrication method provided in one embodiment;

[0067] Figure 11 This is a three-dimensional structural diagram of the structure obtained in step S144 of the semiconductor structure fabrication method provided in one embodiment;

[0068] Figure 12 This is a three-dimensional structural diagram of the structure obtained in step S145 of the semiconductor structure fabrication method provided in one embodiment.

[0069] Figure 13 This is a three-dimensional structural schematic diagram of the structure obtained by forming a gate oxide layer on the surface of the stress layer exposed in a semiconductor structure fabrication method provided in one embodiment.

[0070] Figure 14 This is a three-dimensional structural diagram of the structure obtained in step S15 of the semiconductor structure fabrication method provided in one embodiment.

[0071] Figure 15 This is a flowchart illustrating a method for fabricating a semiconductor structure in one embodiment, in which a word line structure is formed around a channel region and a connection dielectric layer is formed around a first connection terminal and a second connection terminal.

[0072] Figure 16 This is a three-dimensional structural diagram of the structure obtained in step S161 of the semiconductor structure fabrication method provided in one embodiment;

[0073] Figure 17 This is a three-dimensional structural diagram of the structure obtained in step S162 of the semiconductor structure fabrication method provided in one embodiment;

[0074] Figure 18This is a three-dimensional structural diagram of the structure obtained in step S163 of the semiconductor structure fabrication method provided in one embodiment;

[0075] Figure 19 This is a three-dimensional structural diagram of the structure obtained in step S164 of the semiconductor structure fabrication method provided in one embodiment;

[0076] Figure 20 This is a three-dimensional structural diagram of a semiconductor structure fabrication method provided in one embodiment, in which a filling dielectric layer is formed in an isolation trench and the filling dielectric layer fills the isolation trench.

[0077] Figure 21 This is a three-dimensional structural diagram of a semiconductor structure provided in one embodiment;

[0078] Figure 22 A three-dimensional structural schematic diagram of a semiconductor structure provided in another embodiment;

[0079] Figure 23 This is a flowchart of a method for preparing a storage structure provided in one embodiment;

[0080] Figure 24 This is a three-dimensional structural diagram of the structure obtained in step S232 of the method for preparing the storage structure provided in one embodiment;

[0081] Figure 25 This is a three-dimensional structural diagram of the structure obtained in step S233 of the method for preparing the storage structure provided in one embodiment.

[0082] Figure 26 This is a three-dimensional structural diagram of a storage structure provided in one embodiment.

[0083] Explanation of reference numerals in the attached figures:

[0084] 11. Substrate; 12. Isolation layer; 13. Bit line trench; 2. Bit line structure; 30. Active region via; 31. Active pillar; 32. Stress layer; 33. First connection terminal; 34. Second connection terminal; 36. Sacrificial substrate; 4. Word line structure; 41. Word line material layer; 5. Gate oxide layer; 6. Connection terminal dielectric layer; 61. First dielectric material layer; 7. Connection terminal dielectric layer; 71. Second dielectric material layer; 8. Isolation trench; 9. Filling dielectric layer; 200. Storage node structure; 300. Capacitor. Detailed Implementation

[0085] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0087] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0088] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0089] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0090] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0091] With the development of semiconductor technology, three-dimensional memory structures have attracted widespread market attention due to their higher storage density per unit area compared to two-dimensional memory structures, and users are constantly increasing their performance requirements for three-dimensional memory structures. However, existing three-dimensional memory structures suffer from significant design flaws or negative impacts during fabrication, resulting in excessive electron accumulation in the bit line structure or poor contact between the drain and the bit line, leading to low electron mobility and ultimately device failure.

[0092] Therefore, it is necessary to provide a semiconductor structure, a memory structure, and a method for fabricating the same, addressing the problems of excessive electron accumulation in the bit line structure and low electron mobility due to poor contact between the drain and the bit line in the existing technology.

[0093] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0094] S11: Provides a substrate;

[0095] S12: An isolation layer is formed on the surface of the substrate;

[0096] S13: A bitline structure is formed within the isolation layer;

[0097] S14: An active region structure is formed on the bit line structure. The active region structure includes an active pillar and a stress layer. The active pillar is located on the bit line structure, and the stress layer covers the exposed surface of the active pillar. The active region structure includes a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end. The first connection end is electrically connected to the bit line structure.

[0098] S15: A character line structure is formed on the outer periphery of the channel area.

[0099] In the above example, the semiconductor structure fabrication method of the present invention, by forming a stress layer 32 covering the active pillar 31 around the active pillar 31, can greatly increase the electron mobility of the active pillar 31 by introducing stress, thereby improving the performance of the semiconductor structure.

[0100] In step S11, please refer to Figure 1 Step S11 in the middle and Figure 2 Substrate 11 is provided.

[0101] In one embodiment, substrate 11 may include, but is not limited to, at least one of silicon substrate, gallium arsenide substrate, gallium nitride substrate and silicon carbide substrate. Specifically, substrate 11 may be any one of silicon substrate, gallium arsenide substrate, gallium nitride substrate and silicon carbide substrate, or may be a composite substrate composed of two or more of them.

[0102] In step S12, please refer to Figure 1 Step S12 in the middle and Figure 3 An isolation layer 12 is formed on the surface of the substrate 11.

[0103] In one embodiment, the isolation layer 12 may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer; specifically, the isolation layer 12 may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or may be a composite layer composed of two or more of them.

[0104] In step S13, please refer to Figure 1 Step S13 in the middle and Figures 4 to 6 A bitline structure 2 is formed within the isolation layer 12.

[0105] In one example, such as Figure 4 As shown, step S13: forming a bit line structure 2 within the isolation layer 12 may include the following steps:

[0106] S131: A bitline groove 13 is formed within the isolation layer 12; such as Figure 5 As shown; specifically, bit line trenches 13 can be formed in the isolation layer 12 by etching.

[0107] S132: A bit line structure 2 is formed within the bit line groove 13; such as Figure 6 As shown.

[0108] It should be noted that before forming the bit line trench 13 in the isolation layer 12, a chemical mechanical polishing step is also included to ensure that the surface flatness of the isolation layer 12 meets the requirements, so as to avoid adverse effects on the semiconductor structure due to the unevenness of the surface of the isolation layer 12.

[0109] In one embodiment, the bit line structure 2 can be a metal structure; the word line structure 4 can be either a metal structure or a polysilicon structure.

[0110] In step S14, please refer to Figure 1 Step S14 in the middle and Figures 7 to 12 An active region structure is formed on the bit line structure 2. The active region structure includes an active post 31 and a stress layer 32. The active post 31 is located on the bit line structure 2, and the stress layer 32 covers the exposed surface of the active post 31. The active region structure includes a first connection end 33, a second connection end 34, and a channel region (not shown) located between the first connection end 33 and the second connection end 34. The first connection end 33 is electrically connected to the bit line structure 2.

[0111] In one embodiment, such as Figure 7 As shown, step S14: forming an active region structure on bitline structure 2 may include the following steps:

[0112] S141: A surface-bonded sacrificial substrate 36 with a bit line structure 2 is formed on the isolation layer 12; such as Figure 8 As shown;

[0113] S142: An active region via 30 is formed within the sacrificial substrate 36, exposing the bit line structure 2; as shown. Figure 9 As shown;

[0114] S143: An active pillar 31 is formed within the through-hole 30 in the active region; such as Figure 10 As shown;

[0115] S144: Remove sacrificial substrate 36; as shown Figure 11 As shown;

[0116] S145: A stress layer 32 is formed on the exposed surface of the active pillar 31, and the stress layer 32 and the active pillar 31 together constitute the active region structure; such as Figure 12 As shown.

[0117] In one example, the sacrificial substrate 36 may be a silicon sacrificial substrate or a dielectric sacrificial substrate; the method of forming the sacrificial substrate 36 on the surface of the isolation layer 12 where the bit line structure 2 is formed may be an epitaxial growth method or a deposition method.

[0118] In one embodiment, see still Figure 9 and Figure 10 The active region via 30 can penetrate the sacrificial substrate 36 along the thickness direction and extend into the bit line structure 2; the active pillar 31 can be embedded in the bit line structure 2 so that the active pillar 31 can make better contact with the bit line structure 2, reduce the contact resistance, and improve the electron transport rate.

[0119] In one embodiment, the active pillar 31 formed in the active region via 30 can be grown in the via using an epitaxial method; a germanium-silicon pillar can be formed in the active region via 30 as the active pillar 31. The use of the germanium-silicon pillar can improve the adverse effects caused by the need to bond silicon when using silicon as the active pillar 31, and the germanium-silicon pillar is doped silicon germanide; a silicon layer can be formed on the exposed surface of the active pillar 31 as a stress layer 32. The silicon layer as a stress layer 32 can help the active region structure and the bit line structure 2 to have better contact, increase electron mobility, and promote electron transport between the active region structure and the bit line structure 2.

[0120] In one embodiment, see still Figures 9 to 12Multiple active region vias 30 can be formed simultaneously within the sacrificial substrate 36, and the active region vias 30 can be arranged in multiple rows and columns. Active pillars 31 are formed within each active region via 30. After the stress layer 32 is formed, multiple active region structures are obtained, and the active region structures are arranged in multiple rows and columns. Multiple bit line structures 2 are formed within the isolation layer 12, and the multiple bit line structures 2 are arranged in parallel and spaced apart, extending along the row direction of the active region structures. Setting such an orderly structure will not cause chaotic electrical connections inside the semiconductor structure, thereby greatly reducing the risk of short circuits and improving device performance.

[0121] In one embodiment, after forming a stress layer 32 on the exposed surface of the active pillar 31, the method further includes forming a gate oxide layer 5 on the exposed surface of the stress layer 32, resulting in a structure as follows: Figure 13 As shown.

[0122] In step S15, please refer to Figure 1 Step S15 in the middle and Figure 14 A character-line structure 4 is formed on the outer periphery of the channel area.

[0123] In one embodiment, while forming the word line structure 4 around the channel region, a connection end dielectric layer is also formed around the first connection end 33 and the second connection end 34. For example... Figure 15 As shown, forming a word line structure 4 around the channel region and forming a connection end dielectric layer around the first connection end 33 and the second connection end 34 may include the following steps:

[0124] S161: A first dielectric material layer 61 is formed on the surface of the isolation layer 12 where the bit line structure 2 is formed, and the first dielectric material layer 61 fills the gap between adjacent first connection ends; such as Figure 16 As shown;

[0125] S162: A word line material layer 41 is formed on the surface of the first dielectric material layer 61, and the word line material layer 41 fills the gaps between adjacent channel regions; such as Figure 17 As shown;

[0126] S163: A second dielectric material layer 71 is formed on the surface of the word line material layer 41, and the second dielectric material layer 71 fills the gap between adjacent second connection ends; as shown in the example. Figure 18 As shown;

[0127] S164: Etch the second dielectric material layer 71, the word line material layer 41, and the first dielectric material layer 61 to form an isolation trench 8 extending along the column direction of the active region structure between adjacent columns of active region structures, so as to obtain a connection end dielectric layer and multiple word line structures 4 extending along the column direction of the active region structure, each word line structure 4 covering the channel area of ​​the active region structure located in the same column; such as Figure 19 As shown.

[0128] For details, please refer to Figure 19 The connection end dielectric layer may include connection end dielectric layer 6 and connection end dielectric layer 7; connection end dielectric layer 6 is located on the periphery of the first connection end, and connection end dielectric layer 7 is located on the periphery of the second connection end.

[0129] In one embodiment, the first dielectric material layer 61 may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon carbide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the first dielectric material layer 61 may be any one of the silicon oxynitride layer, silicon carbide layer, silicon oxide layer, silicon nitride layer, and silicon carbide layer, or it may be a composite layer composed of two or more of these layers. The word line material layer 41 may be a metal material layer. The second dielectric material layer 71 may include, but is not limited to, the silicon oxynitride layer, silicon carbide layer, silicon oxide layer, silicon nitride layer, and silicon carbide layer. At least one, specifically, the second dielectric material layer 71 may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or a composite layer composed of two or more of them; the connection end dielectric layer may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the connection end dielectric layer may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or a composite layer composed of two or more of them.

[0130] In one embodiment, after forming the isolation trench 8, the method further includes forming a filling medium layer 9 within the isolation trench 8, wherein the filling medium layer 9 fills the isolation trench 8, resulting in a structure as shown below. Figure 20 As shown. The filling dielectric layer 9 may include, but is not limited to, at least one of the following: a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the filling dielectric layer 9 may be any one of the following: a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or it may be a composite layer composed of two or more of these layers.

[0131] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0132] Based on the same inventive concept, the present invention also provides a semiconductor structure, please refer to [link / reference]. Figure 21 The semiconductor structure includes a substrate 11, an isolation layer 12, an active region structure, and a word line structure 4. The substrate 11 has an isolation layer 12, and the isolation layer 12 has a bit line structure 2. The bit line structure 2 is at least partially exposed to the isolation layer 12. The active region structure includes an active pillar 31 and a stress layer 32. The active pillar 31 is located on the bit line structure 2, and the stress layer 32 covers the exposed surface of the active pillar 31. The active region structure includes a first connection terminal 33, a second connection terminal 34, and a channel region (not shown) located between the first connection terminal 33 and the second connection terminal 34. The first connection terminal 33 is electrically connected to the bit line structure 2. The word line structure 4 covers the periphery of the channel region.

[0133] In the above example, the semiconductor structure of the present invention includes a substrate 11, an isolation layer 12, an active region structure, and a word line structure 4. The isolation layer 12 has a bit line structure 2. The active region structure includes an active pillar 31 and a stress layer 32. The active pillar 31 is located on the bit line structure 2, and the stress layer 32 covers the exposed surface of the active pillar 31. By providing a stress layer 32 covering the active pillar 31 around the active pillar 31, the electron mobility of the active pillar 31 can be greatly increased by introducing stress, thereby improving the performance of the semiconductor structure.

[0134] In one embodiment, the substrate 11 may include, but is not limited to, at least one of a silicon substrate 11, a gallium arsenide substrate 11, a gallium nitride substrate 11, and a silicon carbide substrate 11. Specifically, the substrate 11 may be any one of a silicon substrate 11, a gallium arsenide substrate 11, a gallium nitride substrate 11, and a silicon carbide substrate 11, or a composite substrate 11 composed of two or more of these substrates. The isolation layer 12 may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the isolation layer 12 may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or a composite layer composed of two or more of these substrates.

[0135] In one embodiment, the bit line structure 2 can be a metal structure; the word line structure 4 can be either a metal structure or a polysilicon structure.

[0136] In one embodiment, a gate oxide layer 5 may also be coated on the surface of the stress layer 32, such as... Figure 13 As shown.

[0137] In one embodiment, see still Figure 21 The active post 31 can be embedded in the bit line structure 2 so that the active region structure and the bit line structure 2 can make full contact and reduce the contact resistance between the active region structure and the bit line structure 2.

[0138] In one embodiment, see still Figure 21 The active region structure is arranged in multiple rows and columns. The isolation layer 12 has multiple bit line structures 2, which are arranged in parallel and spaced apart, and extend along the row direction of the active region structure. There are multiple word line structures 4, which are arranged in parallel and spaced apart, and extend along the column direction of the active region structure. Each word line structure 4 covers the channel region of the active region structure located in the same column. This orderly arrangement structure will not cause chaotic electrical connections inside the semiconductor structure, thereby greatly reducing the risk of short circuit and improving device performance.

[0139] In one embodiment, such as Figure 22 As shown, the semiconductor structure also includes an insulating dielectric layer located between adjacent word line structures and filling the gaps between active region structures. The insulating dielectric layer may include a terminal dielectric layer and a filling dielectric layer 9. Combined with... Figure 21 and Figure 22 The connecting end dielectric layer covers the periphery of the first connecting end and the periphery of the second connecting end; the filling dielectric layer 9 is located on the periphery of the connecting end dielectric layer and the periphery of the word line structure 4.

[0140] For details, please refer to Figure 21 and Figure 22 The connection end dielectric layer may include connection end dielectric layer 6 and connection end dielectric layer 7; connection end dielectric layer 6 is located around the first connection end 33, and connection end dielectric layer 7 is located around the second connection end 34.

[0141] In one embodiment, the connection end dielectric layer may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the connection end dielectric layer may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or it may be a composite layer composed of two or more of these layers. The filling dielectric layer 9 may include, but is not limited to, at least one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer. Specifically, the filling dielectric layer 9 may be any one of a silicon oxynitride layer, a silicon oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer, or it may be a composite layer composed of two or more of these layers.

[0142] In one embodiment, the active pillar 31 may include a germanium-silicon pillar, which can improve the adverse effects caused by the need to bond silicon when using silicon as the active pillar 31 in the prior art, and the germanium-silicon pillar is a doped silicon germanide; the silicon layer serves as the stress layer 32, which can help the active region structure and the bit line structure 2 to make better contact, increase electron mobility, and promote electron transport between the active region structure and the bit line structure 2. The stress layer 32 includes a silicon layer.

[0143] Based on the same inventive concept, the present invention also provides a method for preparing a storage structure, such as... Figure 23 As shown, the method for fabricating the storage structure includes the following steps:

[0144] S231: The semiconductor structure is prepared by the semiconductor structure preparation method of any of the above schemes;

[0145] S232: A memory node structure 200 is formed on the surface of the active region structure away from the substrate 11; such as Figure 24 As shown,

[0146] S233: A capacitor 300 is formed on the surface of the storage node structure 200 away from the active region structure; such as Figure 25 As shown.

[0147] The method for fabricating the memory structure of the present invention includes fabricating the semiconductor structure in any of the above-mentioned schemes, fabricating the memory node structure 200, and fabricating the capacitor 300. Its beneficial effects can be referred to the beneficial effects of the semiconductor structure and the method for fabricating the semiconductor structure of the present invention, and will not be repeated here.

[0148] In one embodiment, see Figure 25The active region structure is arranged in multiple rows and columns; the isolation layer 12 has multiple bit line structures 2, which are arranged in parallel and spaced apart, and extend along the row direction of the active region structure; there are multiple word line structures 4, which are arranged in parallel and spaced apart, and extend along the column direction of the active region structure, and each word line structure 4 covers the channel region of the active region structure located in the same column; multiple memory node structures 200 are formed on the surface of the active region structure away from the substrate 11, and the memory node structures 200 are arranged one-to-one with the active region structures; multiple capacitors 300 are formed on the surface of the memory node structures 200 away from the active region structure, and the capacitors 300 are arranged one-to-one with the memory node structures 200; the capacitor 300 includes a lower electrode, a capacitor dielectric layer located on the surface of the lower electrode, and an upper electrode located on the capacitor dielectric layer away from the surface of the lower electrode, the lower electrodes of adjacent capacitors 300 are insulated and isolated through the capacitor dielectric layer, and the upper electrodes of all capacitors 300 can be connected to each other.

[0149] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0150] Based on the same inventive concept, the present invention also provides a storage structure, such as... Figure 26 As shown, the memory structure includes: the semiconductor structure described in any of the above embodiments, the memory node structure 200, and the capacitor 300; the memory node structure 200 is located on the surface of the active region structure away from the substrate 11; the capacitor 300 is located on the surface of the memory node structure 200 away from the active region structure.

[0151] In one embodiment, see Figure 26The active region structure is arranged in multiple rows and columns. The isolation layer 12 has multiple bit line structures 2, which are arranged in parallel and spaced apart, and extend along the row direction of the active region structure. There are multiple word line structures 4, which are arranged in parallel and spaced apart, and extend along the row direction of the active region structure. Each word line structure 4 covers the channel area of ​​the active region structure located in the same column. There are multiple storage node structures 200, which are set one-to-one with the active region structures. There are multiple capacitors 300, which are set one-to-one with the storage node structures 200. Each capacitor 300 includes a lower electrode, a capacitor dielectric layer located on the surface of the lower electrode, and an upper electrode located on the capacitor dielectric layer away from the surface of the lower electrode. The lower electrodes of adjacent capacitors 300 are insulated and isolated by the capacitor dielectric layer, and the upper electrodes of all capacitors 300 can be connected to each other.

[0152] The storage structure of the present invention includes a semiconductor structure of any of the above-described embodiments, a storage node structure 200, and a capacitor 300. The beneficial effects of the semiconductor structure are as described above, including lower contact resistance and higher electron mobility. The storage node structure 200 is configured in a one-to-one correspondence with the active region structure, and the capacitor 300 is configured in a one-to-one correspondence with the storage node structure 200. The lower electrode of the capacitor 300 is insulated and isolated, and the upper electrodes of all capacitors 300 are connected to each other, together forming the storage structure of the present invention with lower contact resistance and higher electron mobility.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; An isolation layer is formed on the surface of the substrate; A bitline structure is formed within the isolation layer; An active region structure is formed on the bit line structure. The active region structure includes an active post and a stress layer. The active post is located on the bit line structure, and the stress layer covers the exposed surface of the active post. The active region structure includes a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end. The first connection end is electrically connected to the bit line structure. A character line structure is formed around the periphery of the channel area.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the bit line structure within the isolation layer includes: Bit line trenches are formed within the isolation layer; The bit line structure is formed within the bit line trench.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The formation of the active region structure on the bit line structure includes: A surface-bonded sacrificial substrate having the bit line structure formed on the isolation layer; An active region via is formed within the sacrificial substrate, and the active region via exposes the bit line structure; The active pillar is formed within the through hole of the active region; Remove the sacrificial substrate; The stress layer is formed on the exposed surface of the active pillar, and the stress layer and the active pillar together constitute the active region structure.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The active region via penetrates the sacrificial substrate along the thickness direction and extends into the bit line structure; the active pillar is embedded in the bit line structure.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, A germanium-silicon pillar is formed within the via of the active region as the active pillar, and a silicon layer is formed on the exposed surface of the active pillar as the stress layer.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that, Multiple active region vias are formed within the sacrificial substrate, and the active region vias are arranged in multiple rows and columns; an active pillar is formed within each of the active region vias; after the stress layer is formed, multiple active region structures are obtained, and the active region structures are arranged in multiple rows and columns; multiple bit line structures are formed within the isolation layer, and the multiple bit line structures are arranged in parallel and spaced apart, and extend along the row direction of the active region structures.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, While forming a word line structure around the channel region, a connection end dielectric layer is also formed around the first connection end and the second connection end; the forming of the word line structure around the channel region and the forming of the connection end dielectric layer around the first connection end and the second connection end includes: A first dielectric material layer is formed on the surface of the isolation layer where the bit line structure is formed, and the first dielectric material layer fills the gap between adjacent first connection ends; A word line material layer is formed on the surface of the first dielectric material layer, and the word line material layer fills the gap between adjacent channel regions; A second dielectric material layer is formed on the surface of the word line material layer, and the second dielectric material layer fills the gap between adjacent second connection ends; The second dielectric material layer, the word line material layer, and the first dielectric material layer are etched to form isolation trenches extending along the column direction of the active region structures between adjacent columns of the active region structures, so as to obtain the connection end dielectric layer and multiple word line structures extending along the column direction of the active region structures, each word line structure covering the channel region of the active region structure located in the same column.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After forming the isolation groove, it also includes: A filling medium layer is formed inside the isolation groove, and the filling medium layer fills the isolation groove.

9. A method for fabricating a storage structure, characterized in that, include: The semiconductor structure is prepared using the method for preparing the semiconductor structure as described in any one of claims 1 to 8; A memory node structure is formed on the surface of the active region structure away from the substrate; A capacitor is formed on the surface of the storage node structure that is away from the active region structure.

10. The method for fabricating the storage structure according to claim 9, characterized in that, The number of active region structures, storage node structures, and capacitors are all multiple; each storage node structure corresponds to one active region structure; each capacitor corresponds to one storage node structure.

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