Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. An embodiment of the present invention provides a semiconductor device capable of reducing the width of an underlying wiring. In the semiconductor device of the embodiment, a distance (d1) between an end surface (70a) of an electrode layer (70) facing a side surface of a via (81) and the side surface of the via (81) along a diameter direction of the via (81) is larger than a distance (d2) between an end surface (72a) of an insulator (72) facing the side surface of the via (81) and the side surface of the via (81) along the diameter direction.

Description

[0001] This application is a divisional application of patent application No. 201710741007.2, filed on August 25, 2017, entitled "Semiconductor Device and Method of Manufacturing Thereof".

[0002] This application claims priority to Japanese Patent Application No. 2017-46172 (filed on March 10, 2017). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0004] In order to connect the wiring arranged on the upper and lower layers of a stack including multiple electrode layers, it is required to form vias that penetrate the stack and reach the wiring on the lower layer. Summary of the Invention

[0005] The embodiment provides a semiconductor device and a method for manufacturing the same, which can reduce the width of the underlying wiring.

[0006] According to an embodiment, a semiconductor device includes: a lower layer wiring; an upper layer wiring; a stacked body disposed between the lower layer wiring and the upper layer wiring and having a plurality of electrode layers stacked with an insulator as a separator; a via that is conductive and penetrates the stacked body to connect the upper layer wiring and the lower layer wiring; and an insulating film disposed between the via and the stacked body. The distance along the diameter direction of the via between an end face of an electrode layer facing a side of the via and the side of the via is greater than the distance along the diameter direction between an end face of an insulator facing a side of the via and the side of the via. Attached Figure Description

[0007] Figure 1 This is a schematic top view of the semiconductor device according to the embodiment.

[0008] Figure 2 This is a schematic perspective view of the semiconductor device according to the implementation method.

[0009] Figure 3 yes Figure 1 AA section diagram.

[0010] Figure 4 yes Figure 3 An enlarged cross-sectional view of a portion of the image.

[0011] Figure 5 yes Figure 1 BB cross-sectional view.

[0012] Figure 6 (a) is Figure 5 CC section diagram, Figure 6 (b) is Figure 5 DD cross-sectional view.

[0013] Figures 7 to 22 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0014] Figure 23 This is a schematic top view of the semiconductor device according to the embodiment.

[0015] Figure 24 yes Figure 23 EE cross-sectional view.

[0016] Figure 25 yes Figure 23 FF cross-sectional view.

[0017] Figure 26 (a) ~ Figure 38 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0018] Figure 39 This is a schematic top view of the semiconductor device according to the embodiment.

[0019] Figure 40 (a) ~ Figure 42 (b) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0020] Figure 43 (a) and (b) are Figure 5 An enlarged cross-sectional view of a portion of the image. Detailed Implementation

[0021] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in each drawing, the same elements are labeled with the same symbols.

[0022] In the embodiments, a semiconductor memory device having, for example, a memory cell array with a three-dimensional structure will be described as a semiconductor device.

[0023] Figure 1 This is a schematic top view of the cell array region in the semiconductor device according to the embodiment.

[0024] Figure 2 This is a schematic perspective view of the memory cell array 1 in the semiconductor device according to the embodiment.

[0025] Figure 3 yes Figure 1 A-A cross-sectional view.

[0026] like Figure 1 As shown, multiple columnar sections CL and multiple vias 81 are arranged within the unit array region. The multiple columnar sections CL are interconnected. Figure 2 and Figure 3 The laminate 100 is shown. Multiple vias 81 also penetrate the laminate 100 as described later.

[0027] exist Figure 2 In this diagram, two directions parallel and orthogonal to the main surface of substrate 10 are designated as the X and Y directions, and a direction orthogonal to both the X and Y directions is designated as the Z direction (stack direction). The X, Y, and Z directions in other figures are respectively... Figure 2 The X, Y, and Z directions correspond to each other.

[0028] The memory cell array 1 has: a source layer SL, a stack 100 disposed on the source layer SL, a plurality of columnar portions CL, a plurality of separation portions 61, and a plurality of bit lines BL disposed above the stack 100.

[0029] like Figure 3 As shown, a circuit layer 11 is provided between the substrate 10 and the source layer SL. The circuit layer 11 includes lower layer wiring 12, for example, as metal wiring. Insulating layers 13 are provided between the lower layer wiring 12 and the substrate 10, between the lower layer wiring 12 and the source layer SL, and between the lower layer wiring 12 and each other. The source layer SL is connected to the lower layer wiring 12 through vias (not shown).

[0030] The substrate 10 is, for example, a silicon substrate. Transistors, such as MOSFETs (metal-oxide-semiconductor field-effect transistors), are formed on the surface of the substrate 10. The transistors formed on the circuit layer 11 and the surface of the substrate 10 constitute the detection amplifier circuit, word line driver circuit, and other control circuits of the memory cell array 1.

[0031] The columnar portions CL are formed as generally cylindrical portions extending in the lamination direction (Z direction) of the laminate 100 within the laminate 100. Multiple columnar portions CL are arranged, for example, in an alternating pattern. Alternatively, multiple columnar portions CL may be arranged in a square grid pattern along the X and Y directions.

[0032] The separating portion 61 extends in the X direction, separating the laminate 100 into multiple blocks (or finger-like portions) in the Y direction. For example... Figure 3 As shown, the separation part 61 is an insulating film embedded in the slit.

[0033] Figure 2 The multiple bit lines BL shown are, for example, metal films extending in the Y direction. The multiple bit lines BL are separated from each other in the X direction.

[0034] The upper end of the columnar portion CL, described later, of the semiconductor body 20, via Figure 2 Connector Cb and connector V1 are shown connected to bit line BL.

[0035] like Figure 3 As shown, the source layer SL is a laminated film of a metal-containing layer 15 and a semiconductor layer 16. The metal-containing layer 15 is disposed between the insulating layer 13 and the semiconductor layer 16. The metal-containing layer 15 is, for example, a tungsten layer or a tungsten silicide layer. The semiconductor layer 16 is a polycrystalline silicon layer containing impurities (e.g., phosphorus) and having electrical conductivity.

[0036] A metal nitride film (titanium nitride film) may also be formed between the metal-containing layer (tungsten layer) 15 and the semiconductor layer (polycrystalline silicon layer) 16.

[0037] A stack 100 is provided on the source layer SL. The stack 100 has a plurality of electrode layers 70 stacked in a direction perpendicular to the main surface of the substrate 10 (Z direction). An insulating layer (insulator) 72 is provided between adjacent electrode layers 70. The insulator between the electrode layers 70 may also be a void. An insulating layer 72 is provided between the bottom electrode layer 70 and the source layer SL. An insulating layer 41 is provided on the top electrode layer 70. The source layer SL is thicker than one electrode layer 70.

[0038] Electrode layer 70 is a metal layer. Electrode layer 70 is, for example, a tungsten layer containing tungsten as the main component, or a molybdenum layer containing molybdenum as the main component. Insulating layer 72 is, for example, a silicon oxide layer containing silicon oxide as the main component.

[0039] The columnar portion CL extends within the laminate 100 in the stacking direction of the laminate 100, and the lower end of the semiconductor body 20 of the columnar portion CL is in contact with the semiconductor layer 16 of the source layer SL.

[0040] Figure 4 yes Figure 3 An enlarged cross-sectional view of a portion of the image.

[0041] The columnar portion CL has: a memory film 30, a semiconductor body 20, and an insulating core film 50. The memory film 30 is a laminated film of insulating films having a channel insulating film 31, a charge storage film (charge storage portion) 32, and a block insulating film 33.

[0042] like Figure 3 As shown, the semiconductor body 20 is formed as a tube that extends continuously in the stacking direction within the laminate 100 and reaches the source layer SL. A core film 50 is disposed inside the tubular semiconductor body 20. A memory film 30 is disposed between the laminate 100 and the semiconductor body 20, surrounding the semiconductor body 20 from its outer periphery.

[0043] like Figure 4 As shown, the channel insulating film 31 is disposed between the semiconductor body 20 and the charge storage film 32, and is in contact with the semiconductor body 20. The charge storage film 32 is disposed between the channel insulating film 31 and the bulk insulating film 33. The bulk insulating film 33 is disposed between the charge storage film 32 and the electrode layer 70.

[0044] The semiconductor body 20, the memory film 30, and the electrode layer 70 constitute a memory cell MC. The memory cell MC has a vertical transistor structure in which the electrode layer 70 surrounds the semiconductor body 20 through the memory film 30.

[0045] In this vertical transistor-structured memory cell MC, the semiconductor body 20 is, for example, a silicon channel body, and the electrode layer 70 functions as a control gate. The charge storage film 32 functions as a data storage layer that stores the charge injected from the semiconductor body 20.

[0046] The semiconductor memory device described in the embodiment is a non-volatile semiconductor memory device that can electrically erase and write data and retain the stored content even when the power is cut off.

[0047] The memory cell MC is, for example, a charge-trapping type memory cell. The charge storage film 32 has many trap sites for capturing charges in an insulating film, such as a silicon nitride film. Alternatively, the charge storage film 32 can also be a conductive floating gate surrounded by an insulator.

[0048] The channel insulating film 31 acts as a barrier when charge is injected into the charge storage film 32 from the semiconductor body 20 or when the charge stored in the charge storage film 32 is released to the semiconductor body 20. The channel insulating film 31 includes, for example, a silicon oxide film.

[0049] The insulating film 33 prevents the charge accumulated in the charge storage film 32 from being released to the electrode layer 70. In addition, the insulating film 33 prevents the charge from back-tunneling from the electrode layer 70 to the columnar portion CL.

[0050] The insulating film 33 has a first film 34 and a second film 35. The first film 34 is, for example, a silicon oxide film. The second film 35 is a metal oxide film with a higher dielectric constant than the silicon oxide film. Examples of such metal oxide films include aluminum oxide films, zirconium oxide films, and hafnium oxide films.

[0051] The first membrane 34 is disposed between the charge storage membrane 32 and the second membrane 35. The second membrane 35 is disposed between the first membrane 34 and the electrode layer 70.

[0052] The channel insulating film 31, the charge storage film 32, and the first film 34 extend continuously in the stacking direction of the laminate 100. The second film 35 is also disposed between the electrode layer 70 and the insulating layer 72. The second film 35 is separated and discontinuous in the stacking direction of the laminate 100.

[0053] Alternatively, instead of forming a second film 35 between the electrode layer 70 and the insulating layer 72, a second film 35 may be formed continuously along the stacking direction. Alternatively, the insulating film 33 may be a single-layer film that is continuous along the stacking direction.

[0054] like Figure 2 As shown, a drain-side selection transistor (STD) is provided in the upper layer of the stack 100. A source-side selection transistor (STS) is provided in the lower layer of the stack 100.

[0055] A drain-side select transistor (STD) is a vertical transistor having at least one electrode layer 70 on the upper side as a drain-side select gate, and a source-side select transistor (STS) is a vertical transistor having at least one electrode layer 70 on the lower side as a source-side select gate.

[0056] The portion of the semiconductor body 20 facing the drain-side select gate functions as a channel, and the memory film 30 between the channel and the drain-side select gate functions as the gate insulating film of the drain-side select transistor STD.

[0057] The portion of the semiconductor body 20 facing the source-side select gate functions as a channel, and the memory film 30 between the channel and the source-side select gate functions as the gate insulating film of the source-side select transistor STS.

[0058] like Figure 3 As shown, the electrode layer 70, which functions as a drain-side selection gate, is separated in the Y direction not only by the separation section 61 but also by the separation section 62. Figure 1 As shown, the separation portion 62 extends parallel to the separation portion 61 in the X direction.

[0059] Multiple drain-side select transistors (STDs) connected in series through the semiconductor body 20 can be configured, or multiple source-side select transistors (STSs) connected in series through the semiconductor body 20 can be configured. The multiple drain-side select gates of the multiple drain-side select transistors (STDs) are given the same gate potential, and the multiple source-side select gates of the multiple source-side select transistors (STSs) are given the same gate potential.

[0060] Multiple memory cells MC are disposed between the drain-side select transistor STD and the source-side select transistor STS. The multiple memory cells MC, the drain-side select transistor STD, and the source-side select transistor STS are connected in series through the semiconductor body 20 of the columnar portion CL, forming a memory string. This memory string is arranged, for example, in an alternating manner in a plane direction parallel to the XY plane, and the multiple memory cells MC are arranged in three dimensions in the X, Y, and Z directions.

[0061] Next, we will explain via 81.

[0062] Figure 5 yes Figure 1 BB cross-sectional view.

[0063] Figure 6 (a) is Figure 5 CC section view.

[0064] Figure 6 (b) is Figure 5 DD cross-sectional view.

[0065] exist Figure 1 A portion of the cell array region shown is provided with multiple vias 81 instead of multiple columnar portions CL. Furthermore, multiple columnar portions HR are arranged around the multiple vias 81. The columnar portions HR penetrate the laminate 100 and have the same structure as the columnar portions CL, but are not connected to the bit lines BL. Alternatively, the columnar portions HR are pillars of the insulating film.

[0066] like Figure 5 and Figure 6 As shown, via 81 is formed in a generally cylindrical shape, penetrating the laminate 100, the source layer SL, and the insulating layer 13 directly below the source layer SL, reaching the lower layer wiring 12. The lower end of via 81 is in contact with the lower layer wiring 12. Via 81 is conductive, for example, it is a metallic via.

[0067] An insulating layer 42 is provided on the laminate 100, and an upper layer wiring 18, such as a metallic wiring, is provided on the insulating layer 42. An insulating layer 43 is provided around the upper layer wiring 18. A via 82 is provided between the upper end of a via 81 and the upper layer wiring 18, penetrating the insulating layer 42. The upper layer wiring 18 and the lower layer wiring 12 are electrically connected through the via 82 and the via 81.

[0068] An insulating film 63 is provided on the side of the generally cylindrical via 81 in a manner that surrounds the via 81. The insulating film 63 is disposed between the side of the via 81 and the electrode layer 70, between the side of the via 81 and the insulating layer 72, and between the side of the via 81 and the source layer SL.

[0069] like Figure 6 As shown in (a), the electrode layer 70 surrounds the via 81 through the insulating film 63. Figure 6 As shown in (b), insulating layer 72 surrounds the via 81 through insulating film 63. Source layer SL also surrounds the via 81 through insulating film 63.

[0070] The end face 70a of the electrode layer 70 facing the side of the via 81 is recessed in the diameter direction of the via 81, relative to the end face 72a of the insulating layer 72 facing the side of the via 82. The end faces 15a and 16a of the source layer SL facing the side of the via 81 are also recessed in the diameter direction of the via 81, relative to the end face 72a of the insulating layer 72.

[0071] The distance d1 between the end face 70a of the electrode layer 70 and the side surface of the via 81, along the diameter direction of the via 81, is greater than the distance d2 between the end face 72a of the insulating layer 72 and the side surface of the via 81, along the diameter direction.

[0072] The distance along the diameter between the end faces 15a and 16a of the source layer SL and the side of the via 81 is also greater than the distance along the diameter between the end face 72a of the insulating layer 72 and the side of the via 81.

[0073] The thickness of the insulating film 63 between the end face 70a of the electrode layer 70 and the side of the via 81 along the diameter direction of the via 81 (equivalent to the aforementioned distance d1) is thicker than the thickness of the insulating film 63 between the end face 72a of the insulating layer 72 and the side of the via 81 along the diameter direction (equivalent to the aforementioned distance d2).

[0074] The thickness of the insulating film 63 between the end faces 15a and 16a of the source layer SL and the side of the via 81 along the diameter direction is also thicker than the thickness of the insulating film 63 between the end face 72a of the insulating layer 72 and the side of the via 81 along the diameter direction.

[0075] like Figure 5 As shown, the sides and bottom of via 81 converge within the width of the lower layer wiring 12 and do not extend outwards compared to the edge 12a of the lower layer wiring 12 in the width direction. The end face 70a of the electrode layer 70 is located outwards compared to the edge 12a of the lower layer wiring 12 in the diameter direction of via 81. The end faces 15a and 16a of the source layer SL are also located outwards compared to the edge 12a of the lower layer wiring 12 in the diameter direction of via 81.

[0076] like Figure 6As shown in (a), the distance between the end faces 70a of the electrode layer 70 surrounding the via 81 (distance D1 along the diameter direction of the via 81) corresponds to the outer diameter of the insulating film 63 between the via 81 and the electrode layer 70. This distance (outer diameter) D1 is larger than the wiring width W of the lower wiring layer 12.

[0077] like Figure 5 As shown, the laminate 100 has a portion in which the insulating film 63 and the insulating layer 72 alternately repeat in the lamination direction of the laminate 100.

[0078] Next, the manufacturing method of the semiconductor device according to the embodiment will be described.

[0079] First, refer to Figures 7-15 To explain for Figure 3 The process of constructing the cross-section shown.

[0080] like Figure 7 As shown, a circuit layer 11 including a lower wiring layer 12 is formed on the substrate 10, and a source layer SL is formed on the circuit layer 11. A metal-containing layer 15 is formed on the insulating layer 13 of the circuit layer 11, and a semiconductor layer 16 is formed on the metal-containing layer 15.

[0081] An insulating layer 72, serving as a second layer, and a sacrificial layer 71, serving as a first layer, are alternately stacked on the source layer SL. This alternating stacking of insulating layers 72 and sacrificial layers 71 is repeated to form a laminate 100 having multiple sacrificial layers 71 and multiple insulating layers 72 on the source layer SL. An insulating layer 41 is formed on the uppermost sacrificial layer 71. For example, the sacrificial layer 71 is a silicon nitride layer, and the insulating layer 72 is a silicon oxide layer.

[0082] like Figure 8 As shown, a plurality of memory vias MH are formed in the stack 100. The memory vias MH are formed using a RIE (reactive ion etching) method using a mask layer (not shown). The memory vias MH penetrate the stack 100 and reach the semiconductor layer 16 of the source layer SL.

[0083] like Figure 9 As shown, a laminated film 30a is formed within the memory hole MH. The laminated film 30a is conformally formed along the side and bottom of the memory hole MH. The laminated film 30a includes, for example, […]. Figure 4 The memory film 30 shown includes a channel insulating film 31, a charge storage film 32, and a first film 34. The first film 34, the charge storage film 32, and the channel insulating film 31 are sequentially formed within the memory hole MH.

[0084] A protective silicon film 20a is formed on the inner side of the laminated film 30a. The protective silicon film 20a is formed conformally along the side and bottom of the memory hole MH.

[0085] Next, as Figure 10 As shown, a mask layer 150 is formed on the insulating layer 41, and the protective silicon film 20a and the laminated film 30a deposited at the bottom of the memory hole MH are removed by the RIE method. When this RIE is used, the laminated film 30a formed on the side of the memory hole MH is covered by the protective silicon film 20a and is protected from damage by the RIE.

[0086] After removing the mask layer 150, as Figure 11 As shown, a silicon substrate film 20b is formed within the memory hole MH. The silicon substrate film 20b is formed on the side of the protective silicon film 20a and on the semiconductor layer 16 exposed from the bottom of the memory hole MH. The lower end of the silicon substrate film 20b is in contact with the semiconductor layer 16.

[0087] The protective silicon film 20a and the silicon host film 20b, after being formed as, for example, an amorphous silicon film, are crystallized into a polycrystalline silicon film by heat treatment.

[0088] A core film 50 is formed inside the silicon host film 20b. Multiple columnar portions CL comprising the laminated film 30a, the semiconductor host 20, and the core film 50 are formed within the laminate 100.

[0089] For example, columnar portion HR, which has the same layered structure as columnar portion CL, can also be formed simultaneously with columnar portion CL. Subsequently, the film deposited on insulating layer 41 during the formation of columnar portion CL and / or columnar portion HR is removed by chemical mechanical polishing (CMP) or etch back.

[0090] After the columnar portion CL is formed, as Figure 12 As shown, in a later step, a separation section 62 is formed that separates at least the uppermost sacrificial layer 71 of the electrode layer 70, which can be replaced as a drain-side selection gate.

[0091] After that, as Figure 13 As shown, multiple slits ST are formed in the laminate 100 using a RIE method with a mask layer (not shown). The slits ST penetrate the laminate 100 and reach the source layer SL. The slits ST extend in the X direction, separating the laminate 100 into multiple blocks in the Y direction.

[0092] Next, the sacrificial layer 71 is removed by etchant or etch gas supplied through the gap ST. For example, the sacrificial layer 71, which serves as a silicon nitride layer, is removed using an etchant containing phosphoric acid.

[0093] Sacrifice layer 71 is removed, as... Figure 14As shown, a gap 75 is formed between adjacent insulating layers 72. The gap 75 is also formed between the uppermost insulating layer 72 and the insulating layer 41.

[0094] Multiple insulating layers 72, which are configured in regions with multiple columnar portions CL and HR, are in contact with the sides of the multiple columnar portions CL and HR in such a way that they surround the sides of the multiple columnar portions CL and HR. The multiple insulating layers 72 are supported by such physical bonding with the multiple columnar portions CL and HR, while maintaining the gaps 75 between the insulating layers 72.

[0095] like Figure 15 As shown, there is a gap of 75. Figure 4 The second film 35 shown forms an electrode layer 70. The second film 35 and electrode layer 70 are formed, for example, by CVD. Source gas is supplied to the void 75 through the slit ST. The electrode layer 70 formed on the side of the slit ST is removed.

[0096] Then, an insulating film is embedded in the gap ST to form Figure 3 The separation section 61 shown.

[0097] Next, refer to Figures 16-21 To explain for Figure 5 The process of constructing the cross-section shown.

[0098] like Figure 16 As shown, in the area where the via 81 is to be configured, a circuit layer 11, a source layer SL, and a stack 100 are also sequentially formed on the substrate 10.

[0099] Next, before or after the formation of the columnar portion CL, such as Figure 17 Hole 80 is formed as shown.

[0100] The via 80 penetrates the laminate 100, the source layer SL, and the insulating layer 13 directly below the source layer SL to reach the lower layer wiring 12. The via 80 is formed using a RIE method with a mask layer (not shown). The sacrificial layer 71 of the laminate 100 has not yet been replaced with the electrode layer 70.

[0101] The diameter of the hole 80 is smaller than the width of the wiring in the lower layer 12, and the hole 80 does not extend outward compared to the edge 12a of the lower layer wiring 12.

[0102] For example, using the semiconductor layer 16, which is a silicon layer, as a stopper, the same etching gas is used to continuously etch multiple sacrificial layers 71 and multiple insulating layers 72. Next, using the metal-containing layer 15 as a stopper, the semiconductor layer 16 is etched. Next, using the insulating layer 13 as a stopper, the metal-containing layer 15 is etched. Next, using the underlying wiring 12 as a stopper, the insulating layer 13 is etched.

[0103] The end face 71a of the sacrificial layer 71, the end face 72a of the insulating layer 72, the end face 16a of the semiconductor layer 16, and the end face 15a of the metal-containing layer 15 are continuous in the circumferential direction of the hole 80 and exposed in the hole 80 in a manner that surrounds the hole 80.

[0104] Next, the end face 71a of the sacrificial layer 71 is positioned relative to the surface exposed in the hole 80. Figure 17 The first position shown is farther away from the hole 80 in the diameter direction of the hole 80. Figure 18 The second position shown.

[0105] The end face 71a of the sacrificial layer 71 is moved back to a second position by isotropic etching such as chemical etching or CDE (Chemical Dry Etching). For example, the end face 71a of the sacrificial layer 71, which is a silicon nitride layer, is etched using a phosphoric acid-containing etchant to move it back to the second position.

[0106] Through isotropic etching, the end face 16a of the semiconductor layer 16 and the end face 15a of the metal-containing layer 15 are also etched from the semiconductor layer 16. Figure 17 The first position shown is moved back to Figure 18 The second position shown.

[0107] The end face 71a of the sacrificial layer 71, the end face 16a of the semiconductor layer 16, and the end face 15a of the metal-containing layer 15 are recessed in the diameter direction of the hole 80 compared to the end face 41a of the insulating layer 41 on the hole 80 side, the end face 72a of the insulating layer 72 on the hole 80 side, and the end face 13a of the insulating layer 13 on the hole 80 side.

[0108] A portion of the end face 71a of the retreated sacrificial layer 71, the end face 16a of the semiconductor layer 16, and the end face 15a of the metal-containing layer 15. Figure 18 The two sides of the cross section shown are located on the outer side of the edge 12a of the lower layer wiring 12 in the diameter direction of the hole 80, which is further out than the edge 12a in the wiring width direction of the lower layer wiring 12.

[0109] By retracting the end face 71a of the sacrificial layer 71, a gap 79 is formed between the insulating layer 41 and the insulating layer 72, and between adjacent insulating layers 72. By retracting the end face of the source layer SL (the end face 16a of the semiconductor layer 16 and the end face 15a of the metal-containing layer 15), a gap 77 is formed between the bottommost insulating layer 72 and the insulating layer 13.

[0110] like Figure 19As shown, an insulating film 63 is formed within the aperture 80. For example, by CVD or ALD (atomic layer deposition), the insulating film 63 is conformally formed along the side and bottom of the aperture 80. The insulating film 63 is also formed in the voids 79 formed by the retreat of the end face 71a of the sacrificial layer 71 and the voids 77 formed by the retreat of the end face of the source layer SL.

[0111] The insulating film 63 is a film made of a different material than the sacrificial layer 71, such as a silicon oxide film.

[0112] A cavity (part of the hole 80) remains inside the insulating film 63 within the hole 80. Next, the insulating film 63 formed at the bottom of the hole 80 is removed, for example, by a re-insulating film removal (RIE) method. Figure 20 As shown, the lower layer wiring 12 is exposed at the bottom of hole 80.

[0113] After that, as Figure 21 As shown, a via 81 is formed within the hole 80. Metal material is embedded within the hole 80, for example. The lower end of the via 81 contacts the underlying wiring 12.

[0114] Subsequently, as mentioned above Figures 13-15 As shown, the gap ST is formed and the sacrificial layer 71 passing through the gap ST is replaced by the electrode layer 70.

[0115] Furthermore, such as Figure 5 As shown, an insulating layer 42 is formed on the insulating layer 41, and a via 82 that contacts the upper end of the via 81 is formed within the insulating layer 42. Then, an insulating layer 43 is formed on the insulating layer 42, and an upper layer wiring 18 that contacts the upper end of the via 82 is formed within the insulating layer 43.

[0116] According to the implementation method, lower layer wiring 12 and vias 81 connected to the lower layer wiring 12 are arranged not only around the periphery of the cell array region but also within the cell array region, thereby reducing the chip area. Furthermore, the wiring length between the memory cell array 1 and the control circuit can be shortened, and the operating speed can be increased.

[0117] Sufficient distance is required between the conductive layer (electrode layer 70, source layer SL) and the via 81 to ensure the withstand voltage between the conductive layer and the via 81. Figure 5 , Figure 6(a) shows the distance d1). As a comparative example, a hole with a diameter equal to the diameter of via 81 plus a width of (2×d1) can be considered. The lower layer wiring 12 functions as an etch barrier layer when forming the hole, and the wiring width of the lower layer wiring 12 is larger than the diameter of the hole so that no etching occurs in the area extending from the lower layer wiring 12. If the distance d1 used for the withstand voltage between the conductive layer and the via 81 is increased, the diameter of the hole and the width of the lower layer wiring also increase in the above comparative example. This can lead to an increase in the configuration space of the lower layer wiring and an increase in the chip area.

[0118] According to the implementation method, a diameter ( Figure 6 In (b), D2) is the diameter obtained by adding (2×d1) to the diameter of the via 81. Figure 6 The small hole 80 in (a) allows for a reduction in the width of the lower layer wiring 12. This enables a reduction in chip area.

[0119] Even if the diameter of hole 80 is reduced, after hole 80 is formed, it will still be as described above. Figure 18 As shown, the end face 71a of the sacrificial layer 71 to be replaced as the electrode layer 70 and the end faces 15a and 16a of the source layer SL are moved back in the diameter direction of the via 80, thus ensuring the withstand voltage between the conductive layer (electrode layer 70, source layer SL) and the via 81.

[0120] The amount of the conductive layer recedes, i.e. the thickness of the insulating film 63 between the conductive layer and the via 81 (the thickness along the diameter direction of the via 81), is set to a thickness that can ensure sufficient withstand voltage between the conductive layer and the via 81.

[0121] In addition, the amount of the conductive layer can be set so that even if the insulating film 63 is etched more or less when the sacrificial layer 71 is removed, an insulating film 63 with a sufficient thickness to ensure the above-mentioned withstand voltage can remain.

[0122] In addition, the increased amount of retreat of the conductive layer imparts high strength against flexural stress to the periphery of the via 81 in the laminate 100 where the sacrificial layer 71 is removed to form the void 75.

[0123] Figure 22 The following example illustrates how, without etching, the end face 71a of the sacrificial layer 71 on the hole 80 side is oxidized so that it is positioned relative to the area exposed in the hole 80. Figure 17 The first position shown is a second position away from the hole 80 in the diametrical direction of the hole 80.

[0124] For example, in an oxidizing atmosphere, the end of the sacrificial layer 71, which serves as a silicon nitride layer, on the side of the hole 80 is oxidized to form an insulating film (silicon oxide film) 64 at its end. The insulating film 64 is formed between the end face 71a of the sacrificial layer 71 and the hole 80, with the end face 71a of the sacrificial layer 71 located between... Figure 17 The first position shown is compared to the second position which is farther away from the hole 80 in the diameter direction of the hole 80.

[0125] Alternatively, concentrated nitric acid can be used, for example, to oxidize the end of the semiconductor layer 16 on the side of the hole 80, forming an insulating film (silicon oxide film) 65 at its end. The insulating film 65 is formed between the end face 16a of the semiconductor layer 16 and the hole 80, with the end face 16a of the semiconductor layer 16 located between... Figure 17 The first position shown is compared to the second position which is farther away from the hole 80 in the diameter direction of the hole 80.

[0126] Alternatively, the end of the metal-containing layer 15 on the side of the hole 80 can be oxidized to form an insulating film (metal oxide film) 66 at its end. The insulating film 66 is formed between the end face 15a of the metal-containing layer 15 and the hole 80, with the end face 15a of the metal-containing layer 15 located between... Figure 17 The first position shown is compared to the second position which is farther away from the hole 80 in the diameter direction of the hole 80.

[0127] exist Figure 22 After the steps, such as Figure 19 As shown, an insulating film 63 is formed along the side and bottom of the hole 80, and then the aforementioned process continues. Figure 20 The next steps.

[0128] Figure 23 This is a schematic top view showing another example of a cell array region.

[0129] Figure 24 yes Figure 23 EE cross-sectional view.

[0130] Figure 25 yes Figure 23 FF cross-sectional view.

[0131] Figure 24 The structure shown, in that the conductive layer 78 is disposed between the source layer SL and the laminate 100, is similar to the aforementioned Figure 3 The structure shown is different. An insulating layer 44 is disposed on the semiconductor layer 16 of the source layer SL, and a conductive layer 78 is disposed on the insulating layer 44. An insulating layer 72 is disposed on the conductive layer 78, and the bottommost electrode layer 70 is disposed on the insulating layer 72. Other configurations are the same as those shown. Figure 3 same.

[0132] The columnar portion CL penetrates the laminate 100, the conductive layer 78, and the insulating layer 44. The semiconductor body 20 of the columnar portion CL contacts the semiconductor layer 16 of the source layer SL below the conductive layer 78. The separation portion 61 separates the laminate 100 and the conductive layer 78 into multiple blocks in the Y direction.

[0133] The conductive layer 78 is thicker than both the electrode layer 70 and the insulating layer 72. The conductive layer 78 is, for example, a polysilicon layer doped with impurities. The conductive layer 78 functions as the source-side select gate (SGS) of the source-side select transistor (STS). The lower electrode layer 70 can be used as the control gate of the memory cell (MC) instead of serving as the source-side select gate.

[0134] In addition, the conductive layer 78 functions as a barrier layer during etching to form holes and / or gaps in the laminate 100.

[0135] like Figure 25 As shown, a conductive via 85 penetrates the laminate 100. The portion below the via 85 of the source layer SL becomes a lower layer wiring 87 separated from the source layer SL by an insulating film 14. The lower layer wiring 87, like the source layer SL, has a laminated structure containing a metal layer 15 and a semiconductor layer 16.

[0136] Via 85 penetrates the laminate 100, conductive layer 78, insulating layer 44, and semiconductor layer 16 of lower wiring 87 to reach metal-containing layer 15 of lower wiring 87. The lower end face of via 85 is in contact with metal-containing layer 15. The side face of the lower end of via 85 is in contact with semiconductor layer 16.

[0137] The lower layer wiring 12 is located below the lower layer wiring 87. A via 86 is provided between the lower layer wiring 87 and the lower layer wiring 12 to connect the lower layer wiring 87 and the lower layer wiring 12. The upper layer wiring 18 and the lower layer wiring 12 are electrically connected through via 82, via 85, the lower layer wiring 87 and via 86.

[0138] An insulating film 91 is provided between the side of the via 85 and the laminate 100, and between the side of the via 85 and the conductive layer 78. The insulating film 91 has a sufficient thickness to ensure the withstand voltage between the electrode layer 70 and the via 85, and between the conductive layer 78 and the via 85.

[0139] like Figure 23 As shown, the insulating film 91 surrounds the cylindrical via 85. Additionally, multiple vias 85 are located in... Figure 23 Within the cell array region shown, the cells are arranged overlappingly along the line of the separation portion 61 extending in the X direction. The diameter of the via 85 is larger than the width of the separation portion 61.

[0140] The hole for forming the through hole 85 and the slit ST for forming the separation part 61 are formed simultaneously.

[0141] The following is for reference Figures 26-34 The method of forming the through hole 85 and the separation part 61 will be explained.

[0142] Figure 26 of (b) Figure 27 of (b) Figure 28 (b) Figure 29 of (b) Figure 30 (b) Figure 31 (b) Figure 32 (b) Figure 33 (b) and Figure 34 (b) is Figure 23 Process cross-sectional view of the FF section.

[0143] Figure 26 of (a) Figure 27 of (a) Figure 28 of (a) Figure 29 of (a) Figure 30 of (a) Figure 31 of (a) Figure 32 of (a) Figure 33 (a) and Figure 34 (a) is Figure 23 Process cross-sectional diagram of the GG section.

[0144] The illustration of substrate 10 is omitted in these figures.

[0145] Figure 26 The layers shown in (a) and (b) are formed sequentially. In the section where the via 85 is to be formed, as... Figure 26 As shown in (b), after forming via 86 on the lower layer wiring 12, source layer SL is stacked, and source layer SL on via 86 is separated by insulating film 14 to form lower layer wiring 87 connected to lower layer wiring 12 via via 86.

[0146] Figure 35 (a) shows a cross-section of the lower layer wiring 87. An insulating film 14 surrounds, for example, the cylindrical lower layer wiring 87.

[0147] A conductive layer 78 is formed on the lower wiring layer 87 and the source layer SL, separated by an insulating layer 44. A laminate 100 comprising multiple sacrificial layers 71 and multiple insulating layers 72 is formed on the conductive layer 78.

[0148] Subsequently, similar to the aforementioned embodiment, a plurality of columnar portions CL and HR are formed in the laminate 100. The lower end of the semiconductor body 20 of the columnar portion CL is in contact with the semiconductor layer 16 of the source layer SL.

[0149] After that, as Figure 27 As shown in (a), a gap ST is formed in the laminate 100. At the same time as the gap ST is formed, a... Figure 27 The first hole 84 is shown in (b).

[0150] Multiple slits ST and multiple first holes 84 are formed simultaneously using the same RIE step with a mask layer (not shown). Both the slits ST and the first holes 84 penetrate the stack 100 to reach the conductive layer 78. Using the conductive layer 78 as a barrier layer, multiple sacrificial layers 71 and multiple insulating layers 72 are sequentially etched using the same gas in a RIE process.

[0151] like Figure 23 As shown, a plurality of first holes 84 are arranged overlappingly on the line of a slit ST extending along the X direction.

[0152] The diameter of the first hole 84 is larger than the width of the slot ST. Therefore, the first hole 84 tends to be etched faster than the slot ST, and the thick conductive layer 78 absorbs the difference in etching rate (deviation of bottom position) between the slot ST and the first hole 84. Furthermore, the difference in etching rate (deviation of bottom position) between the multiple first holes 84 is also absorbed by the thick conductive layer 78. This prevents the formation of first holes 84 that would penetrate to a position lower than the conductive layer 78, ensuring that the bottoms of the multiple first holes 84 and the multiple slot STs are reliably located within the conductive layer 78.

[0153] Next, the insulating layer (e.g., silicon oxide layer) 44 is used as a barrier layer, and the conductive layer 78 remaining below the bottom of the gap ST and the conductive layer 78 remaining below the bottom of the first hole 84 are simultaneously etched by the RIE method.

[0154] like Figure 28 As shown in (a) and (b), at the bottom of the slit ST and the bottom of the first hole 84, for example, the insulating layer 44, which is a silicon oxide layer, is exposed.

[0155] Subsequently, the sacrificial layer 71 is removed by etching through the gap ST and the first hole 84. For example, the sacrificial layer 71, which serves as a silicon nitride layer, is removed using an etchant containing phosphoric acid.

[0156] like Figure 29 As shown in (a) and (b), gaps 75 are formed between adjacent insulating layers 72 and between the uppermost insulating layer 72 and insulating layer 41. At this time, the multiple insulating layers 72 are supported by the already formed columnar portions CL and HR, maintaining the gaps 75.

[0157] like Figure 30As shown in (a) and (b), an electrode layer 70 is formed in the void 75. The source gas for the electrode layer 70 is supplied to the void 75 through the slit ST and the first hole 84.

[0158] Subsequently, an insulating film is formed within the gap ST and the first hole 84 using, for example, a CVD method. Figure 31 As shown in (b), an insulating film 91 is conformally formed along the side and bottom of the first hole 84. A cavity (part of the first hole 84) remains inside the insulating film 91 within the first hole 84.

[0159] The width of the slit ST is smaller than the diameter of the first hole 84, therefore... Figure 31 As shown in (a), the gap ST is filled with an insulating film 61. Furthermore, the insulating film 61 and the insulating film 91 are represented by different symbols, but they are films of the same material (e.g., silicon oxide) formed simultaneously in the same step.

[0160] Subsequently, using the RIE method with the semiconductor layer 16 of the lower wiring 87 as a barrier layer, the insulating film 91 at the bottom of the first hole 84 and the insulating layer 44 below the insulating film 91 are etched. Figure 32 As shown in (b), the semiconductor layer 16 is exposed at the bottom of the first hole 84.

[0161] At this point, the insulating films 61 and 91 accumulated on the insulating layer 41 become thinner or disappear. For example... Figure 32 As shown in (a), the insulating film 61 remains in the gap ST.

[0162] Next, the semiconductor layer 16 exposed at the bottom of the first hole 84 is etched using the RIE method, which uses the metal-containing layer 15 as a barrier layer.

[0163] By removing the insulating layer 44 and the semiconductor layer 16 below the first hole 84, such as Figure 33 As shown in (b), a second hole 83 with a smaller diameter than the first hole 84 is formed below the first hole 84. The second hole 83 is connected to the first hole 84, and the metal-containing layer 15 of the lower wiring 87 is exposed at the bottom of the second hole 83.

[0164] The diameter of the second hole 83 is smaller than the planar dimension (diameter or width) of the lower layer wiring 87. The side of the second hole 83 does not extend outward compared to the edge of the lower layer wiring 87.

[0165] Next, as Figure 34 As shown in (b), through holes 85 are formed within the first hole 84 and the second hole 83. For example, metallic material is embedded within the first hole 84 and the second hole 83.

[0166] After that, as Figure 25As shown, an insulating layer 42 is formed on the insulating layer 41, and a via 82 that contacts the upper end of the via 85 is formed within the insulating layer 42. Then, an insulating layer 43 is formed on the insulating layer 42, and an upper layer wiring 18 that contacts the upper end of the via 82 is formed within the insulating layer 43.

[0167] Figures 36-38 Show Figure 23 Another example of the process cross-section of the FF section is shown in the process cross-section diagram.

[0168] like Figure 36 As shown, no source layer SL is provided between the first hole 84 and the lower layer wiring 12. In the layer that forms the active layer SL, an insulating layer 18 is provided between the first hole 84 and the lower layer wiring 12.

[0169] Figure 35 (b) shows a cross-section of the insulating layer 18. Between the first hole 84 and the underlying wiring 12, the source layer SL is removed, for example, in a circular shape.

[0170] Similarly, proceed to the aforementioned... Figure 31 The steps shown in (b) are as follows: Figure 36 As shown, an insulating film 91 is formed on the side and bottom of the first hole 84.

[0171] Next, the insulating film 91 at the bottom of the first hole 84 and the insulating layers 44, 18, and 13 below the insulating film 91 are etched using the RIE method, which uses the lower layer wiring 12 as a barrier layer. The insulating film 91 and the insulating layers 44, 18, and 13 are, for example, silicon oxide films.

[0172] like Figure 37 As shown, a second hole 83 with a smaller diameter than the first hole 84 is formed below the first hole 84. The second hole 83 is connected to the first hole 84, and the lower layer wiring 12 is exposed at the bottom of the second hole 83.

[0173] The diameter of the second hole 83 is smaller than the planar dimension (width) of the lower layer wiring 12. The side of the second hole 83 does not extend outward compared to the edge of the lower layer wiring 12.

[0174] During the etching process to form the second hole 83, a mask layer 151 is pre-formed on the insulating film 91 deposited on the laminate 100. The carbon-based material mask layer 151 can be formed without sealing the first hole 84 using, for example, a film deposition method with poor coverage. (Also includes...) Figure 31 The entire surface of the laminate 100 shown in (a) forms a mask layer 151.

[0175] Even if the combined thickness of the insulating film 91 and insulating layers 44, 18, and 13 at the bottom of the first hole 84 is significantly thicker than the thickness of the insulating film 91 stacked on the laminate 100, the etching of the laminate 100 can still be prevented by the mask layer 151.

[0176] Next, as Figure 38 As shown, vias 85 are formed within the first hole 84 and the second hole 83. For example, metallic material is embedded within the first hole 84 and the second hole 83. The lower end of the via 85 contacts the underlying wiring 12.

[0177] The first hole 84 described above has a diameter obtained by adding twice the width of the insulating film 91 (thickness in the diametrical direction of the via 85) to the diameter of the via 85. The insulating film 91 has a sufficient thickness to ensure the withstand voltage between the via 85 and the conductive layers (electrode layer 70, conductive layer 78).

[0178] Even if the thickness of the insulating film 91 required to ensure the aforementioned withstand voltage is increased, and the diameter of the first hole 84 is increased, the first hole 84 will not reach the lower layer wiring 87 or the lower layer wiring 12. Therefore, the planar dimensions of the lower layer wiring 87 or the lower layer wiring 12 can be made no larger than the diameter of the first hole 84. The etching forming the first hole 84 can be reliably stopped by the thick conductive layer (barrier layer) 78, and the first hole 84 does not penetrate to the lower layer wiring 87 or the lower layer wiring 12.

[0179] Next, after forming an insulating film 91 within the first hole 84, a second hole 83 with a smaller diameter than the first hole 84 is formed below the bottom of the first hole 84. By forming the via 85 for penetrating the laminate 100 in two stages, the withstand voltage distance between the via 85 and the conductive layers (electrode layer 70, conductive layer 78) can be ensured, while simultaneously reducing the planar dimensions of the lower layer wiring 87 or the lower layer wiring 12. This allows for a reduction in chip area.

[0180] Figure 39 This is a schematic top view showing yet another example of a cell array region.

[0181] like Figure 39 As shown, multiple vias 85 (first holes 84) can also be arranged overlappingly along the lines of the separation portions 62 extending in the X direction. After the separation portions 62 are formed, the laminate 100 is etched along each separation portion 62 to form the first holes 84. In this case, it is also possible to form the slit ST and the first holes 84 simultaneously.

[0182] In the aforementioned Figure 18In the example shown, the end face 71a of the sacrificial layer 71 was moved back in the diameter direction of the hole 80 before the sacrificial layer 71 was replaced with the electrode layer 70. However, the end face of the electrode layer 70 may be moved back in the diameter direction of the hole 80 after the sacrificial layer 71 has been replaced with the electrode layer 70.

[0183] The following is for reference Figures 40-42 The process of retracting the end face of electrode layer 70 will be described.

[0184] In the laminate 100 comprising multiple sacrificial layers 71 and multiple insulating layers 72, after the columnar portions CL and HR are formed, a slit ST and a hole 80 are simultaneously formed. The diameter of the hole 80 is larger than the width of the slit ST.

[0185] and Figure 23 Similarly, as shown with hole 84 (via 85), a plurality of holes 80 (via 81) can be arranged overlappingly along the line of the slit ST (separation section 61) extending in the X direction. Or, with Figure 39 Similarly, as shown in the hole 84 (via hole 85), a plurality of holes 80 (via holes 81) can be arranged overlappingly on the line of the separation portion 62 extending in the X direction.

[0186] After that, as Figure 40 As shown in (a) and (b), the sacrificial layer 71 is replaced with the electrode layer 70 through these gaps ST and holes 80.

[0187] Next, as Figure 41 As shown in (b), the end face 70a of the electrode layer 70 on the hole 80 side is moved back so that it is away from the hole 80 in the diameter direction of the hole 80. The end faces 15a and 16a of the source layer SL are also moved back.

[0188] At this time, as Figure 41 As shown in (a), the end face 70a on the slit ST side of the electrode layer 70 is also recessed so that it is away from the slit ST in the width direction of the slit ST. The end faces 15a and 16a on the slit ST side of the source layer SL are also recessed so that they are away from the slit ST in the width direction of the slit ST.

[0189] Next, as Figure 42 As shown in (b), an insulating film 63 is formed along the side and bottom of the hole 80. The insulating film 63 is also formed in the gap 79 formed by the retraction of the end face 70a of the electrode layer 70 and the gap 77 formed by the retraction of the end faces 15a and 16a of the source layer SL.

[0190] At this time, as Figure 42As shown in (a), an insulating film 61 is also formed within the slit ST. The width of the slit ST is smaller than the diameter of the hole 80, therefore, the slit ST is filled with the insulating film 61. An insulating film 61 is also formed in the gaps 79 and 77 on the sides of the slit ST, which are formed by the retraction of the electrode layer 70 and the source layer SL.

[0191] After that, in the future Figure 42 After the insulating film 63 at the bottom of the hole 80 shown in (b) is removed, a via 81 is formed in the hole 80 to contact the underlying wiring 12.

[0192] In addition, Figure 40 Following steps (a) and (b), instead of retracting the end face 70a of the electrode layer 70 by etching, an insulating film can be formed at the end of the electrode layer 70 on the hole 80 side and the end of the electrode layer 70 on the gap ST side by oxidation. Alternatively, an insulating film can also be formed at the end of the source layer SL on the hole 80 side and the end of the source layer SL on the gap ST side by oxidation.

[0193] Figure 43 (a) and (b) are Figure 5 An enlarged cross-sectional view of a portion of the image.

[0194] Depending on the amount of retreat of the end face 71a of the sacrificial layer 71 or the end face 70a of the electrode layer 70 to the second position achieved by etching, the volume of the gap 79 generated by the retreat, the film thickness of the insulating film 63, etc., a recess 63a may sometimes be formed on the inner peripheral surface of the insulating film 63 on the side of the via 81.

[0195] The recess 63a is recessed in the direction toward the end face 70a of the electrode layer 70 at a position facing the end face 70a of the electrode layer 70. In the insulating film 63 surrounding the outer peripheral surface of the via 81, the inner diameter of the portion facing the electrode layer 70 is larger than the inner diameter of the portion facing the insulating layer 72.

[0196] In addition, depending on the etching that causes the end face 71a of the sacrificial layer 71 (or the end face 70a of the electrode layer 70) to recede, the etching when the sacrificial layer 71 is removed, and the oxidation conditions of the end of the sacrificial layer 71 (or the end of the electrode layer 70), sometimes the end face 70a of the electrode layer 70 (the boundary between the electrode layer 70 and the insulating film 63) cannot be a straight shape along the film thickness direction.

[0197] Figure 43 (a) shows an example of the shape in which the central portion of the end face 70a of the electrode layer 70 is recessed in the direction away from the insulating film 63 compared to the edge in the direction of film thickness.

[0198] Figure 43(b) shows an example of the shape in which the central portion of the end face 70a of the electrode layer 70 protrudes toward the insulating film 63 side compared to the edge in the film thickness direction.

[0199] In the above embodiment, a silicon nitride layer is exemplified as the first layer 71, but a metal layer or a silicon layer doped with impurities can also be used as the first layer 71. In this case, the first layer 71 remains as the electrode layer 70, so there is no need to replace the first layer 71 with an electrode layer.

[0200] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can also be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention described in the technical solution and its equivalents.

Claims

1. A semiconductor device comprising: The lower layer routing layer includes a first lower layer routing layer and a second lower layer routing layer; The upper routing layer includes a first upper routing layer and a second upper routing layer; A stacked body disposed between the lower wiring layer and the upper wiring layer, and having a first electrode layer and a second electrode layer stacked in a first direction separated by an insulator; A source layer is disposed between the lower wiring layer and the stack-up; A conductive layer is disposed between the source layer and the laminate, and in the first direction, its thickness is greater than the thickness of one of the first electrode layer and the second electrode layer; A first conductive via, which passes through the stack, the source layer and the conductive layer to connect the first upper wiring layer and the first lower wiring layer; as well as A second conductive via, which penetrates the laminate, the source layer, and the conductive layer to connect the second upper wiring layer and the second lower wiring layer, is disposed next to the first conductive via in a second direction intersecting the first direction. A portion of the laminate is located between the first conductive via and the second conductive via in the second direction.

2. The semiconductor device according to claim 1, It also includes a first insulating film disposed between the first conductive via and the laminate, and between the first conductive via and the conductive layer, wherein the first conductive via is surrounded by the first insulating film in the second direction.

3. The semiconductor device according to claim 2, It also includes a second insulating film disposed between the first conductive via and the source layer. The first conductive via is surrounded by the second insulating film in the second direction, and the thickness of the second insulating film is greater than the thickness of the first insulating film in the second direction.

4. The semiconductor device according to claim 2, The first insulating film includes a recess that is recessed toward the laminate in the second direction.

5. The semiconductor device according to claim 2, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, wherein in the second direction, the first portion is arranged on the laminate side and the second portion is arranged on the first conductive via side.

6. The semiconductor device according to claim 2, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, wherein in the second direction, the distance between the first conductive via and the first portion is greater than the distance between the first conductive via and the second portion.

7. The semiconductor device according to claim 1, The distance between the first conductive via and the source layer is greater than the distance between the first conductive via and one of the first and second electrode layers.

8. The semiconductor device according to claim 1, One of the first electrode layers and the second electrode layer has a first hole surrounding the first conductive via, and the source layer has a second hole surrounding the first conductive via, the diameter of the second hole being larger than the diameter of the first hole.

9. The semiconductor device according to claim 1, It also has multiple columnar parts, each columnar part including: A semiconductor body that is in contact with the source layer and extends through the stack in a first direction of the stack; and A charge storage section is disposed between the semiconductor body and one of the first and second electrode layers.

10. The semiconductor device according to claim 9, The source layer includes a semiconductor layer in contact with the semiconductor body and a metal-containing layer stacked beneath the semiconductor layer.

11. The semiconductor device according to claim 9, The columnar portion is disposed in the unit array region, and the first conductive via and the second conductive via are disposed in the region adjacent to the unit array region.

12. The semiconductor device according to claim 1, It also includes a separation section that divides the laminate into multiple blocks, and the first conductive via and the second conductive via are disposed on the extension line of the separation section.

13. A semiconductor device comprising: The lower layer routing layer includes a first lower layer routing layer and a second lower layer routing layer; The upper routing layer includes a first upper routing layer and a second upper routing layer; A stack, disposed between the lower wiring layer and the upper wiring layer, includes a first electrode layer and a second electrode layer stacked in a first direction separated by an insulator; A source layer is disposed between the lower wiring layer and the stack-up; A source-side selection gate is disposed between the source layer and the laminate, and in the first direction, its thickness is greater than the thickness of one of the first electrode layer and the second electrode layer; A first conductive via passes through the stack, the source layer, and the source-side selection gate to connect the first upper wiring layer and the first lower wiring layer. as well as A second conductive via, which passes through the stack, the source layer, and the source-side selection gate to connect the second upper wiring layer and the second lower wiring layer, is disposed next to the first conductive via in a second direction intersecting the first direction. A portion of the laminate is located between the first conductive via and the second conductive via in the second direction.

14. A semiconductor device comprising: The lower layer routing layer includes a first lower layer routing layer and a second lower layer routing layer; The upper routing layer includes a first upper routing layer and a second upper routing layer; A stack, disposed between the lower wiring layer and the upper wiring layer, includes a first electrode layer and a second electrode layer stacked in a first direction separated by an insulator; A source layer is disposed between the lower wiring layer and the stack-up; A conductive layer is disposed between the source layer and the laminate, and in the first direction, its thickness is greater than the thickness of one of the first electrode layer and the second electrode layer; as well as The first conductive via and the second conductive via penetrate the laminate, the source layer, and the conductive layer to connect the upper wiring layer and the lower wiring layer. One of the first electrode layers and the second electrode layer surrounds each of the first conductive via and the second conductive via. The first conductive via and the second conductive via directly connect the upper wiring layer to the lower wiring layer.

15. The apparatus according to claim 14, One of the first electrode layers and the second electrode layer surrounds the outer periphery of each of the first conductive via and the second conductive via in a ring.

16. A semiconductor device comprising: The lower layer routing layer includes a first lower layer routing layer and a second lower layer routing layer; The upper routing layer includes a first upper routing layer and a second upper routing layer; A source layer is disposed between the lower wiring layer and the upper wiring layer; Multiple stacks are disposed between the source layer and the upper wiring layer. Each stack includes multiple electrode layers stacked in a first direction. Adjacent stacks are separated from each other by a separation portion in a second direction that intersects the first direction. A conductive layer is disposed between the source layer and the laminate, and in the first direction, its thickness is greater than the thickness of one of the plurality of electrode layers; A first conductive via, which passes through the stack, the source layer and the conductive layer to connect the first upper wiring layer and the first lower wiring layer; as well as A second conductive via, which penetrates the laminate, the source layer, and the conductive layer to connect the second upper wiring layer and the second lower wiring layer, is disposed next to the first conductive via in a third direction intersecting the first and second directions. A portion of the laminate is located between the first conductive via and the second conductive via in the third direction.

17. The semiconductor device according to claim 16, It also has an insulating layer disposed between the source layer and the conductive layer.

18. The semiconductor device according to claim 16, It also includes a first insulating film disposed between the first conductive via and the laminate, and between the first conductive via and the conductive layer, wherein the first conductive via is surrounded by the first insulating film in the third direction.

19. The semiconductor device according to claim 18, It also includes a second insulating film disposed between the first conductive via and the source layer. The first conductive via is surrounded by the second insulating film in the third direction, and the thickness of the second insulating film is greater than that of the first insulating film in the third direction.

20. The semiconductor device according to claim 18, The first insulating film includes a recess that is recessed toward the laminate in the third direction.

21. The semiconductor device according to claim 18, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, wherein in the third direction, the first portion is arranged on the laminate side and the second portion is arranged on the first conductive via side.

22. The semiconductor device according to claim 18, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, and in the third direction, the distance between the first conductive via and the first portion is greater than the distance between the first conductive via and the second portion.

23. The semiconductor device according to claim 16, The distance between the first conductive via and the source layer is greater than the distance between the first conductive via and one of the multiple electrode layers.

24. The semiconductor device according to claim 16, It also has multiple columnar parts, each columnar part including: A semiconductor body that is in contact with the source layer and extends through the stack in a first direction; and A charge storage section is disposed between the semiconductor body and one of the plurality of electrode layers.

25. The semiconductor device according to claim 24, The source layer includes a semiconductor layer in contact with the semiconductor body and a metal-containing layer stacked beneath the semiconductor layer.

26. The semiconductor device according to claim 24, The columnar portion is disposed in the unit array region, and the first conductive via and the second conductive via are disposed in the region adjacent to the unit array region.

27. The semiconductor device according to claim 16, The separation section includes a third insulating film.

28. A semiconductor device comprising: The lower layer routing layer includes a first lower layer routing layer and a second lower layer routing layer; The upper routing layer includes a first upper routing layer and a second upper routing layer; A stack-up, disposed between the lower wiring layer and the upper wiring layer, includes a plurality of electrode layers stacked in a first direction, wherein the plurality of electrode layers are control gates included in the first of a plurality of blocks; A source layer is disposed between the lower wiring layer and the stack-up; A conductive layer is disposed between the source layer and the laminate, and in the first direction, its thickness is greater than the thickness of one of the plurality of electrode layers; A first conductive via, which penetrates the stack, the source layer, and the conductive layer to connect the first upper wiring layer and the first lower wiring layer, and is surrounded by one of the plurality of electrode layers; and The second conductive via penetrates the stack, the source layer, and the conductive layer to connect the second upper wiring layer and the second lower wiring layer, and is surrounded by one of the plurality of electrode layers. A portion of the laminate is located between the first conductive via and the second conductive via.

29. The semiconductor device according to claim 28, It also includes an insulating layer disposed between the source layer and the conductive layer.

30. The semiconductor device according to claim 28, It also includes a first insulating film disposed between the first conductive via and one of the plurality of electrode layers, and between the first conductive via and the conductive layer, wherein the first conductive via is surrounded by the first insulating film in a second direction intersecting the first direction.

31. The semiconductor device according to claim 30, It also includes a second insulating film disposed between the first conductive via and the source layer. The first conductive via is surrounded by the second insulating film in the second direction, and the thickness of the second insulating film is greater than the thickness of the first insulating film in the second direction.

32. The semiconductor device according to claim 30, The first insulating film includes a recess that is recessed toward the laminate in the second direction.

33. The semiconductor device according to claim 30, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, wherein in the second direction, the first portion is arranged on the laminate side and the second portion is arranged on the first conductive via side.

34. The semiconductor device according to claim 30, The first insulating film includes a first portion and a second portion alternately arranged in the first direction, wherein in the second direction, the distance between the first conductive via and the first portion is greater than the distance between the first conductive via and the second portion.

35. The semiconductor device according to claim 28, The distance between the first conductive via and the source layer is greater than the distance between the first conductive via and one of the plurality of electrode layers.

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