Methods for manufacturing memory, memory and memory system

Abstract

This application provides a method for fabricating a memory, a memory, and a memory system. The method includes: forming a stacked layer and a step-filled structure on a substrate. The stacked layer includes a core region and a step region. A step structure is formed in the step region of the stacked layer. The step-filled structure covers the step structure. A memory channel is formed in the core region, and a dummy channel is formed in the step region. A memory channel structure is formed in the memory channel and a dummy channel structure is formed in the dummy channel. Both the memory channel and the dummy channel include a channel layer. The thickness of the channel layer in the memory channel structure is less than the thickness of the channel layer in the dummy channel structure. This enables the fabrication of a high-strength dummy channel structure, reduces the tilting phenomenon of the dummy channel structure due to the shrinkage of the step-filled structure, and ensures good support performance of the dummy channel structure and good storage performance of the memory channel structure.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a memory, a memory, and a memory system. [Background Technology]

[0002] 3D NAND is an emerging type of memory. Unlike 2D NAND, which places storage cells on a plane, 3D NAND technology vertically stacks multiple layers of storage cells, thus creating a memory with a storage capacity several times greater than that of 2D NAND.

[0003] In 3D NAND, the storage channel structure is located in the core area of ​​the stacked layer to provide storage functionality. Dummy channel structures are set in the step area of ​​the stacked layer to provide support functionality. However, during manufacturing, the dummy channel structure is prone to tilting due to the shrinkage of the step area. This tilting not only affects the support capacity of the dummy channel structure, but also further pulls the storage channel structure to tilt, affecting the storage performance of the storage channel structure. [Summary of the Invention]

[0004] The present invention provides a method for manufacturing a memory, a memory, and a memory system, which can prepare a high-strength dummy channel structure and reduce the tilting phenomenon of the dummy channel structure and the memory channel structure.

[0005] On one hand, embodiments of this application provide a method for manufacturing a memory, including:

[0006] A stacked layer and a step-fill structure are formed on a substrate. The stacked layer includes a core region and a step region. A step structure is formed in the step region of the stacked layer. The step-fill structure covers the step structure. A memory channel via is formed in the core region, penetrating the stacked layer and extending into the substrate. A dummy channel via is formed in the step region, penetrating the step structure and the step-fill structure.

[0007] A storage channel structure is formed in the storage channel hole, and a virtual channel structure is formed in the virtual channel hole. Both the storage channel structure and the virtual channel structure include a channel layer, and the thickness of the channel layer in the storage channel structure is less than the thickness of the channel layer in the virtual channel structure.

[0008] In some embodiments, forming the stacked layers and step-filled structure on the substrate includes:

[0009] A stacked layer is formed on a substrate, and a sacrificial trench structure is formed in the core region that penetrates the stacked layer and extends into the substrate;

[0010] A step structure is formed in the step area, and a step filling structure is formed to cover the step structure;

[0011] A fictitious channel hole is formed in the stepped area, penetrating the stepped structure and the stepped filling structure;

[0012] Remove the sacrificial channel structure to obtain the storage channel hole.

[0013] In some embodiments, forming a storage channel structure in the storage channel aperture and forming a dummy channel structure in the dummy channel aperture includes:

[0014] A storage functional layer and a channel layer located on the storage functional layer are formed on the inner wall of the storage channel hole and the inner wall of the dummy channel hole.

[0015] An insulating layer is formed to fill the storage channel hole and the dummy channel hole, resulting in a storage channel structure located in the storage channel hole and a dummy channel structure located in the dummy channel hole, wherein the insulating layer is located on the channel layer.

[0016] In some embodiments, prior to forming the insulating layer, the method further includes:

[0017] A photoresist layer is formed to cover the dummy channel aperture;

[0018] The channel layer in the storage channel via is etched back;

[0019] Remove the photoresist layer.

[0020] In some embodiments, after forming the storage channel structure and the dummy channel structure, the method further includes:

[0021] A portion of the insulating layer in the end of the storage channel structure facing away from the substrate is removed to expose the channel layer in the end, while a portion of the insulating layer in the end of the dummy channel structure facing away from the substrate is also removed.

[0022] Plugs are formed in the storage channel hole and the dummy channel hole respectively, and the plugs in the storage channel hole are electrically connected to the exposed channel layer.

[0023] In some embodiments, removing the sacrificial channel structure includes removing the sacrificial channel structure by an ashing process.

[0024] In some embodiments, a step structure is formed in the step area, and a step filling structure is formed covering the step structure, including:

[0025] A stop layer is formed on the stacked layers, and the stop layer and the stacked layers are etched to form a step structure and etched gaps in the step region;

[0026] The etched voids are filled with insulating material;

[0027] The surface of the insulating material is planarized using the stop layer.

[0028] Remove the stop layer to expose the surfaces of the stacked layers and the sacrificial channel structure.

[0029] In some embodiments, the stacked layer includes a first sub-stacked layer and a second sub-stacked layer, wherein the stacked layer is formed on the substrate, and a sacrificial channel structure is formed in the core region that penetrates the stacked layer and extends to the substrate, including:

[0030] A first sub-stacked layer is formed on the substrate;

[0031] A first sub-memory channel hole is formed in the first sub-stack layer, the first sub-memory channel hole penetrates the first sub-stack layer and extends into the substrate, and the first sub-memory channel hole is filled with sacrificial material;

[0032] A second sub-stack layer is formed on the first sub-stack layer;

[0033] A second sub-memory channel hole is formed in the second sub-stack layer, and the sacrificial material is removed to obtain the memory channel hole. The second sub-memory channel hole corresponds to the first sub-memory channel hole and is located in the core region of the stack layer.

[0034] A sacrificial channel structure is formed in the storage channel hole.

[0035] On the other hand, embodiments of this application also provide a memory, including:

[0036] Semiconductor layer;

[0037] A stacked structure located on the semiconductor layer, the stacked structure including a core region and a step region, the stacked structure having a step structure in the step region;

[0038] A step-filling structure covering the aforementioned step structure;

[0039] A memory channel structure located in the core region, penetrating the stacked structure and extending into the semiconductor layer; and

[0040] A virtual channel structure is located within the step structure and the step filling structure. Both the virtual channel structure and the storage channel structure include a channel layer, and the thickness of the channel layer in the storage channel structure is less than the thickness of the channel layer in the virtual channel structure.

[0041] In some embodiments, the storage channel structure and the dummy channel structure further include a stacked storage functional layer and an insulating layer, with the channel layer located between the storage functional layer and the insulating layer.

[0042] In some embodiments, the memory further includes a storage channel via, a dummy channel via, and a plug, wherein the storage channel structure is located in the storage channel via, the dummy channel structure is located in the dummy channel via, and the plug is located in the storage channel via on the side opposite to the semiconductor layer and in the dummy channel via on the side opposite to the semiconductor layer, and the channel layer in the end of the storage channel structure on the side opposite to the semiconductor layer is electrically connected to the plug.

[0043] On the other hand, embodiments of this application also provide a memory system, the memory system including at least one of the above-described memory and a controller coupled to the memory, the controller being used to control the memory to perform data write and read operations.

[0044] The memory fabrication method, memory, and memory system provided in this application embodiment form a stacked layer and a step-filled structure on a substrate. The stacked layer includes a core region and a step region. A step structure is formed in the step region of the stacked layer. The step-filled structure covers the step structure. A memory channel hole is formed in the core region, and a dummy channel hole is formed in the step region. Subsequently, a memory channel structure is formed in the memory channel hole, and a dummy channel structure is formed in the dummy channel hole. Both the memory channel structure and the dummy channel structure include a channel layer. The thickness of the channel layer in the memory channel structure is less than the thickness of the channel layer in the dummy channel structure. This enables the fabrication of a high-strength dummy channel structure, reduces the tilting phenomenon of the dummy channel structure caused by the shrinkage of the step-filled structure, and further reduces the tilting phenomenon of the memory channel structure caused by the tilting of the dummy channel structure. This ensures good support performance of the dummy channel structure and good storage performance of the memory channel structure, thereby improving the reliability of the memory device. [Attached Image Description]

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic flowchart of a method for manufacturing a memory provided in an embodiment of this application;

[0047] Figure 2 This is a cross-sectional view of another memory provided in this application embodiment during the manufacturing process;

[0048] Figures 3a to 3l This is a cross-sectional structural diagram of the memory under different process steps in the manufacturing method provided in the embodiments of this application;

[0049] Figure 4 yes Figure 3j Enlarged structural diagram at point M;

[0050] Figure 5 This is a schematic diagram of the memory system provided in an embodiment of this application.

Detailed Implementation Methods

[0051] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] In this description, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0053] In this description, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0054] Understandably, the meanings of “on”, “above”, and “above” in this text should be interpreted in the broadest sense, so that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. “A plurality” means two or more. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0056] This application provides a method for manufacturing a memory, a memory, and a memory system.

[0057] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this application. The method for manufacturing the memory includes the following steps S101 and S102, wherein:

[0058] Step S101: A stacked layer and a step-fill structure are formed on the substrate. The stacked layer includes a core region and a step region. A step structure is formed in the step region of the stacked layer. The step-fill structure covers the step structure. A memory channel hole is formed in the core region that penetrates the stacked layer and extends into the substrate. A dummy channel hole is formed in the step region that penetrates the step structure and the step-fill structure.

[0059] Step S102: A storage channel structure is formed in the storage channel hole, and a virtual channel structure is formed in the virtual channel hole. Both the storage channel structure and the virtual channel structure include a channel layer, and the thickness of the channel layer in the storage channel structure is less than the thickness of the channel layer in the virtual channel structure.

[0060] It should be understood that the steps shown in the above manufacturing method are not exclusive, and other steps may be performed before, after, or between any of the steps shown.

[0061] Specifically, by including a channel layer in both the storage channel structure and the dummy channel structure during their formation, and ensuring that the thickness of the channel layer in the storage channel structure is less than that in the dummy channel structure, a high-strength dummy channel structure can be manufactured. This improves its tensile strength, reduces the tilting phenomenon caused by the shrinkage of the step-filling structure in the dummy channel structure, and consequently reduces the tilting phenomenon caused by the tilting of the storage channel structure. This ensures good support performance of the dummy channel structure and good storage performance of the storage channel structure, thereby improving the reliability of the storage device.

[0062] For other implementations, please refer to Figure 2 , Figure 2 This is a cross-sectional view of another memory 10 provided in this application embodiment during the fabrication process. After the stacked layer 12 is formed on the substrate 11, the memory channel structure 13 is first formed directly in the core region AA of the stacked layer 12. Then, the step region BB of the stacked layer 12 is etched to form the step structure 111, and a step filling structure 14 is formed to cover the step structure 111 to fill the plateau step region BB. Then, a dummy channel hole is formed through the step filling structure 14 and the step structure 111, and an oxide, such as silicon oxide, is filled in it to form the dummy channel structure 15. Because the stepped structure 111 is stepped, and the stacked layers 12 are generally made of nitrides and oxides, while the stepped filling structure 14 is generally made of oxides, the materials differ. Therefore, when forming the stepped filling structure 14 and the dummy channel structure 15, the stepped filling structure 14 will shrink under stress. This shrinkage will generate tensile stress on the dummy channel structure 15, especially on the dummy channel structure 15 at the junction of the stepped structure 111 and the stepped filling structure 14. Since the dummy channel structure 15 made of oxides has low strength, it is difficult to resist this tensile stress and is prone to tilting. This tilted dummy channel structure 15 not only cannot provide reliable support for subsequent operations, but will also further deform the surrounding stacked layers 12, causing the storage channel structure 13 to tilt as well, affecting the storage performance of the storage channel structure 13. The memory manufacturing method provided in this embodiment (i.e., the above steps S101 and S102) can at least partially solve these technical problems.

[0063] Please see Figures 3a to 3l , Figures 3a to 3l These are cross-sectional structural diagrams of the memory 20 under different process steps in the above manufacturing methods S101 and S102. The following will combine... Figures 3a to 3l Further describe the above steps S101 and S102, wherein:

[0064] Step S101: A stacked layer 22 and a step-fill structure 24 are formed on the substrate 21. The stacked layer 22 includes a core region AA and a step region BB. A step structure 223 is formed in the step region BB of the stacked layer 22. The step-fill structure 24 covers the step structure 223. A memory channel hole H is formed in the core region AA, penetrating the stacked layer 22 and extending into the substrate 21. A dummy channel hole Q is formed in the step region BB, penetrating the step structure 23 and the step-fill structure 24.

[0065] The material of the substrate 21 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0066] In some implementations, please refer to [link / reference]. Figures 3a to 3g The stepped structure 223 is formed after the storage channel hole H is formed and before the dummy channel hole Q is formed. At this time, the above step S101 may specifically include the following steps S1011-S1014, wherein:

[0067] Step S1011: A stacked layer 22 is formed on the substrate 21. The stacked layer 22 includes a core region AA and a step region BB. A sacrificial channel structure 23 is formed in the core region AA, which penetrates the stacked layer 22 and extends into the substrate 21.

[0068] Among them, the material used to make the sacrificial channel structure 23 can be a material that does not affect the formation of the subsequent storage channel structure and is easy to remove, such as amorphous carbon.

[0069] The stacked layer 22 typically includes a gate sacrificial layer 221 and a gate insulating layer 222. The number of layers in the stacked layer 22 can be 8, 32, 64, or 128, etc. When the number of layers in the stacked layer 22 is small, such as 8 layers, the stacked layer 22 can be directly deposited to form the stacked layer 22, and then the memory channel via H and the sacrificial channel structure 23 located in the memory channel via H can be formed. When the number of layers in the stacked layer 22 is large, such as 128 layers, the stacked layer 22 needs to be split into multiple parts, such as splitting it into a first sub-stacked layer 22A and a second sub-stacked layer 22B, and formed in two deposition processes. At this time, the memory channel via H is also formed in two etching processes, that is, in Figures 3a-3b In this context, step S1011 may specifically include:

[0070] A first sub-stacked layer 22A is formed on substrate 21;

[0071] A first sub-memory channel hole h1 is formed in the first sub-stacked layer 22A. The first sub-memory channel hole h1 penetrates the first sub-stacked layer 22A and extends into the substrate 21. The first sub-memory channel hole h1 is filled with sacrificial material.

[0072] A second sub-stack layer 22B is formed on the first sub-stack layer 22A;

[0073] A second sub-storage channel hole h2 is formed in the second sub-stack layer 22B, and the sacrificial material is removed to obtain a storage channel hole H. The second sub-storage channel hole h2 corresponds to the first sub-storage channel hole h1 and is located in the core region AA of the stack layer 22.

[0074] A sacrificial channel structure 23 is formed in the storage channel hole H.

[0075] The step region BB can be located on both sides of the core region AA, or the core region AA can be located on both sides of the step region BB, without any specific limitation. Both the first sub-stack layer 22A and the second sub-stack layer 22B include an alternately stacked gate sacrificial layer 221 and a gate insulating layer 222. The gate insulating layer 222 is made of an oxide, such as silicon oxide, and the gate sacrificial layer 221 is made of a nitride, such as silicon nitride. It is usually different from the material of the sacrificial channel structure 23 to avoid affecting the gate sacrificial layer 221 during the removal of the sacrificial channel structure 23.

[0076] The first sub-stacked layer 22A and the second sub-stacked layer 22B can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma-assisted deposition. The first sub-memory channel via h1 and the second sub-memory channel via h2 can be formed using dry or wet etching.

[0077] Step S1012: A step structure 223 is formed in the step area BB, and a step filling structure 24 is formed to cover the step structure 223.

[0078] Among them, Figures 3c-3e In this process, the step structure 223 can be formed by repeatedly etching the stacked layer 22. The step-filling structure 24 can be formed by deposition processes such as CVD, PVD or plasma-assisted deposition, and planarization processes such as chemical mechanical polishing (CMP). The material used to fabricate the step-filling structure 24 mainly includes insulating materials such as silicon oxide.

[0079] In some implementations, step S1012 may specifically include:

[0080] A stop layer 25 is formed on the stacked layer 22, and the stop layer 25 and the stacked layer 22 are etched to form a step structure 223 and an etched gap M in the step region BB;

[0081] The etched void M is filled with insulating material;

[0082] The surface of the insulating material is planarized through the stop layer 25;

[0083] Remove the stop layer 25 to expose the surfaces of the stacked layer 22 and the sacrificial channel structure 23.

[0084] The stop layer 25 may include multiple stacked film layers, such as a silicon nitride layer 251 and a silicon oxide layer 252, with the silicon oxide layer 252 located on top of the silicon nitride layer 251. The step structure 223 is the step-shaped structure portion of the stacked layer 22 after etching. Specifically, when etching to form the step structure 223, the silicon nitride layer 251 can be used as the stop position for rough grinding. Then, the silicon nitride layer 251 is removed by wet etching and fine grinding is performed to obtain a step-filled structure 24 with a flat surface.

[0085] S1013. A virtual channel hole Q is formed in the step area BB, penetrating the step structure 223 and the step filling structure 24.

[0086] Among them, Figures 3e-3f In this process, a dummy channel via Q can be formed by wet etching or dry etching. This dummy channel via Q typically penetrates the step-fill structure 24 and the step structure 223 and extends into the substrate 21. Its extension depth within the substrate 21 can be the same as or different from the extension depth of the aforementioned storage channel via H within the substrate 21. It is readily understood that, in addition to the core region AA and the step region BB, the stacked layer 22 may also include a transition region (not shown in the figure) located between the core region AA and the step region BB. In this case, a dummy channel via Q can also be formed in the transition region.

[0087] S1014. Remove the sacrificial channel structure 23 to obtain the storage channel hole H.

[0088] Among them, Figures 3f-3g In the process, the sacrificial channel structure 23 can be removed by an ashing process. The ashing process can be carried out in a reaction chamber, heated under low pressure, and a plasma gas containing oxygen or oxygen ions is introduced into the reaction chamber to remove the sacrificial channel structure. For example, oxygen ions can oxidize amorphous carbon to carbon dioxide and remove it. S102, a storage channel structure 26 is formed in the storage channel hole H, and a dummy channel structure 27 is formed in the dummy channel hole Q. Both the storage channel structure 26 and the dummy channel structure 27 include a channel layer n2, and the thickness of the channel layer n2 in the storage channel structure 26 is less than the thickness of the channel layer n2 in the dummy channel structure 27. Among them, in Figures 3g-3jIn this process, the storage channel structure 26 and the dummy channel structure 27 can be fabricated using the same process, and the storage channel structure 26 and the dummy channel structure 27 have the same material.

[0089] It should be noted that the storage channel structure 26 in this embodiment is not formed directly. Instead, a sacrificial channel structure 23 is formed first, followed by a step structure 223, a step-fill structure 24, and a dummy channel hole Q. After removing the sacrificial channel structure 23 to obtain the storage channel hole H, the storage channel structure 26 is formed in the storage channel hole H. This preparation method mainly brings two beneficial effects: ① When forming the step-fill structure 24, even if the step-fill structure 24 shrinks and exerts a certain pressure on the stacked layer 22 (especially the step structure 223), the strength of the sacrificial channel structure 23 itself can resist the pressure, preventing deformation of the stacked layer 22 (especially the core region AA). ② When forming the storage channel structure 26, the dummy channel structure 27 can be prepared using the same process as the storage channel structure 26, without the need for additional processes. In some embodiments, the above step S102 may specifically include:

[0090] A storage functional layer n1 and a channel layer n2 located on the storage functional layer n1 are formed on the inner wall of the storage channel hole H and the inner wall of the dummy channel hole Q.

[0091] An insulating layer n3 is formed to fill the storage channel hole H and the dummy channel hole Q, resulting in a storage channel structure 26 located in the storage channel hole H and a dummy channel structure 27 located in the dummy channel hole Q, wherein the insulating layer n3 is located on the channel layer n2.

[0092] The insulating layer n3 can be made of oxides, such as silicon oxide. The storage functional layer n1 can include a barrier layer, a charge trapping layer, and a tunneling layer (not shown in the figure), and the materials of the barrier layer, charge trapping layer, and tunneling layer can be silicon oxide, silicon nitride, and silicon oxide, respectively. The channel layer n2 can be made of polysilicon, thereby forming an "ONOP" structure storage channel structure 26 and a dummy channel structure 27. The specific structures of the storage functional layer n1, channel layer n2, and insulating layer n3 can be found in [reference needed]. Figure 4 , Figure 4 for Figure 3j A magnified structural diagram at point M.

[0093] It should be noted that since the dummy channel structure 27 and the storage channel structure 26 are fabricated in the same process, on the one hand, no additional process steps are required, simplifying the process flow and saving process costs. On the other hand, the dummy channel structure 27 and the storage channel structure 26 have the same materials, such as storage functional layer n1 and channel layer n2 (usually polysilicon). The strength of polysilicon is much greater than that of insulating materials such as oxides or nitrides. Therefore, even if the step-fill structure 24 shrinks due to stress, the shrinkage is not likely to cause the dummy channel structure 27 to tilt, and consequently, it is not likely to cause the storage channel structure 26 to tilt. This better ensures the subsequent support capacity of the dummy channel structure 27 and the subsequent storage performance of the storage channel structure 26.

[0094] In some embodiments, the thickness of the channel layer n2 in the storage channel structure 26 can be made smaller than the thickness of the channel layer n2 in the dummy channel structure 27 by etching back the channel layer n2 in the storage channel structure 26 separately. For example, before forming the insulating layer n3 as described above, the method for fabricating the memory 20 may further include the following steps:

[0095] A photoresist layer m is formed to cover the dummy channel hole Q;

[0096] The channel layer n2 in the storage channel hole H is etched back;

[0097] Remove the photoresist layer m.

[0098] The purpose of etching back is primarily to planarize the surface of the channel layer n2 and reduce lattice defects. This etching back can be performed using dry etching and / or wet etching. The material of the photoresist layer m can include photoresist (PR), which is a patterned photoresist. Typically, the photoresist layer m can be formed using a photomask. Methods for removing the photoresist layer m can include an ashing process.

[0099] It should be noted that when the photoresist layer m covers the dummy channel aperture Q, it mainly refers to the end opening of the dummy channel aperture Q covered by the photoresist layer m, and does not necessarily mean that the dummy channel aperture Q must be filled. It can be as follows: Figure 3i The filling shown can also be omitted, such as only covering the end opening of the virtual channel hole Q, or filling a small part below the end opening, as long as it can cover the end opening of the virtual channel hole Q so that the channel layer n2 in the virtual channel hole Q will not be etched back in the future. There are no specific restrictions.

[0100] It should be noted that when the channel layer n2 in the storage channel hole H is etched back, the thickness of the channel layer n2 will be reduced. Since this embodiment only performs back etching on the channel layer n2 in the storage channel hole H and does not perform back etching on the channel layer n2 in the dummy channel hole Q, only the channel layer n2 in the storage channel hole H will be thinned, and the thickness of the channel layer n2 in the dummy channel hole Q will not be affected. Therefore, the strength of the dummy channel structure 27 can be improved as much as possible without affecting the storage performance of the storage channel structure 26, and the tensile strength of the dummy channel structure 27 can be improved.

[0101] In some implementations, please refer to Figures 3j-3k After step S105 above, the method for manufacturing the memory 20 may further include:

[0102] Remove a portion of the insulating layer n3 in the end of the storage channel structure 26 facing away from the substrate 21 to expose the channel layer n2 in the end, and at the same time remove a portion of the insulating layer n3 in the end of the dummy channel structure 27 facing away from the substrate 21.

[0103] Inserts 28 are formed in the storage channel hole H and the dummy channel hole Q respectively, and the inserts 28 in the storage channel hole H are electrically connected to the exposed channel layer n2.

[0104] Specifically, a portion of the insulating layer n3 in the memory channel structure 26 and a portion of the insulating layer n3 in the dummy channel structure 27 can be removed using the same etching process to form openings at the ends of the memory channel structure 26 and the dummy channel structure 27, respectively. Then, using the same process, a plug 28 is formed in the opening, thereby simplifying the process flow as much as possible. The plug 28 can be made of conductive materials, such as tungsten, silicon, or other conductive materials. Subsequently, the plug 28 in the memory channel hole Q can be connected to the peripheral circuitry via leads and vias to achieve the connection between the memory channel structure 26 and the peripheral circuitry.

[0105] It is easy to understand that the size of the plug 28 in the dummy channel hole Q and the size of the plug 28 in the storage channel hole H may not be the same. Typically, the diameter of the dummy channel hole Q is larger than the diameter of the storage channel hole H. The larger the diameter, the larger the size (e.g., width and / or depth) of the opening created by etching the insulating layer n3 to subsequently form the plug 28, thus increasing the size of the subsequently formed plug 28. For example, in... Figure 3kIt is evident that the height of the plug 28 in the dummy channel hole Q is greater than the height of the plug 28 in the storage channel hole H. If the diameter of the dummy channel hole Q is much larger than the diameter of the storage channel hole H, the size of the plug 28 in the dummy channel hole Q will also be affected by the aforementioned insulating layer n3 formation process (mainly referring to the filling process). For example, if the difference in diameter is too large, the filling capacity of some common filling processes may not be able to completely fill the dummy channel hole Q with the insulating layer n3. In this case, the dummy channel hole Q is not completely sealed (equivalent to an opening already existing). If the insulating layer n3 is subsequently etched, the opening in the dummy channel hole Q will continue to expand, resulting in a larger size for the subsequently formed plug 28.

[0106] It should be noted that since conductive materials generally have high strength, forming plugs 28 in both the dummy channel hole Q and the storage channel hole H using the same process can further increase the strength of the dummy channel structure 27 and improve its tensile strength. Of course, considering that only the plug 28 in the storage channel hole H needs to be connected to the external circuitry, it is also possible to use a mask to form the plug 28 only in the storage channel hole H, without forming it in the dummy channel hole Q; no specific restrictions are imposed here.

[0107] In addition, please see Figure 3l After the plug 28 is fabricated, a gate gap (not shown in the figure) can be formed in the stacked layer 22. The gate sacrificial layer 221 is removed through the gate gap, and then a conductive material is filled to form the gate 224. At this time, the stacked layer 22 becomes a stacked structure 22'. The conductive material can be any one or a combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

[0108] In some embodiments, after forming the gate 224, a common source layer (not shown) electrically connected to the memory channel structure 26 can also be fabricated. Specifically, the substrate 21 can be removed first to expose the channel layer n2 in the memory channel structure 26 near the end of the substrate 21. Then, on the side of the stacked structure 22' where the substrate 21 is removed, a common source layer (not shown) is formed that encapsulates the exposed channel layer n1. The material of the common source layer includes polysilicon.

[0109] Based on the above-described method for manufacturing the memory 20, this application embodiment also provides a memory 20, which can be fabricated using any of the above-described methods for manufacturing the memory 20. Please refer to... Figure 3l , Figure 3lThis is a cross-sectional view of the memory 20 provided in an embodiment of this application. The memory 20 includes: a semiconductor layer; a stacked structure 22' located on the semiconductor layer, the stacked structure 22' including a core region AA and a step region BB, the stacked structure 22' forming a step structure 223 in the step region BB; a step filling structure 24 covering the step structure 223; a memory channel structure 26 located in the core region AA, penetrating the stacked structure 22' and extending into the semiconductor layer; and a dummy channel structure 27 located in the step region BB, penetrating the step structure 223 and the step filling structure 24. The dummy channel structure 27 and the memory channel structure 26 both include a channel layer n2, and the thickness of the channel layer n2 in the memory channel structure 26 is less than the thickness of the channel layer n2 in the dummy channel structure 27.

[0110] In this embodiment, by making the thickness of the channel layer n2 in the storage channel structure 26 smaller than the thickness of the channel layer n2 in the dummy channel structure 27, the strength of the dummy channel structure 27 is significantly improved compared to other dummy channel structures made only of insulating materials such as silicon oxide or silicon nitride. Thus, even if the step filling structure 24 shrinks under stress, the high-strength dummy channel structure 27 can still provide better tensile strength and support, preventing the dummy channel structure 27 from tilting due to the shrinkage of the step filling structure 24, and thus preventing the storage channel structure 26 from tilting.

[0111] The semiconductor layer can be either a substrate 21 or a common source layer, depending on the specific product requirements. The stacked structure 22' includes alternately stacked gate 224 and gate insulating layer 222. The gate insulating layer 222 is made of an oxide, such as silicon oxide, while the gate 224 is made of a conductive material, which can be any one or a combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides. The step-filled structure 24 is primarily made of insulating materials such as silicon oxide.

[0112] In some embodiments, the storage channel structure 26 and the dummy channel structure 27 further include a stacked storage functional layer n1 and an insulating layer n3, with the channel layer n2 located between the storage functional layer n1 and the insulating layer n3.

[0113] In some embodiments, the memory 20 further includes a storage channel via H, a dummy channel via Q, and a plug 28. The storage channel structure 26 is located in the storage channel via H, the dummy channel structure 27 is located in the dummy channel via Q, and the plug 28 is located in the storage channel via H on the side away from the semiconductor layer and in the dummy channel via Q on the side away from the semiconductor layer. The channel layer n2 in the end of the storage channel structure 26 on the side away from the semiconductor layer is electrically connected to the plug 28.

[0114] The plug 28 can be made of conductive materials, such as tungsten, silicon, or other conductive materials. When the plug 28 is formed in the dummy channel hole Q and the storage channel hole H using the same process, the strength of the dummy channel structure 27 can be further increased, and its tensile strength can be improved.

[0115] It should be understood that the structure and manufacturing process of each component of the memory 20 in the embodiments of this application can be referred to the above-described embodiments of the manufacturing method of the memory 20, and will not be repeated here.

[0116] In summary, the memory 20 and its fabrication method provided in this application involve forming a stacked layer 22 and a step-filling structure 24 on a substrate 21. The stacked layer 22 includes a core region AA and a step region BB. A step structure 223 is formed in the step region BB of the stacked layer 22. The step-filling structure 24 covers the step structure 223. A memory channel via H is formed in the core region AA, and a dummy channel via Q is formed in the step region BB. Subsequently, a memory channel structure 26 is formed in the memory channel via H, and a dummy channel structure 27 is formed in the dummy channel via Q. Both the storage channel structure 26 and the virtual channel structure 27 include a channel layer n2, and the thickness of the channel layer n2 in the storage channel structure 26 is less than the thickness of the channel layer n2 in the virtual channel structure 27. This allows for the fabrication of a high-strength virtual channel structure 27, reducing the tilting phenomenon of the virtual channel structure 27 caused by the shrinkage of the step filling structure 24. Consequently, it also reduces the tilting phenomenon of the storage channel structure 26 caused by the tilting of the virtual channel structure 27, ensuring good support performance of the virtual channel structure 27 and good storage performance of the storage channel structure 26, and improving the reliability of the memory 20.

[0117] Furthermore, embodiments of this application also provide a memory system. Please refer to [link to relevant documentation]. Figure 5 , Figure 5This is a schematic diagram of the memory system provided in an embodiment of this application. The memory system 100 includes at least one of the above-described memory 20 and a controller 30 electrically connected to the memory 20. The controller 30 is also connected to an external host, which can transmit user instructions and stored data to the controller 30. The user instructions may include write instructions, erase instructions, and read instructions, etc. The controller 30 can determine which storage location in the memory 20 to write, erase, and read based on these instructions.

[0118] In the examples of this application, memory 20 is not limited to three-dimensional NAND memory. Without departing from the disclosure or teachings of this application, memory 20 may be implemented as various other types of non-volatile memory that can retain the stored data when the power is disconnected.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of fabricating a memory, comprising: include: A stacked layer and a step-fill structure are formed on a substrate. The stacked layer includes a core region and a step region. A step structure is formed in the step region of the stacked layer. The step-fill structure covers the step structure. A memory channel via is formed in the core region, penetrating the stacked layer and extending into the substrate. A dummy channel via is formed in the step region, penetrating the step structure and the step-fill structure. A storage channel structure is formed in the storage channel hole, and a virtual channel structure is formed in the virtual channel hole; The process of forming a storage channel structure in the storage channel hole and forming a virtual channel structure in the virtual channel hole includes: A storage functional layer and a channel layer located on the storage functional layer are formed on the inner wall of the storage channel hole and the inner wall of the dummy channel hole. A photoresist layer is formed to cover the dummy channel aperture; The channel layer in the memory channel hole is etched back so that the thickness of the channel layer in the memory channel structure is less than the thickness of the channel layer in the dummy channel structure; Remove the photoresist layer.

2. The method of claim 1, wherein The formation of the stacked layers and stepped fill structure on the substrate includes: A stacked layer is formed on a substrate, and a sacrificial trench structure is formed in the core region that penetrates the stacked layer and extends into the substrate; A step structure is formed in the step area, and a step filling structure is formed to cover the step structure; A fictitious channel hole is formed in the stepped area, penetrating the stepped structure and the stepped filling structure; Remove the sacrificial channel structure to obtain the storage channel hole.

3. The method for manufacturing a memory according to claim 1, characterized in that, The step of forming a storage channel structure in the storage channel hole and forming a virtual channel structure in the virtual channel hole further includes: An insulating layer is formed to fill the storage channel hole and the dummy channel hole, resulting in a storage channel structure located in the storage channel hole and a dummy channel structure located in the dummy channel hole, wherein the insulating layer is located on the channel layer.

4. The method for manufacturing a memory according to claim 3, characterized in that, After forming the storage channel structure and the virtual channel structure, the method further includes: A portion of the insulating layer in the end of the storage channel structure facing away from the substrate is removed to expose the channel layer in the end, while a portion of the insulating layer in the end of the dummy channel structure facing away from the substrate is also removed. Plugs are formed in the storage channel hole and the dummy channel hole respectively, and the plugs in the storage channel hole are electrically connected to the exposed channel layer.

5. The method for manufacturing a memory according to claim 2, characterized in that, The removal of the sacrificial channel structure includes: The sacrificial channel structure is removed by an ashing process.

6. The method for manufacturing a memory according to claim 2, characterized in that, A step structure is formed in the step area, and a step filling structure is formed to cover the step structure, including: A stop layer is formed on the stacked layers, and the stop layer and the stacked layers are etched to form a step structure and etched gaps in the step region; The etched voids are filled with insulating material; The surface of the insulating material is planarized using the stop layer. Remove the stop layer to expose the surfaces of the stacked layers and the sacrificial channel structure.

7. The method for manufacturing a memory according to claim 2, characterized in that, The stacked layer includes a first sub-stacked layer and a second sub-stacked layer. The stacked layer is formed on a substrate, and a sacrificial channel structure is formed in the core region, penetrating the stacked layer and extending to the substrate. A first sub-stacked layer is formed on the substrate; A first sub-memory channel hole is formed in the first sub-stack layer, the first sub-memory channel hole penetrates the first sub-stack layer and extends into the substrate, and the first sub-memory channel hole is filled with sacrificial material; A second sub-stack layer is formed on the first sub-stack layer; A second sub-memory channel hole is formed in the second sub-stack layer, and the sacrificial material is removed to obtain the memory channel hole. The second sub-memory channel hole corresponds to the first sub-memory channel hole and is located in the core region of the stack layer. A sacrificial channel structure is formed in the storage channel hole.

8. A memory, characterized in that, include: Semiconductor layer; A stacked structure located on the semiconductor layer, the stacked structure including a core region and a step region, the stacked structure having a step structure in the step region; A step-filling structure covering the aforementioned step structure; A memory channel structure located in the core region, penetrating the stacked structure and extending into the semiconductor layer; as well as A virtual channel structure is located in the step area and penetrates the step structure and the step filling structure. Both the virtual channel structure and the storage channel structure include a channel layer, and the thickness of the channel layer in the storage channel structure is less than the thickness of the channel layer in the virtual channel structure.

9. The memory according to claim 8, characterized in that, The storage channel structure and the virtual channel structure further include a storage functional layer and an insulating layer stacked together, with the channel layer located between the storage functional layer and the insulating layer.

10. The memory according to claim 9, characterized in that, The memory further includes a storage channel via, a dummy channel via, and a plug. The storage channel structure is located in the storage channel via, and the dummy channel structure is located in the dummy channel via. The plug is located in the storage channel via on the side away from the semiconductor layer and in the dummy channel via on the side away from the semiconductor layer. The channel layer in the end of the storage channel structure on the side away from the semiconductor layer is electrically connected to the plug.

11. A memory system, characterized in that, It includes at least one memory as described in any one of claims 8-10, and a controller coupled to the memory, the controller being used to control the memory to perform data write and read operations.

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