Semiconductor device and method of manufacturing the same, memory, and storage system

Abstract

The application discloses a semiconductor device and a preparation method thereof, a memory and a storage system. A reinforcing structure is formed at a sacrifice layer of each step in a step structure, an insulating structure is formed at a position corresponding to the sacrifice layer on an inner wall of a contact hole, and a conductive material is deposited in the contact hole. Thus, when each sacrifice layer is replaced by a gate layer, a completed contact and the insulating structure can provide good support for the stacked structure, preventing the bending of the stacked structure. The application can effectively avoid the problem of high etching requirement of a pseudo channel. Meanwhile, the application does not need to provide a metal or a stop layer required for forming a contact for the semiconductor device, effectively reducing the risk of etching through in the process of forming the contact.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a semiconductor device, its fabrication method, memory, and storage system. Background Technology

[0002] 3D NAND (3D NAND FLASH MEMORY) is an emerging type of flash memory that overcomes the limitations of 2D or planar NAND flash memory by stacking memory chips together.

[0003] In 3D NAND, stepped structures are used to bring out the metal of each layer. To prevent the entire stepped structure from collapsing after the sacrificial material of the word lines is removed, some pseudo-channels need to be etched in the area where the stepped structure is located to provide support, so that contact holes can be formed later, allowing the contacts in the contact holes to connect to the corresponding gate layers.

[0004] As the number of layers in 3D NAND increases, adjacent pseudo-channels need to be spaced a certain distance apart in order to ensure the process window for contact holes to fall. However, if the distance is too large, it will cause word lines to bend, which places high demands on the etching of pseudo-channels. Summary of the Invention

[0005] The purpose of this disclosure is to provide a semiconductor device and its fabrication method, a memory, and a memory system to solve the problem of high etching requirements for pseudo-channels.

[0006] In a first aspect, to achieve the above objective, this disclosure provides a method for fabricating a semiconductor device, comprising:

[0007] Provide substrate;

[0008] A stacked structure is formed on one side of the substrate, the stacked structure including a stepped structure with multiple steps; wherein the stacked structure includes alternately stacked sacrificial layers and insulating layers, and the top layer of the steps is the sacrificial layer;

[0009] A reinforcing structure is formed at the sacrificial layer of each step;

[0010] A contact hole is formed that extends through the reinforced structure and toward the substrate;

[0011] An insulating structure is formed on the inner wall of the contact hole at the location corresponding to the sacrificial layer;

[0012] Conductive material is deposited in the contact hole.

[0013] In some embodiments, forming an insulating structure at the location corresponding to the sacrificial layer on the inner wall of the contact hole includes:

[0014] The sacrificial layer is etched through the contact hole to form a groove;

[0015] The insulating structure is formed at the groove.

[0016] In some embodiments, forming the insulating structure at the groove includes:

[0017] The contact hole is filled with oxide to form the insulating structure at the groove.

[0018] In some embodiments, forming a contact hole extending through the reinforcement structure and toward the substrate includes:

[0019] A contact hole is formed through the reinforced structure and extends close to the substrate.

[0020] In some embodiments, forming a contact hole extending through the reinforcement structure and toward the substrate includes:

[0021] A contact hole is formed that passes through the reinforced structure and extends into the substrate.

[0022] In some embodiments, prior to the step of depositing conductive material in the contact hole, the method for fabricating the semiconductor device further includes:

[0023] The reinforcement structure is etched through the contact hole to thin the reinforcement structure in a direction parallel to the substrate.

[0024] In some embodiments, depositing conductive material in the contact hole includes:

[0025] Conductive material is deposited in the contact holes, and each of the sacrificial layers and the reinforcement structure is replaced with a gate layer.

[0026] In some embodiments, replacing each of the sacrificial layers and the reinforcement structure with a gate layer includes:

[0027] Remove each of the sacrificial layers and the reinforcing structure to form a cavity;

[0028] The cavity is filled with conductive material to form a gate layer.

[0029] In some embodiments, after the step of forming the reinforced structure, the method for fabricating the semiconductor device further includes:

[0030] A dielectric layer is formed on the side of the stacked structure away from the substrate;

[0031] The formation of the contact hole extending through the reinforced structure and toward the substrate includes:

[0032] A contact hole is formed that extends through the dielectric layer and the reinforcement structure toward the substrate.

[0033] In some embodiments, forming the reinforced structure includes:

[0034] The sacrificial layer at the top of the step is oxidized to transform at least a portion of the sacrificial layer at the top of the step into the reinforcing structure.

[0035] In some embodiments, forming the reinforced structure includes:

[0036] An ion implantation process is performed on the sacrificial layer at the top of the step to transform at least a portion of the sacrificial layer at the top of the step into the reinforcing structure.

[0037] In a second aspect, to address the same technical problem, this disclosure provides a semiconductor device comprising:

[0038] A stacked structure, the stacked structure including a stepped structure with multiple steps; wherein the stacked structure includes alternately stacked gate layers and insulating layers, and the top layer of the steps is the gate layer;

[0039] A contact lead-out structure passes through the gate layer and the insulating layer at the corresponding step in the stepped structure and extends to the bottom side of the stepped structure. The contact lead-out structure is electrically connected to the gate layer located at the top layer of the corresponding step.

[0040] An insulating structure is located between the gate layer (excluding the top layer of the step) and the contact lead-out structure.

[0041] In some embodiments, the contact lead-out structure extends through the gate layer and the insulating layer at the corresponding step in the stepped structure, toward the bottom side of the stepped structure, and close to the bottom side of the stepped structure.

[0042] In some embodiments, the contact lead-out structure penetrates the gate layer and the insulating layer at the corresponding step in the stepped structure and extends toward the bottom side of the stepped structure.

[0043] In some embodiments, the semiconductor device further includes a dielectric layer covering the stacked structure.

[0044] In some embodiments, the contact lead-out structure extends through the dielectric layer.

[0045] In a third aspect, this disclosure provides a memory comprising:

[0046] The semiconductor device as described in any of the above embodiments, and the peripheral circuit, wherein the peripheral circuit is electrically connected to the semiconductor device.

[0047] In a fourth aspect, this disclosure provides a storage system, comprising:

[0048] The memory described in the third aspect, and the controller, the controller being electrically connected to the memory and used to control the memory to store data.

[0049] This disclosure provides a semiconductor device and its fabrication method, a memory, and a memory system. By forming a reinforcing structure at the sacrificial layer of each step in a stepped structure, and then forming an insulating structure on the inner wall of the contact hole corresponding to the sacrificial layer, and depositing conductive material in the contact hole, the completed contacts and insulating structure provide good support for the stacked structure when each sacrificial layer is replaced with a gate layer, preventing bending of the stacked structure. Using this disclosure, the problem of high etching requirements for pseudo-channels can be effectively avoided; at the same time, this disclosure eliminates the need to provide the metal or stop layer required for forming contacts in the semiconductor device, effectively reducing the risk of etch-through during contact formation. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment of the present disclosure;

[0051] Figure 2 This is a schematic flowchart of the method for fabricating the semiconductor device provided in this disclosure;

[0052] Figure 3a -j is a schematic diagram of the semiconductor device provided in this disclosure during the fabrication process;

[0053] Figure 4 This is a schematic diagram of a semiconductor device in another embodiment provided in this disclosure;

[0054] Figure 5 This is a schematic diagram of another structure of a semiconductor device in another embodiment provided in this disclosure;

[0055] Figure 6 This is a top view of a cross-section of a semiconductor device provided in this disclosure;

[0056] Figure 7 This is another top view of the cross-section of the semiconductor device provided in this disclosure;

[0057] Figure 8 This is a schematic diagram of the structure of the memory provided in this disclosure;

[0058] Figure 9 This is a schematic diagram of the storage system provided in this disclosure. Detailed Implementation

[0059] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0060] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0061] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0062] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0063] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the cross-section of a semiconductor device in various directions, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0064] It should be noted that the illustrations provided in this disclosure are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] The semiconductor devices disclosed herein can be applied to wafers or three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products.

[0066] Please see Figure 1 , Figure 1 This is a schematic diagram of a semiconductor device structure provided in one embodiment of the present disclosure, such as... Figure 1 As shown, the semiconductor device has a stepped structure. This stepped structure is mainly used to bring out the word lines 2 of each step so that the contact holes fall on each step. In order to prevent the stepped structure from collapsing after the sacrificial material of the word lines 2 is removed, related technologies mainly use dummy channels 1 to etch some steps that penetrate from the side away from the substrate and extend towards the substrate in the stepped structure. These dummy channels 1 provide support for the stepped structure, thereby effectively preventing the stepped structure from collapsing.

[0067] Please continue reading Figure 1 In one embodiment of this disclosure, the main approach is to increase the number of steps in the stepped structure of the semiconductor device to meet users' storage needs for large-capacity memory. However, as the number of steps in the stepped structure of the semiconductor device increases, the number of pseudo-channels 1 that need to be etched also increases. Since two pseudo-channels 1 on the same step need to be separated by a certain distance L, and this distance L should not be too large, otherwise the word lines 2 at that step will bend. Therefore, this embodiment presents a technical problem of high requirements for the etching of pseudo-channels.

[0068] To resolve the above technical issues, please refer to [link / reference]. Figure 2 and Figure 3a -j, Figure 2 This is a schematic flowchart of the semiconductor device fabrication method provided in this disclosure. Figure 3a -j is a schematic diagram of the semiconductor device provided in this disclosure during the fabrication process. It should be noted that... Figure 3a -j only shows an exemplary structure related to the present disclosure. The semiconductor device provided in this disclosure may further include other components and / or structures for realizing the full functionality of the device.

[0069] Specifically, one embodiment of the present disclosure provides a method for fabricating a semiconductor device, which includes steps 101 to 106.

[0070] Please see Figure 2 Step 101 and Figure 3a .

[0071] Step 101, provide substrate 12.

[0072] In one embodiment of this disclosure, the substrate 12 may be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The substrate 12 may also be a substrate including semiconductors of other elements or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0073] Please see Figure 2 Step 102 and Figure 3b .

[0074] Step 102: A stacked structure 11 is formed on one side of the substrate 12. The stacked structure 11 includes a stepped structure 111 with multiple steps. The stacked structure 11 includes alternately stacked sacrificial layers 1112 and insulating layers 1111, and the top layer of the steps is the sacrificial layer 1112.

[0075] In this disclosure, the stacked structure 11 is formed by stacking the insulating layer 1111 and the sacrificial layer 1112. Specifically, the fabrication process of the semiconductor device 10 provided in this disclosure is as follows: first, multiple steps are alternately deposited on the substrate 12, each step including the insulating layer 1111 and the sacrificial layer 1112. An exemplary material for the insulating layer 1111 can be silicon oxide, and an exemplary material for the sacrificial layer 1112 can be silicon nitride. The insulating layer 1111 and the sacrificial layer 1112 have different etching selectivity. Figure 3b As shown, the step includes a sacrificial layer 1112 and an insulating layer 1111 arranged along the direction from away from substrate 12 to towards substrate 12. However, in other embodiments, it may also include a sacrificial layer 1112, an insulating layer 1111, and a sacrificial layer 1112 arranged along the direction from away from substrate 12 to towards substrate 12, or it may include multiple sets of sacrificial layers 1112 and insulating layers 1111 arranged along the direction from away from substrate 12 to towards substrate 12, etc. By etching the sides of the multiple steps, a structure is formed as shown... Figure 3b The step structure 111 shown allows the stacked structure 11 formed by multiple etched steps to include a core region 11A and a step region 11B. Since each step decreases in length along a direction parallel to the substrate 12 from near to far from the substrate 12, the stacked steps form the step region 11B. The portion of the semiconductor device without the step region 11B is called the core region 11A. The step region 11B can be located around the core region 11A or in the middle of the core region 11A.

[0076] In one embodiment of this disclosure, such as Figure 3bAs shown, the side of each step is perpendicular to the substrate 12, but in other embodiments, the side of each step may not be perpendicular to the substrate 12, but may be tilted at an angle.

[0077] In one embodiment of this disclosure, such as Figure 3b As shown, one side of each step is aligned. Since the length of each step decreases sequentially from near to far from the substrate 12 along a direction parallel to the substrate 12, the other side of each step extends to a position sequentially closer to the aligned side from near to far from the substrate 12. In another embodiment, the two sides of each step are aligned along a centerline perpendicular to the substrate 12. Since the length of each step decreases sequentially from near to far from the substrate 12 along a direction parallel to the substrate 12, the two sides of each step extend to positions symmetrical with respect to the centerline, and both extend sequentially closer to the centerline from near to far from the substrate 12.

[0078] In another embodiment of this disclosure, such as Figure 3b As shown, each step decreases in equal increments along its length parallel to the substrate 12 from near the substrate 12 to away from the substrate 12. However, in other embodiments, each step may decrease in an irregular amount along its length parallel to the substrate 12 from near the substrate 12 to away from the substrate 12.

[0079] Please see Figure 2 Step 103 and Figure 3c .

[0080] Step 103: A reinforcing structure 11121 is formed at the sacrificial layer 1112 of each step.

[0081] In this disclosure, the main difference between the reinforced structure 11121 and the unreinforced sacrificial layer 1112 is that their etching rates are different (the etching rate of the unreinforced sacrificial layer 1112 is greater than that of the reinforced structure 11121).

[0082] Specifically, in one embodiment, the step of forming the reinforcing structure 11121 may be: transforming the entire sacrificial layer 1112 at each step of the stepped structure 111 into the reinforcing structure 11121, such as... Figure 3c As shown.

[0083] In another embodiment, the step of forming the reinforcing structure 11121 may also be: converting a portion of the sacrificial layer 1112 at each step in the stepped structure 111 into the reinforcing structure 11121 (not shown in the figure).

[0084] It should be noted that the reinforcing structure 11121 can be the entire sacrificial layer 1112 at each step, or it can be only a portion of the sacrificial layer 1112 at each step. That is, the ratio of the length of the reinforcing structure 11121 to the length of the exposed sacrificial layer 1112 at the corresponding step along the direction of the substrate 12 can be 1 or less than 1. However, it should be noted that the length of the reinforcing structure 11121 along the direction parallel to the substrate 12 must be longer than the length of the contact hole subsequently formed at the corresponding sacrificial layer 1112 along the direction parallel to the substrate 12, and the reinforcing structure 11121 must surround the contact hole.

[0085] In one embodiment of this disclosure, the conversion process for transforming part or all of the sacrificial layer 1112 at each step into the reinforcing structure 11121 may include: oxidizing the sacrificial layer 1112 at the top layer of the step to convert at least a portion of the sacrificial layer 1112 at the top layer of the step into the reinforcing structure 11121. In another embodiment, the conversion process for transforming part or all of the sacrificial layer 1112 at each step into the reinforcing structure 11121 may further include: performing an ion implantation process on the sacrificial layer 1112 at the top layer of the step to convert at least a portion of the sacrificial layer 1112 at the top layer of the step into the reinforcing structure 11121.

[0086] By using an oxidation process or an ion implantation process to treat the sacrificial layer 1112 at the top layer of the step, the sacrificial layer 1112 can be modified, so that the etching rate of the reinforced structure 11121 obtained after the treatment is lower than the etching rate of the original unreinforced sacrificial layer 1112 in the subsequent etching process.

[0087] Please see Figure 2 Step 104 and Figures 3d-3e .

[0088] Step 104: Form a contact hole 14 that extends through the reinforcement structure 11121 and toward the substrate 12.

[0089] In this disclosure, please refer to Figure 3d After obtaining the reinforced structure 11121, the method for fabricating the semiconductor device provided in this disclosure further includes: forming a dielectric layer 13 on the side of the stacked structure 11 away from the substrate 12. Specifically, the process for forming the dielectric layer 13 is as follows: filling the side of the stepped structure 111 away from the substrate 12 with an insulating material to form the dielectric layer 13. The material of the dielectric layer 13 may include insulating materials such as silicon oxide.

[0090] Please see Figure 3eAfter forming the dielectric layer 13, the step of forming a contact hole 14 extending through the reinforcement structure 11121 and toward the substrate 12 includes: forming a contact hole 14 extending through the dielectric layer 13 and the reinforcement structure 11121 toward the substrate 12. Specifically, an etching process is used to etch from the side of the dielectric layer 13 away from the substrate 12 toward the substrate 12, thereby forming a contact hole 14 that simultaneously passes through the step structure 111 and the dielectric layer 13.

[0091] In one embodiment, the contact hole 14 passes through the dielectric layer 13 and part of the step structure 111. It should be noted that the contact hole 14 at least passes through the dielectric layer 13 and the reinforcing structures 11121 at each step, so that the contact hole 14 contacts the sacrificial layer 1112 at each step. That is, the contact hole 14 must have a reinforcing structure contact surface 141 that contacts the reinforcing structure 11121 in the sacrificial layer 1112. Specifically, the reinforcing structure contact surface 141 is mainly used to make the contact hole 14 less susceptible to etching than the contact surface between the contact hole 14 and the unreinforced sacrificial layer 1112 during subsequent etching, given that the etching efficiency of the reinforcing structure contact surface 141 is less than that of the contact surface between the contact hole 14 and the unreinforced sacrificial layer 1112.

[0092] In this disclosure, the etching depth of the contact hole 14 can be preset. Specifically, the step of forming the contact hole 14 extending through the reinforcing structure 11121 and toward the substrate 12 may include: forming the contact hole 14 extending through the reinforcing structure 11121 and close to the substrate 12. In another embodiment, the step of forming the contact hole 14 extending through the reinforcing structure 11121 and toward the substrate 12 may further include: forming the contact hole 14 extending through the reinforcing structure 11121 and into the substrate 12.

[0093] It should be noted that by increasing the etching depth of the contact hole 14, the contact hole 14 is brought closer to the substrate 12. This allows the filled contact hole 14 to provide support for the semiconductor device during subsequent filling, eliminating the need for additional support structures (such as pseudo-channels for support). This provides excellent stress relief for the semiconductor device and effectively prevents the semiconductor device provided by this disclosure from collapsing when the sacrificial material of the word line is removed.

[0094] Furthermore, by extending the contact hole 14 into the substrate 12, this disclosure enables the contact hole 14 to provide maximum support for the semiconductor device after subsequent filling, completely eliminating the collapse phenomenon that would occur when the sacrificial material of the word line is removed. This disclosure not only provides a more stable support effect for the semiconductor device but also skips the process of forming a pseudo-channel during the semiconductor device fabrication process, thereby reducing the significant time and fabrication costs required during semiconductor device fabrication. Simultaneously, this disclosure eliminates the need for providing the metal or stop layer required for etching the contacts in the semiconductor device, effectively reducing the risk of etching through during the contact etching process.

[0095] Please see Figure 2 Step 105 and Figures 3f-3g .

[0096] Step 105: An insulating structure 143 is formed on the inner wall of the contact hole 14 at the location corresponding to the sacrificial layer 1112.

[0097] In this disclosure, the step of forming an insulating structure 143 at the location corresponding to the sacrificial layer 1112 on the inner wall of the contact hole 14 includes: etching the sacrificial layer 1112 through the contact hole 14 to form a groove 142; and forming the insulating structure 143 at the groove 142. Specifically, the insulating structure 143 is formed at the groove 142 by filling the contact hole 14, wherein the filling process mainly involves filling the contact hole 14 with an oxide. The location corresponding to the sacrificial layer 1112 is the contact point with the sacrificial layer 1112, excluding the contact surface 141 with the reinforced structure.

[0098] In this process, by performing an oxidation process or an ion implantation process on the uncovered sacrificial layer 1112 in the stepped structure 111, the treated sacrificial layer 1112 can be modified to obtain a reinforced structure 11121. This method makes the reinforced structure 11121 more difficult to etch (i.e., the etching rate is lower) than the unreinforced sacrificial layer 1112. Therefore, when processing the unreinforced sacrificial layer 1112 and the reinforced structure 11121, the unreinforced sacrificial layer 1112 can be etched more easily, thereby forming the groove 142.

[0099] In this disclosure, by utilizing the characteristic that the reinforcing structure 11121 and the unreinforced sacrificial layer in the contact hole 14 have different etching rates, grooves 142 can be formed at the contact points with the sacrificial layer 1112, except for those with the reinforcing structure contact surface 141, through etching, without forming grooves at the contact points between the reinforcing structure contact surface 141 and the contact hole 14. The main purpose of forming the grooves 142 is to form an insulating structure 143 at the grooves 142, so that during subsequent deposition of conductive material, the deposited conductive material can only be connected to the reinforcing structure 11121, and not to any other sacrificial layers in the contact hole 14 except for those with the reinforcing structure contact surface 141.

[0100] Specifically, the process of forming the insulating structure 143 at the groove 142 is as follows: first, insulating material is deposited until the contact hole 14 and the groove 142 are completely filled; then, an etching process (e.g., dry or wet etching) can be used to etch a straight-through groove with an increased spacing into the insulating material at the contact hole 14 and the groove 142, and some insulating material is retained at the groove 142 and the substrate 12. The insulating material retained at the groove 142 becomes the insulating structure 143 (e.g., ...). Figure 3g (As shown). It is understood that during the etching process, a portion of the insulating material in the groove 142 may not be etched or may be etched away, as long as some insulating material is retained to form the insulating structure 143 to block the connection between the subsequently deposited conductive material and the sacrificial layer.

[0101] Optionally, in one embodiment, the portion of insulating material retained at the substrate 12 may not be etched away during the etching process, thereby forming a layer at the substrate 12 such as... Figure 3g The insulating structure 143 is shown. Specifically, the height of the insulating structure 143 formed on the substrate 12 within the contact hole 14 needs to be less than the height of the top layer of each step in the stepped structure 111, that is, it is necessary to ensure at least the connectivity between the subsequently deposited conductive material and the sacrificial layer at the top layer of each step in the stepped structure 111. In another embodiment, to prevent bending of the stepped structure, the height of the insulating structure 143 formed on the substrate 12 within the contact hole 14 needs to be as low as possible, so that sufficient conductive material can be filled in the contact hole 14 to provide good support for the stepped structure 111. Preferably, the insulating structure 143 on the substrate 12 can be removed by etching to expose the substrate 12 in the contact hole 14, thereby allowing more conductive material to be filled in the contact hole 14 to provide better support for the stepped structure 111.

[0102] In some embodiments, to improve the deposition efficiency and effect of conductive materials, the semiconductor device fabrication method provided in this disclosure further includes: etching the reinforcement structure 11121 through the contact hole 14 to thin the reinforcement structure 11121 in a direction parallel to the substrate, thereby forming a... Figure 3g The structure shown. Specifically, the reinforcing structure 11121 can be thinned using an etching process.

[0103] Please see Figure 2 Step 106 and Figure 3h .

[0104] Step 106: Deposit conductive material in the contact hole 14.

[0105] In this disclosure, by depositing conductive material in the contact hole 14 to form the contact 15, the contact 15 can provide good stress assistance when the sacrificial material is removed in the subsequent semiconductor device. This solves the problem of dependence on using a pseudo-channel to provide support for the semiconductor device, thereby saving the process step of forming the pseudo-channel and reducing the fabrication time and cost of the semiconductor device.

[0106] Furthermore, since there is no process flow that forms a pseudo-channel, there is no need to worry about the spacing between the process window where the contact hole 14 falls and the adjacent pseudo-channels on the same step during the semiconductor device fabrication process. This reduces the occurrence of word line bending and improves the yield of semiconductor devices.

[0107] Please see Figures 3i-3j .

[0108] As a preferred embodiment, the method for fabricating the semiconductor device provided in this disclosure further includes: depositing a conductive material in the contact hole 14, and replacing each of the sacrificial layers 1112 and the reinforcing structure 11121 with a gate layer 1113.

[0109] In this disclosure, the specific process of replacing each of the sacrificial layers 1112 and the reinforcing structure 11121 with the gate layer 1113 is as follows: removing each of the sacrificial layers 1112 and the reinforcing structure 11121 to form a cavity; filling the cavity with a conductive material to form the gate layer 1113.

[0110] Specifically, since the sacrificial layer 1112, the reinforcing structure 11121, and the insulating layer 1111 have different etching selectivity, the sacrificial layer 1112 and the reinforcing structure 11121 can be removed by a corresponding etching process to form a cavity, while retaining the insulating structure 143. Then, a conductive material is deposited in the cavity as the gate layer 1113. The conductive material can include metals such as tungsten (W), and can also include polysilicon or metal silicides, such as metal silicides selected from cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), W, and titanium (Ti). Due to the presence of the insulating structure 143, the contact 15 can only communicate with and achieve electrical conduction with the gate layer 1113 at each step of the stepped structure 111, thereby achieving the purpose of individually controlling each contact only for its corresponding step.

[0111] The semiconductor device fabrication method disclosed herein first processes the sacrificial layer 1112 of each step, such that the etching rate of the resulting reinforced structure 11121 is much lower than the etching rate of the unreinforced sacrificial layer. Then, the step structure 111 is etched to form a contact hole 14 extending towards the substrate 12 through the reinforced structure 11121 of the sacrificial layer 1112. Then, taking advantage of the characteristic that the etching rate of the reinforced structure 11121 is much lower than the etching rate of the unreinforced sacrificial layer, the contact hole 14 is etched to form a groove 142. Next, insulating material is filled into the contact hole 14 and the groove 142, and a back-etching process is performed to remove some of the insulating material from the contact hole 14 and the groove 142, leaving insulating material in the substrate 12 and the groove 142. Simultaneously, an insulating structure 143 is formed at the groove 142. This insulating structure 143 allows the subsequently formed contact 15 to communicate only with the gate layer 1113 of the corresponding step. Furthermore, conductive material is deposited in the contact hole 14 to form the contact 15. The contact 15 can provide good stress assistance to the semiconductor device, thus eliminating the need for the process of forming a pseudo-channel and providing good support for the semiconductor device. This reduces the fabrication time and cost of the semiconductor device.

[0112] Please see Figure 4 , Figure 4 This is a schematic diagram of a semiconductor device provided in this disclosure, such as... Figure 4 As shown, the semiconductor device 20 provided in this disclosure includes: a stacked structure 21, a contact lead-out structure 24, and an insulating structure 2113.

[0113] In some embodiments, the semiconductor device may further include a substrate 22, which is located on one side of the stacked structure 21. Optionally, the substrate 22 is located on the bottom side of the stacked structure 21. Specifically, the substrate 22 may be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The substrate 22 may also be a substrate including semiconductors of other elements or compound semiconductors, and may also be a stacked structure, such as Si / SiGe. The stacked structure 21 includes a gate layer 2112 and an insulating layer 2111. The stacked structure 21 is formed by stacking the insulating layer 2111 and the gate layer 2112. Furthermore, the stacked structure 21 has multiple steps. One layer of insulating layer 2111 and one layer of gate layer 2112 are stacked to form one step. Through the alternating stacking of multiple steps, a structure is formed as shown in the figure. Figure 4 The step structure 211 shown is wherein the top layer of the step is the gate layer 2112.

[0114] Optionally, in some embodiments, the semiconductor device may not include substrate 22. Since the specific structure of the semiconductor device varies in different application scenarios, the specific structure of the semiconductor device can be adaptively configured according to actual needs, and is not limited here.

[0115] like Figure 4 As shown, the stacked structure 21 is located on one side of the substrate 22, and each step decreases in size from small to large along its length parallel to the substrate 22. The contact lead-out structure 24 passes through the gate layer 2112 and the insulating layer 2111 at the corresponding step in the stepped structure 211, and extends towards the bottom side of the stepped structure 211. The contact lead-out structure 24 is electrically connected to the gate layer 2112 located at the top layer of the corresponding step. The insulating structure 2113 is located between the gate layer (excluding the gate layer 2112 at the top layer of the step) and the contact lead-out structure 24.

[0116] In this disclosure, the layered structure 21 includes a core region 21A and a stepped region 21B, and the stepped region 21B has a stepped structure 211 composed of multiple steps. See also... Figure 4 The semiconductor device 20 provided in this disclosure further includes a dielectric layer 23. The dielectric layer 23 covers multiple steps, that is, the dielectric layer 23 covers the stacked structure 21.

[0117] The contact lead-out structure 24 passes through the side of the medium layer 23 away from the bottom side of the step structure 211 and through the top layer of each step, and extends toward the bottom side of the step structure 211.

[0118] In one embodiment, the insulating structure 2113 may be located between and around the contact lead-out structure 24, and in all gate layers except the gate layer 2112 at the top of the step, such as... Figure 4 As shown.

[0119] In another implementation, please refer to Figure 5 , Figure 5 This is another schematic diagram of the semiconductor device provided in this disclosure. The insulating structure 2113 may also be located in part of the gate layer other than the gate layer 2112 at the top layer of the step, between and around the contact lead-out structure 24. Specifically, as shown... Figure 5 As shown.

[0120] It should be noted that, Figure 5 This is merely a schematic diagram of one structure in this disclosure; the location of the insulating structure 2113 is not limited to, for example, the following. Figure 5 The position shown is acceptable as long as the insulating structure 2113 is located between the gate layer (excluding the gate layer 2112 at the top of the step) and the contact lead-out structure 24, and surrounds the contact lead-out structure 24; specific examples are not listed here. As an optional embodiment, the contact lead-out structure 24 passes through the gate layer 2112 and the insulating layer 2111 at the corresponding step in the step structure 211, extends towards the bottom side of the step structure 211, and is close to the bottom side of the step structure 211 (e.g., ...). Figure 5 The two contact lead-out structures 24 shown are located near the core area 21A.

[0121] As another optional embodiment, the contact lead-out structure 24 penetrates the gate layer 2112 and the insulating layer 2111 at the corresponding step in the stepped structure 211, extending towards the bottom side of the stepped structure 211 (e.g., Figure 5 The two contact lead-out structures 24 shown are located away from area 21A.

[0122] In some embodiments, see Figure 6 , Figure 6 This is a top view of a cross-section of a semiconductor device provided in this disclosure, such as... Figure 6 As shown, Figure 6This is a top view of the semiconductor device provided in this disclosure in the direction perpendicular to the substrate (Y direction), and this top view is a cross-sectional view of the semiconductor device along the cross-sectional direction (i.e., the X direction). In this disclosure, the semiconductor device provided includes a row of (X direction) steps (N steps and N+1 steps), each step having a contact lead-out structure 24, and the contact lead-out structure 24 being surrounded by an insulating structure 2113.

[0123] In other embodiments, please refer to Figure 7 , Figure 7 This is another top view schematic diagram of the cross-section of the semiconductor device provided in this disclosure, such as... Figure 7 As shown, Figure 7 This is a top view of the semiconductor device provided in this disclosure in the direction perpendicular to the substrate (Y direction), and this top view is a cross-sectional view of the semiconductor device along the cross-sectional direction (i.e., the X direction). In this disclosure, the semiconductor device provided includes multiple rows (X direction) of steps (N layers of steps and N+1 layers of steps). Each layer of steps has two contact lead-out structures 24, and each contact lead-out structure 24 is surrounded by an insulating structure 2113.

[0124] It should be noted that, Figure 7 The diagram only shows a two-row structure, but it is not limited to a three-row, four-row, or other structure with more than two rows. When the semiconductor device is set to a three-row, four-row, or other structure with more than two rows, a contact lead-out structure 24 with the corresponding number of rows is set at each step.

[0125] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the memory provided in this disclosure. The memory 200 can be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0126] The memory 200 includes a semiconductor device 201 and peripheral circuitry 202. The semiconductor device 201 can be any of the semiconductor devices described in the above embodiments, and the peripheral circuitry 202 can be a CMOS (Complementary Metal-Oxide-Semiconductor). The semiconductor device 201 can be stacked with the peripheral circuitry 202, or they can be staggered; this application is not limited in this regard. The peripheral circuitry 202 is electrically connected to the semiconductor device 201 to transmit signals. The peripheral circuitry 202 can be used for logic operations and to control and detect the switching states of each memory cell in the semiconductor device 201 via metal interconnects, thereby enabling data storage and retrieval.

[0127] The semiconductor device 201 includes a substrate, a stacked structure, a contact lead-out structure, and an insulating structure. The stacked structure is located on one side of the substrate, and each step decreases in number along its length parallel to the substrate, with the distance from the substrate increasing sequentially; the top layer of each step is the gate layer. The contact lead-out structure passes through the gate layer and the insulating layer at the corresponding step in the stepped structure and extends towards the bottom of the stepped structure. The contact lead-out structure is electrically connected to the gate layer at the top layer of the corresponding step. The insulating structure is located between the gate layer (excluding the gate layer at the top layer of the step) and the contact lead-out structure.

[0128] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of the storage system provided in this disclosure. The storage system 300 includes a memory 301 and a controller 302. The memory 301 can be the memory in any of the above embodiments, and the memory 301 can include any of the semiconductor devices in the above embodiments. The controller 302 is electrically connected to the memory 301 and is used to control the memory 301 to store data. The memory 301 can perform data storage operations based on the control of the controller 302.

[0129] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0130] The semiconductor device in the memory 301 includes a substrate, a stacked structure, a contact lead-out structure, and an insulating structure. The stacked structure is located on one side of the substrate, and each step decreases in size along its length parallel to the substrate, with the distance from the substrate increasing sequentially; wherein the top layer of each step is the gate layer. The contact lead-out structure passes through the gate layer and the insulating layer at the corresponding step in the stepped structure and extends towards the bottom of the stepped structure. The contact lead-out structure is electrically connected to the gate layer located at the top layer of the corresponding step. The insulating structure is located between the gate layer (excluding the gate layer at the top layer of the step) and the contact lead-out structure.

[0131] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, include: Provide substrate; A stacked structure is formed on one side of the substrate, the stacked structure including a stepped structure with multiple steps; wherein the stacked structure includes alternately stacked sacrificial layers and insulating layers, and the top layer of the steps is the sacrificial layer; A portion of the sacrificial layer at each step in the stepped structure is transformed into a reinforcing structure, wherein the etching rate of the unreinforced sacrificial layer is greater than the etching rate of the reinforcing structure. A contact hole is formed that extends through the reinforced structure and toward the substrate; The sacrificial layer is etched through the contact hole to form a groove, the contact hole and the groove are filled with insulating material, the insulating material in the contact hole and part of the insulating material in the groove are removed to form an insulating structure at the groove; Conductive material is deposited in the contact hole and the groove.

2. The method of producing a semiconductor device according to Claim 1, wherein The formation of the contact hole extending through the reinforced structure and toward the substrate includes: A contact hole is formed through the reinforced structure and extends close to the substrate.

3. The method of producing a semiconductor device according to Claim 1, wherein The formation of the contact hole extending through the reinforced structure and toward the substrate includes: A contact hole is formed that passes through the reinforced structure and extends into the substrate.

4. The method of producing a semiconductor device according to Claim 1, wherein Prior to the step of depositing conductive material in the contact hole, the method for fabricating the semiconductor device further includes: The reinforcement structure is etched through the contact hole to thin the reinforcement structure in a direction parallel to the substrate.

5. The method of producing a semiconductor device according to Claim 1, wherein The deposition of conductive material in the contact hole includes: Conductive material is deposited in the contact holes, and each of the sacrificial layers and the reinforcement structure is replaced with a gate layer.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The step of replacing each of the sacrificial layers and the reinforcement structure with a gate layer includes: Remove each of the sacrificial layers and the reinforcing structure to form a cavity; The cavity is filled with conductive material to form a gate layer.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, Following the step of forming the reinforced structure, the method for fabricating the semiconductor device further includes: A dielectric layer is formed on the side of the stacked structure away from the substrate; The formation of the contact hole extending through the reinforced structure and toward the substrate includes: A contact hole is formed that extends through the dielectric layer and the reinforcement structure toward the substrate.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The formation of the reinforced structure includes: The sacrificial layer at the top of the step is oxidized to transform at least a portion of the sacrificial layer at the top of the step into the reinforcing structure.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The formation of the reinforced structure includes: An ion implantation process is performed on the sacrificial layer at the top of the step to transform at least a portion of the sacrificial layer at the top of the step into the reinforcing structure.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method of any one of claims 1 to 9, wherein the semiconductor device comprises: A stacked structure, the stacked structure including a stepped structure with multiple steps; wherein the stacked structure includes alternately stacked gate layers and insulating layers, and the top layer of the steps is the gate layer; A contact lead-out structure passes through the gate layer and the insulating layer at the corresponding step in the stepped structure and extends to the bottom side of the stepped structure. The contact lead-out structure is electrically connected to the gate layer located at the top layer of the corresponding step. An insulating structure is located between the gate layer (excluding the top gate layer of the step) and the contact lead-out structure. The stepped structure is provided with a longitudinally extending contact hole and a groove that communicates with and surrounds the contact hole. The contact lead-out structure is located in the contact hole and the groove. The insulating structure is located in the groove and surrounds the portion of the contact lead-out structure located in the groove.

11. The semiconductor device as claimed in claim 10, characterized in that, The contact lead-out structure passes through the gate layer and the insulating layer at the corresponding step in the stepped structure, extends towards the bottom side of the stepped structure, and is close to the bottom side of the stepped structure.

12. The semiconductor device as claimed in claim 10, characterized in that, The contact lead-out structure penetrates the gate layer and the insulating layer at the corresponding step in the stepped structure and extends towards the bottom side of the stepped structure.

13. The semiconductor device as claimed in claim 10, characterized in that, The semiconductor device further includes a dielectric layer that covers the stacked structure.

14. The semiconductor device as claimed in claim 13, characterized in that, The contact lead-out structure extends through the dielectric layer.

15. A memory, characterized in that, include: The semiconductor device according to any one of claims 10-14, and the peripheral circuit, wherein the peripheral circuit is electrically connected to the semiconductor device.

16. A storage system, characterized in that, The storage system includes: The memory as described in claim 15, and A controller, electrically connected to the memory, is used to control the memory to store data.

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