Oscillator for initiating pulse communication with reduced latency

Abstract

An oscillator (31) is provided for use in pulse communication of a pulse signal with a start-up delay and a pulse oscillation signal (e.g., for use in a transmitter of OOK pulse communication with pulse modulation). The oscillator (31) includes an LC resonator (35) having a slot impedance and comprising a high-side node (Vp) and a low-side node Vm, and having a slot voltage corresponding to [Vp-Vm]. A pulse start-up circuit (39A) includes a PMOS transistor having a source connected to a power supply voltage VDD and a drain connected to the Vp node via a resistor R (where R is significantly larger than the slot impedance), and connected in parallel with a damping capacitor. A PMOS control terminal is coupled to receive a jump start pulse to initiate a pulse signal. The oscillator (31) may include high-side (39A) and low-side pulse (39B) start-up circuits.

Description

Background Technology

[0001] Digital isolators can use oscillators to communicate digitally with pulse (oscillation) signals across isolation barriers. Figure 1 This describes a digital isolator 10 having a TX oscillator 11 and an RX receiver (tank) 12 coupled capacitively or inductively across an isolation barrier 15. Data signals are encoded 17 and transmitted as pulse signals 11, which are sensed by the receiver and decoded 18 back into digital form.

[0002] Communication is based on pulse modulation, such as pulse coding, pulse amplitude, pulse width, and pulse position. For example, pulse communication can be based on on / off keying (OOK) and edge coding (e.g., one pulse for the rising edge and two pulses for the falling edge).

[0003] While this background information refers to digital isolators, this disclosure more generally relates to oscillator designs for pulse communication. Summary of the Invention

[0004] This brief summary of the invention is provided as a general introduction to the disclosure, as illustrated by the detailed description and accompanying drawings, summarizing aspects and features of the disclosure. It is not a complete overview of the disclosure and should not be construed as identifying key elements or features of the disclosed invention, or otherwise characterizing or defining the scope of the disclosed invention.

[0005] This disclosure describes an apparatus and method for pulse communication using an oscillator that reduces startup delay by employing active kick-start.

[0006] According to an aspect of this disclosure, an oscillator for use in pulse communication of a pulse signal having a start-up delay and a pulse oscillation signal includes an LC resonator comprising an inductor L and a capacitor C, and having a slot impedance. The LC resonator includes a high-side node (Vp) and a low-side node Vm, and has a slot voltage corresponding to [Vp-Vm]. The pulse start-up circuit includes: a PMOS transistor having a source connected to a power supply voltage VDD, and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the slot impedance; and a damping capacitor connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

[0007] According to other aspects of this disclosure, a circuit for transmitting a pulse signal having a start-up delay and a pulse oscillation signal includes a transmitter circuit system comprising an oscillator configured to generate the pulse signal. The oscillator includes an LC resonator comprising an inductor L and a capacitor C, and having a slot impedance. The LC resonator includes a high-side node (Vp) and a low-side node Vm, and has a slot voltage corresponding to [Vp-Vm]. The pulse start-up circuit system includes: a PMOS transistor having a source connected to a power supply voltage VDD, and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the slot impedance; and an attenuation capacitor connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate the pulse signal.

[0008] According to other aspects of this disclosure, a method for pulse communication of a pulse signal having a start-up delay and a pulse oscillation signal is disclosed for use in a system having a transmitter oscillator comprising an LC resonator including an inductor L and a capacitor C, and having a slot impedance. The LC resonator includes a high-side node (Vp) and a low-side node Vm, and has a slot voltage corresponding to [Vp-Vm]. The method comprises: initiating a pulse signal from the oscillator using a jump-start pulse; and generating the jump-start pulse using a pulse-start circuit comprising: a PMOS transistor having a source connected to a power supply voltage VDD, and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the slot impedance, and an attenuation capacitor connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive the jump-start pulse to initiate the pulse signal.

[0009] Other aspects and features of the invention claimed in this patent document will be apparent to those skilled in the art from the following disclosure. Attached Figure Description

[0010] Figure 1 The digital isolator 10 is described as having a TX oscillator 11 and an RX receiver (slot) 12 coupled capacitively or inductively across an isolation barrier 15, configured for, for example, OOK pulse modulation.

[0011] Figures 2A to 2B Explain the oscillator used for pulse communication (e.g., for use in digital isolators): Figure 2A This describes an example oscillator 21 used for pulse communication, which includes the generation of pulse (oscillation) signals; and Figure 2B This describes an example pulse signal with a pulse width based on a start-up delay followed by a pulse oscillation (a steady-state oscillation with a defined swing).

[0012] Figure 3A The example oscillator 31 with active jump start circuit 39A / 39B according to this disclosure is used to start pulse communication with reduced delay.

[0013] Figure 3B The example pulse signal waveform is described, which includes an example pulse signal with a defined start delay after the pulse is initiated, followed by a pulse oscillation (a steady-state oscillation with a defined swing). Detailed Implementation

[0014] This specification and accompanying drawings constitute this disclosure, which includes design examples and implementation schemes, and includes various technical features and advantages of oscillators for pulse communication using active jump start to reduce start-up delay.

[0015] The example application is based on digital isolation of a transmitter oscillator for pulse (oscillation) communication, which is capacitively (or inductively) coupled to the receiver across an isolation barrier. An alternative example application is a transmitter oscillator for pulse communication coupled to an antenna for wireless communication with a remote receiver. Example pulse modulation includes OOK (on / off keying) and edge coding.

[0016] This disclosure uses the following terms: a pulse signal or pulse oscillation signal comprises a start-up oscillation period (start-up delay), followed by a specified steady-state oscillation period (pulse oscillation period), wherein the pulse width is determined by the start-up delay and the pulse oscillation period (steady-state oscillation). The start-up delay may also be referred to as wake-up or settling time. For pulse communication, including examples of OOK modulation, the start-up delay is an important aspect of the pulse width and is therefore a significant determinant of system power, latency, and speed.

[0017] In short, an oscillator for use in pulse communication of a pulsed signal with a start-up delay and a pulse oscillation signal comprises an LC resonator having a slot impedance and including a high-side node (Vp) and a low-side node Vm, and having a slot voltage corresponding to [Vp-Vm]. The pulse start-up circuit includes a PMOS transistor having a source connected to a supply voltage VDD and a drain connected to the Vp node via a resistor R (where R is significantly larger than the slot impedance), and connected in parallel with a damping capacitor. A PMOS control terminal is coupled to receive a jump start pulse (e.g., 1 ns) to initiate the pulse signal. The oscillator may include high-side and low-side pulse start-up circuits. An example application is a transmitter oscillator for OOK pulse communication with pulse modulation.

[0018] Figure 2A This describes an oscillator 21 used for pulse communication, which generates pulse (oscillation) signals. Figure 2BThis describes an example pulse signal with a pulse width based on a start-up delay followed by a pulse oscillation (a steady-state oscillation with a defined swing).

[0019] Oscillator 21 is configured for digital isolation applications, and the oscillator is configured as a transmitter for pulse communication (OOK) across isolation barriers.

[0020] Oscillator 21 includes an oscillator core 23 with an LC resonator (slot) 25 and a two-stage feedback generator 27. The LC resonator 25 includes coupled inductors L1 and L2, whose center tap is grounded. The slot inductors L1 / L2 are connected between the high-side node Vp and the low-side node Vm. The voltage difference between nodes Vp and Vm is the slot voltage [Vp-Vm], which defines the oscillator's (voltage) swing (each of nodes Vp / Vm experiences half of the slot voltage swing). Parasitic capacitance (tunable via slot inductors L1 / L2) is not shown.

[0021] Oscillator 21 includes high-side and low-side startup circuits 29A and 29B coupled to corresponding nodes Vp and Vm. Startup circuits 29A and 29B include corresponding startup capacitors CA and CB to provide initial energy in the LC resonator slot 25 during VIN transition. VIN is the input to startup circuits 29A / 29B (and provides an enable signal to the feedback generator). For higher VIN, startup capacitors CA and CB become part of the LC resonator slot, which limits oscillation and reduces the oscillation frequency. The pumped energy is proportional to the capacitance ratio of the startup capacitors and the slot capacitors, as well as VDD (e.g., 1.8V); therefore, for higher oscillation, CA and CB should be lower capacitances, while for faster startup, CA and CB should be higher capacitances.

[0022] refer to Figure 2B The instance pulse signal is initiated by a VIN current pulse input to resonator slot 25 through the start-up capacitor CA / CB. The instance start-up delay after initiation is 5 ns before pulse oscillation (steady-state oscillation) is achieved.

[0023] The pulse width and pulse oscillation period (effective power transfer) are determined by the receiver's pulse signal sensing requirements. An example pulse signal consists of a 5ns start-up delay 29SU followed by a 7ns pulse oscillation (steady-state oscillation) 29SS, for a total pulse width of 12ns, where the pulse oscillation 29SW (slot voltage) is 1.8V.

[0024] Figure 3A and 3B This invention describes an example oscillator 31 with an active jump-start circuit, which is used to initiate pulse communication with reduced startup delay. The example oscillator 31 can be implemented in an example digital isolator using capacitive isolation, offering advantages in low power and isolation voltage specifications.

[0025] Figure 3A This describes an example oscillator 31 with example high-side and low-side active jump start circuits 39A and 39B. Figure 3B The example pulse signal waveform is described, which includes an example pulse signal with a defined start delay after the pulse is initiated, followed by pulse oscillation (steady-state oscillation).

[0026] like Figure 3B As described herein, the active jump-start circuit according to this disclosure can provide a pulse oscillation signal in which the start-up delay 39SU (from 5ns) is reduced to 2ns, thereby achieving a pulse oscillation period (steady-state oscillation) 39SS (from 7ns to) 9ns. The resulting pulse width is reduced (from 12ns to) 11ns.

[0027] The example oscillator 31 includes an example oscillator core 33 and example active jump-start circuits 39A and 39B. The example oscillator core 33 uses... Figure 2A The oscillator core configuration in the [disclosure name]. According to this disclosure, active jump-start circuits 39A and 39B are used to reduce startup delay and replace [other components]. Figure 1 The passive capacitor startup circuit 29A / 29B (eliminating startup capacitors CA / CB) is included.

[0028] The oscillator core can contain any suitable structure for an LC resonator. In an example implementation, in addition to the LC resonator 35, the oscillator core 33 also includes a two-stage feedback generator 37.

[0029] The LC resonator 35 includes coupled inductors L1 and L2, with the center tap grounded (although the inductor center tap can be connected to different voltages). If the inductor center tap is grounded, then the low-side active snap-start circuit 39B is not required (if the voltage of the inductor center tap is different from ground, then the low-side active snap-start circuit is recommended). Parasitic capacitances (tunable via slot inductors L1 / L2) are not shown.

[0030] The resonator slot-coupled inductors L1 / L2 are connected between the high-side node Vp and the low-side node Vm. The voltage difference between nodes Vp and Vm is the slot voltage [Vp-Vm], which defines the oscillator's (voltage) swing (each of nodes Vp / Vm experiences half of the slot voltage swing).

[0031] Example active snap-start circuits 39A and 39B are coupled to the corresponding LC resonator slot nodes Vp and Vm. Input VIN is used to enable feedback generator 37, but is not input to active snap-start circuits 39A / 39B.

[0032] The active jump-start circuit 39A includes a PMOS M1 with a source coupled to VDD and a drain coupled to the resonator slot Vp node via a resistor R. A CATT capacitor is connected in parallel with R to the PMOS drain, thereby forming a low-pass filter for attenuating the oscillation frequency. An optional low-side active jump-start circuit 39B includes an NMOS M2 with a source coupled to ground and a drain coupled to the resonator slot Vm node via a resistor R. A CATT capacitor is connected in parallel with R to the NMOS drain, thereby forming a low-pass filter.

[0033] For the two example jump-start circuits, R is chosen to be significantly greater than the slot impedance, for example, 5 to 10X, so that the jump-start circuit does not affect the steady-state oscillation. For the example slot parallel resonant impedance of 1K, the example jump-start circuit can be configured with R = 10K and CATT = 100fF.

[0034] The active jump start circuit 39A receives the jump start voltage pulse at the control terminal M1, generates the jump start current pulse through the resonator inductors L1 / L2, and initiates the pulse signal. The initial start current of the two active jump start circuits 39A / 39B is VDD / R, and the energy is only input to the resonator slot 35 for the duration of the jump start pulse (e.g., 1 ns).

[0035] Receiver pulse sensing based on pulse oscillation (efficient power transfer) requires selection of pulse width. (Reference) Figure 3B The example pulse signal is a 9ns pulse oscillation (steady-state oscillation) 39SS, with a total pulse width of 11ns, and the pulse oscillation (slot voltage) 39SW is 1.8V.

[0036] The CATT capacitor attenuates the oscillation frequency without affecting the startup DC current and provides protection against M1 / M2 GOI by keeping the leakage of M1 / M2 low. When the jump start pulse is turned off, M1 and M2 float but are off and present high impedance.

[0037] This disclosure, provided by the specification and accompanying drawings, illustrates exemplary designs and applications of aspects and features of the invention, but does not limit the scope of the invention, which is defined by the claims. To avoid obscuring the principles and features of the disclosed exemplary designs and applications, known circuits, connections, functions, and operations are not described in detail. This disclosure can be used as the basis for modifications, substitutions, and alternatives by those skilled in the art, including adaptations for other applications.

Claims

1. An oscillator for use in pulse communication of a pulse signal having a start-up delay and a pulse oscillation signal, comprising: An LC resonator consists of an inductor L and a capacitor C, and has slot impedance. The LC resonator described herein includes a first node Vp and a second node Vm; A pulse-start circuit includes: A PMOS transistor is configured to have a source connected to a power supply voltage VDD and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the tank impedance. A damping capacitor, which is connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

2. The oscillator according to claim 1, wherein the pulse start circuit is a high-side pulse start circuit having a first resistor R and a first attenuation capacitor, and further comprises: The low-side pulse start-up circuit includes: An NMOS transistor has a source connected to a common terminal of the circuit and a drain connected to the Vm node via a second resistor R, wherein the second resistor R is significantly larger than the slot impedance. The second attenuation capacitor is connected in parallel with the second resistor R to the drain. The NMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

3. The oscillator of claim 1, wherein the jump start pulse is applied to the PMOS control input such that the initial start current through L is VDD / R.

4. The oscillator according to claim 1, wherein the attenuation capacitor attenuates the oscillation frequency without affecting the pulse signal initiated by the jump start pulse.

5. The oscillator according to claim 1, wherein the duration of the jump start pulse is in the range of 1 ns.

6. The oscillator of claim 1, wherein pulse communication is based on on-off keying (OOK) and edge encoding.

7. The oscillator of claim 1, wherein the oscillator is used as a transmit oscillator in a digital isolator.

8. A circuit for transmitting a pulse signal having a start-up delay and a pulse oscillation signal, the circuit comprising: A transmitter circuit system comprising an oscillator configured to generate a pulse signal, the oscillator comprising: An LC resonator consists of an inductor L and a capacitor C, and has slot impedance. The LC resonator described herein includes a first node Vp and a second node Vm; A pulse-start circuit system, comprising: A PMOS transistor is configured to have a source connected to a power supply voltage VDD and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the tank impedance. A damping capacitor, which is connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

9. The circuit of claim 8, wherein the pulse-start circuit system is a high-side pulse-start circuit having a first resistor R and a first attenuation capacitor, and further comprises: The low-side pulse start-up circuit system includes: An NMOS transistor has a source connected to a common terminal of the circuit and a drain connected to the Vm node via a second resistor R, wherein the second resistor R is significantly larger than the slot impedance. The second attenuation capacitor is connected in parallel with the second resistor R to the drain. The NMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

10. The circuit of claim 8, wherein the jump start pulse is applied to the PMOS control input such that the initial start current through L is VDD / R.

11. The circuit of claim 8, wherein the attenuation capacitor attenuates the oscillation frequency without affecting the pulse signal initiated by the jump start pulse.

12. The circuit of claim 8, wherein the duration of the jump start pulse is in the range of 1 ns.

13. The circuit of claim 8, wherein pulse communication is based on on-off keying (OOK) and edge encoding.

14. The circuit of claim 8, wherein the transmitter circuit system is used in a digital isolator.

15. A method for pulse communication of a pulse signal having a start-up delay and a pulse oscillation signal, the method being used in a system having a transmitter oscillator comprising an LC resonator, the LC resonator comprising an inductor L and a capacitor C, and having a slot impedance, wherein the LC resonator comprises a high-side node Vp and a low-side node Vm, the method comprising: A pulse signal is initiated from the oscillator using a jump start pulse; The sudden-start pulse is generated using a pulse-start circuit, the pulse-start circuit comprising: A PMOS transistor is configured to have a source connected to a power supply voltage VDD and a drain connected to the Vp node via a resistor R, wherein R is significantly larger than the tank impedance. A damping capacitor, which is connected in parallel with the resistor R to the drain. The PMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

16. The method of claim 15, wherein the pulse start circuit is a high-side pulse start circuit having a first resistor R and a first attenuation capacitor, and further comprises: The low-side pulse start-up circuit includes: An NMOS transistor has a source connected to a common terminal of the circuit and a drain connected to the Vm node via a second resistor R, wherein the second resistor R is significantly larger than the slot impedance. The second attenuation capacitor is connected in parallel with the second resistor R to the drain. The NMOS transistor includes a control terminal coupled to receive a jump start pulse to initiate a pulse signal.

17. The method of claim 15, wherein the attenuation capacitor attenuates the oscillation frequency without affecting the pulse signal initiated by the jump start pulse.

18. The method of claim 15, wherein the duration of the sudden-start pulse is in the range of 1 ns.

19. The method of claim 15, wherein the pulse communication is based on on-off keying (OOK) and edge encoding.

20. The method of claim 15, wherein the transmitter oscillator is used in a digital isolator.

Images