Memory storage system and method performed thereby

Abstract

A method performed by a controller includes assigning a first state indicator to entries in a first address line in volatile memory belonging to a first region of a LUT stored in non-volatile memory and assigning a second state indicator to entries in the first address line in the volatile memory belonging to a second region of the LUT; setting the first or second state indicator to a dirty state based on whether a cache update entry at address m in the volatile memory belongs to the first region or the second region of the LUT; and writing all entries in the volatile memory associated with the first region or the second region containing the update entry to the non-volatile memory based on the dirty state of the first and second state indicators at the address m.

Description

Technical Field

[0001] This disclosure relates to solid-state drives (SSDs) and methods that enhance dirty information in cache lines to efficiently update logical-to-physical (L2P) addressing and thus enhance SSD performance. Background Technology

[0002] Solid-state drives (SSDs) typically offer faster performance, are more compact, and are less sensitive to vibration or physical shock compared to conventional hard disk drives. Given these advantages, SSDs are increasingly used as a replacement or complement to hard disk drives in computing devices and other consumer products, even though the cost per gigabyte of storage capacity for SSDs is significantly higher than that of hard disk drives. SSDs utilize physical memory cells, including non-volatile semiconductor storage devices (such as NAND flash memory devices), to store data. A controller within the SSD manages data transfer between the host and the SSD's memory cells. Writing data to and reading data from the SSD's physical memory cells typically involves transferring data between the host and the non-volatile semiconductor storage devices, external to the SSD.

[0003] SSDs experience large data flows when receiving multiple read and write requests from the host. These host requests take the form of commands containing logical address information (such as logical block addresses (LBAs) and namespace identifiers (NSIDs)). The SSD translates this logical address information into physical addresses in the non-volatile semiconductor memory (NAND memory page addresses). The SSD uses an access lookup table (LUT) to translate the logical addresses in the host commands into physical addresses in the NAND memory. The LUT maps logical addresses in the namespace to physical addresses in the NAND memory. The SSD then uses the physical addresses to fulfill the requests (e.g., reading data from the NAND memory). Typically, LUTs are very large (approximately 1 / 1000th of the SSD's capacity) and stored in the NAND memory. To enable the SSD to translate logical addresses into physical addresses when processing host requests, the LUT is loaded into the volatile memory within the SSD for fast access.

[0004] Read and write commands from the host and internal processing within the SSD (such as scrap collection) can cause address changes stored in the LUT. The SSD cache updates the LUT in volatile memory during the processing of host requests. These updates are then periodically stored in non-volatile semiconductor memory (NSM) so that LUT changes are preserved before power loss from the volatile memory. However, due to the large size of the LUT, such updates can increase SSD latency by writing large amounts of data from volatile to NSM. Furthermore, if such updates are not stored in NSM before power loss, the updated address information will be lost, leading to SSD errors and potential failure. This presents a challenge in efficiently managing updates to the logical-to-physical LUT in NSM. Summary of the Invention

[0005] According to embodiments of this disclosure, a memory storage system is provided, comprising a non-volatile semiconductor memory device configured to store lookup tables (LUTs) including entries grouped into at least one first region and at least one second region. The memory storage system further includes a volatile semiconductor memory device configured to temporarily store the entries from the LUTs of the non-volatile semiconductor memory device. Furthermore, the memory storage system includes a controller configured to store and retrieve data in the non-volatile semiconductor memory device in response to a command received from a host outside the memory storage system. The controller includes a cache comprising a plurality of cache lines communicatively coupled to the volatile semiconductor memory device and configured to temporarily store entries read from address m of a plurality of addresses of the volatile semiconductor memory device in cache line z of the plurality of cache lines.

[0006] The controller is configured to assign a first status indicator and a second status indicator to each of the plurality of cache lines in the cache corresponding to a plurality of cache addresses of the volatile semiconductor memory device, wherein the first status indicator corresponds to an entry of the first cache address of the volatile semiconductor memory device belonging to the first region of the LUT, and the second status indicator corresponds to an entry of the first cache address of the volatile semiconductor memory device belonging to the second region of the LUT. The controller is also configured to update the LUT entry at address m in the volatile semiconductor memory device read from cache line z of the cache. Additionally, the controller is configured to set either the first status indicator or the second status indicator to a dirty state based on whether the updated entry in cache line z read from address m is in the corresponding first region or second region of the LUT. Furthermore, the controller is configured to copy all entries in the volatile semiconductor memory device associated with the first or second region containing the updated entries to the non-volatile semiconductor memory device based on the dirty state of the first or second status indicator of the cache line z.

[0007] According to another embodiment of this disclosure, a method is provided executed by a controller of a memory storage system, the memory storage system including a non-volatile semiconductor memory device configured to store lookup tables (LUTs) comprising entries grouped into at least one first region and at least one second region. The memory storage system also includes a volatile semiconductor memory device configured to temporarily store the entries from the LUTs of the non-volatile semiconductor memory device. Furthermore, the memory system includes a cache comprising a plurality of cache lines communicatively coupled to the volatile semiconductor memory device and configured to temporarily store entries read from addresses m of a plurality of address lines of the volatile semiconductor memory device in cache line z of the plurality of cache lines.

[0008] The method includes assigning a first status indicator and a second status indicator to each of a plurality of cache lines in a cache corresponding to a plurality of cache addresses of the volatile semiconductor memory device, wherein the first status indicator is assigned to an entry of the first cache address of the volatile semiconductor memory device belonging to a first region of the LUT, and the second status indicator is assigned to an entry of the first cache address of the volatile semiconductor memory device belonging to a second region of the LUT. The method further includes updating the entry of the LUT at address m in the volatile semiconductor memory device read from cache line z of the cache. Additionally, the method includes setting the first status indicator or the second status indicator to a dirty state based on whether the updated entry in cache line z read from address m is in the corresponding first region or second region of the LUT. Furthermore, the method includes copying all entries in the volatile semiconductor memory device associated with the first region or second region containing the updated entry to the non-volatile semiconductor memory device based on the dirty state of the first status indicator or the second status indicator of cache line z.

[0009] In some embodiments, the controller is further configured to read the entry of the LUT at address m into cache line z and write the cache line z back to address m of the volatile semiconductor memory device. In some embodiments, the controller is configured to update only one entry of the LUT in the cache at a time. In other embodiments, the controller is configured to repeatedly update the entry of the LUT in the volatile semiconductor memory device via the cache based on commands received from the host.

[0010] In some embodiments, the LUT maps a logical cluster address (LCA) to a media cluster address (MCA) in the non-volatile semiconductor memory device. In another embodiment, the non-volatile semiconductor memory device is configured to store a second LUT that maps an index associated with each of the at least one first region and the at least one second region to a media cluster address (MCA) in the non-volatile semiconductor memory device. In other embodiments, the controller is configured to access the second LUT to determine the starting MCA address of the region containing the updated entry in the non-volatile semiconductor memory device. In some embodiments, the controller is configured to copy the LUT from the non-volatile semiconductor memory device to the volatile semiconductor memory device upon first startup of the memory storage system.

[0011] In another embodiment, the first and second status indicators each include one bit. In another embodiment, each bit of the LUT entry at address m is set to a clean state before being updated in the cache. In some embodiments, the controller sets the bit to '0' for the clean state and '1' for the dirty state. In some embodiments, the cache includes a write-back cache. In some embodiments, the cache is formed in a portion of the volatile semiconductor memory device. In other embodiments, the non-volatile semiconductor memory device is NAND semiconductor memory. In another embodiment, the non-volatile semiconductor memory device is dynamic random access memory (DRAM). In some embodiments, the cache includes static random access memory (SRAM). In some embodiments, the controller includes a system-on-chip (SoC) controller. In other embodiments, at least a portion of the volatile semiconductor memory device is external to the SoC controller. Attached Figure Description

[0012] The foregoing and other objectives and advantages will become clear from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals refer to all like parts, and wherein:

[0013] Figure 1 A schematic diagram illustrating an SSD configured according to one or more embodiments of the present disclosure;

[0014] Figure 2 This describes the interaction between the host and the controller when an SSD processes commands acting on a non-volatile semiconductor memory device according to one or more embodiments of the present disclosure;

[0015] Figure 3 This describes the interaction between the host and the controller when the Logical Cluster Address (LCA) to Media Cluster Address (MCA) lookup table (LUT) according to one or more embodiments of this disclosure is initially stored in a non-volatile memory device;

[0016] Figure 4 This describes an exemplary LCA-MCA LUT arranged in NAND memory and reconfigured in DRAM according to one or more embodiments of the present disclosure;

[0017] Figure 5A This describes an instance of using a single dirty bit as a cache notification to update a single entry in a LUT according to one or more embodiments of this disclosure, and Figure 5B This describes an instance of using a pair of dirty bits as cache notification to update a single entry in a LUT according to one or more embodiments of this disclosure; and

[0018] Figure 6 This is a flowchart of a method for updating an LCA-MCA LUT stored in a non-volatile semiconductor memory device, according to one or more embodiments of the present disclosure. Detailed Implementation

[0019] To provide a full understanding of the apparatus described herein, certain illustrative embodiments will be described. Although the embodiments and features described herein are specifically described in conjunction with an SSD having a controller, it should be understood that all components and other features outlined below can be combined with each other in any suitable manner and can be adapted and applied to other types of SSD architectures with similar needs for efficiently updating lookup tables stored in the semiconductor storage device of the SSD when processing commands from a host.

[0020] To date, the non-volatile memory of SSDs (such as NAND flash memory devices) stores the Logical Cluster Address (LCA) to Media Cluster Address (MCA) LUT in zero-indexed areas (often referred to as even and odd areas). Each entry in the LUT contains the MCA corresponding to the translation between the LCA and MCA, and when data at the LCA is overwritten by the host with new data, the new data is written to the new MCA, thus requiring an update to the corresponding LUT entry. During host command processing, the SSD controller loads the LCA-MCA LUT stored in the non-volatile memory of the SSD into the volatile memory of the SSD (such as Dynamic Random Access Memory (DRAM)) for fast access by cache (such as Static Random Access Memory (SRAM)). Each read access to the LCA-MCA LUT in volatile memory includes a DRAM burst of data temporarily stored in a cache line. Each cache line corresponds to the data value of the DRAM burst read from the DRAM address. The cache is used as a write-back cache, where updates are applied to LUT entries in the cache line, and the entire cache line is then written back to the DRAM address associated with the cache line upon its first read from DRAM memory. After being updated by the controller, updates to the entries in the LCA-MCA LUTs in DRAM are then flushed back to NAND memory, making the updated LCA-MCALUTs available when the SSD is powered off (where DRAM and SRAM lose data). To limit the amount of data flushed per update, flushing can be performed per region, where a region consisting of a group of 32, 64, or 128 LUT entries (configurable and depending on the total storage size of the SSD) is flushed at any given time. During the flushing of data from DRAM to NAND memory, the entire region containing the updates is copied to NAND memory for faster updates.

[0021] However, the amount of data transferred between the DRAM and SSD controllers must always be a full DRAM burst (which depends on the DRAM data bus width and DRAM data bus burst length), so that cache lines are arranged to align with the DRAM burst boundaries. The LCA-MCA LUT is a huge table (typically gigabytes in size), and each entry (MCA) can be a number of bits suitable for word-aligned memory (e.g., odd or non-powers of 2) (depending on the SSD capacity, e.g., 33 bits for a 16 TB SSD), with additional ECC bits added per DRAM burst to pack LUT entries as tightly as possible to save DRAM. This means that individual MCA entries will typically be within a single DRAM burst, but MCA entries can also span two DRAM bursts. This results in cache lines spanning even-numbered LUT regions, odd-numbered LUT regions, or both. The controller associates individual bits with each cache line to track updates to the LCA-MCA LUT entries. The LCA-MCA LUT contained in DRAM is copied to the cache in the DRAM burst for updates by the cache during host command processing. This DRAM burst copies a single DRAM burst to the cache line and then to the SRAM at any given time. The LCA-MCA LUT data in the cache line is updated and subsequently written back to DRAM. A single bit is set to dirty when the information contained in the cache line changes based on any changes in the mapping of LCA to MCA by the SSD controller. For example, a single bit is set to '1' when an entry in the LCA-MCA LUT data contained in the cache line changes.

[0022] However, due to the accumulation of LUT entries in DRAM, cache lines can exist that span two adjacent LUT regions. In this situation, when one region has an update while the adjacent region does not, a single dirty bit from the cache line is insufficient to identify which of the two regions contains the update. Therefore, both regions will need to be flushed to NAND, and since each region includes multiple entries, when only one of the two regions contains updated information, the controller unnecessarily copies data from all entries in that region from DRAM back to NAND memory during DRAM flushing. This results in a waste of SSD controller resources, DRAM bandwidth, and NAND memory bandwidth. This unnecessary large amount of data transfer across two LUT regions also increases the number of program / erase (P / E) cycles on NAND, which shortens the expected lifespan of NAND and leads to an increase in memory errors associated with shortened lifespan.

[0023] This disclosure describes systems and methods for mitigating this problem and improving the efficiency of updating LCA-MCA LUTs in SSDs. This disclosure also describes a controller implementation for enhancing the indication of dirty information via cache memory. This enhancement is provided by explicitly identifying the LUT region where an update has occurred using two or more information bits per cache line of the cache memory. Regarding this enhancement, cache lines spanning two adjacent LUT regions are explicitly marked such that only the updated LUT region is included in the refresh of the NAND memory.

[0024] Figure 1 This is a block diagram of a computing system 100 including at least one host 110 communicating with a solid-state device (SSD) 120, according to embodiments of the present disclosure. The host 110 includes a processor or core, a controller, memory, and other components generally known in the art, and for simplicity... Figure 1 The computing system includes other components not shown in the diagram. SSD 120 provides non-volatile storage functionality for use by host 110. SSD 120 may contain an integrated circuit including a controller. This integrated circuit may also be referred to as a System-on-Chip (SoC) controller 130. SoC is advantageous in SSDs because it provides a single integrated circuit containing all the necessary circuitry and electronics required for SSD operation. SoC therefore eliminates the need for a modular, discrete component architecture connected by multiple buses and buffers.

[0025] The SoC controller 130 is communicatively coupled to a memory array of a non-volatile semiconductor-based memory device 140 (e.g., a NAND-based flash memory device) serving as the storage medium. The storage medium may include multiple NAND devices, such as (for example) 32, 64, 128, or 256 individual NAND devices, each capable of running individual commands on its individual die (not shown). As an example, a memory array 140 comprising n NAND devices, each with d dies, can serve up to (n×d) commands from the SoC controller 130 at any given time, where n and d are integers greater than zero. The SSD 120 also includes volatile memory external to the SoC controller 130, such as dynamic random access memory (“DRAM”) 150. The DRAM 150 includes several buffers (not shown) for buffering data during read and write operations between the host 110 and the memory device 140 after receiving commands from the host 110.

[0026] Volatile memory is used in conjunction with a controller because it is fast and responsive. However, the contents stored in volatile memory are lost when power is off. Volatile memory is also expensive and thus increases the overall cost of an SSD. In some implementations, all or part of the external memory DRAM 150 may reside within the SoC controller 130. When located within the SoC controller 130, at least a portion of the external memory may be implemented using fast memory technologies, such as static random access memory (SRAM). In some implementations, the portion of the DRAM located within the SoC 130 may be implemented as a cache 135, as described below. In some implementations, the cache 135 includes a write-back cache. In other implementations, all or part of the external memory may be implemented using fast non-volatile memory technologies, including (but not limited to) magnetic random access memory (MRAM), resistive random access memory (ReRAM), or phase-change memory (PCM).

[0027] The SoC controller 130 includes a host interface 122 capable of communicating with the host 110 to receive commands such as (for example) read and write requests. The SoC controller 130 also includes a communication interface 122 for communicating with the storage element 140 (via multiple channels, for example...) Figure 1 The diagram shows NAND channels CH1, CH2, ..., CHn (where n is an integer), a NAND interface 124, and a memory interface 126 for communicating with memory 150 external to the SoC. For example, the host interface 122 on the SoC 130 may include interfaces with... Serial Advanced Technology Attached (SATA) connectors or NVMe connectors that operate together with the PCIe (Peripheral Component Interface High Speed, hereinafter referred to as PCIe) bus. TM Connector (NVMe) TM It is an abbreviation for "NVM High Speed," where "NVM" stands for Non-Volatile Memory (hereinafter referred to as NVMe). For example, NAND interface 124 may include an Open NAND Flash Interface (ONFI), a Switchable NAND Interface, or a manufacturer's proprietary interface. Memory interface 126 may include, for example, interfaces according to (but not limited to) the following: Double Data Rate (DDR) memory bus standards, such as DDR3, DDR4, or DDR5; Low Power Double Data Rate (LPDDR) memory bus standards, such as LPDDR3, LPDDR4, or LPDDR5; Hybrid Memory Cube (HMC) memory bus standards.

[0028] The SoC controller 130 may include various internal sub-controllers, such as an NVMe controller 132 coupled to the host interface 122, a memory controller 136 coupled to the memory interface 126 via a cache 135, and a NAND controller 138 coupled to the NAND interface 124. The NVMe controller 132 may be configured according to NVM Express, released on June 10, 2019. TM The basic specification (version 1.4) (hereinafter referred to as "NVMe 1.4") operates. The NVMe controller 132, L2P engine 134, NAND controller 138, and memory controller 136 are interconnected via a common bus and are configured by the SoC controller 130, which controls and configures the data operations and transfers between these controllers 132, 136, and 138 (control and configuration functions not shown). The memory controller 136 is connected to the DRAM 150 via the memory interface 126. The memory controller 136 is also coupled to the NVMe controller 132, the NAND controller 138, and the L2P engine via the cache 135. The NAND controller 138 is connected to the NAND interface 124 to communicate with the storage element 140, such as... Figure 1 As shown in the diagram. Therefore, any interaction between DRAM 150 and NAND storage element 140 occurs via memory interface 126, cache 135, memory controller 136, NAND controller 138, and NAND interface 124. Additionally, memory controller 136 communicates with NVMe controller 132 and logic-to-physical (L2P) engine 134, such as... Figure 1 As shown in the diagram and described below. In some implementations, the L2P engine 134 is also implemented in the control and configuration functions of the SoC controller 130.

[0029] Control and configuration functions may include programmable application-specific integrated circuit (ASIC) logic, programmable firmware running on one or more processors, or a combination of both. Control and configuration functions may include a logic-to-physical (L2P) engine 134, which translates logical address information specified in commands received from host 110 into physical address information associated with NAND memory 140. Control and configuration functions may include a flash translation layer, which enables SoC controller 130 to perform various activities that facilitate the processing of read and write commands received from host 110. One such activity may involve orchestrating the data flow of commands between NVMe controller 132 and NAND controller 138.

[0030] Once the NVMe controller 132 receives a command from the host 110, such as a read command or a write command, the L2P engine 134 in the control and configuration function maps the logical block address contained in the host command to a physical NAND address. The L2P engine 134 may use a lookup table contained in the cache 135 and / or DRAM 150 to obtain the required NAND address. These NAND addresses are then used in NAND commands based on host commands received by the firmware or generated internally, which are sent to the NAND controller 138. The NAND controller 138 then uses the NAND addresses to perform actions or functions on the memory device 140, as defined by the host or internal commands. For example, if the host command is a read command, then the NAND controller 138 retrieves data from the specified NAND address in the memory 140, where multiple NAND read commands may be issued to the NAND controller 138 to retrieve data. As another example, if the host command is a write command, then the NAND controller 138, upon receiving a NAND write command based on a host write command, causes host data to be written from the host 110 and / or DRAM 150 to a specified NAND address in the memory 140. In yet another example, obsolete item collection activities can be performed internally by control and configuration functions within the SoC controller 130, causing multiple read, write, and erase NAND commands to be issued to the NAND controller 138 to perform obsolete item collection functions.

[0031] Figure 2 This describes the interaction between host 110 and SSD 120 according to an embodiment of this disclosure. Host 110 is configured to run multiple applications, such as... Figure 2Examples of applications A and B are shown below. Applications running on host 110 generate commands that cause SSD 120 to access data stored in NAND memory 140. These commands can be read or write commands. To access a specific portion of NAND memory 140, the host command contains addressing information used by SSD 120 to provide a request from host 110. The addressing information provided by host 110 is about a logical namespace and includes a namespace identifier (NSID) and a logical block address (LBA) within that namespace. Host 110 sends the logical addressing information to SSD 120 via a host commit queue. Host 110 may use a separate commit queue for each application. When a host command is received by SSD 120, SoC controller 130 maps the namespace-based addressing information (NSID, LBA) to a linear logical cluster address (LCA). While multiple individual applications may interact with the individual namespaces and LBAs of said applications, the mapping is performed by the SoC controller 130, which combines each NSID, LBA addressing information into a single LCA value indexed to a common address space. This mapping is performed by... Figure 1 The L2P engine 134 shown in the diagram performs the following: In some implementations, mapping from LBA to LCA is performed algorithmically using predefined formulas and / or lookup tables. In some implementations, the mapping is updated when a namespace is created, deleted, or its size changes.

[0032] After the LCA is determined, the L2P engine 134 maps the LCA to a physical location in the NAND memory 140. Each physical location in the NAND memory 140 is defined by a Media Cluster Address (MCA). The length of the MCA depends on the capacity of the SSD 120 (e.g., 33 bits for a 16 TB SSD). Data can be stored in the NAND memory array 140 in any particular order, and therefore there can be no predetermined or algorithmic relationship between the LCA and MCA in the SSD 120. Mapping the LCA to the MCA is therefore done by accessing a lookup table (LUT) stored in the DRAM 150, but the mapping is not fixed and can be changed by updating the entries in the LUT. The LUT stored in the DRAM 150 is a working copy of the master LUT stored in the NAND memory array 140. The LCA is used to index into the LUT to find the MCA entry, and for efficiency, there is a fixed arithmetic method for quickly deriving the index of the entry in the LUT from the LCA, which implies that the entries preferably have a common size. However, the common size value can vary depending on the storage size of the NAND memory array 140. In some implementations, the LUT is very large and can be approximately 1 / 1000th the size of the NAND memory 140. The entries for each LUT region in the DRAM 150 are arranged sequentially according to the LCA, but the LUT regions themselves do not need to be sequential. Processing of write commands from the host 110 that can overwrite existing data and internal processing within the SSD 120, such as scrap collection, can lead to the need to reallocate data stored in the NAND memory 140. This reallocation of data can cause a change in the MCA address associated with the LCA in the host command, thereby causing the LUT in the DRAM 150 to be frequently updated during the operation of the SSD 120. The LUT is therefore continuously updated as host commands or activities such as scrap collection are processed by the SSD 120.

[0033] However, since DRAM 150 is volatile memory, its contents are lost when power to SSD 120 is removed (e.g., when SSD 120 is powered off). This is disadvantageous because the LUT will no longer be usable for mapping the LCA address received from the host to the physical MCA address within NAND memory 140, leading to errors when processing host commands. Furthermore, due to the large size of the LUT in DRAM 150, copying the entire LUT to another part of SSD 120 (e.g., copying the portion to NAND memory 140) cannot be completed within the short time between the power loss of SSD 120 and the loss of data from DRAM 150.

[0034] According to embodiments of this disclosure, an SSD 120 is provided in which the LUT is initially stored in a portion of NAND memory 140, which is a non-volatile memory that retains data even when power is off. The LUT in NAND memory 140 is then loaded or copied to DRAM 150 at boot time for fast access by SoC 130 (specifically, L2P engine 134 and cache 135) during host command processing. Thus, the copy of the LUT in NAND memory is the original, and the LUT in DRAM is a working copy. In some embodiments, multiple originals of the LUT may exist in the NAND to prevent errors or failures in the NAND die or device. Additionally, according to another embodiment of this disclosure, since entries in the working copy of the LUT in DRAM 150 are updated when the SoC controller 130 processes host commands or internal commands (e.g., generated via an internal discarded item collection process), the updated entries in the LUT are refreshed from the LUT in DRAM 150 or copied to the original (or several originals) of the LUT in NAND memory 140 to replace their original values ​​at some point after the update in DRAM 150 occurs. This ensures that the original (or several originals) of the LUT stored in NAND memory 140 contains the most recent and up-to-date data mapping from LCA to MCA in SSD 120. In this way, if a power outage event occurs (e.g., due to power cut-off or failure), the most recently updated LUT in NAND memory 140 can be used to initialize DRAM 150 when SSD 120 is restarted. In some implementations, when a power outage event is detected, a backup power source (e.g., a supercapacitor or battery) provides sufficient power to ensure that any updates to components (or components) not yet refreshed from the LUT in DRAM 150 to the NAND memory are included in the final refresh from DRAM 150 to NAND memory 140 before the SSD is slowly shut down. According to yet another embodiment of this disclosure, the LUT update from DRAM 150 to NAND memory 140 is enhanced and optimized so that only the regions of the LUT containing the actual updated entries are copied from DRAM 150 to NAND memory 140. This improves the efficiency of SSD 120 because no DRAM or NAND memory bandwidth is wasted, as no unnecessary data is included in the refresh from DRAM 150 to NAND memory 140 (or in the final refresh from DRAM 150 to NAND memory 140 in the event of a power outage). This also reduces the number of program / erase (P / E) cycles performed by NAND memory 140, thereby extending its lifespan.

[0035] Figure 3 illustrate Figure 1 The interaction between host 110 and SSD 120. To be more specific... Figure 3The internal data flow within SSD 120 is shown after host 110 issues a command. As previously described, host 110 issues a command (e.g., a read command or a write command) to SSD 120 to access NAND memory 140 and the data contained therein. The host command includes at least one NSID and LBA. After receiving logical addressing information (NSID, LBA) from host 110, SoC controller 130 converts the NSID and LBA combination into LCA. This conversion can be performed by L2P engine 134 using an algorithm. L2P engine 134 uses the LCA indexed into an LCA-MCA LUT to generate an MCA within NAND memory 140 targeted by host 110 (used to write data to NAND memory 140 in the case of a host write command or to retrieve data from NAND memory 140 in the case of a host read command).

[0036] The LCA-MCA LUT is a large table and is stored in DRAM 150 for fast access by the SoC controller 130. According to embodiments of this disclosure, the LCA-MCA LUT 310 is initially stored in a portion 320 of NAND memory 140, such as... Figure 3 As shown in the diagram. During SSD 120 boot, LUT 310 is loaded into DRAM 150. Because the LUT in NAND memory 140 is not aligned with the DRAM burst boundary (DRAM 150 has a shorter linewidth than NAND memory 140), LUT 310 can be rearranged into LUT 330 with different memory cells (i.e., NAND memory page to DRAM burst length) when loaded into DRAM 150. LUT 330 in DRAM 150 may also be stacked differently from LUT 310 in NAND memory 140. It should be noted that the LCA and MCA LUT entries in LUT 310 and LUT 330 are identical during the initial load from NAND memory 140 to DRAM 150, and the original entry for LUT 310 has just been rearranged into LUT 330. Once LUT 330 is loaded into DRAM 150, SoC controller 130 triggers a DRAM burst with its processing commands (host commands or internally generated commands). Each DRAM burst causes the data value of an entire cache line in DRAM 150 to be read into cache 135. This is because all accesses to the LCA-MCA mapping defined in LUT 310 are performed via cache 135 to ensure the coherence of the LCA-MCA mapping in LUT 310. It should be understood that the cache line boundaries of cache 135 are aligned with the boundaries of the smallest data burst of DRAM 150 (at 64 bytes in DDR5 technology) and therefore there is no need to reconfigure LUT entries between DRAM 150 and cache 135. Figure 3 As shown, LUT entry 340 stored at address 150 (e.g., at address m, where m is an integer in units of DRAM burst size) is read as a DRAM burst into cache 135 (as cache line 345) after SoC controller 130 triggers a DRAM burst.

[0037] Next, the LUT entries in cache 135 are read by L2P engine 134 to convert LCA to MCA during command processing. As previously described, host commands processed by SoC controller 130 can cause data to be allocated / redistributed to locations in NAND memory 140. Typically, this will occur with write commands, but in the case of read commands, it is usually only necessary to read the LCA to the MCA table. In some cases, reads can cause exceeding NAND memory read interference limits, where memory pages need to be flushed (rewritten to different locations), but this usually occurs as a separate background activity performed by the control and configuration functions of SoC controller 130. Allocation / redistribution can cause data in NAND memory to be rearranged and thus update / insert / delete entries to / from the original LCA-MCA LUT 310. Additionally, SoC controller 130 can also process internal commands (e.g., internal commands for discarded item collection) that move valid data stored in NAND memory from one location to another. This causes resources within NAND memory 140 to be deallocated and subsequently reallocated, thus updating at least one entry in the original LCA-MCA LUT 310. Since cache 135 is a write-back cache, such updates are first written to cache line 345 in cache 130 by the L2P engine 134 of the SoC controller 130. It should be noted that the L2P engine 134 updates only one LCA-MCA entry in cache 135 at any given time. The L2P engine also includes some sideband information accompanying each update to indicate the location of the update in LUT entry 340. After the L2P engine 134 writes to the cache, a DRAM burst write occurs to address m in DRAM (from which the LUT entry in cache line 345 originates). The SoC controller 130 is notified of the existence of the updated entry at address m in DRAM and, in conjunction with the sideband information, determines the starting address of the MCA of the LUT region in the updated original LUT 310. In some implementations, this can be done via a second LUT stored in NAND memory 140 that maps the LUT region index to the MCA start address. Then, SoC controller 130 triggers a refresh of the LUT region from LUT 330 in DRAM 150 to LUT 310 in NAND memory 140, where the original LCA-MCA entry is stored. Although Figure 3 A double arrow is shown between DRAM 150 and NAND memory 140, but it should be noted that any interaction between DRAM 150 and NAND memory 140 occurs via memory interface 126, memory controller 136, NAND controller 138 and NAND interface 124.

[0038] Figure 4 The arrangement of LCA-MCA LUT 310 and LCA-MCA LUT 330 stored in portion 320 of NAND memory 140 and DRAM 150, respectively, is described. Figure 4 Data from several cache lines 345 contained in cache 135 with updated entries A, B, C, and D containing LCA-MCA LUT 330 is also shown. It should be noted that each of the cache lines 345 will be read individually from cache 135 back to DRAM 150. Figure 4 In this implementation, the regions of LUT 310 are alternately referred to as 'even' regions and 'odd' regions, each incrementing / decrementing from index n, where n is an integer. In some implementations, each region of LUT 310 includes 64 LCA-MCA entries. As previously described, the LCA-MCA LUT 310 is initially stored in portion 320 of NAND memory 140 and loaded or copied to DRAM 150 at boot time. When LUT 310 is copied to DRAM 150, a reallocation occurs due to misalignment between the DRAM burst boundary and NAND memory 140 (the DRAM burst size of DRAM 150 can be much smaller than the memory page size of NAND memory 140, e.g., 64 bytes versus 16 kilobytes). Additionally, different types of ECC may exist, with different numbers of ECC bits used with the LUT entries in NAND memory 140 and DRAM 150. The reconfiguration of LUT 310 results in LUT 330 in DRAM 150, where LUT regions are stacked to form the DRAM burst alignment frame of DRAM 150. This results in some DRAM address lines having LUT entries from both regions, such as DRAM address m in the middle of the address lines, where the 'odd' region n ends and the 'even' region n+1 begins, as shown. Figure 4 It is displayed in the middle.

[0039] Once DRAM 150 receives an updated LUT entry from cache 135, SoC controller 130 refreshes the area in LUT 330 containing the updated LUT entry to NAND memory 140, allowing LUT 310 to be updated with new LCA-MCA addressing information. It is important for SoC controller 130 to identify specific locations within DRAM 150 containing updates so that only the updated areas are refreshed. According to embodiments of this disclosure, sideband information including two dirty bits is assigned to each cache line 345 by the cache controller (not shown) of cache 135. The dirty bits themselves may not be stored in DRAM 150. The two dirty bits are used to identify the LUT area within cache line 345 where the update occurred. One dirty bit is assigned as an even dirty bit and the other as an odd dirty bit. When an update occurs, the dirty bit is set to a dirty state or '1' to indicate to the cache controller of cache 135 that the corresponding (odd or even) LUT area contains updated information. Each dirty bit is independent, but if an update occurs on cache line 345 (which spans two LUT area changes (one odd and one even), altering the data in both the odd and even LUT areas associated with cache line 345), then both the odd and even dirty bits are set to dirty or '1'. If no update occurs, the dirty bit remains clean or '0' to indicate to the SoC controller 130 that no update exists in the corresponding (odd or even) LUT area. It should be noted that with each data burst read from DRAM 150 into the cache, the dirty bit is initially set to clean or '0' before any LUT entry in cache line 345 is updated and written to cache 135.

[0040] For example, Figure 4 The LUT 330 in the DRAM 150 shown has four updated entries A, B, C, and D from cache 135. It should be noted that each of these updates has been individually written to cache 135 and written back to DRAM 150 as a result of commands processed by SoC controller 130. Updated entries A, B, C, and D have accumulated since the last refresh of NAND memory 140. Update A occurred in the entry at DRAM address m-2 in the 'odd' region n. Updates B and C both occurred at DRAM address m, where update B is in the 'even' LUT region n+1 and update C is in the 'odd' LUT region n. Update D occurred at DRAM address m+1 in the 'even' LUT region n+1. Therefore, the dirty bits of cache lines 345 written back to DRAM addresses m-2, m, and m+1 are set to '01', '11', and '10' respectively. Figure 4As shown in the diagram. Following instructions from the SoC controller 130, a region containing entries in the LUT 330 with a dirty bit set to '1' is copied to the NAND memory 140. Figure 4 In the example shown, the 'odd' region n and the 'even' region n+1 are copied to replace the corresponding entries in the LUT 310 stored in the NAND memory 140. In both regions n and n+1, the corresponding dirty bits are set to '1', as shown below. Figure 4 As shown in the diagram. It should be understood that the LUT 310 in NAND memory 140 is updated as updates from DRAM 150 become available, and the LCA-MCA entries stored in the LUT 310 in NAND memory 140 are not arranged in any order. In the case of an update to one of the regions, the use of two dirty bits enhances the process of updating the LUT 310 in NAND memory 140, as will be discussed regarding... Figure 5A and 5B describe.

[0041] Figure 5A and 5B This describes the arrangement of LCA-MCA LUT 310 and LCA-MCA LUT 330, stored in portions 320 of NAND memory 140 and DRAM 150, respectively. In LUT 330, only one entry E has been updated in cache 150. The updated entry E belongs to the 'odd' region n and is stored at address m in DRAM 150. However, address m in DRAM 150 also stores an LCA-MCA LUT entry belonging to the 'even' region n+1. This... Figure 5A and 5B As shown in the image, horizontal address m in DRAM 150 contains light and dark gray shaded areas. Figure 5A In this process, the L2P engine 134 of the SoC controller 130 assigns a single dirty bit as sideband information to each corresponding cache line 345. Therefore, after an update in cache 135, the dirty bit assigned to the cache line 345 corresponding to address m of DRAM 150 containing the updated LCA-MCA LUT entry E is set to dirty state '1', and the cache line data is copied to address m of DRAM 150. When this occurs, the SoC controller 130 scans the dirty bits of each address line in DRAM 150 and identifies the dirty bits set to dirty state and the corresponding one or more LUT regions to be refreshed. Then, the SoC controller 130 triggers one or more LUT regions to be refreshed from DRAM 150 to NAND memory 140.

[0042] exist Figure 5AIn the example shown, the SoC controller 130 identifies address m as having its dirty bit set to '1', indicating the presence of an updated entry E. However, address m of DRAM 150 contains entries belonging to both 'even' region n+1 and 'odd' region n. A single dirty bit only identifies DRAM address lines containing updated entries, but this indication lacks granularity and doesn't provide information about whether the update in address m belongs to region n+1 or region n. This information is important because the LUT 310 stored in NAND memory 140 is updated based on regions in NAND memory 140, not individual addresses of DRAM 150. Therefore, the SoC controller 130 sets the dirty bits for regions n and n+1 to '1'. Then, the SoC controller 130 flushes the LUT entries belonging to both regions n and n+1 to NAND memory 140. Figure 5A As can be seen, refreshing the LUT entries in region n+1 is unnecessary because it does not contain updated information. However, assigning only a single dirty bit as sideband information to each cache line 345 by the L2P engine 134 does not provide the SoC controller 130 with enough information to decipher which of region n, region n+1, or both contain updated information. This unnecessary transfer of information wastes DRAM bandwidth, wastes NAND memory bandwidth, and increases the P / E cycle count on the NAND memory 140.

[0043] According to embodiments of this disclosure, the L2P engine 134 assigns two dirty bits as sideband information to each cache line 345, such as... Figure 5B The following example illustrates this. After an update in cache 135, the dirty bits in cache line 345 associated with address m of DRAM 150 containing the updated LCA-MCALUT entry E in 'odd' region n are set to '01'. The state of these dirty bits indicates that address m of DRAM 150 does not contain an updated entry in 'even' region n+1 and does contain an updated entry (E) in 'odd' region n. Therefore, SoC controller 130 sets the dirty bit of region n to '1' and keeps the dirty bit of region n+1 at '0'. SoC controller 130 is notified that an updated entry exists only at DRAM address m in 'odd' region n and determines the MCA start address of LUT region n in NAND memory 140. In some embodiments, this may be done via a second LUT stored in NAND memory 140 that maps each LUT region index (e.g., index n-1, n, n+1) to the MCA start address in NAND memory 140. Next, the SoC controller 130 refreshes the LUT entries that belong only to region n to the NAND memory 140.

[0044] As from Figure 5A and 5BIt is clear that the increased granularity provided by the two dirty bits enables the SoC controller to explicitly identify LUT regions containing updated entries, thereby causing only the LUT entries in the relevant regions to be flushed to the NAND memory 140. This increases DRAM bandwidth, increases NAND memory bandwidth, and reduces the P / E cycle number on the NAND memory 140, thereby saving resources and enhancing the performance of the SSD 120.

[0045] Figure 6 This illustration provides an exemplary flowchart of a method 600 for updating a LUT stored in NAND memory according to embodiments of the present disclosure. The method can be implemented using an SSD 120 as described above. The LUT may include an LCA-MCA LUT. Method 600 assumes that the LCA-MCA LUT, initially stored in non-volatile memory (e.g., NAND memory 140), has been copied to volatile memory, such as DRAM 150, at boot time of the SSD 120. The DRAM burst size may differ from the NAND flash memory page size of NAND memory 140 and may include a different number of ECC bits when data is stored in DRAM 150 or NAND memory 140, causing the LUT to be reconfigured when it is loaded from NAND memory 140 to DRAM 150. This results in DRAM addresses spanning even-numbered LUT regions and odd-numbered LUT regions, or both, as described above. Figure 3 and 4 It is displayed in the middle.

[0046] Method 600 for updating the LUT begins at step 610, where a DRAM burst is read into cache line 345 of cache 135, wherein the LUT entry from DRAM 150 at address m is copied into cache line 345 of cache 135. Cache 135 may include write-back cache. The method then continues to step 620, where SoC controller 130 assigns two dirty bits to each cache line 345 of cache 135, wherein one dirty bit is assigned to an entry belonging to the 'even' region of the LUT and the other dirty bit is assigned to an entry belonging to the 'odd' region of the LUT. Initially, SoC controller 130 sets both dirty bits to clean or '0'.

[0047] In step 630, the L2P engine 134 writes to the address in cache line 345. Then, the LUT entries in cache line 345 of cache 135 are updated by the L2P engine 134 of SoC controller 130 as commands (e.g., host write commands or internally generated commands) are processed (step 640). As data is allocated / reallocated in NAND memory 140 during command processing, SoC 130 updates the LCA-MCA entries in cache line 345 of cache 135 by writing to cache 135. When updating entries in cache line 345, L2P engine 134 provides sideband information to cache 135 at each write to indicate whether the updated entry is in an odd or even region of the LUT. Therefore, if the LUT entry has been updated, the SoC controller 130 sets a bit in a pair of dirty bits in the cache 135 to '1', wherein the pair of bits is set to '10' when the updated entry in the cache 135 belongs to the 'even' region of the LUT, set to '01' when the updated entry in the cache 135 belongs to the 'odd' region of the LUT, set to '11' when the cache 135 contains updated entries belonging to both the 'even' and 'odd' regions of the LUT, or keeps the dirty bits at '00' when no updated information is written to the cache 135.

[0048] Next, in step 650, the SoC controller 130 may trigger a DRAM burst to write the contents of cache line 345 of cache 135 back to the DRAM address m from which the contents were initially loaded. Once the contents of cache 135 are written back to DRAM 150, the SoC controller 130 uses information from dirty bits in cache 135 to determine region n in the LUT containing the updated entry. Here, the SoC controller 130 may set bits in DRAM to '1' to identify the corresponding LUT region containing the updated entry. The SoC controller 130 may also determine the MCA start address of the corresponding LUT region n in NAND memory 140. In some embodiments, this may be done via a second LUT stored in NAND memory 140 that maps each LUT region index (e.g., indices n-1, n, n+1 as described above) to the MCA start address in NAND memory 140.

[0049] Next, the method proceeds to step 660, where the SoC controller 130 refreshes or writes entries belonging to the LUT region n containing the updated entries (identified by set bit '1') to the NAND memory 140. The increased granularity provided by the two dirty bits used in method 600 allows the SoC controller to explicitly identify the LUT region containing the updated entries, thereby causing only the LUT entries in the relevant region to be refreshed to the NAND memory 140, as described above regarding... Figure 5A and5B Description. This increases DRAM bandwidth, increases NAND memory bandwidth, and reduces the P / E cycle number on NAND memory 140, thereby saving resources and enhancing the performance of SSD 120.

[0050] In the preceding text, all descriptions of “layer” and “engine” should be understood to mean multiple circuits within a controller that facilitate the described function. Such circuits may include electronic components formed on a semiconductor chip, such as (for example) transistors and resistors. It should be noted that the terms “about” or “approximately” in the preceding text indicate a range of ±20% of the stated value. Additionally, all descriptions of “command,” “action,” or “function” in the preceding text should be understood to be based on algorithms and instructions stored on a non-transitory computer-readable medium, which, when executed by a processor, cause the controller of the integrated circuitry of the solid-state drive (SSD) to perform commands, actions, or functions.

[0051] Those skilled in the art will appreciate other objects, advantages, and embodiments of the various aspects of the invention, which are within the scope of the description and drawings. For example, but not limited to, structural or functional elements can be rearranged according to the invention. Similarly, the principles of the invention can be applied to other instances, which, even if not explicitly described in detail herein, will still be within the scope of the invention.

Claims

1. A memory storage system, comprising: A non-volatile semiconductor memory device configured to store a lookup table (LUT) comprising entries grouped into at least one first region and at least one second region; A volatile semiconductor memory device configured to temporarily store the entries of the LUT from the non-volatile semiconductor memory device; and A controller configured to store and retrieve data in the non-volatile semiconductor memory device in response to commands received from a host outside the memory storage system, the controller including a cache comprising a plurality of cache lines communicatively coupled to the volatile semiconductor memory device and configured to temporarily store entries read from address m of a plurality of addresses of the volatile semiconductor memory device in cache line z of the plurality of cache lines, the controller being configured to: A first status indicator and a second status indicator are assigned to each of the plurality of cache lines in the cache corresponding to the plurality of cache addresses of the volatile semiconductor memory device, wherein the first status indicator corresponds to an entry of the first cache address of the volatile semiconductor memory device belonging to the first region of the LUT, and the second status indicator corresponds to an entry of the first cache address of the volatile semiconductor memory device belonging to the second region of the LUT. Update the LUT entry at address m in the volatile semiconductor memory device read from the cache line z of the cache. The first status indicator or the second status indicator is set to a dirty state based on whether the updated entry in the cache line z read from address m is in the corresponding first or second area of ​​the LUT. Based on the dirty state of the first or second status indicator of the cache line z, all entries in the volatile semiconductor memory device associated with the first or second region containing the updated entry are copied to the non-volatile semiconductor memory device.

2. The memory storage system of claim 1, wherein the controller is further configured to: The entry of the LUT at address m is read into the cache line z; and Write the cache line z back to the address m of the volatile semiconductor memory device.

3. The memory storage system of claim 1, wherein the controller is configured to update only one entry of the LUT in the cache at a time.

4. The memory storage system of claim 1, wherein the controller is configured to repeatedly update the entries of the LUT in the volatile semiconductor memory device via the cache based on commands received from the host.

5. The memory storage system of claim 1, wherein the LUT maps the logical cluster address LCA to the media cluster address MCA in the non-volatile semiconductor memory device.

6. The memory storage system of claim 1, wherein the non-volatile semiconductor memory device is configured to store a second LUT that maps an index associated with each of the at least one first region and the at least one second region to a Media Cluster Address (MCA) in the non-volatile semiconductor memory device.

7. The memory storage system of claim 6, wherein the controller is further configured to: Access the second LUT to determine the starting MCA address of the region containing the updated entry in the non-volatile semiconductor memory device.

8. The memory storage system of claim 1, wherein the controller is further configured to: When the memory storage system is first started, the LUT is copied from the non-volatile semiconductor memory device to the volatile semiconductor memory device.

9. The memory storage system of claim 1, wherein the first and second status indicators each comprise one bit.

10. The memory storage system of claim 9, wherein each entry of the LUT at address m is set to a clean state before being updated in the cache.

11. The memory storage system of claim 10, wherein the controller sets the bit to '0' for the clean state and sets the bit to '1' for the dirty state.

12. The memory storage system of claim 1, wherein the cache includes a write-back cache.

13. The memory storage system of claim 1, wherein the cache is formed in a portion of the volatile semiconductor memory device.

14. The memory storage system of claim 1, wherein the non-volatile semiconductor memory device is a NAND semiconductor memory.

15. The memory storage system of claim 1, wherein the volatile semiconductor memory device is a dynamic random access memory (DRAM).

16. The memory storage system of claim 1, wherein the cache is a static random access memory (SRAM).

17. The memory storage system of claim 1, wherein the controller comprises a system-on-chip (SoC) controller.

18. The memory storage system of claim 17, wherein at least a portion of the volatile semiconductor memory device is external to the SoC controller.

19. A method executed by a controller of a memory storage system, the memory storage system comprising: A non-volatile semiconductor memory device configured to store a lookup table (LUT) comprising entries grouped into at least one first region and at least one second region; A volatile semiconductor memory device configured to temporarily store the entries of the LUT from the non-volatile semiconductor memory device; The method includes a cache comprising a plurality of cache lines communicatively coupled to the volatile semiconductor memory device and configured to temporarily store entries read from address m of the plurality of address lines of the volatile semiconductor memory device in cache line z of the plurality of cache lines, the method comprising the following steps: A first status indicator and a second status indicator are assigned to each of the plurality of cache lines in the cache corresponding to the plurality of cache addresses of the volatile semiconductor memory device, wherein the first status indicator is assigned to the entry of the first cache address of the volatile semiconductor memory device belonging to the first region of the LUT, and the second status indicator is assigned to the entry of the first cache address of the volatile semiconductor memory device belonging to the second region of the LUT. Update the LUT entry at address m in the volatile semiconductor memory device read from the cache line z of the cache; The first status indicator or the second status indicator is set to a dirty state based on whether the updated entry in the cache line z read from the address m is in the corresponding first or second area of ​​the LUT; and Based on the dirty state of the first or second status indicator of the cache line z, all entries in the volatile semiconductor memory device associated with the first or second region containing the updated entry are copied to the non-volatile semiconductor memory device.

20. The method of claim 19, further comprising the following steps: The entry of the LUT at address m is read into the cache line z; and Write the cache line z back to the address m of the volatile semiconductor memory device.

21. The method of claim 19, wherein the update step is performed on only one entry of the LUT in the cache at a time.

22. The method of claim 19, wherein the update step is repeatedly executed based on commands received from the host.

23. The method of claim 19, wherein the LUT maps the logical cluster address LCA to the media cluster address MCA in the non-volatile semiconductor memory device.

24. The method of claim 19, wherein the non-volatile semiconductor memory device is configured to store a second LUT that maps an index associated with each of the at least one first region and the at least one second region to a Media Cluster Address (MCA) in the non-volatile semiconductor memory device.

25. The method of claim 24, further comprising the following steps: Access the second LUT to determine the starting MCA address of the region containing the updated entry in the non-volatile semiconductor memory device.

26. The method of claim 19, further comprising the following steps: When the SSD is first booted, the LUT is copied from the non-volatile semiconductor memory device to the volatile semiconductor memory device.

27. The method of claim 19, wherein each of the first and second status indicators comprises one bit.

28. The method of claim 27, further comprising the following steps: Before the entry of the LUT at address m is updated in the cache, each bit is set to a clean state.

29. The method of claim 28, wherein setting a bit to the clean state comprises setting the bit to '0', and setting a bit to the dirty state comprises setting the bit to '1'.

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