Multi-channel data processing method, device, equipment and storage medium
By employing multi-channel data processing methods and arbitration scheduler management, the problem of SCM media PCM being unable to reuse traditional array arrangements was solved, achieving efficient utilization of PCM media and data flow design, and meeting the performance requirements of SCM components.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ALIBABA (CHINA) CO LTD
- Filing Date
- 2022-06-09
- Publication Date
- 2026-07-14
AI Technical Summary
In existing storage products, the PCM storage medium of SCM products cannot reuse the array layout and controller data flow design of traditional Flash and DRAM media, resulting in the inability to effectively utilize its characteristics.
A multi-channel data processing method is proposed, which involves receiving command packets, splitting them to determine channel information, processing commands in a multi-channel storage array, and using an arbitration scheduler to manage channels, thereby realizing the array layout and data flow design of PCM media.
It achieves efficient utilization and scheduling of PCM media, meets the performance requirements of SCM components, and ensures effective scheduling of data and commands and array arrangement of storage media.
Smart Images
Figure CN115083451B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a multi-channel data processing method, a multi-channel data processing device, a corresponding electronic device, and a corresponding computer-readable storage medium. Background Technology
[0002] In traditional storage products, mainstream storage products, such as NVMe devices (referring to NVMe standard SSD solid-state drives), define their media layout and controller data flow design based on the characteristics of Flash (Flash EEPROM Memory, a type of storage chip whose data can be modified by a specific program). Storage products can also include memory products; mainstream memory products, such as DIMM (Dual Inline Memory Module), define their media layout and controller data flow design based on the characteristics of DRAM (Dynamic Random Access Memory).
[0003] As a storage component between storage and memory, SCM (Storage Class Memory) uses PCM (Phase-Change Memory) as its storage medium. PCM has different characteristics from Flash and DRAM. As a completely new storage component, SCM cannot reuse the media layout and controller data flow design of the aforementioned mainstream products. Summary of the Invention
[0004] In view of the above problems, embodiments of this application are proposed to provide a multi-channel data processing method, a multi-channel data processing apparatus, a corresponding electronic device, and a corresponding computer-readable storage medium to overcome or at least partially solve the above problems.
[0005] This application discloses a multi-channel data processing method applied to server equipment, involving storage components. The storage components are arranged based on a multi-channel storage array. The method includes:
[0006] Receive a command packet for data processing, and split the command packet into several commands; the command packet is generated based on the command for data processing.
[0007] Determine the channel information for each command;
[0008] The target memory medium corresponding to the channel information in the multi-channel storage array is determined, and the command is processed through the target memory medium.
[0009] Optionally, the storage component has a corresponding interface protocol, and the splitting of the command packet into several commands includes:
[0010] Obtain the access data format information specified by the interface protocol; the access data format information includes the read / write data length;
[0011] The command packet is split according to the length of the read / write data to obtain several commands.
[0012] Optionally, determining the channel information for each command includes:
[0013] The channel information of each command is determined based on the multi-channel storage array, and / or the channel information carried in each command is obtained.
[0014] The commands obtained from the splitting are defined based on the controller in the storage array. Determining the channel information of each command based on the multi-channel storage array includes:
[0015] Obtain the channel information of the multi-channel storage array, wherein the channel information corresponds to the memory medium within the storage array, and the memory medium within the storage array has a corresponding physical address;
[0016] Obtain the physical address of the split command;
[0017] The physical addresses of the split commands are mapped to the channel information of the memory medium to determine the channel information corresponding to each command.
[0018] Optionally, processing the command through the target memory medium includes:
[0019] The target memory medium in the storage array is obtained using the channel information;
[0020] Each command is transmitted to the target memory medium, and the commands are processed through the target memory medium.
[0021] Optionally, the multi-channel storage array includes an arbitration scheduler for managing the corresponding channels of the memory medium. The transmission of commands to the target memory medium and the processing of the commands through the target memory medium include:
[0022] Based on the channel information, the split commands are transmitted to the arbitration scheduler corresponding to the channel of the target memory medium.
[0023] The arbitration scheduler sends commands to the channel command cache corresponding to the target memory medium based on the channel information, thereby enabling the target memory medium to process the commands.
[0024] Optionally, transmitting the split commands to the arbitration scheduler corresponding to the channel of the target memory medium based on the channel information includes:
[0025] The commands are transmitted to the controller's internal cache according to the order and priority of command splitting;
[0026] The command is moved from the controller's internal cache to the arbitration scheduler corresponding to the channel of the target memory medium based on the channel information.
[0027] Optionally, the command includes command content and / or data content, and the arbitration scheduler includes a data arbitrator and a command arbitrator; the arbitration scheduler that moves the command to the corresponding channel of the target memory medium based on the channel information includes:
[0028] When the command type of the command is a write command, the data content of the write command is moved to the data arbitrator of the corresponding channel of the target memory medium according to the channel information and priority of the write command, and the write command is synchronously transmitted to the command arbitrator of the corresponding channel of the target memory medium.
[0029] And / or, when the command type of the command is a read command, the read command is synchronously transmitted to the command arbitrator of the corresponding channel of the target memory medium according to the channel information of the read command and the priority of the read command.
[0030] Optionally, the arbitration scheduler includes a channel arbitrator, which invokes a data arbitrator and a command arbitrator; the step of issuing commands to the channel command cache corresponding to the target memory medium through the arbitration scheduler based on the channel information includes:
[0031] When the command type of the command is a write command, the channel arbiter obtains the channel write data cache corresponding to the target memory medium based on the channel information, and sends the data content in the data arbiter to the channel write data cache.
[0032] And / or, when the command type of the command is a read command, the channel arbitrator obtains the channel read data cache corresponding to the target memory medium based on the channel information, and the memory controller of the target memory medium responds to the command content in the command arbitrator, and caches the data requested to be read by the command content in the channel read data cache.
[0033] This application also discloses a multi-channel data processing device applied to server equipment, involving a storage component. The storage component is arranged based on a multi-channel storage array. The device includes:
[0034] The command splitting module is used to receive a command package for data processing, split the command package into several commands, and generate the command package based on the command for data processing.
[0035] The channel information determination module is used to determine the channel information for each command;
[0036] The command processing module is used to determine the target memory medium corresponding to the channel information in the multi-channel storage array, and process the command through the target memory medium.
[0037] Optionally, the storage component has a corresponding interface protocol, and the command splitting module includes:
[0038] The access data format information acquisition submodule is used to acquire the access data format information specified by the interface protocol; the access data format information includes the read / write data length.
[0039] The command splitting submodule is used to split the command packet according to the length of the read / write data to obtain several commands.
[0040] Optionally, the channel information determination module includes:
[0041] The channel information acquisition submodule is used to determine the channel information of each command based on the multi-channel storage array, and / or to acquire the channel information carried in each command.
[0042] The commands obtained from the decomposition are defined based on the controller in the storage array, and the channel information acquisition submodule includes:
[0043] The channel information acquisition unit is used to acquire the channel information of the multi-channel storage array, wherein the channel information corresponds to the memory medium in the storage array and the memory medium in the storage array has a corresponding physical address.
[0044] The physical address acquisition unit is used to acquire the physical address of the split command;
[0045] The address mapping unit is used to map the physical address of the split command to the channel information of the memory medium to determine the channel information corresponding to each command.
[0046] Optionally, the command processing module includes:
[0047] The target memory medium determination submodule is used to obtain the target memory medium in the storage array using the channel information;
[0048] The command processing submodule is used to transmit various commands to the target memory medium and process the commands through the target memory medium.
[0049] Optionally, the storage array includes an arbitration scheduler for managing the corresponding channels of the memory medium, and the command processing submodule includes:
[0050] The command transmission unit is used to transmit the split commands to the arbitration scheduler corresponding to the channel of the target memory medium based on the channel information;
[0051] The command issuing unit is used to issue commands to the channel command cache corresponding to the target memory medium through the arbitration scheduler based on the channel information, so as to realize the target memory medium's processing operation of the command.
[0052] Optionally, the command transmission unit includes:
[0053] An internal cache subunit is used to transmit the commands to the controller's internal cache according to the splitting order and priority of the commands;
[0054] The command transfer subunit is used to transfer the command from the controller's internal cache to the arbitration scheduler corresponding to the target memory medium's channel based on the channel information.
[0055] Optionally, the arbitration scheduler includes a channel arbitrator, which invokes a data arbitrator and a command arbitrator; the command issuing unit includes:
[0056] The first command issuing subunit is used to obtain the channel write data cache corresponding to the target memory medium through the channel arbitrator based on the channel information when the command type of the command is a write command, and send the data content in the data arbitrator to the channel write data cache.
[0057] The second command issuing subunit is used to, when the command type of the command is a read command, obtain the channel read data cache corresponding to the target memory medium based on the channel information through the channel arbitrator, and respond to the command content in the command arbitrator through the memory controller of the target memory medium, and cache the data requested to be read by the command content in the channel read data cache.
[0058] This application also discloses an electronic device, including: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of any of the multi-channel data processing methods.
[0059] This application also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the multi-channel data processing methods.
[0060] The embodiments of this application have the following advantages:
[0061] This application involves a storage component that can be arranged based on a multi-channel storage array. When the server device uses this multi-channel storage array for data processing, command packets can be split, and corresponding commands can be sent through the appropriate channels based on channel information. Based on the management of the memory media of each channel, commands are sent and processed to the corresponding target memory media. The application proposes an array topology and multi-channel layout for the storage component, as well as a data transmission mechanism for channel-based scheduling and management commands. This ensures that component performance is met while effectively scheduling data and commands, realizing the array arrangement of storage media and data flow design within the storage component. Attached Figure Description
[0062] Figure 1 This is a schematic diagram showing the location of the storage-class memory (SCM) within the storage component;
[0063] Figure 2 This is a schematic diagram of the PCM media arrangement framework provided in the embodiments of this application;
[0064] Figure 3 This is an array topology diagram of the storage components provided in the embodiments of this application;
[0065] Figure 4 This is a flowchart illustrating the steps of an embodiment of a multi-channel data processing method according to this application;
[0066] Figure 5 This is a flowchart illustrating the steps of another embodiment of the multi-channel data processing method of this application;
[0067] Figure 6 This is an application scenario diagram of data processing using the application storage component provided in the embodiments of this application;
[0068] Figure 7 This is a structural block diagram of an embodiment of a multi-channel data processing device according to this application. Detailed Implementation
[0069] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0070] To facilitate understanding of this application by those skilled in the art, the terms or nouns involved in the following embodiments of this application are explained below:
[0071] NVMe: Non-Volatile Memory Express, is a communication interface and driver that fully utilizes the higher bandwidth offered by PCIe.
[0072] PCIe: short for PCI Express, abbreviated as PCI-E, is a high-speed bus inside a computer. PCIeGen5 is essentially just a new standard of PCI Express, achieving a transfer speed of up to 32 GT / s and a bandwidth of up to 128GB / s in x16 configurations.
[0073] SSD: Solid State Disk or Solid State Drive, also known as a solid state drive, is a hard drive made of solid state electronic storage chip arrays.
[0074] PCM: Phase-Change Memory, is a type of memory that uses the difference in conductivity exhibited by special materials when they transform between crystalline and amorphous states to store data. It also features fast read / write speeds, short data access response times, long lifespans, and stable data storage.
[0075] SCM: Storage Class Memory, is a type of physical computer memory that serves as a storage component between storage and main memory. It is characterized by its low cost and high performance.
[0076] DRAM: Dynamic Random Access Memory.
[0077] HDD: Hard Disk Drive, a basic type of computer storage device.
[0078] TAPE: Magnetic tape, a storage device that primarily uses magnetic tape as the storage medium and consists of a tape drive and its controller. It is an auxiliary storage device for computers.
[0079] DMA: Direct Memory Access, which copies data from one address space to another.
[0080] ECC: Error Correcting Code, is an encoding method that can automatically detect and correct errors that occur during transmission over a certain length.
[0081] Array: In this embodiment of the application, an array refers to the arrangement of a certain storage medium.
[0082] PCM storage controller: Phase change storage controller, which can manage the read and write addresses and data of the storage array through a series of software and hardware functions.
[0083] Phy: Physical, which can be referred to as the port physical layer.
[0084] Host: The host computer.
[0085] Protocol: a set of rules or protocols.
[0086] FEC: Forward Error Correction is a method that adds redundant information to data packets during network transmission, enabling the receiving end to directly recover lost data packets after packet loss.
[0087] Bandwidth: In this embodiment of the application, it refers to the throughput of reading and writing data.
[0088] Latency: In this embodiment of the application, it refers to the read and write access latency of the storage device.
[0089] Channel: In contrast to PCM channel, it refers to different channels having different communication buses.
[0090] Address mapping: The correspondence and relationship between host address and physical address.
[0091] SDP: Single Die Package, where each dielectric chip contains a single die.
[0092] DDP: Double Die Package, where each dielectric chip contains two dies.
[0093] Die: refers to the unpackaged die of a chip. A die can be equivalent to an independent functional chip. It will be packaged as a unit to form a chip. That is, a chip may contain several dies.
[0094] Bank: Simply put, it is a matrix composed of rows and columns.
[0095] Row: A row or column in an array of rows and columns.
[0096] Page: A unit for reading and writing memory. A page consists of several bytes.
[0097] As a storage component between storage and memory, SCM differs from traditional mainstream storage and memory products. SCM products exhibit storage-like memory characteristics, primarily determined by performance. The performance of a storage component is determined by its access speed, which can be expressed as its access time. Figure 1 As shown, DRAM access time can be within 10ns, SCM access time can be between 10ns and 1us, Nand SSD access time can be between 10us and 100us, and HDD / TAPE access time can be between 1ms and 10ms. SCM outperforms Nand SSDs and HDD / TAPEs, but is cheaper than DRAM, possessing the inherent characteristics of low cost and high performance. The storage medium for SCM products is PCM, which has different characteristics from Flash and DRAM. As a new storage medium, its cost / performance and reliability parameters fall between Flash and DRAM. In system applications, it can serve as a replacement for high-performance non-volatile and low-cost DDR, requiring a balance between high bandwidth, low latency, and low cost.
[0098] As a brand-new storage component, SCM typically involves designing its memory controller array layout based on multiple dimensions such as channels and capacity, from the perspective of the underlying logic of storage components. However, when SCM products use new PCM chips, the variables that need to be considered in the array design process are different from those of other memory controllers, as PCM media is a non-volatile memory medium. It not only needs to take into account the traditional memory dimensions such as channels and capacity, but also needs to consider a series of comprehensive issues such as non-volatile storage dies, bandwidth, and address mapping. Based on this, the array layout and controller data flow design of PCM cannot directly reuse the array design of other memory types.
[0099] In this embodiment, a set of array topology and channel-based schemes for PCM media can be proposed based on the characteristics of PCM and the component requirements of SCM. This achieves full and efficient utilization and scheduling of PCM resources while meeting component requirements. Furthermore, based on the array scheme of PCM and the component requirements of SCM, a command data transmission mechanism for mid-to-back-end channel-based scheduling and management is proposed. This effectively schedules data and commands while ensuring component performance, thereby realizing the array layout and data flow design of PCM.
[0100] Specifically, by analyzing the interface frequency, bus width, read / write command characteristics, and latency of the PCM medium, and comprehensively considering the system's requirements for the capacity, bandwidth, and latency of the SCM product, multiple parallel PCM channels can be designed. Furthermore, a command and data management scheme for dies within the same channel can be implemented to meet the capacity, bandwidth, and latency requirements of the SCM component. This allows for the development of array topologies and channel-based schemes for the PCM medium based on PCM characteristics and SCM component requirements, as well as a command data transmission mechanism for mid-to-back-end channel scheduling and management.
[0101] To achieve a solution for managing multi-channel, multi-die PCM arrays and related data control, refer to Figure 2 This diagram illustrates a schematic of the PCM media layout framework provided in this embodiment. The layout framework or array is based on the storage media, and the storage array obtained by arranging multiple storage media can be defined as a storage component. The PCM media layout may include a front-end control module 210, a mid-end control module 211, and a back-end control module 213. The front-end control module 210 is primarily responsible for splitting the command packets after receiving them. The mid-end control module 211 is primarily responsible for caching the split commands and related data within the command packets, as well as transferring and encoding / decoding the split commands and related data. The back-end control module 213 is primarily responsible for managing commands and related data across multiple channels and executing related commands.
[0102] In practical applications, such as Figure 3 As shown, the front-end control module 210 may include a protocol parsing module 310. The protocol parsing module 310 is mainly responsible for splitting the received command packets according to the protocol. This protocol is a protocol that satisfies the access to the controller's internal protocol, so that the split commands can access the controller's internal protocol.
[0103] The mid-range control module 211 may include a mid-range controller 311, a controller data transfer acceleration engine 312, and an ECC encoding / decoding engine 313. The mid-range controller 311 is mainly responsible for caching the split commands and related data in the commands. For example, when the command is a write command, the data content carried in the write command can be cached. Its internal cache can adopt various types, such as SRAM or external DDR of the controller. This application embodiment does not limit it. The controller data transfer acceleration engine 312 is mainly responsible for managing and scheduling the commands and data in the controller's internal cache through multiple PCM channels. The ECC encoding / decoding engine 313 is mainly responsible for encoding and decoding the data with error correction codes according to the data stability characteristics of PCM to ensure the reliability of the stored data.
[0104] The backend control module 213 may include an arbitration scheduler 314, a PCM interface controller 315, and a PCM media array 316. The arbitration scheduler 314 is mainly responsible for issuing and scheduling commands and related data to different channels when managing commands and related data for multiple channels. The PCM interface controller 315 is mainly responsible for issuing commands and reading data for the PCM mechanism of related channels. The PCM media array 316 is mainly for the implementation of a multi-channel storage array for PCM.
[0105] Based on the characteristics of PCM and the component requirements of SCM, an array topology and channel-based scheme for PCM media are proposed. In the specific implementation process, the following input constraints of PCM media need to be considered: (1) PCM capacity configuration, (2) PCM interface frequency, (3) PCM read / write access rate and response time, (4) PCM packaging form and (5) SCM bandwidth latency requirements based on PCIe Gen5, so as to determine the requirements of these input constraints that need to be met when implementing the component requirements of SCM, and to design the array topology and channel-based scheme of PCM media based on the required input constraints.
[0106] Among them, (1) PCM capacity configuration, which can be used to determine the number of PCM dies to meet the requirements of SCM components. It is mainly based on the single die capacity provided by the supplier. Under the capacity requirements of SCM products, the number of PCM dies required is determined, thereby determining how to design the channel and die architecture. (2) PCM interface frequency, which can be used to determine the number of channels to meet the bandwidth requirements of SCM products. It is mainly based on the overall bandwidth requirements of SCM. Combined with the bandwidth specifications under the single PCM interface frequency, the overall number of channels is determined. (3) PCM read and write access rate and response time, which can be determined from the perspective of SCM component delay. Based on the delay specifications inside the controller, the read and write process design of the controller is determined. (4) PCM packaging form, which mainly affects the single board design. It needs to consider the number of packages in the single board design under fixed channels, the capacity to be achieved by each package and the corresponding channel layout, and also needs to consider the packaging form when the PCB of the SCM component has sufficient space layout. (5) The system is based on the SCM bandwidth latency requirements under PCIe Gen5. It mainly determines the overall number of channels from the perspective of PCIe Gen5 interface requirements, combined with the bandwidth specifications of a single PCM interface frequency, and determines the controller read and write process design based on the latency specifications inside the controller. That is, under the condition that the SCM product meets the PCIe Gen5 interface, the PCM array and controller read and write process are designed.
[0107] For example, suppose an SCM product is required to support the PCIe Gen5 interface protocol and needs to meet a read / write bandwidth of 32GB / s. In this case, the command and data processing bandwidth can be achieved through a full hardware solution. For example, mainstream SCM components require support for capacities of 256GB-1TB. Assuming the SCM product's capacity requirement is 256GB, the PCM array designed based on this requirement needs to meet this 256GB capacity configuration. If the supplier provides a single PCM die with a capacity of 16GB, then 16 PCM dies are required to meet the 256GB capacity configuration. When packaging the PCM, if SDP is used, the physical channels configured for the PCM array should be 16. However, to ensure the rationality of the PCB layout for the SCM component, DDP is usually used. In this case, the physical channels configured for the PCM array are 8, with one DDP in each physical channel. Each channel has one packaged chip, and each chip contains 2 dies. The capacity of this DDP is 32GB to meet the 256GB capacity configuration requirement.
[0108] Assuming the SCM product meets the PCIe Gen5 interface requirements and the required read / write bandwidth is 32GB / s, with DDP packaging as described above, each channel has a bandwidth of 1.5GB / s (750MB / s write bandwidth per die). Each channel's PCM interface controller needs to achieve a bandwidth of 4GB / s to ensure the system's bandwidth requirements are met. Therefore, each channel requires independent PCM interface controller management. Taking a 64-bit data granularity for read / write commands as an example, the controller's internal cache can be configured with two 32-bit systems: two controller data transfer acceleration engines and two ECC encoding / decoding engines, each managing the data and command scheduling of the four PCM channels. This means each set of four PCM channels uses one 32-bit PCM interface controller, ensuring the overall system achieves a write bandwidth close to 32GB / s. It should be noted that the read and write commands in this example, which use 64-bit data granularity, can be defined as any size as required to adapt to the requirements of PCM products in the actual implementation process. Data granularity can be defined as the size of the read and write data blocks transmitted, accessed, and managed within the controller. The process of defining granularity needs to take into account the physical structure of the PCM medium, the data access unit, the ECC design scheme, and other dimensions. This application does not impose any restrictions on this.
[0109] In this application embodiment, based on the proposed PCM array design method, different channel numbers, PCM packaging methods, and back-end command and data scheduling methods can be designed according to different parameters. This application embodiment is aimed at storage-type memory media. From a hardware perspective, it can only be compatible with storage-type memory media products and cannot be compatible with the characteristics of Flash and DRAM products. Taking the characteristics of PCM media (including component bandwidth, interface frequency, packaging configuration, capacity, etc.) as an example, the array and channel design of PCM is carried out, and a system solution suitable for PCM is sorted out.
[0110] It should be noted that although the embodiments of this application cannot be used for array design for non-storage memory media, even though traditional Flash and DRAM have different characteristics from PCM media, the design scheme based on memory arrays summarized in the embodiments of this application can still be used to design a scheme that can define the topology scheme and the back-end data command interaction strategy based on traditional Flash and DRAM storage arrays, based on the similar parameters of different storage media (such as component bandwidth, interface frequency, package configuration, capacity, etc.).
[0111] Reference Figure 4 This diagram illustrates a flowchart of an embodiment of a multi-channel data processing method according to this application, applied to a server device. The storage component in the server device involves a storage-type memory medium, such as a PCM medium. The PCM medium is based on... Figure 2 and Figure 3 The multi-channel storage array shown is arranged such that the array of multiple storage media can be defined as a storage component, which may specifically include the following steps:
[0112] Step 401: Receive a command packet for data processing, and split the command packet into several commands;
[0113] For multi-channel, multi-die managed PCM arrays and related data control schemes, the storage memory media is arranged based on a multi-channel storage array. The storage array consists of a large number of storage cells, typically arranged in an N x M matrix. A multi-channel storage array refers to the multi-channel patterning of the storage array, i.e., dividing the storage array into multiple channels. During data processing based on this storage memory media, to ensure that different received commands can access the controller's internal mechanisms, the front-end control module can split the received data processing commands. Specifically, according to the internal access protocol, the commands generated from the data processing commands are split into several commands, allowing the controller to respond to and process these split commands.
[0114] Specifically, the storage component has a corresponding interface protocol. This interface protocol is mainly for the internal processing of the controller. When splitting the command packet, the access data format information specified by the interface protocol can be obtained. The access data format information can refer to the length of the read and write data. At this time, the command packet can be split into a format that meets the requirements according to the protocol requirements. That is, the received command packet is split according to the length of the read and write data specified by the interface protocol to obtain several commands.
[0115] It should be noted that the commands obtained from the split can be custom commands within the controller, and not commands from the SCM protocol segment.
[0116] Step 402: Determine the channel information for each command;
[0117] In data control based on multi-channel management, in order to realize command transmission to the media arranged with multi-channel storage array, the channel information of each command can be determined by the intermediate control module, so as to transmit the command to the corresponding memory media based on the determined channel information.
[0118] In this case, the storage-type memory media in the storage component are arranged based on a multi-channel storage array. In this case, the channel information of each command can be determined according to the multi-channel storage array. In another case, when the command carries its own channel information, the channel information carried by each command can also be obtained directly from each command.
[0119] In practical applications, the storage memory media in the storage unit have corresponding channel information. For example, the channel number can correspond to each memory medium, and each memory medium in a multi-channel storage array has a corresponding physical address. That is, there can be a mapping relationship between the channel information of each memory medium and the physical address of each memory medium. The split commands are defined based on the controller in the storage array. At this time, the controller can define the physical address corresponding to the split commands. After obtaining the physical address of each command, the physical address of the split commands can be mapped to the channel information of the memory medium to determine the channel information corresponding to each command.
[0120] Step 403: Determine the target memory medium corresponding to the channel information in the multi-channel storage array, and process the command through the target memory medium.
[0121] The channel information for each command is obtained by mapping the physical address of each command to the channel information of the memory medium. At this time, the back-end control module can directly determine the target memory medium in the multi-channel storage array based on the channel information, so as to transmit commands to the target memory medium and process the commands through the target memory medium. Based on the management of the memory medium of each channel, data and commands can be effectively scheduled.
[0122] The commands for data processing can include read commands and / or write commands. In this case, the processing performed by the target memory medium on the commands can be manifested as the target memory medium responding to the read command by performing a data reading operation, and / or responding to the write command by performing a data writing operation.
[0123] This application involves a storage component that can be arranged based on a multi-channel storage array. When the server device uses this multi-channel storage array for data processing, command packets can be split, and corresponding commands can be sent through the appropriate channels based on channel information. Based on the management of the memory media of each channel, commands are sent and processed to the corresponding target memory media. The application proposes an array topology and multi-channel layout for the storage component, as well as a data transmission mechanism for channel-based scheduling and management commands. This ensures that component performance is met while effectively scheduling data and commands, realizing the array arrangement of storage media and data flow design within the storage component.
[0124] Reference Figure 5 This diagram illustrates a flowchart of another embodiment of a multi-channel data processing method according to this application, applied to a server device. The storage component in the server device involves a storage-type memory medium, such as a PCM medium, which is based on... Figure 2 and Figure 3 The multi-channel storage array shown is arranged such that the array of multiple storage media can be defined as a storage component, which may specifically include the following steps:
[0125] Step 501: The command packet is split into several commands according to the internal protocol of the controller through the protocol parsing module;
[0126] For multi-channel, multi-die managed PCM arrays and related data control schemes, the storage-type memory media is arranged based on a multi-channel storage array. During the data processing based on this storage-type memory media, in order to ensure that different received commands can satisfy access to the controller's internal system, the front-end control module can split the received commands for data processing. Specifically, it can split the commands generated based on the data processing commands into several commands according to the internal access protocol, so that the controller can respond to and process the split commands.
[0127] Specifically, the storage component has a corresponding interface protocol. This interface protocol is mainly designed for the internal processing of the controller. When splitting the command packet, the access data format information specified by the interface protocol can be obtained. The access data format information can refer to the granularity of the controller's internal access, that is, the length of the read and write data. At this time, the command packet can be split into a format that meets the requirements according to the protocol requirements. That is, the received command packet is split according to the read and write data length specified by the interface protocol to obtain several commands.
[0128] In practical applications, when a host initiates read / write commands to an SCM device, the host will split the read / write commands into a compliant format according to protocol requirements, such as those of the PCIe and SCM interface protocols. For example, different SCM devices may have different requirements, typically involving 64-byte and 256-byte modes. Upon receiving a command packet for data processing, such as a read / write command, the length of data processed internally by the controller is fixed, say 64 bytes. Therefore, the controller front-end, or front-end control module, first needs to split the received data length, for example, 256 bytes, into four 64-byte commands, thus completing the command or data splitting process.
[0129] Step 502: Based on the channel information corresponding to each command, transmit the split commands to the arbitration scheduler corresponding to the channel of the target memory medium.
[0130] In data control based on multi-channel management, in order to realize command transmission to storage media arranged in a multi-channel storage array, the channel information of each command can be determined by the intermediate control module, so that the command can be transmitted to the corresponding memory media based on the determined channel information. The operation of command transmission to the corresponding memory media in multi-channel can be mainly implemented based on the arbitration scheduler of the corresponding channel.
[0131] In a multi-channel storage array, there is an arbitration scheduler for managing the corresponding channels of a set of memory media. The arbitration scheduler can control the commands and data in the controller's internal cache and needs to transfer the processed commands to the controller's internal cache.
[0132] After different commands are broken down into granular units for internal controller access according to the protocol, the front-end control module will transmit these commands to the controller's internal buffer according to the order and priority of command breakdown. The resulting commands may contain command content and / or data content. The data content can be data read and written by the host to the SCM. When buffering commands according to their breakdown order and priority, on the one hand, the command content can be transmitted via the data path according to the breakdown order and priority; on the other hand, the data content can be transmitted to DRAM or the controller's internal buffer according to priority. Within the controller's internal buffer, DRAM primarily serves as a write data buffer to store large amounts of write data. When the front-end control module's DMA engine initiates a data transfer from the host, DRAM speeds of 64GB / s are required.
[0133] In practical applications, when caching according to the splitting order and priority, there may be situations where commands split later have higher priority. In this case, the controller will manage different command teams according to the priority of different commands (i.e., based on the private commands obtained by splitting defined internally by the controller), that is, put high-priority commands into high-priority teams.
[0134] When the DMA engine of the front-end control module initiates the transfer of write data to the host, the controller data transfer acceleration engine can transfer the command from the controller's internal cache to the arbitration scheduler corresponding to the target memory medium based on the channel information.
[0135] Among them, the controller data transfer acceleration engine can serve as a data transmission module connecting the back-end DRAM and the back-end command / data cache. The controller data transfer acceleration engine can manage and schedule commands and data in the internal cache of the controller through multiple PCM channels. For example, each controller data transfer acceleration engine can manage commands and data that can be scheduled through 8 PCM channels.
[0136] An arbitration scheduler for managing a set of memory media channels can include a command arbitrator and a data arbitrator. The command arbitrator is responsible for scheduling and managing command content across multiple channels, while the data arbitrator is responsible for scheduling and managing data content across multiple channels. When moving commands based on channel information, this can manifest as follows: when the command type is a write command, the data content of the write command is moved to the data arbitrator corresponding to the target memory media channel according to the channel information and priority of the write command, and the write command is synchronously transmitted to the command arbitrator corresponding to the target memory media channel; and / or, when the command type is a read command, the read command is synchronously transmitted to the command arbitrator corresponding to the target memory media channel according to the channel information and priority of the read command.
[0137] In a preferred embodiment, considering the data stability characteristics of PCM, the reliability of stored data can be guaranteed by an ECC encoding engine. In this case, each group of PCM channels, for example, every 8 PCM channels, can use an ECC encoder (ECCEncoder) and a decoder (Decoder), and guarantee a read / write bandwidth of nearly 32GB / s.
[0138] Step 503: The arbitration scheduler sends the command to the channel command cache corresponding to the target memory medium based on the channel information, so as to realize the target memory medium's processing operation of the command.
[0139] An arbitration scheduler for managing a set of memory media channels may also include a channel arbitrator. This channel arbitrator is mainly responsible for scheduling and managing the data and commands of the PCM channels. It can call the data content in the data arbitrator and the command content in the command arbitrator. That is, multi-channel scheduling and management of data requires the combination of the channel arbitrator and the data arbitrator, and multi-channel scheduling and management of commands requires the combination of the channel arbitrator and the command arbitrator.
[0140] At this point, the command can be sent to the channel command cache corresponding to the target memory medium through the arbitration scheduler, so that the target memory medium can process the command.
[0141] In a multi-channel storage array, each memory medium has a corresponding channel command cache, and each channel has an independent PCM interface controller. That is, there are multiple sets of PCM interface controllers and Phys to independently manage multiple PCMs. Each channel's PCM interface controller and Phys have the authority to issue commands and read data from the corresponding channel's PCM medium.
[0142] The channel command cache of the memory medium can include a channel write data cache and a channel read data cache. When the command type is a write command, the channel arbitrator can obtain the corresponding channel write data cache of the target memory medium based on the channel information. The data content in the data arbitrator is sent to the channel write data cache through the PCM interface controller of the target memory medium to realize the response to the write command and write the data content. When the command type is a read command, the channel arbitrator can obtain the corresponding channel read data cache of the target memory medium based on the channel information. The memory controller of the target memory medium, i.e., the PCM interface controller, responds to the command content in the command arbitrator and caches the data requested by the command content in the channel read data cache to complete the read operation of the required data. This allows the data in the subsequent channel read data cache to be returned to the host through the data channel.
[0143] This application involves a storage component that can be arranged based on a multi-channel storage array. When the server device uses this multi-channel storage array for data processing, command packets can be split, and corresponding commands can be sent through the appropriate channels based on channel information. Based on the management of the memory media of each channel, commands are sent and processed to the corresponding target memory media. The application proposes an array topology and multi-channel layout for the storage component, as well as a data transmission mechanism for channel-based scheduling and management commands. This ensures that component performance is met while effectively scheduling data and commands, realizing the array arrangement of storage media and data flow design within the storage component.
[0144] Reference Figure 6 This diagram illustrates an application scenario for data processing using the application memory medium provided in this application embodiment. In this scenario, the medium arrangement method and data / command control scheme of a multi-channel PCM array proposed based on the characteristics of the PCM medium enable the storage component SCM for this PCM medium to meet the bandwidth latency performance of the PCIe Gen5 interface device while ensuring that its cost is lower than that of volatile storage components. It can be used as an SCM in server devices, where the server device 611 can communicate with the client device 610.
[0145] Among them, PCM media can be based on such as Figure 2 and Figure 3The multi-channel storage array shown is arranged such that an array of multiple storage media is defined as a storage unit. For example, the PCM array is configured with 8 physical channels, which can be channels for storing user data, such as CH0-CH7. If the SCM product meets the PCIe Gen5 interface, the required read / write bandwidth is 32GB / s. When packaged in the DDP format described above, the bandwidth of each channel is 1.5GB / s (the write bandwidth of a single die is 750MB / s). Each channel's PCM interface controller needs to meet a bandwidth of 4GB / s to ensure the system's bandwidth requirements. Therefore, each channel needs to be managed using an independent PCM interface controller. Furthermore, taking a data granularity of 64 bits for read and write commands as an example, the internal cache configuration of the controller can use two 32-bit systems, namely two controller data transfer acceleration engines and two ECC encoding and decoding engines, which respectively manage the data and command scheduling of four PCM channels. That is, each set of 32-bit PCM interface controllers is used for every four PCM channels, ensuring that the overall system achieves a write bandwidth of approximately 3GB / s.
[0146] It should be noted that the controller's internal cache is configured with two ECC codec engines. These ECC codec engines can correct errors that occur during transmission / storage. In addition to configuring the eight physical channels of the PCM array, two physical channels can be configured for each ECC codec engine. The four configured physical channels can be the storage channels corresponding to ECC parity checks, such as CH8-CH11, to enable the storage and retrieval of error correction codes during the ECC codec process for the data to be read or written.
[0147] In this application scenario, when the server device 611 receives a read / write command for data processing sent by the client device 610, the Host in the front-end control module can initiate a read / write command for the SCM device. At this time, according to the requirements of the PCIe and SCM interface protocols, the command packets of the received read / write commands can be split and data moved, and transmitted to the controller's internal cache according to the command splitting order and priority. The split commands can contain command content and / or data content. The data content can be the data that the Host reads and writes to the SCM. When caching the commands according to the command splitting order and priority, on the one hand, the command content can be transmitted through the data path according to the command splitting order and priority, and on the other hand, the data content can be transmitted to DRAM or the control's internal cache buffer according to the priority.
[0148] The controller data transfer acceleration engine serves as a data transfer module connecting the back-end DRAM and the back-end command / data cache. Each controller data transfer acceleration engine manages and schedules commands and data across four PCM channels. When the front-end control module's DMA engine initiates a write data transfer to the host, the controller data transfer acceleration engine can transfer the command from the controller's internal cache to the arbitration scheduler corresponding to the target memory medium's channel based on channel information. For host write commands, the controller data transfer engine will move the DRAM data to the corresponding back-end data arbitrator via the DMA engine according to the command's physical address (channel number) and priority, and synchronously transmit the write command to the corresponding command arbitrator. For host read commands, the controller data transfer engine will synchronously transmit the corresponding read command to the corresponding command arbitrator according to the command's physical address (channel number) and priority.
[0149] Then, based on the arbitration scheduler, the corresponding command can be sent to the corresponding channel command cache according to the channel number information. Based on the PCM interface controller and Phy of each channel, commands can be sent and data can be read from the PCM medium of that channel.
[0150] The arbitration scheduler, used to manage a set of memory media channels (e.g., four PCM channels), may also include a channel arbitrator. This channel arbitrator primarily schedules and manages the data and commands of the PCM channels. It can call the data content within the data arbitrator and the command content within the command arbitrator. In other words, multi-channel scheduling and management of data requires the combination of the channel arbitrator and the data arbitrator, while multi-channel scheduling and management of commands requires the combination of the channel arbitrator and the command arbitrator. Specifically, the operation of issuing commands to the channel command buffer is mainly based on the channel arbitrator.
[0151] In this application scenario, two channel arbiters can exist, managing channels CH0-CH3 and CH4-CH7 respectively. When a channel arbiter receives read / write and DMA commands from the Data Path DMA Engine, it can issue the corresponding command to the corresponding channel command cache based on channel information (e.g., channel number). When the issued command is a host write command, the channel arbiter will send data from DRAM to the corresponding channel write data cache, thus responding to the write command and writing the data content. When the command is a host read command, the corresponding read data can be cached in the channel read data cache through the PCM Phy of the target memory medium, completing the read operation of the required data, so that the data in the subsequent channel read data cache can be returned to the host through the data channel.
[0152] In this embodiment, a set of array topology and channel-based schemes for PCM media can be proposed based on the characteristics of PCM and the component requirements of SCM. This achieves full and efficient utilization and scheduling of PCM resources while meeting component requirements. Furthermore, based on the array scheme of PCM and the component requirements of SCM, a command data transmission mechanism for mid-to-back-end channel-based scheduling and management is proposed. This effectively schedules data and commands while ensuring component performance, thereby realizing the array layout and data flow design of PCM.
[0153] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.
[0154] Reference Figure 7 This diagram illustrates a structural block diagram of an embodiment of a multi-channel data processing device according to this application. Applied to a server device, it involves a storage component arranged based on a multi-channel storage array, and specifically may include the following modules:
[0155] The command splitting module 701 is used to receive a command package for data processing, split the command package into several commands, and generate the command package based on the command for data processing.
[0156] The channel information determination module 702 is used to determine the channel information of each command;
[0157] The command processing module 703 is used to determine the target memory medium corresponding to the channel information in the multi-channel storage array, and process the command through the target memory medium.
[0158] In one embodiment of this application, the storage component has a corresponding interface protocol, and the command splitting module 701 may include the following sub-modules:
[0159] The access data format information acquisition submodule is used to acquire the access data format information specified by the interface protocol; the access data format information includes the read / write data length.
[0160] The command splitting submodule is used to split the command packet according to the length of the read / write data to obtain several commands.
[0161] In one embodiment of this application, the channel information determination module 702 may include the following sub-modules:
[0162] The channel information acquisition submodule is used to determine the channel information of each command based on the multi-channel storage array, and / or to acquire the channel information carried in each command.
[0163] The commands obtained from the decomposition are defined based on the controller in the storage array, and the channel information acquisition submodule may include the following units:
[0164] The channel information acquisition unit is used to acquire the channel information of the multi-channel storage array, wherein the channel information corresponds to the memory medium in the storage array and the memory medium in the storage array has a corresponding physical address.
[0165] The physical address acquisition unit is used to acquire the physical address of the split command;
[0166] The address mapping unit is used to map the physical address of the split command to the channel information of the memory medium to determine the channel information corresponding to each command.
[0167] In one embodiment of this application, the command processing module 703 may include the following sub-modules:
[0168] The target memory medium determination submodule is used to obtain the target memory medium in the storage array using the channel information;
[0169] The command processing submodule is used to transmit various commands to the target memory medium and process the commands through the target memory medium.
[0170] In one embodiment of this application, the storage array includes an arbitration scheduler for managing channels corresponding to the memory medium, and the command processing submodule may include the following units:
[0171] The command transmission unit is used to transmit the split commands to the arbitration scheduler corresponding to the channel of the target memory medium based on the channel information;
[0172] The command issuing unit is used to issue commands to the channel command cache corresponding to the target memory medium through the arbitration scheduler based on the channel information, so as to realize the target memory medium's processing operation of the command.
[0173] In one embodiment of this application, the command transmission unit may include the following sub-units:
[0174] An internal cache subunit is used to transmit the commands to the controller's internal cache according to the splitting order and priority of the commands;
[0175] The command transfer subunit is used to transfer the command from the controller's internal cache to the arbitration scheduler corresponding to the target memory medium's channel based on the channel information.
[0176] In one embodiment of this application, the arbitration scheduler includes a channel arbitrator, which invokes a data arbitrator and a command arbitrator; the command issuing unit may include the following sub-units:
[0177] The first command issuing subunit is used to obtain the channel write data cache corresponding to the target memory medium through the channel arbitrator based on the channel information when the command type of the command is a write command, and send the data content in the data arbitrator to the channel write data cache.
[0178] The second command issuing subunit is used to, when the command type of the command is a read command, obtain the channel read data cache corresponding to the target memory medium based on the channel information through the channel arbitrator, and respond to the command content in the command arbitrator through the memory controller of the target memory medium, and cache the data requested to be read by the command content in the channel read data cache.
[0179] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.
[0180] This application also provides an electronic device, including:
[0181] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the various processes of the above-described multi-channel data processing method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.
[0182] This application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described multi-channel data processing method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.
[0183] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0184] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0185] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0186] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0188] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0189] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0190] The foregoing has provided a detailed description of a multi-channel data processing method, a multi-channel data processing device, a corresponding electronic device, and a corresponding computer-readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A multi-channel data processing method, characterized in that, This method applies to server equipment and involves storage components. The storage components are arranged based on a multi-channel storage array. The multi-channel storage array contains an arbitration scheduler for managing channels corresponding to memory media. The arbitration scheduler includes a channel arbitrator, which invokes a data arbitrator and a command arbitrator. The method includes: Receive a command packet for data processing, and split the command packet into several commands; the command packet is generated based on the command for data processing. Determine the channel information for each command; The target memory medium in the multi-channel storage array is obtained using the channel information; Based on the channel information, the split command is transmitted to the arbitration scheduler corresponding to the channel of the target memory medium. When the command type of the command is a write command, the channel arbiter obtains the channel write data cache corresponding to the target memory medium based on the channel information, and sends the data content in the data arbiter to the channel write data cache. And / or, when the command type of the command is a read command, the channel arbitrator obtains the channel read data cache corresponding to the target memory medium based on the channel information, and the memory controller of the target memory medium responds to the command content in the command arbitrator, and caches the data requested to be read by the command content in the channel read data cache.
2. The method according to claim 1, characterized in that, The storage component has a corresponding interface protocol, and the splitting of the command packet to obtain several commands includes: Obtain the access data format information specified by the interface protocol; the access data format information includes the read / write data length; The command packet is split according to the length of the read / write data to obtain several commands.
3. The method according to claim 1 or 2, characterized in that, The determination of the channel information for each command includes: The channel information of each command is determined based on the multi-channel storage array, and / or the channel information carried in each command is obtained. The commands obtained from the splitting are defined based on the controller in the storage array. Determining the channel information of each command based on the multi-channel storage array includes: Obtain the channel information of the multi-channel storage array, wherein the channel information corresponds to the memory medium within the storage array, and the memory medium within the storage array has a corresponding physical address; Obtain the physical address of the split command; The physical addresses of the split commands are mapped to the channel information of the memory medium to determine the channel information corresponding to each command.
4. The method according to claim 1, characterized in that, The step of transmitting the split command to the arbitration scheduler corresponding to the target memory medium based on the channel information includes: The commands are transmitted to the controller's internal cache according to the order and priority of command splitting; The command is moved from the controller's internal cache to the arbitration scheduler corresponding to the channel of the target memory medium based on the channel information.
5. The method according to claim 4, characterized in that, The command includes command content and / or data content, and the arbitration scheduler includes a data arbitrator and a command arbitrator; The arbitration scheduler that moves the command to the corresponding channel of the target memory medium based on the channel information includes: When the command type of the command is a write command, the data content of the write command is moved to the data arbitrator of the corresponding channel of the target memory medium according to the channel information and priority of the write command, and the write command is synchronously transmitted to the command arbitrator of the corresponding channel of the target memory medium. And / or, when the command type of the command is a read command, the read command is synchronously transmitted to the command arbitrator of the corresponding channel of the target memory medium according to the channel information of the read command and the priority of the read command.
6. A multi-channel data processing device, characterized in that, This device is applied to server equipment and involves storage components. The storage components are arranged based on a multi-channel storage array. The multi-channel storage array contains an arbitration scheduler for managing channels corresponding to the memory medium. The arbitration scheduler includes a channel arbitrator, which invokes a data arbitrator and a command arbitrator. The device includes: The command splitting module is used to receive a command package for data processing, split the command package into several commands, and generate the command package based on the command for data processing. The channel information determination module is used to determine the channel information for each command; The command processing module is used to determine the target memory medium corresponding to the channel information in the multi-channel storage array, and process the command through the target memory medium; The target memory medium determination submodule is used to obtain the target memory medium in the multi-channel storage array using the channel information; The command transmission unit is used to transmit the split commands to the arbitration scheduler corresponding to the target memory medium based on the channel information. The first command issuing subunit is used to obtain the channel write data cache corresponding to the target memory medium through the channel arbitrator based on the channel information when the command type of the command is a write command, and send the data content in the data arbitrator to the channel write data cache. The second command issuing subunit is used to, when the command type of the command is a read command, obtain the channel read data cache corresponding to the target memory medium based on the channel information through the channel arbitrator, and respond to the command content in the command arbitrator through the memory controller of the target memory medium, and cache the data requested to be read by the command content in the channel read data cache.
7. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the multichannel data processing method as described in any one of claims 1-5.
8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the multi-channel data processing method as described in any one of claims 1 to 5.