Devices and methods for refreshing the sketch circuitry of a sub-bin.

Abstract

This application relates to apparatus and methods for refreshing sketch circuitry for bins. Rows of a memory may have different information retention times. Row addresses can be categorized into different bins based on these retention times. Sketch circuitry can be used to store information about which row addresses are associated with which bins. When an address is generated as part of a refresh operation, the address can be used to generate multiple different hash values, which can be used to index entries in the memory structure. The entry can indicate which bin the address is associated with. Based on the bin information, the memory can refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address).

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. More specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Background Technology

[0002] Information can be stored as physical signals in individual memory cells (e.g., the charge on a capacitive element). The memory may be volatile, and the physical signals may decay over time (which could degrade or destroy the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells by, for example, rewriting the information to restore the physical signals to their initial values.

[0003] Different memory cells can lose information at different rates (e.g., different memory decay rates). To preserve information, the rate at which memory cells are refreshed can be based on the fastest expected rate of information decay for each memory cell. However, this can be inefficient because some memory cells may be over-refreshed, and the memory may unnecessarily spend time refreshing that could have been used to perform other functions. Summary of the Invention

[0004] In one aspect, this application provides an apparatus comprising: a refresh address generator configured to provide an address; a plurality of hash circuits each configured to generate a corresponding one of a plurality of hash values ​​based on the address; logic circuitry configured to examine a plurality of entries in a memory structure, wherein each of the examined entries is associated with one of the plurality of hash values, wherein a binning signal is provided based on the examined entries; and wherein the refresh address generator is configured to determine whether to provide an address as a refresh address based on the binning signal.

[0005] In another aspect, this application provides an apparatus comprising: a storage structure including a plurality of entries, each of the plurality of entries being associated with one of a plurality of hash circuits and one of a plurality of hash values ​​generated by associated hash circuits in the plurality of hash circuits; and a refresh control circuit configured to generate a refresh address, examine a selected entry among the plurality of entries associated with the refresh address, and determine a refresh rate for the refresh address based on the selected entry among the plurality of entries.

[0006] In another aspect, this application provides a method comprising: generating an address; generating a plurality of hash values ​​based on the address; examining a selected entry in a storage structure based on the plurality of hash values; and determining, in part, whether to provide the address as a refresh address based on the value of the selected entry.

[0007] In another aspect, this application provides a system comprising: a memory device including a plurality of word lines; a controller configured to perform access operations on the plurality of word lines, the controller including: an error detection circuit configured to determine whether a word line among the plurality of word lines is a weak word line; a plurality of hash circuits, each configured to generate one of a plurality of hash values ​​based on the weak word line; a memory structure configured to store entries indexed by the plurality of hash values; and a refresh control circuit configured to determine the rate of refresh operations based on the entries in the memory structure. Attached Figure Description

[0008] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure.

[0010] Figure 3 This is a table representing an instance storage structure according to some embodiments of this disclosure.

[0011] Figure 4 This is a flowchart of an example method according to some embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram of a memory and a memory tester according to some embodiments of the present disclosure.

[0013] Figure 6 A set of tables is provided to illustrate the process of writing entries into a storage structure according to some embodiments of the present disclosure.

[0014] Figure 7 This is a flowchart of an example method according to some embodiments of the present disclosure.

[0015] Figure 8 This is a block diagram of a memory system according to some embodiments of the present disclosure. Detailed Implementation

[0016] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and these drawings are shown by way of illustrating specific embodiments in which the described systems and methods can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the systems and methods disclosed herein, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0017] Information in volatile memory devices can be stored in memory cells (e.g., as charge on capacitive elements) and can decay over time. In each bank of a memory array, memory cells can be organized into rows (word lines) and columns (bit lines). Memory cells can be refreshed on a row-by-row basis. To prevent information loss or corruption due to this decay, the memory can undergo background refresh processes, such as automatic refresh operations as part of a self-refresh mode. During a refresh operation, information can be rewritten to the memory cells associated with the word lines to restore their initial state. Automatic refresh operations can be performed sequentially on the word lines of the memory.

[0018] The refresh rate can be selected to prevent information loss, ideally ensuring that each memory cell is refreshed before the information stored in it is lost. Different memory cells (e.g., different rows of memory) can lose information at different rates. For example, some rows (due to manufacturing variations, changes in chip location, etc.) may decay faster than others. It may be useful to group rows together (e.g., bins) based on the expected data decay rate, allowing different groups to be refreshed at different rates. For example, bins of identified 'weak' rows with a higher information decay rate can be refreshed more frequently than bins of identified 'normal' rows with a lower information decay rate. However, this is inefficient when storing information about bins separately for each row of memory. It is desirable to use data structures that allow for more efficient recording of which rows belong to which bins.

[0019] This disclosure presents a sketch circuit for refreshing bins. The sketch circuit represents a data structure applicable to recording information in a manner that does not require separate storage space for each row. The sketch circuit includes a storage structure comprising a table of entries, each of which is indexed by a hash function and the value output by the hash function. For example, a first hash generator (which uses a first hash operation) may provide a first value based on an address that can be associated with a first entry in a table indexed by a first value and a first hash function. A second hash generator (which uses a second hash operation) may provide a second value based on an address that can be associated with a second entry, etc. Since each hash function may include collisions (e.g., each hash value may be associated with several row addresses), each row of entries (e.g., each set of entries associated with a given hash function) may contain far fewer entries than row addresses. Although there may be a certain number of collisions on a given row, using multiple 'rows' (e.g., multiple hash functions) can help preserve information.

[0020] In an instance refresh operation using refresh circuitry, as part of the refresh operation, a refresh address generator can generate addresses (e.g., by using a counter to generate a sequence of addresses). This provides the addresses to multiple hash generators, each of which generates a hash value associated with the address. Each value (and hash circuit) can be used to index entries in the memory structure. Thus, multiple entries (one entry for each hash circuit) can be retrieved. The values ​​of these entries can be used to determine which refresh bin the address belongs to. For example, there may be two bins (normal and weak rows) and each entry in the memory structure may be a binary bit, where a logic high indicates a weak row and a logic low indicates a normal row. If any of the entries retrieved from the memory structure is logic high, then the row can be determined to be a weak row. The refresh control circuitry can refresh weak rows more frequently than normal rows. For example, as part of a refresh cycle, the refresh control circuitry can cycle through all memory addresses, and every other cycle, it can refresh only the rows identified as weak rows.

[0021] While collisions between different row addresses in a hash circuit can cause rows to be incorrectly identified as belonging to a 'weak' bin, using a sketch circuit often allows for an overestimation of the number of rows in a 'weak' bin, which is safer than a structure that allows for false alarms. Using binning also allows for improved performance because the refresh rate for 'normal' rows can be lower than in conventional memory where the refresh rate is set based on the rate required for the weakest row. This frees up memory bandwidth for other tasks and reduces memory power consumption.

[0022] The memory structure may be loaded with information indicating which rows belong to which refresh groups. For example, the memory can be tested and weak rows can be identified. The addresses of the weak rows can be fed to a hash generator, and those values ​​can be used to index entries in the memory structure. In some embodiments, the memory structure may include non-volatile memory elements (e.g., fuses, antifuse, etc.). Therefore, the entries associated with identified weak rows can be changed (e.g., fuses can be blown). In some embodiments, this testing and setup of the memory structure can be performed at the factory. In some embodiments, the memory may be able to perform post-packaging repair (PPR) to change entries in fields. In some embodiments, the controller may include the memory structure and can dynamically change entries based on error detection. This allows the controller to adjust the rate at which different word lines are dynamically refreshed.

[0023] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0024] Semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including multiple memory banks. Figure 1 In one embodiment, the memory array 118 is shown as comprising eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL is performed by row decoder 108, and the selection of bit lines BL and / BL is performed by column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 120 is transmitted to the sense amplifier SAMP via complementary main data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0025] The semiconductor device 100 may employ a plurality of external terminals, including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a CS signal clock terminal for receiving clock CK and / or CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0026] An external clock CK and / or CK is provided to the clock terminal of input circuit 112. The external clocks can be complementary. Input circuit 112 generates an internal clock ICLK based on CK and / or CK. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits included in input / output circuit 122, for example, to a data receiver to time the reception of written data.

[0027] A memory address can be supplied to the C / A terminal. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which indicates a bank of memory in the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD used to indicate the memory cell to be accessed.

[0028] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0029] Device 100 can receive access commands as read commands. When a read command is received and read commands are supplied in a timely manner for the bank address, row address, and column address, read data is read from the memory cells corresponding to the row address and column address in the memory array 118. The read command is received by command decoder 106, which provides an internal command that causes the read data from the memory array 118 to be provided to the read / write amplifier 120. The read data is output to the outside from the data terminal DQ via input / output circuitry 122.

[0030] Device 100 can receive access commands as write commands. When a write command is received and write commands are supplied in a timely manner for the bank address, row address, and column address, write data supplied to the data terminal DQ is written to the memory cells in memory array 118 corresponding to the row and column addresses. The write command is received by command decoder 106, which provides an internal command that causes the write data to be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuit 122 to receive the write data. The write data is supplied to read / write amplifier 120 through input / output circuit 122 and to memory array 118 through read / write amplifier 120 for writing into memory cells MC.

[0031] The device 100 may also receive commands that cause it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be sent to the memory device 100 from an external source. In some embodiments, the self-refresh mode command may be generated periodically by a component of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF may be a pulse signal activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may thereafter be cyclically activated at the desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Therefore, refresh operations may continue automatically. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and may return the device 100 to an idle state and / or resume other operations.

[0032] A refresh signal AREF is supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which refreshes one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, refresh address RXADD may represent a single word line. In some embodiments, refresh address RXADD may represent multiple word lines, which may be refreshed sequentially or simultaneously by row decoder 108. In some embodiments, the number of word lines represented by refresh address RXADD may vary from one refresh address to another. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and supply refresh address RXADD. Refresh control circuitry 116 can be controlled to change details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or it can operate based on internal logic.

[0033] Refresh control circuitry 116 can selectively output a target refresh address (e.g., one or more victim addresses specified by an intruder) or an auto-refresh address (e.g., a sequence of auto-refresh addresses) as a refresh address RXADD. Based on the type of refresh address RXADD (and in some embodiments, one or more additional signals indicating the type of operation), line decoder 108 can perform a target refresh or auto-refresh operation. The auto-refresh address can be a sequence of addresses provided based on the activation of refresh signal AREF. For example, a counter can be used to increment or otherwise 'count' the possible row address values ​​of RXADD. Refresh control circuitry 116 can cycle the sequence of auto-refresh addresses at a rate determined by AREF. A refresh cycle can represent an auto-refresh address generator refreshing each row of memory (e.g., providing each value of the auto-refresh address). In some embodiments, the auto-refresh operation can typically occur at a timing such that the sequence of auto-refresh addresses is expected to have no information degradation between auto-refresh operations for a given word line. In other words, the auto-refresh operation can be performed to refresh each word line at a rate faster than the desired rate of information decay.

[0034] Different row addresses of memory array 118 may have different data decay rates. Therefore, some word lines may require more frequent refreshes to retain their information compared to other word lines. Different word lines may be categorized into different groups or bins based on their performance characteristics (e.g., information decay rate). For example, a first bin may include word lines identified as 'weak' (e.g., those with information decay times below a certain threshold), while a second bin may include the remainder of the word line (e.g., a 'normal' bin). More bins may be used in other instances. During an auto-refresh operation, the auto-refresh address can be examined to see which bin the word line associated with that address belongs to, and the refresh rate of the word line can be determined based on the bin. For example, during every refresh cycle (e.g., cycling through all possible values ​​of the auto-refresh address), an auto-refresh address that is only identified as a portion of a 'weak' bin may be provided as the refresh address RXADD. In other embodiments, other modes of varying refresh operation rates between bins are possible. As described in more detail herein, memory device 100 may store bin information in a sketch circuit.

[0035] Because the refresh control circuit 116 stores the information for binning rows into groups based on its desired information decay rate, the refresh rate of each bin can be set based on the rapidly expected information loss rate within the groups. Therefore, this allows rows grouped into 'stronger' (e.g., normal) bins to be refreshed less frequently than weak rows. Since 'normal' rows are typically expected to be far more numerous than 'weak' rows, this could reduce the overall rate of refresh operations in the memory device 100. Conversely, this could improve the performance of the memory 100, for example, by reducing the power consumption used to refresh the memory 100 and / or by freeing up more time for the memory 100 to perform non-refresh operations to increase bandwidth.

[0036] The refresh control circuit 116 can also determine a target refresh address based on the access patterns of neighboring addresses (e.g., the intruder address corresponding to the intruder row) in the memory array 118, where the target refresh address is the address that needs to be refreshed (e.g., the victim address corresponding to the victim row). The refresh control circuit 116 can use one or more signals from the device 100 to calculate the target refresh address RXADD. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder.

[0037] In some embodiments, the refresh control circuit 116 may sample the current value of the row address XADD provided by the address decoder 104 along the row address bus and determine a target refresh address based on one or more of the sampled addresses. The sampled addresses may be stored in the data storage unit of the refresh control circuit. When the row address XADD is sampled, it may be compared with an address stored in the data storage unit. In some embodiments, an intruder address may be determined based on the sampled address and / or the stored address. For example, a comparison between the sampled address and the stored address may be used to update a count value associated with the stored address (e.g., an access count), and the intruder address may be calculated based on the count value. The refresh address RXADD may then be used based on the intruder address.

[0038] While this disclosure generally relates to identifying intruder and victim word lines and addresses, it should be understood that, as used herein, an intruder word line may not necessarily cause data degradation in adjacent word lines, and a victim word line may not necessarily undergo such degradation. The refresh control circuit 116 may use criteria to determine whether an address is an intruder address, thereby capturing potential intruder addresses rather than definitively determining which addresses are causing data degradation in neighboring victims. For example, the refresh control circuit 116 may determine potential intruder addresses based on access address patterns, and this criterion may include some addresses that are not intruders and miss some addresses that are intruders. Similarly, victim addresses may be determined based on the expectation that which word lines will be affected by an intruder, rather than definitively determining which word lines are experiencing an increased rate of data decay.

[0039] Power supply potentials VDD and VSS are supplied to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifiers (SAMPs) included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0040] Power potentials VDDQ and VSSQ are also supplied to the power terminals. These power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same potentials as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different potentials from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0041] Figure 2 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, Figure 1 The refresh control circuit 116 may include a refresh control circuit 200. The refresh control circuit 200 receives a refresh signal AREF, which controls the refresh control circuit 200 to provide timing for the refresh address RXADD. Figure 2 The text also shows a column decoder 250 (e.g., ...). Figure 1 The row decoder 108 can refresh one or more word lines of the memory array based on the refresh address RXADD.

[0042] The refresh control circuit 200 includes a refresh cycle generator 202 that receives a refresh signal AREF and determines the timing of a refresh operation based on AREF. The refresh cycle generator 202 also determines whether an automatic refresh operation or a target refresh operation should be performed and provides signals indicating the type of refresh operation to be performed, such as a target refresh signal RHR and an internal refresh signal IREF. The refresh control circuit 200 includes a refresh address generator 204 that generates a refresh address RXADD based in part on signals received from the refresh cycle generator 202. During a target refresh operation, a target refresh address generator 206 of the refresh address generator 204 can provide a target refresh address as RXADD. During an automatic refresh operation, an automatic refresh generator 208 of the refresh address generator 204 can generate an automatic refresh address Pre_RXADD and provide it to a refresh binning circuit 210, which can indicate which bin the automatic refresh address Pre_RXADD belongs to. Based on this information, the refresh address generator 204 can determine whether to provide the automatic refresh address Pre_RXADD as the refresh address RXADD.

[0043] The refresh cycle generator 202 can receive a refresh signal AREF and can provide internal refresh signals IREF and / or RHR at regular intervals based on the refresh signal AREF. Signals IREF and RHR can be used to indicate which type of refresh operation should be performed. For example, in some embodiments, an active IREF but inactive RHR may indicate an automatic refresh operation, while both IREF and RHR being active may indicate a target refresh operation. Other modes of signals may be used in other embodiments. In response to the activation of the refresh signal AREF, the refresh cycle generator 202 may indicate that one or more refresh operations should be performed. In some embodiments, in response to a single activation of AREF, the refresh cycle generator 202 may execute multiple 'pumps' each associated with a refresh operation. In example operation, when AREF is activated, the refresh cycle generator 202 may execute 2, 4, 6, or 8 pumps each associated with a refresh operation. More or fewer refresh operations may also be used depending on the activation of AREF. The refresh cycle generator 202 may use internal logic to determine whether each refresh operation should be a target refresh operation or an automatic refresh operation.

[0044] Refresh address generator 204 may include circuitry for generating a refresh address RXADD when a target refresh operation is requested (e.g., when both IREF and RHR are active). Target refresh address generator 206 may generate a target refresh address and provide it as RXADD. For example, target address generator 206 may trace intruder word lines and provide addresses associated with victim word lines of those intruder word lines as refresh addresses RXADD. For example, the refresh address may represent word lines adjacent to the intruder (e.g., R+1 and R-1). Other relationships (e.g., R+ / -2, R+ / -3, etc.) may also be used.

[0045] Refresh address generator 204 may include auto-refresh address generator 208, which can provide an auto-refresh address Pre_RXADD as a refresh address in response to an auto-refresh operation (e.g., IREF active and RHR inactive). The auto-refresh address may be generated from a sequence of refresh addresses. For example, a counter may be used to count the value of Pre_RXADD such that all word lines are refreshed during a refresh cycle. In some embodiments, the auto-refresh address Pre_RXADD may be associated with more than one word line. For example, with a normal row address (e.g., ... Figure 1 Compared to the XADD in the previous method, the auto-refresh address may be truncated and can be associated with each word line that shares the truncated portion. The auto-refresh address Pre_RXADD can be provided to the refresh bin circuit 210 to determine which bin the auto-refresh address Pre_RXADD belongs to. The refresh address generator 204 can then determine, in part, whether to provide the address Pre_RXADD as the refresh address RXADD based on the bin information.

[0046] The refresh bin control circuit 210 uses a sketch data structure to store information about which rows are part of which refresh bins. The refresh bin control circuit 210 uses a data storage structure 214, which stores a table of values ​​indicating whether a given row is in a specific bin. (See also: ...) Figure 3 To explain in more detail, a table can have entries organized into rows indexed by a hash function and columns indexed by values ​​output by the hash function. It should be understood that references to the organization of entries in terms of rows and columns refer to a way of conceptualizing the organization of entries. Entries can be physically organized in any way.

[0047] The refresh bin control circuit 210 includes multiple hash circuits 212. Each hash circuit 212 (Hash0 to HashM) can collectively receive an auto-refresh address Pre_RXADD and provide corresponding values ​​Value0 to ValueM. The hash circuit 212 can receive the address Pre_RXADD as an input value and provide a corresponding value based on the address Pre_RXADD. The address Pre_RXADD can have a first number of bits (e.g., 17 bits). The value can have a second number of bits, less than the first number. Therefore, the total number of possible states for the value can be less than the number of states for the address Pre_RXADD. Therefore, a conflict can exist between the input state (e.g., the value of Pre_RXADD) and the output state (e.g., the value of Value) provided by each hash circuit 212. For example, each state of Value can represent 8, 16, 32, or some other number of possible values ​​for Pre_RXADD. In some embodiments, each of the values ​​output by the hash circuit 212 can have the same number of bits. If each hash circuit 212 can provide N total possible values, and there are M total hash circuits 212, then the storage structure 214 can hold N×M total entries.

[0048] Each of the refresh circuits 212 can hash the input value in a different manner by implementing different hash operations (e.g., Pre_RXADD). In some embodiments, this can be attributed to each hash circuit 212 implementing different hash functions. In some embodiments, the difference can be caused by different seed values ​​input to each of the hash circuits 212. For example, each hash circuit 212 may have the same hash function, but may be implanted in different ways. In some embodiments, mixing different hash functions with seeds can be used to change the hash operations between the hash circuits 212.

[0049] Entry(s) associated with (e.g., indexed by) the provided values ​​Value0 to ValueM (and the hash circuitry providing those values) can be retrieved and provided to logic circuitry 216. Logic circuitry 216 can use the entries to determine which bin the provided address Pre_RXADD belongs to and can provide a signal Bin to refresh address generator 204. In some embodiments, only two bins may exist (e.g., normal and weak rows) and the bin signal Bin may be a binary signal. In some embodiments, the bin signal may have more states (e.g., more bits) to indicate more bins.

[0050] In some embodiments, memory structure 214 may represent non-volatile memory. For example, memory structure 214 may include non-volatile memory elements, such as fuses or antifuse. In some embodiments, entries in memory structure 214 may be set as part of a testing procedure (e.g., in a factory). In some embodiments, memory may be able to modify entries in memory structure 214 as part of a post-packaging repair (PPR) operation. For example, if a row is determined to be weak in a field, the PPR operation can be used to modify one or more entries in memory structure 214. Figures 5 to 7 The loading of entries in the storage structure is discussed in more detail.

[0051] In an example embodiment, two bins may exist, and the refresh address generator 204 may refresh addresses in the weak bin at twice the frequency of refreshing addresses in the normal bin. For example, in the first refresh cycle, bin information may be ignored, and all addresses Pre_RXADD may be refreshed. After the first refresh cycle is completed, a flag may be set. Although the flag is set, during the second refresh cycle, address Pre_RXADD may be provided only as RXADD and refreshed if the signal Bin indicates that address Pre_RXADD is a weak row. At the end of the second refresh cycle, the flag may be reset, and the behavior of the first refresh cycle may be repeated. In this way, the refresh control circuit 200 may alternate between refreshing every row and refreshing only rows in the weak bin in each refresh cycle.

[0052] In some embodiments, the refresh control circuit 200 may include two auto-refresh address generators. Different auto-refresh generators may each generate addresses in a manner similar to auto-refresh address generator 208. When the bin signal is active, the first auto-refresh address generator can provide its address as the refresh address, while when the bin signal is inactive, the second auto-refresh address generator can provide its address as the refresh address. The refresh cycle generator can operate the two auto-refresh address generators at different rates (e.g., using internal signals) to refresh weak and non-weak addresses at different rates. If more than two bins are used (e.g., the Bin signal has more than two states), additional auto-refresh address generators can be provided, such as one auto-refresh address generator for each state of the Bin signal.

[0053] Figure 3 Table 300 is an instance storage structure according to some embodiments of the present disclosure. In some embodiments, table 300 may represent the logical organization of storage structure 214. Table 300 may represent a simplified instance having three hash functions (Hash0 to Hash2), each of which can produce a value with 6 possible values ​​(e.g., 0 to 5).

[0054] Table 300 shows an example scenario where an address (e.g., Pre-RXADD) is provided and hashed into three values ​​by each of three hash circuits (Hash0, Hash1, and Hash2). Each hash circuit has independently produced a distinct value for each of these hash circuits in this case. Therefore, Hash0 has been provided with a value of 4, Hash1 with a value of 1, and Hash2 with a value of 0. As indicated by the shaded entries in Table 300, each hash value and its output can be used to index the entries in Table 300. Therefore, the entries retrieved in this example will be 1, 0, and 1.

[0055] Figure 3 The example implementation illustrates an embodiment where the stored entries are binary to represent two possible bins (e.g., weak and normal). In this example, there is disagreement among the retrieved entries (1, 0, and 1) regarding which bin the input address belongs to. Logic circuits (e.g., Figure 2 (216) can determine which bin an address belongs to based on the retrieved entry. For example, if any of the retrieved entries is logic high, the logic circuit can set the bin signal Bin at a high logic level (e.g., indicating a weak bin). Therefore, in the case indicated by the shaded entry, the bin signal will be active.

[0056] To consider another example, the second address could cause Hash0 to provide a value of 2, Hash1 to provide a value of 1 (indicating a collision between the first and second addresses in the hash circuit Hash1), and Hash2 to provide a value of 2. Since all these entries are 0, the total bin signal can be 0, thus indicating a normal row.

[0057] Figure 4 This is a flowchart of an example method according to some embodiments of the present disclosure. In some embodiments, method 400 may be implemented by one or more of the devices or systems described herein. Method 400 may generally represent a process for determining which bin an automatic refresh belongs to.

[0058] Method 400 may typically begin with a box 410 describing the generated address. The address may be an automatically refreshed address (e.g., Figure 2 (Pre_RXADD). As part of the sequence of automatically refreshed addresses, the addresses can be generated by an address generator. For example, as part of a refresh cycle, the method may include: generating a first address as part of a first refresh operation; generating a second address as part of a second refresh operation, and so on, until a final address (e.g., the last address in a sequence of addresses covering all word lines of the memory) is generated. In the next refresh operation, as part of a second refresh cycle, the first address may be generated again. The steps described in blocks 420 to 440 may be performed for each address generated.

[0059] Box 410 may typically be followed by box 420, which describes generating multiple hash values ​​based on an address. Method 400 may include providing the generated addresses collectively to each of a plurality of hash circuits. Method 400 may include performing different hash operations on the address through each of the hash circuits, and providing a corresponding one of a plurality of hash values ​​based on the hashed address.

[0060] Box 420 may typically be followed by box 430, which describes examining selected entries in a data storage structure based on a plurality of hash values. The data storage structure may include entries logically organized in a table indexed by hash functions and hash values. Box 420 may include reading each of the selected entries by indexing each of the plurality of hash values ​​and the hash circuitry associated with said hash values.

[0061] Block 430 may typically be followed by block 440, which describes determining whether to provide an address as a refresh address based in part on the value of the selected entry. For example, block 430 may include comparing selected entries read from the data storage structure (e.g., with logic circuitry 216) to determine whether any of the selected entries indicates an address associated with a weak row (e.g., any of the selected entries is a high logic level), and if so, then providing a binning signal at the active level. Refresh control circuitry (e.g., Figure 1 116 and / or Figure 2 Method 400 can determine whether to provide an address as a refresh address based on the binning signal. For example, method 400 may include alternating between providing an address as a refresh address during a first refresh cycle when the binning signal is at an active level and providing an address as a refresh address during a second refresh cycle without considering the binning signal.

[0062] Figures 5 to 7 Discussions are used to load information into data storage structures (e.g., Figure 2 Example devices and processes in (214). Typically described based on external test equipment coupled to the memory during the initial testing process (e.g., at the factory, during packaging, etc.). Figures 5 to 7 Some operations are performed in the test instrument and others are performed by the memory. However, it should be understood that in other exemplary embodiments, various functions and circuits may be arranged differently between the test instrument and the memory. For example, the memory may include built-in test circuitry instead of an external test instrument, which can perform similar functions to the test instrument without requiring an external test instrument. Similarly, although described relative to specific criteria used to load information into the data storage structure and determine which addresses belong to which bins. Figures 5 to 7 However, different binning systems and criteria for determining which row goes into which bin can be used in other example implementations.

[0063] Figure 5 This is a block diagram of a memory and a memory tester according to some embodiments of the present disclosure. In some embodiments, memory 502 may represent Figure 1 The memory device 100. Figure 5 A tester 510 is shown coupled to memory 502. Tester 510 can test the retention time of rows in memory and determine which bin a given row should be assigned to. Tester 510 stores information on memory 502 by writing information to storage structure 506 of memory 502 (e.g., by changing the state of one or more non-volatile memory elements).

[0064] Memory 502 includes memory array 504 (e.g., Figure 1 118) and storage structure 506 (e.g., Figure 2 (214). The storage structure 506 may include non-volatile storage elements, such as fuses and / or antifuses. In some embodiments, the storage structure 506 may be a fuse array of the memory 502.

[0065] Tester 510 may be an external device coupled to memory 502 to perform various tests on memory 502. For example, the tester may locate defective rows, measure the retention time of rows (e.g., the rate of information decay), perform various other tests, and combinations thereof. For simplicity, tester 510 will be discussed only in terms of testing the retention time of rows to determine which refresh bin to place the rows into. It should be understood that the tester can perform any number of tests and may include... Figure 5 Additional components not shown in the image.

[0066] exist Figure 5 In the example view, tester 510 includes test logic 512, which can be used to measure the information retention time of one or more rows of memory array 504. Based on the measured retention time, the test logic can classify the tested row address Test_XADD as normal or as a weak address Weak_XADD. The identified weak row addresses Weak_XADD can be provided to one or more hash circuits 514, which can determine which entries in the memory structure will be changed. In this case, the entries can then be written to memory structure 506 via fuse logic circuit 516, which can change the state of fuses (and / or antifuses) in memory structure 506 based on the entries provided by hash circuit 514. In embodiments where fuses / antifuses are not part of memory structure 506, different methods can be used to write entries to memory structure 506, and fuse logic 516 can be omitted.

[0067] Test logic 512 may execute one or more test procedures to measure the retention time of a given row in order to determine the rate at which information is lost in the row. For example, test logic 512 may write test data to the row specified by address Test_XADD, wait for a period of time, and then read test data from the row. The read test data may be compared with the written test data to determine if there is any difference. If a difference exists, then test logic 512 may determine that the row Test_XADD being tested cannot retain data for at least the specified time period. In some embodiments, test logic 512 may repeat this process for different time lengths and determine the maximum amount of test time for the row to retain information. Based on the time length, it may be determined whether the row is a weak row. In some embodiments, test logic 512 may test a single time length and determine whether the row is a weak row or a normal row based on whether there are any errors in the read information.

[0068] Hash circuit 514 can receive the identified weak row Weak_XADD from test logic 512. Hash circuit 514 can match hash circuits in memory (e.g., Figure 2 The operation of hash circuit 212). In some embodiments, the tester 510 may use the hash circuit on memory 502, and hash circuit 514 may be omitted. Hash circuit 514 may include a plurality of hash circuits, each of which can generate a hash value based on the input address Weak_XADD.

[0069] The hash value generated by hash circuit 514 can be provided to fuse logic circuit 516, which can write those values ​​into memory structure 506. For example, fuse logic 516 can blow fuses (and / or antifuses) in memory structure 506 to set the value of an entry to a location indexed by the hash circuit and the value. Figure 6 The instance procedure for writing values ​​to storage structure 506 is described in more detail.

[0070] In some embodiments, memory 502 may use internal test logic (e.g., built-in test circuitry or BIST) instead of external tester 510. The internal test logic performs tests and determines that one or more rows are weak (e.g., do not meet memory retention criteria). Memory 502 may then perform post-packaging operations (similar to post-packaging repair or PPR operations) to change the state of one or more entries in memory structure 506. In this way, weak rows identified in fields (or rows that become weak after factory testing) can have their binning information added to memory structure 506.

[0071] Figure 6 This is a set of tables illustrating the process of writing entries to a storage structure according to some embodiments of the present disclosure. In some embodiments, tables 610 to 630 may represent the process of writing entries to a storage structure using a tester (e.g., Figure 5 The fuse logic circuit 516) is written into the memory structure (e.g., Figure 5 Entries 506). Tables 610 to 630 are largely similar to... Figure 3 Table 300, and therefore for the sake of simplicity, will not be... Figure 6 Repeat about Figure 3 The details explained.

[0072] Table 610 shows the first identified weak address Weak_XADD0 written to the memory structure. In this example, as indicated by the shaded entries, the first hash value is 4, the second hash value is 1, and the third hash value is 0. Therefore, the entries indexed by these values ​​can be changed. In this case, a fuse indexed by the values ​​and hash function (e.g., as indicated by a value of 1) can be blown to indicate which entries are associated with the weak row (e.g., Weak_XADD0).

[0073] Table 620 shows the second identified weak address, Weak_XADD1, which has a first hash value of 2, a second hash value of 3, and a third hash value of 0. The entries indexed by Hash0 and the value of 2, and those indexed by Hash1 and the value of 3, can be modified (e.g., circuit breaking). In this case, a collision occurs in the third hash function between the first address Weak_XADD0 and the second address Weak_XADD1 (e.g., both produce a value of 0). Since this entry has been modified, it can be maintained.

[0074] Table 630 shows the third identified weak address, Weak_XADD2, which has a first hash value of 3, a second hash value of 2, and a third hash value of 5. These entries can be modified. It should be noted that even though the three addresses have been loaded into the storage structure, due to collisions, there may not be three modified entries on each row.

[0075] Figure 7 This is a flowchart of an example method according to some embodiments of the present disclosure. Method 700 may represent loading information into a storage structure (e.g., Figure 2 214 and / or Figure 5 The method in (506). In some embodiments, method 700 may be performed by one or more of the devices or systems described herein.

[0076] Method 700 may typically begin with block 710, which describes a row of a test memory array. The test may include measuring the information retention time of the row. In some embodiments, block 710 may include detecting errors in information read from the memory, rather than performing a specific test operation.

[0077] Box 710 may typically be followed by box 720, which describes the identification of weak line addresses based on tests. Weak line addresses may be associated with weak word lines. Weak line addresses may be identified based on a metric of information retention time exceeding a threshold.

[0078] Box 720 may typically be followed by box 730, which describes generating a hash value based on a weak row address. For example, the weak row address may be provided to a set of hash circuits, each of which may perform a different hash operation on the weak row address. The hash operation may be a different hash function, receive different seeds, or a combination thereof. The hash operation may match the hash operation used on memory for retrieving information (e.g., Figure 2 Hash circuit 212).

[0079] Box 730 may generally be followed by box 740, which describes changes to entries in a storage structure based on hash values. For example, an entry may be part of a table indexed by different hash operations (e.g., different hash circuits) and by hash values ​​generated using those operations. In some embodiments, non-volatile memory elements may be used to store the entries. In some embodiments, the entries may be binary, and if a hash value associated with a weak row address indicates the entry, then the entry may be set to an active level (or maintained at an active level).

[0080] In some embodiments, the steps of method 700 may be performed by a tester external to the memory device. For example, method 700 may be performed as part of testing the memory device in a factory. In some embodiments, the steps of method 700 may be performed by the memory itself. For example, built-in self-test circuitry may perform the test, and a process similar to post-packaging repair may be used to modify entries in the memory structure.

[0081] In some embodiments, the steps of method 700 may be performed by a controller operating the memory device. As part of a specific test operation, the controller may test the memory, and / or may test the memory by monitoring error detection circuitry. For example, if an error is detected in data read from a particular row, this may indicate that the behavior is weak. The controller may then update a storage structure that may be located on the controller. The storage structure may include volatile storage elements and may be dynamically updated over time. In this manner, method 700 may include dynamically assigning rows to different bins by writing entries to the storage structure.

[0082] Figure 8 This is a block diagram of a memory system according to some embodiments of the present disclosure. The memory system may include a memory controller 800 and a memory 802. The controller 800 can provide various commands and signals (e.g., along...) Figure 1 The memory 802 is operated using the C / A terminal, DQ terminal, and CK terminal. Figure 8 The embodiment shows a controller 800, which is implemented previously, for example in Figure 2 The embodiments described herein are of many features and structures of memory components. For the sake of brevity, however, will not be... Figure 8 Repeat in detail those structures and operations similar to those described with respect to the previous diagrams. Figure 8 Specific structure and operation.

[0083] Controller 800 includes error detection circuitry 820. Error detection circuitry 820 determines whether information read from memory array 804 of memory 802 contains errors. In some embodiments, error detection circuitry 820 may be coupled to error correction code (ECC) circuitry that may be located on memory 804 or controller 800. Error detection circuitry 820 may count the number of times errors are detected in information read from word lines. When the count meets or exceeds a threshold (which may be 1), error detection circuitry 820 may mark the row address as a weak row. Error detection circuitry 820 may also use other criteria to identify weak rows. For example, error detection circuitry 820 may be coupled to various test circuitry (e.g., built-in self-test circuitry of memory 802) that can perform test operations to locate weak rows. The identified weak row Err_XADD may be provided to refresh bin control circuitry 810.

[0084] The refresh bin control circuit 810 can generate multiple hash values ​​(e.g., Value0 to ValueM) based on each of a plurality of hash circuits 812, each of which can perform a different hash operation. These values ​​can be used to index and retrieve multiple entries for a storage structure. Logic circuit 816 can then modify these entries to indicate that the entries are associated with an identified weak row address Err_XADD. Figure 8 In this embodiment, the storage structure can be dynamically updated over time because new weak rows have been identified.

[0085] The refresh control circuit 822 can generate an automatic refresh address Pre_XADD, and in a manner roughly similar to... Figures 2 to 4 The operation described herein retrieves bin information from refresh bin control circuit 810. Refresh control circuit 822 can then determine the frequency of refreshing the auto-refresh address Pre_RXADD based on the bin information (e.g., based on the state of the bin signal Bin). In some embodiments, the auto-refresh address Pre_XADD associated with weak rows can be refreshed more frequently than other rows.

[0086] In some cases, it may be advantageous to have refresh bin control 810 and refresh control circuitry 812 on the controller 800. The controller 800 knows when to provide an address as the refresh address RXADD or not to provide an address. Because weak rows are identified, the overall rate of refresh operations can be reduced, and it is not necessary to set the overall rate of refresh operations based on the retention time of the weakest row. The reduced rate of refresh operations allows the controller 800 to perform more access operations on the memory 802, thereby increasing the system bandwidth.

[0087] As used herein, signal activation can refer to any portion of the signal waveform in which the circuit responds. For example, if the circuit responds to a rising edge, then a signal switching from a low level to a high level can be activated. One type of activation is a pulse, where the signal switches from a low level to a high level for a period of time and then returns to a low level. This can trigger circuitry that responds to rising edges, falling edges, and / or signals at high logic levels. Those skilled in the art will understand that while embodiments may be described with respect to a particular type of activation (e.g., active high) used by a particular circuit, other embodiments may use other types of activation (e.g., active low).

[0088] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate apparatus or apparatus portion of a system, apparatus, or method according to the invention.

[0089] Finally, the foregoing discussion is intended only to illustrate the system of the invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in particular detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Thus, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: Refresh the address generator, which is configured to provide addresses; A plurality of hash circuits, each configured to generate a corresponding one of a plurality of hash values ​​based on the address, each of the plurality of hash values ​​comprising a plurality of bits, wherein each of the plurality of hash circuits is configured to perform a different hash operation; A logic circuit configured to examine multiple entries in a memory structure, wherein each of the examined entries is associated with one of multiple hash values, and binning signals are provided based on the examined entries; and The refresh address generator is configured to determine whether to provide the address as a refresh address based on the binning signal.

2. The device of claim 1, wherein the refresh address generator is configured to provide the address in response to a refresh signal.

3. The device according to claim 1, wherein the address is an automatically refreshed address.

4. The device of claim 1, wherein if any of the plurality of items being inspected is active, then the sub-box signal is provided in the active state.

5. The device of claim 1, wherein if the sub-box signal is active, then the refresh address generator is configured to provide the address as the refresh address.

6. The device of claim 5, wherein if the sub-bin signal is inactive and the refresh cycle flag is active, then the refresh address generator is configured not to provide the address.

7. The device of claim 6, wherein the state of the refresh cycle flag changes whenever the refresh address generator completes a refresh cycle.

8. The device of claim 1, wherein the storage structure includes a non-volatile storage element configured to store the plurality of entries.

9. The apparatus of claim 1, wherein each of the plurality of hash circuits is configured to perform a different hash operation.

10. The device of claim 1, further comprising a second refresh address generator configured to provide a second address, wherein if the binning signal is active, the address is provided as the refresh address, and wherein if the binning signal is inactive, the second address is provided as the refresh address.

11. The device according to claim 1, wherein the compartment signal represents one of two or more states of the compartment signal.

12. An apparatus comprising: A storage structure comprising multiple entries, each of the multiple entries being associated with one of a plurality of hash circuits and one of a plurality of hash values ​​generated by an associated hash circuit of the plurality of hash circuits, wherein each of the plurality of hash values ​​comprises a plurality of bits, and each of the plurality of hash circuits is configured to perform a different hash operation; A refresh control circuit is configured to generate a refresh address, examine a selected entry among a plurality of entries associated with the refresh address, and determine a refresh rate for the refresh address based on the selected entry among the plurality of entries.

13. The device of claim 12, further comprising a plurality of hash circuits, each of the plurality of hash circuits being configured to generate a corresponding one of a plurality of hash values ​​based on the refresh address, wherein the selected entry of the plurality of entries is selected based on the plurality of hash values.

14. The device of claim 12, wherein the refresh control circuitry is configured to refresh the refresh address more frequently based on the fact that any one of the selected entries of the plurality of entries is active.

15. The device of claim 12, wherein the storage structure and the refresh control circuit are part of a memory.

16. The device of claim 15, wherein, as part of the testing process of the memory, the state of a plurality of entries is set by a tester.

17. The device of claim 15, wherein the state of a plurality of entries is set via the memory as part of a post-packaging repair operation.

18. A method comprising: Generate an address; Multiple hash values ​​are generated based on the address via multiple hash circuits, each of the multiple hash values ​​comprising multiple bits, and each of the multiple hash circuits being configured to perform a different hash operation; The selected entry in the storage structure is examined based on the multiple hash values; Whether to provide the address as a refresh address is determined in part based on the value of the selected entry.

19. The method of claim 18, further comprising generating the address as part of an automatic refresh operation.

20. The method of claim 18, further comprising generating the plurality of hash values ​​according to each of a plurality of hash operations.

21. The method of claim 18, further comprising providing the address as the refresh address if any of the selected entries is active.

22. The method of claim 18, further comprising: Test the rows of the memory array; Based on the test, at least one weak line is identified; Generate multiple hash values ​​based on the at least one weak row; and The values ​​of entries in the storage structure are set based on the multiple hash values.

23. The method of claim 22, further comprising testing the row with a tester.

24. The method of claim 22, further comprising setting the value of the entry by changing the state of one or more non-volatile memory elements.

25. A system comprising: A memory device that includes multiple word lines; A controller configured to perform access operations on the plurality of word lines, the controller comprising: An error detection circuit is configured to determine whether a word line among the plurality of word lines is a weak word line; A plurality of hash circuits, each configured to generate one of a plurality of hash values ​​based on the weak word line, wherein each of the plurality of hash values ​​comprises a plurality of bits, and each of the plurality of hash circuits is configured to perform a different hash operation; A storage structure configured to store entries indexed by the plurality of hash values; A refresh control circuit configured to determine the rate of refresh operations based on the entries in the memory structure.

26. The system of claim 25, wherein the controller is configured to refresh the weak word line more frequently than the non-weak word line.

27. The system of claim 25, wherein the controller is configured to dynamically update the entries in the storage structure.

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