sram cell

Abstract

An SRAM cell includes multiple transistors, a set of contacts coupling the multiple transistors, byte lines electrically coupled to the multiple transistors, bit lines and bit lines electrically coupled to the multiple transistors, VDD wiring electrically coupled to the multiple transistors, and VSS wiring electrically coupled to the multiple transistors. As the minimum feature size (λ) of an SRAM cell gradually decreases across different technology nodes, the area of ​​the SRAM cell, represented by the square of the minimum feature size, is the same or substantially the same.

Description

Technical Field

[0001] This invention relates to a memory structure, and more particularly to an SRAM structure capable of precisely controlling the size to effectively reduce the size of a Static Random Access Memory (SRAM) structure. Background Technology

[0002] Improvements in integrated circuit performance and cost have been primarily achieved through process scaling techniques based on Moore's Law. However, process variations in transistor performance as they miniaturize to 28nm (or lower) processes present a challenge. In particular, shrinking SRAM devices to increase storage density, lowering operating voltage (VDD) to reduce standby power consumption, and increasing yield required to achieve larger capacity SRAMs are becoming increasingly difficult to achieve.

[0003] SRAM is one of the most commonly used memory types. An SRAM typically consists of an SRAM array and peripheral circuitry, including column address decoders, row address decoders, and input / output circuitry. An SRAM array comprises multiple SRAM cells, each containing a static latch and two cross-coupled inverters. Therefore, it does not require periodic DRAM refresh to retain stored information, as long as there is sufficient power supply voltage for the cell: a high voltage VDD and a low voltage VSS. The same high voltage VDD and low voltage VSS are also connected to the SRAM peripheral circuitry (decoders, I / O circuitry). Furthermore, the high voltage VDD typically corresponds to a logic "1" stored in the SRAM, while the low voltage VSS corresponds to a logic "0" stored in the SRAM.

[0004] Figure 1 The SRAM cell architecture is illustrated, namely a six-transistor (6-T) SRAM cell. It consists of two cross-coupled inverters (PMOS pull-up transistors PU-1 and PU-2 and NMOS pull-down transistors PD-1 and PD-2) and two access transistors (NMOS transmission gate transistors PG-1 and PG-2). The high potential voltage VDD is coupled to the PMOS pull-up transistors PU-1 and PU-2, and the low potential voltage VSS is coupled to the NMOS pull-down transistors PD-1 and PD-2. When the byte line (WL) is enabled (i.e., a column is selected in the array), the access transistors turn on and connect the storage node (Node-1 / Node-2) to the vertically running bit line (BL and BLB).

[0005] Figure 2This is a "stick diagram" illustrating the wiring and connections between the six transistors of an SRAM. A stick diagram typically only includes the active region (vertical red lines) and the gate line (horizontal blue lines). Of course, there are many more connections, directly coupling the six transistors on one hand, and on the other hand, coupling the byte line (WL), bit line (BL and BL Bar), high-level voltage VDD, and low-level voltage VSS, etc.

[0006] However, due to interference between contact sizes, even when the process is miniaturized to 28nm or lower (the so-called "minimum feature size", "λ" or "F"), the total area of ​​the SRAM cell is reduced by the metal wiring connecting the byte line (WL), bit line (BL and BLB), high potential voltage VDD, and low potential voltage VSS, etc. 2 or F 2 This indicates a significant increase when the minimum feature size decreases, such as Figure 3 (See J. Chang et al., “15.1A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuit Schemes for High-Density and Low-VMIN Applications,” IEEE International Conference on Solid State Circuits (ISSCC), 2020, pp. 238-240).

[0007] When the minimum feature size decreases, the total area of ​​the SRAM cells (in λ) 2 or F 2The reason for the rapid increase in the number of transistors (indicated by the following) is as follows: A traditional 6T SRAM has 6 transistors connected by multiple interconnections. The first interconnection metal layer M1 connects to the gate and the diffusion layers (often called the transistor's "diffusion region") of the source and drain regions. Furthermore, there is a need to add a second interconnection metal layer M2 and / or a third interconnection metal layer M3 to facilitate signal transmission (e.g., byte lines WL and / or bit lines (BL and BL Bar)). Since only the first interconnection metal layer M1 is needed, and a plug structure Via-1 composed of some type of conductive material is formed to connect the second interconnection metal layer M2 and the first interconnection metal layer M1, there is no need to increase the die size. One vertical structure formed by connecting the diffusion region to the first interconnection metal layer M1 via a contact Con is called "Diffusion-Con-M1". Similarly, another structure formed by connecting the gate to the first interconnection metal layer M1 via a contact structure can be called "Gate-Con-M1". Furthermore, if the first interconnect metal layer M1 needs to be connected to the second interconnect metal layer M2 via a plug Via1, the resulting connection structure is called "M1-Via1-M2". A more complex interconnect structure connecting the gate-level to the second interconnect metal layer M2 can be called "Gate-Con-M1-Via1-M2". Additionally, the stacked interconnect system may also include structures such as "M1-Via1-M2-Via2-M3" or "M1-Via1-M2-Via2-M3-Via3-M4". However, since the gates and diffusion regions of the two access transistors (such as the through-gate transistors PG-1 and PG-2 illustrated in Figure 1A) must be connected to the byte lines WL and / or bit lines (BL and BL Bar) disposed in the second interconnect metal layer M2 or the third interconnect metal layer M3, and in conventional SRAM structures such interconnects must first pass through the first interconnect metal layer M1. That is, the interconnect system of state-of-the-art SRAM structures does not allow the gate or diffusion region to be directly connected to the second interconnect layer M2 without passing through the first interconnect layer M1. Therefore, the necessary space between one interconnect structure connected to the first interconnect layer M1 and another interconnect structure connected to the first interconnect layer M1 will still increase the die size, and in some cases, such wiring connections may hinder the intention to directly connect the second interconnect metal layer M2 to the region of the first interconnect metal layer M1 using certain effective channels.Furthermore, it is difficult to form a self-alignment structure between the plug Via1 and the contact, as the plug Via1 and the contact are connected to their respective interconnect systems.

[0008] Furthermore, in a traditional 6T SRAM cell, at least one NMOS transistor and one PMOS transistor are located in adjacent p-type doped substrate and n-type well regions, respectively. These two regions are formed adjacent to each other in a tightly packed region, thus forming a parasitic junction structure known as an n+ / p / n / p+ parasitic bipolar device. Its outline is shown in Figure 2A, from the n+ region of the NMOS transistor to the p-type well region, then to the adjacent n-type well region, and finally to the p+ region of the PMOS transistor. Significant noise can occur at the n+ / p or p+ / n junction. Abnormally large currents may flow abnormally through this n+ / p / n / p+ junction, potentially causing some operations of the CMOS circuit to suddenly stop and leading to circuit failure of the entire chip. This anomaly, known as latch-up, is detrimental to CMOS operation and must be avoided. One way to improve immunity to latch-up (a weakness of CMOS) is to increase the distance between the n+ and p+ regions. Increasing the distance between the n+ and p+ regions to avoid latch-up problems also increases the size of the SRAM cells.

[0009] Therefore, when the minimum feature size decreases, how should the SRAM cell be redesigned to make the λ 2 Maintaining the total area of ​​the represented SRAM cells within an acceptable range is a challenge. Summary of the Invention

[0010] This invention provides an SRAM structure. An SRAM cell includes multiple transistors, a set of contacts coupled to the multiple transistors, byte lines electrically coupled to the multiple transistors, bit lines and bit lines electrically coupled to the multiple transistors, a VDD connection electrically coupled to the multiple transistors, and a VSS connection electrically coupled to the multiple transistors. Furthermore, as the minimum feature size (λ) of this SRAM cell gradually decreases at different technology nodes, the area size of the SRAM cell, represented by the square of the minimum feature size, is the same or substantially the same.

[0011] According to another aspect of the invention, as the minimum feature size of the SRAM cell gradually decreases from 28nm (e.g., 16nm, 10nm, 7nm, 5nm, 3nm, etc.), the area size of the SRAM cell, expressed as the square of the minimum feature size, is the same or substantially the same.

[0012] According to another aspect of the invention, when λ decreases from 28 nm to 5 nm, the area size of the SRAM cell is 84λ. 2 ~139λ 2 between.

[0013] According to another aspect of the invention, the length of a transistor is between 3 and 4λ.

[0014] According to another aspect of the invention, the gate region of one of the plurality of transistors is directly connected to the source region or drain region of the transistor through the first metal interconnect without needing to pass through another metal layer below the first metal interconnect.

[0015] According to another aspect of the invention, the VDD wiring or VSS wiring is distributed beneath the original silicon surface of the substrate in which the plurality of transistors are formed.

[0016] According to another aspect of the invention, the bottom surface of the n+ region of the NMOS transistor in the plurality of transistors is completely isolated by a first insulator, and the bottom surface of the p+ region of the PMOS transistor in the plurality of transistors is completely isolated by a second insulator.

[0017] According to another aspect of the invention, the edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

[0018] According to another aspect of the invention, the set of contacts includes a set of first contacts and a set of second contacts, the set of first contacts being connected to a first metal layer, and the set of second contacts being connected to a second metal layer but disconnected from the first metal layer.

[0019] One object of the present invention may be to provide an SRAM structure with a smaller area. The SRAM cell includes multiple transistors, a set of contacts coupling the multiple transistors, byte lines electrically coupling the multiple transistors, bit lines and bit lines electrically coupling the multiple transistors, a VDD connection electrically coupling the multiple transistors, and a VSS connection electrically coupling the multiple transistors, wherein the area of ​​the SRAM cell is 84λ when the minimum feature size is 5nm. 2 ~672λ 2 Within this range, when the minimum feature size is 7nm, the area of ​​the SRAM cell is 84λ. 2 ~440λ 2Within this range, when the minimum feature size is between 10 nm and greater than 7 nm, the area of ​​the SRAM cell is 84λ. 2 ~300λ 2 Within this range, when the minimum feature size is between 16nm and greater than 10nm, the SRAM cell size is 84λ. 2 ~204λ 2 Within this range, when the minimum feature size is between 22nm and greater than 16nm, the area of ​​the SRAM cell is 84λ. 2 ~152λ 2 Within this range, when the minimum feature size is between 28 nm and greater than 22 nm, the area of ​​the SRAM cell is 84λ. 2 ~139λ 2 Within the range.

[0020] Another embodiment of the present invention provides an SRAM structure directly connected from the gate / diffusion layer to a metal layer. The SRAM includes a plurality of transistors, a plurality of contacts coupled to the plurality of transistors, a first metal layer disposed on and electrically coupled to the plurality of transistors, a second metal layer disposed on the first metal layer and electrically coupled to the plurality of transistors, and a third metal layer disposed on the second metal layer and electrically coupled to the plurality of transistors. The plurality of contacts includes a set of first contacts and a set of second contacts, the set of first contacts being connected to the first metal layer, and the set of second contacts being connected to the second metal layer but disconnected from the first metal layer.

[0021] According to another aspect of the invention, the vertical length of the first contact is shorter than the vertical length of the second contact.

[0022] According to another aspect of the invention, the gate region of one of the plurality of transistors is directly connected to the source region or drain region of the transistor through the first metal interconnect without needing to pass through another metal layer below the first metal interconnect.

[0023] According to another aspect of the invention, the bottom surface of the n+ region of the NMOS transistor in the plurality of transistors is completely isolated by a first insulator, and the bottom surface of the p+ region of the PMOS transistor in the plurality of transistors is completely isolated by a second insulator, wherein the edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

[0024] Another object of the present invention may be to provide an SRAM structure with microtransistors. The SRAM includes a plurality of transistors. One of the transistors includes: a gate structure having a length, a channel region, a first conductive region electrically coupled to the channel region, and a first contact hole located above the first conductive region, wherein the periphery of the first contact hole is independent of a photolithography process.

[0025] According to another aspect of the invention, the first contact hole includes a periphery surrounded by a circumference of the first conductive region.

[0026] According to another aspect of the invention, the gate region of one of the plurality of transistors is directly connected to the source region or drain region of the transistor through the first metal interconnect without needing to pass through another metal layer below the first metal interconnect.

[0027] The advantages and spirit of the present invention can be understood from the following description together with the accompanying drawings. These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the various drawings and the preferred embodiments illustrated therein.

[0028] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a standard 6T SRAM.

[0030] Figure 2 It corresponds to Figure 1 The bar chart of the 6T SRAM is shown, where the active region corresponds to the vertical line and the gate line corresponds to the horizontal line.

[0031] Figure 3 It is based on currently available process specifications for the total area of ​​SRAM cells of different process sizes λ (or F), expressed in terms of λ. 2 (or F) 2 The diagram is represented by ).

[0032] Figure 4 This is a schematic diagram illustrating the cross-section of traditional NMOS and PMOS structures.

[0033] Figure 5 This is a top view of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) used in the SRAM according to the present invention.

[0034] Figure 6 This is a cross-sectional view illustrating the pad oxide layer, the pad nitride layer on the substrate, and the STI-oxide 1 formed in the substrate.

[0035] Figure 7 This is a schematic diagram illustrating the true gate (TG) and the pseudo shielding gate (DSG) formed above the active region.

[0036] Figure 8 This diagram illustrates the spin-on dielectric (SOD) being deposited and the carefully designed gate photomask being deposited and etched.

[0037] Figure 9 This is a schematic diagram illustrating the removal of the nitride layer above the dummy shielding gate (DSG), the DSG, the corresponding portion of the dielectric insulator, and the p-type substrate 102 corresponding to the DSG.

[0038] Figure 10 This is a schematic diagram illustrating the removal of the gate photomask layer, the etching of SOD, and the deposition of oxide 2 layer to form STI-oxide 2.

[0039] Figure 11 The diagram illustrates the deposition and etching of oxide 3 layers to form oxide 3 spacers, the formation of a lightly doped drain (LDD) in a p-type substrate, the deposition and back etching of a nitride layer to form a nitride spacer, and the removal of the dielectric insulator.

[0040] Figure 12 This is a diagram illustrating an intrinsic silicon electrode grown using selective epitaxial growth (SEG) technology.

[0041] Figure 13 This diagram illustrates the deposition and etchback of the CVD-STI-oxide 3 layer, the removal of the intrinsic silicon electrode, and the formation of the source (n+ source) and drain (n+ drain) of the mMOSFET.

[0042] Figure 14 This diagram illustrates the deposition and etching of oxide spacers to form contact hole openings.

[0043] Figure 15(a) is a schematic diagram illustrating the deposition of a layer of SOD to fill the voids on the substrate and the use of CMP to smooth the surface.

[0044] Figure 15(b) is a top view of Figure 15(a).

[0045] Figure 16 This is a diagram illustrating the photoresist layer formed on the structure in Figure 15(b).

[0046] Figure 17 This diagram illustrates anisotropic etching techniques used to remove the nitride cap layer from the exposed gate extension region to reveal the conductive metal gate layer.

[0047] Figure 18(a) illustrates the removal of the photoresist layer and SOD layer to form an opening region on top of the source and drain regions and to form spacers.

[0048] Figure 18(b) is a top view of Figure 18(a).

[0049] Figure 19(a) is a diagram illustrating the emerging Metal-1 interconnect layer.

[0050] Figure 19(b) is a top view of Figure 19(a), in which the gate is connected to the source region through the Metal-1 layer.

[0051] Figure 20(a) is a top view of the transistor of the new 6T SRAM up to the construction stage where multiple openings are made on top of the gate extension region and the drain region.

[0052] Figures 20(b) and 20(c) are two cross-sections of the transistor configuration stage along cut lines 1 and 2 shown in Figure 20(a).

[0053] Figure 21(a) is a top view of the transistors of the new 6T SRAM up to the fabrication stage where it uses selective epitaxial growth (SEG) to grow heavily doped conductive silicon plugs (CoP).

[0054] Figures 21(b) and 21(c) are two cross-sections of the transistor construction stage along cut lines 1 and 2 shown in Figure 21(a).

[0055] Figure 22(a) is a top view of the transistors of the new 6T SRAM up to the fabrication stage where an oxide layer or low-k dielectric layer is deposited above the height of these conductor pillars (CoP).

[0056] Figures 22(b) and 22(c) are two cross-sections of the transistor construction stage along cut lines 1 and 2 shown in Figure 22(a).

[0057] Figure 23(a) is a top view of the transistors of the new 6T SRAM up to the formation stage of depositing the metal M1 layer and thin oxide layer on the metal M1 layer, and using these exposed head conductor pillars (CoP) as seeds to form heavily doped silicon pillars (CoP2) through the SEG method.

[0058] Figures 23(b) and 23(c) are two cross-sections of the transistor construction stage along cut lines 1 and 2 shown in Figure 23(a).

[0059] Figure 24(a) is a top view of the transistors of the new 6T SRAM, showing the construction stage of depositing an oxide or low-k dielectric layer between and above the metal M1 layer, followed by the deposition of the metal M2 layer and the connection of the heavily doped silicon pillars (CoP2).

[0060] Figures 24(b) and 24(c) are two cross-sections of the transistor construction stage along cut lines 1 and 2 shown in Figure 24(a).

[0061] Figures 25(a) and 25(b) are cross-sectional views illustrating the PMOS and NMOS transistors used in an SRAM cell, respectively.

[0062] Figure 26(a) shows a top view of the combined structure of the new PMOS 52 and the new NMOS 51 shown in Figures 25(a) and 25(b).

[0063] Figure 26(b) is a cross-sectional view of the combination of the new PMOS 52 and the new NMOS 51 along the cut line (Y-axis) in Figure 26(a).

[0064] Figure 27 It is a cross-sectional view illustrating a combination of traditional PMOS and NMOS transistors.

[0065] Figure 28(a) is a top view illustrating another combination structure of the new PMOS 52 and the new NMOS 51 shown in Figures 25(a) and 25(b).

[0066] Figure 28(b) is a cross-sectional view of the combination of the new PMOS 52 and the new NMOS 51 along the cut line (X-axis) in Figure 28(a).

[0067] Figure 29 This is a cross-sectional view illustrating another combination of traditional PMOS and NMOS transistors.

[0068] Figure 30 This is a top view illustrating another combination of PMOS and NMOS transistors used in the new SRAM cell.

[0069] Figure 31(a) is Figure 2 The schematic diagram of the "stick diagram" shown is shown in Figure 31(b), which is a stick diagram of a novel 6T SRAM with dimensions according to the present invention.

[0070] Figure 32 This is a list illustrating the definitions of the different photomask layers used in Figures 33-37.

[0071] Figures 33(a) to (g) illustrate one embodiment of the present invention.

[0072] Figures 34(a) to (h) illustrate another embodiment of the invention.

[0073] Figures 35(a) to (h) illustrate another embodiment of the present invention.

[0074] Figures 36(a) to (h) illustrate another embodiment of the present invention.

[0075] Figures 37(a) to (h) also illustrate another embodiment according to the present invention.

[0076] Figure 38 The diagram illustrates different technology nodes from three different foundries A, B, and C, and the SRAM cell region of this invention (denoted as λ). 2express).

[0077] Explanation of reference numerals in the attached figures

[0078] 100: Transistor (mMOSFET)

[0079] 101: Gate Structure

[0080] 103: Source Extreme

[0081] 105: Quarantine Zone

[0082] 107: Drain

[0083] 109: Contact Hole

[0084] 111: Contact Hole

[0085] 102:Substrate

[0086] 302: Pad oxide layer

[0087] 304: Nitride layer on the bonding pad

[0088] 402: Dielectric insulator

[0089] 602: Gate layer

[0090] 604: Nitride layer

[0091] 608: Silicon Valley

[0092] 802: Gate photomask layer

[0093] 702: Spin-on Dielectric (SOD)

[0094] 1502: Spacer layer

[0095] 1504: Lightly Doped Drain (LDD)

[0096] 1506: Nitride spacer layer

[0097] 1602: Intrinsic silicon electrode

[0098] 1704: Source Region (n+ Source)

[0099] 1706: Drain region (n+ drain)

[0100] 1802: Oxide spacer

[0101] 1902: Photoresist layer

[0102] 1903: Gate Extension Region

[0103] 1904: Oxides

[0104] 2012, 2010: Opening

[0105] 2110: Conductor Post (CoP)

[0106] 2120: Dielectric layer

[0107] 2140: M1 layer

[0108] 2180: Silicon Pillar

[0109] 33: Gate structure

[0110] 331: Gate dielectric layer

[0111] 332: Gate conductive layer

[0112] 333: Dielectric Coverage

[0113] 341: Oxide layer

[0114] 342: Nitride layer

[0115] 34: Isolation material

[0116] 35: Source Region

[0117] 36: Drain region

[0118] 48: Local isolation

[0119] 491: STI-1 layer

[0120] 492: STI-2 layer; 51: NMOS transistor

[0121] 52: PMOS transistor

[0122] 55: Source Region

[0123] 56: Drain region; 551: Lightly doped drain (LDD)

[0124] 552: Heavy P+ doped region

[0125] 553: Tungsten

[0126] G(L): Length

[0127] G(W): Width

[0128] S(L): Length

[0129] S(W): Width

[0130] D(L): Length

[0131] D(W): Width

[0132] CS(L): Length of the opening

[0133] CS(W): Width of the opening

[0134] CD(L): Length of the opening

[0135] CD(W): Width of the opening

[0136] WL: Byte Line

[0137] BL, BLB: Bitline

[0138] VDD: High potential voltage

[0139] VSS: Low voltage potential

[0140] PD-1, PD-2, PG-1, PG-2, PU-1, PU-2: Transistor M1: First interconnect metal layer

[0141] M2: Second inner interconnect metal layer

[0142] M3: Third Inner Interconnect Metal Layer

[0143] Xn+Xp: Preserve edge distance

[0144] TEC-Si: Composite source / drain region Detailed Implementation

[0145] In traditional 6T SRAM cells, even with miniaturization of the manufacturing process down to 28nm or smaller (the so-called "minimum feature size," "λ," or "F"), the transistor size cannot be proportionally reduced. This invention discloses a novel SRAM structure in which the linear dimensions of the source, drain, and gate of the transistors are precisely controlled, and these linear dimensions can be as small as the minimum feature size (λ). Therefore, when two adjacent transistors are connected together through their drain / source, the distance between the gate edges of the two adjacent transistors can be as small as 2λ. Furthermore, within the drain region (source and gate regions), the linear dimensions of the source, drain, and gate contact holes can be less than λ, for example, 0.6λ to 0.8λ.

[0146] Figure 5 This is an example of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) 100 used in SRAM according to the present invention. Figure 5As shown, the mMOSFET 100 includes: (1) a gate structure 101 having a length G(L) and a width G(W); (2) on the left side of the gate structure 101, a source 103 having a length S(L) and a width S(W) of a linear dimension from the edge of the gate structure 101 to the edge of the isolation region 105; (3) on the right side of the gate structure 101, a drain 107 having a length D(L) and a width D(W) of a linear dimension from the edge of the gate structure 101 to the edge of the isolation region 105; (4) at the center of the source 103, a contact hole 109 formed by self-alignment technology has an opening with a length and width labeled CS(L) and CS(W), respectively; and (5) also at the center of the drain 107, a contact hole 111 formed by self-alignment technology has an opening with a length and width labeled CD(L) and CD(W), respectively. The lengths G(L), D(L), and S(L) can be precisely controlled to a minimum feature size λ. Furthermore, the length and width of the openings labeled CS(L) and CS(W) or the length and width of the openings labeled DS(L) and DS(W) can be less than λ, for example, 0.6λ to 0.8λ.

[0147] The manufacturing process of the above-described mMOSFET 100 used in the SRAM of this invention is briefly described below. A detailed description of the structure of the mMOSFET 100 and its manufacturing process is provided in U.S. Patent Application No. 17 / 138,918, filed December 31, 2020, entitled “MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE / DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD”, and the entire contents of U.S. Patent Application No. 17 / 138,918 are incorporated herein by reference.

[0148] like Figure 6 As shown, a pad oxide layer 302 and a pad nitride layer 304 are formed on the substrate 102. The active region of the mMOSFET is also defined, and a portion of the silicon material outside the active region is removed to create a trench structure. An oxide-1 layer is deposited in the trench structure and etched back to form a shallow trench isolation (STI-oxide 1) 306 below the original horizontal surface of the silicon substrate (“HSS”).

[0149] The pad oxide layer 302 and the pad nitride layer 304 are removed, and a dielectric insulator 402 is formed over the HSS. Then, a gate layer 602 and a nitride layer 604 are deposited over the HSS, and the gate layer 602 and the nitride layer 604 are etched to form the true gate of the mMOSFET and a dummy shield gate with the desired linear distance from the true gate, as shown below. Figure 7 As shown. Figure 7 As shown, the length of the true gate is λ, the length of the pseudo-shielding gate is also λ, and the distance between the edge of the true gate and the pseudo-shielding gate is also λ.

[0150] Then, a spin-coated dielectric (SOD) 702 is deposited, followed by etch-back of the SOD 702. A well-designed gate mask layer 802 is then formed using lithography techniques, such as... Figure 8 As shown. Subsequently, using anisotropic etching technology, the nitride layer 604 above the dummy shielding gate (DSG) is removed, as are the DSG portions of the dielectric insulator 402 corresponding to the DSG and the p-type substrate 102 corresponding to the DSG, as shown. Figure 9 As shown.

[0151] In addition, such as Figure 10 As shown, the gate photomask layer 802 is removed, SOD 702 is etched, STI-oxide-2 1002 is deposited, and then etched back. Next, an oxide-3 layer is deposited and etched back to form an oxide-3 spacer layer 1502, a lightly doped drain (LDD) 1504 is formed in the p-type substrate 102, a nitride layer is deposited and etched back to form a nitride spacer layer 1506, and the dielectric insulator 402 is removed, as shown. Figure 11 As shown.

[0152] Furthermore, intrinsic silicon electrodes 1602 are grown using selective epitaxial growth (SEG) technology, such as... Figure 13 As shown. Then, a CVD-STI-oxide 3-layer 1702 is deposited and etched back to remove the intrinsic silicon electrode 1602, and the source region (n+ source) 1704 and drain region (n+ drain) 1706 of the mMOSFET are formed, as shown. Figure 13As shown. Since the source region (n+source) 1704 and drain region (n+drain) 1706 are formed between the mMOSFETs, and the true gate (TG) and CVD-STI-oxide 3 layer 1702 are initially occupied by the pseudo-shielded gate (DSG), the length and width of the source region (n+source) 1704 (or drain region (n+drain) 1706) are small as λ. The opening of the source region (n+source) 1704 (or drain region (n+drain) 1706) can be smaller than λ, for example, 0.8λ. This opening can be reduced if an additional oxide spacer 1802 is formed, such as... Figure 14 As shown.

[0153] Furthermore, the new SRAM structure allows the first interconnect metal layer (M1 layer) to directly connect to the gate, source, and / or drain regions via self-aligned miniaturized contacts, without the need for conventional contact hole-aperture photomasks and / or Matel-0 conversion layers for M1 connections. Figure 13 Next, a layer of SOD 1901 is deposited to fill the vacancies on the substrate, including the openings in the source region (n+source) 1704 (or the drain region (n+drain) 1706). CMP is then used to planarize the surface, as shown in Figure 15(a). Figure 15(b) is a top view of Figure 15(a), illustrating multiple fingers in the horizontal direction.

[0154] Furthermore, by using a carefully designed photomask and implementing a photoresist layer 1902, some stripe patterns along the X-axis in Figure 15(b) have individual spaces of length GROC(L) to expose the gate extension area along the Y-axis in Figure 15(b), the result is as follows: Figure 16 The top view is shown in the figure. The most aggressive design rule is when GROC(L) = λ, as... Figure 16 As shown. Then, anisotropic etching is used to remove the nitride-cap layer in the exposed gate extension region, exposing the conductive metal gate layer. Figure 17 ).

[0155] Subsequently, the photoresist layer 1902 is removed, followed by the SOD layer 1901, exposing the openings on top of the source region 1704 and drain region 1706 again. A layer of oxide 1904 with a well-designed thickness is then deposited, and spacers are formed on the openings of the source region 1704 and drain region 1706, as well as the four sidewalls of the exposed gate extension region 1903, using anisotropic etching. Thus, naturally stacked contact hole openings are formed in the exposed gate extension region, source region 1704, and drain region 1706, respectively. Figure 18(a) shows a cross-section of this transistor structure. Figure 18(b) shows a top view of the transistor structure in Figure 18(a). The vertical length CRMG(L) of the opening in the exposed gate extension region 1903 is less than the length GROC(L), which can be λ.

[0156] Finally, a Metal-1 layer 1905 with a carefully designed thickness is formed to fill all the holes of the aforementioned contact hole openings, creating a smooth, flat surface after the wafer surface morphology is completed. All connections between these contact hole openings are then created using lithography to achieve the necessary Metal-1 interconnect network, as shown in Figure 19(a). Figure 19(b) is a top view of the mMOSFET shown in Figure 19(a). Thus, this Metal-1 layer accomplishes the task of achieving contact filling and plug connections to the gate and source / drain, as well as direct interconnects connecting all transistors. This eliminates the need for expensive and very tightly controlled conventional contact hole lithography and subsequent very difficult contact hole drilling processes, especially given the most challenging aspect of further shrinking transistors to billions of level geometries. Furthermore, it eliminates the need for fabricating metal plugs in the contact hole openings and CMP processes to achieve metal studs with complex integrated circuit processing steps (e.g., creating zero-metal structures that are certainly required for certain forward-looking technologies).

[0157] Furthermore, conventional SRAM cells or standard cells may not allow the gate or diffusion region to be directly connected to the second interconnect metal layer M2 without passing through the first interconnect metal layer M1 (or may not allow the first interconnect metal layer M1 to be directly connected to the third interconnect metal layer M3 without passing through the second interconnect metal layer M2 structure, or the first interconnect metal layer M1 to be directly connected to the xth interconnect metal layer Mx without passing through interconnect structures such as M2 to Mx). This invention discloses a novel interconnect structure in which the gate or diffusion region (source / drain) is self-aligned and directly connected to the second interconnect metal layer M2 without passing through the transition connection of the first interconnect metal layer M1 via a vertical conductive plug composed of contacts Contact-A and Via1-A. The contacts Contact-A and Via1-A are formed at other locations on the same die during the fabrication of the contacts Contact and the plug Via1, respectively. In this way, the necessary space between the first interconnect metal layer M1 and the other interconnect metal layer, as well as the wiring obstruction problem in the interconnect, will be reduced. The following is a brief introduction to this new interconnect structure, in which the gate and diffusion region are directly connected to the second interconnect metal layer M2 in a self-aligned manner without the transition connection through the first interconnect metal layer M1.

[0158] Figure 20 illustrates cross-sectional and top views of the transistors in the new 6T SRAM, up to the fabrication stage where multiple openings are formed at the top of the gate extension region and diffusion region. Figure 20(a) is a top view of the transistor fabrication stage. Figures 20(b) and 20(c) are two cross-sections of the transistor fabrication stage along cut lines 1 and 2 shown in Figure 20(a), respectively. Similar to... Figure 17 As shown in Figure 18(b), apertures 2010 and 2012 are formed on top of the gate extension region and the drain region, respectively. Surrounding these apertures 2010 and 2012 is an insulator 2014 (e.g., oxide or low-k dielectric). One key difference is that the gate extension region also includes a silicon region 608, which can be part of the polysilicon gate when the polysilicon gate is used as the gate conductor 602, or a layer formed on the gate metal when the gate metal is used as the gate conductor 602. As shown in Figure 20(c), the gate extension region also includes a nitride layer 604 above the silicon region 608. As shown in Figure 20(b), aperture 2010 exposes the silicon region 608 by etching at least a portion of the nitride layer 604.

[0159] Next, selective epitaxial growth (SEG) (or selective atomic layer deposition) is used to grow heavily doped conductive silicon plugs 2110, called conductor pillars (CoP), as shown in Figure 21 (Figure 21(a) is a top view of this transistor fabrication stage, and Figures 21(b) and 21(c) are two cross-sections of this transistor fabrication stage along cut lines 1 and 2 in Figure 21(a), respectively). Then, an oxide layer or a low-k dielectric layer 2120 is deposited to a height higher than these conductor pillars 2110. Then, CMP (Chemical Mechanical Polishing) or etch-back techniques are used to obtain a flat wafer surface, as shown in Figure 22 (Figure 22(a) is a top view of this transistor fabrication stage, and Figures 22(b) and 22(c) are two cross-sections of this transistor fabrication stage along cut line 1 and cut line 2, respectively, as shown in Figure 22(a). The "exposed heads" of the conductor pillars (CoP) 2110 form very useful landing pads (LPads) for subsequent connection shaping between the metal interconnects and the conductor pillars (CoP) 2110 to connect the gate region or drain region, respectively.

[0160] Furthermore, a metal M1 layer 2140 and a thin oxide layer 2160 are deposited on top of the metal M1 layer 2140. Using photolithography, a suitable oxide removal technique, and then a metal etching technique, the design pattern of the interconnects within the metal M1 is defined. Here, specific conductor pillar areas designed to connect the gate region or drain region respectively are directly connected to the subsequent metal M2 layer and are not covered by the metal M1 layer 2140, but instead expose the heads of their conductor pillars (CoP) 2110 again. Through using the heads of these exposed conductor pillars (CoP) 2110, heavily doped silicon pillars (CoP2) 2180 can be grown on them, and those heavily doped silicon pillars (CoP2) 2180 will be used entirely as Via conductors (referred to as Via1-A), as shown in Figure 23 (Figure 23(a) is a top view of this transistor fabrication stage, and Figures 23(b) and 23(c) are two cross-sections of this transistor fabrication stage along cut lines 1 and 2 shown in Figure 23(a), respectively).

[0161] A layer of oxide or low-k dielectric 2410 is then deposited, thick enough to isolate the metal M1 layer 2140 from the subsequent metal layers. The dielectric layer 2410 can be made slightly thinner than the height of the doped silicon pillar (CoP2) 2180, allowing some exposed areas to naturally function as Via conductors (referred to as Via1-A). The metal M2 layer 2420 is then deposited and defined using lithography techniques to complete the metal M2 interconnects. Therefore, a direct connection can be achieved between the metal M2 layer and the gate or diffusion region, i.e., M2-Via1.A-CoP-Gate or M2-Via1.A-CoP-Drain (or Source), as shown in Figure 24 (Figure 24(a) is a top view of this transistor construction stage, and Figures 24(b) and 24(c) are two cross-sections of this transistor construction stage along cutting lines 1 and 2 shown in Figure 24(a), respectively). Of course, based on this embodiment, other metal layers or dielectric layers may also exist between the first metal layer and the second metal layer, and the conductor pillars may be connected to the second metal layer, but disconnected from the first metal layer and other metal layers.

[0162] Furthermore, this invention discloses a novel SRAM structure in which the n+ and p+ regions of the source and drain regions in NMOS and PMOS transistors are completely isolated by insulators. Such insulators not only increase the risk of latch-up but also increase the isolation distance into the silicon substrate to separate the contacts in the NMOS and PMOS transistors, thereby reducing the surface distance between contacts (e.g., 3λ), and consequently, the size of the SRAM. A novel SRAM structure in which the n+ and p+ regions of the source and drain regions of NMOS and PMOS transistors are completely isolated by insulators is briefly described below. A detailed description of the novel combined structure of PMOS and MNOS is provided in U.S. Patent Application No. 17 / 318,097, filed May 12, 2021, entitled “COMPLEMENTARY MOSFET STRUCTURE WITH LOCALIZED ISOLATIONS IN SILICONSUBSTRATE TO REDUCE LEAKAGES AND PREVENT LATCH-UP,” the entire contents of which are incorporated herein by reference.

[0163] Please refer to Figures 25(a) and 25(b). Figure 25(a) is a cross-sectional view of PMOS transistor 52, and Figure 25(b) is a cross-sectional view of NMOS transistor 51. The gate structure 33 includes a gate dielectric layer 331 and a gate conductive layer 332 (e.g., gate metal) formed on a horizontal or pristine surface of a semiconductor substrate (e.g., a silicon substrate). A dielectric cover 333 (e.g., a composite of an oxide layer and a nitride layer) is located above the gate conductive layer 332. Furthermore, an insulator 34, which may include a composite of an oxide layer 341 and a nitride layer 342, may be used above the sidewalls of the gate structure 33. Trenches are formed in the silicon substrate, with all or at least a portion of the source region 35 and the drain region 36 located in their respective trenches. The source (or drain) region in the PMOS transistor 32 may include a P+ region or other suitable doped distribution regions (e.g., gradually or progressively changing from the P- region and the P+ region). Furthermore, a local isolation 48 (e.g., a nitride or other high-k dielectric material) is located in one trench and below the source region, while another local isolation 48 is located in another trench and below the drain region. This local isolation 48 is below the horizontal silicon surface (HSS) of the silicon substrate and may be referred to as a local isolation silicon substrate (LISS) 48. The LISS 48 may be a composite of a thick nitride layer or a dielectric layer. For example, the local isolation or LISS 48 may include a composite local isolation comprising an oxide layer (referred to as an Oxide-3V layer 481) covering at least a portion of the sidewalls of the trench and another oxide layer (Oxide-3B layer 482) covering at least a portion of the bottom wall of the trench. The Oxide-3V layer 481 and the Oxide-3B layer 482 may be formed via a thermal oxidation process. The composite local isolation 48 also includes a nitride layer 483 (referred to as Nitride-3) located above the Oxide-3B layer 482 and in contact with the Oxide-3V layer 481. The nitride layer 483 or Nitride-3 can be replaced with any suitable insulating material, provided that the Oxide-3V layer remains in optimal condition and is properly designed. Furthermore, the STI (Shallow Trench Isolation) regions in Figures 25(a) and 25(b) can include a composite STI 49 comprising an STI-1 layer 491 and an STI-2 layer 492, wherein the STI-1 layer 491 and STI-2 layer 492 can be respectively made of thick oxide materials using different processes.

[0164] Furthermore, the source (or drain) regions in Figures 25(a) and 25(b) may include a composite source region 55 and / or a drain region 56. For example, as shown in Figure 25(a), in a PMOS transistor 52, the composite source region 55 (or drain region 56) includes at least a lightly doped drain (LDD) 551 and a heavily P+ doped region 552 in a trench. In particular, it should be noted that the lightly doped drain (LDD) 551 is close to the exposed silicon surface with a uniform (110) crystal orientation. The exposed silicon surface has a vertical boundary with a suitable recess thickness compared to the edge of the gate structure, which is marked as TEC (etched-away transistor thickness, defined as the sharp edge of the effective channel length) in Figure 25(a). The exposed silicon surface is substantially aligned with the gate structure. The exposed silicon surface may be the terminal face of a transistor channel.

[0165] The lightly doped drain (LDD) 551 and the heavily P+ doped region 552 can be formed from the exposed TEC region using selective epitaxial growth (SEG) technology (or other suitable techniques such as atomic layer deposition (ALD) or selective ALD-SALD growth), serving as a seed crystal to form a new well-structured (110) lattice on the LISS region. This seed crystal has no seed effect on altering the crystal structure of the newly formed crystal (110) of the composite source region 55 or drain region 56. This newly formed crystal (including the lightly doped drain (LDD) 551 and the heavily P+ doped region 552) can be named TEC-Si, as shown in Figure 25(a). In one embodiment, the TEC is aligned or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewalls of the LDD 551 opposite to the TEC can be aligned with the sidewalls of the spacer 34. Similarly, the TEC-Si of the composite source / drain region of the NMOS transistor 51 (including the LDD region and the heavily N+ doped region) is shown in Figure 25(b). The composite source (or drain) region may also include tungsten (or other suitable metal) plugs 553, which are formed to be horizontally connected to the TEC-Si portion to complete the entire source / drain region, as shown in Figures 25(a) and 25(b). As shown in Figure 25(a), the active channel current flowing to the future metal interconnect, such as the Metal-1 layer, passes through the LDD 551 and the heavily doped conductive region 552 to reach the tungsten 553 (or other metal), directly entering through some good metal-to-metal ohmic contacts connected to Metal-1, whose resistance is much lower than that of conventional silicon-to-metal contacts.

[0166] A combined structure of the new PMOS52 and the new NMOS51 is shown in Figure 26(a), which is a top view, and Figure 26(b) shows a cross-sectional view of the new combined structure. The new PMOS52 and the new NMOS51 are along the cut line (Y-axis) in Figure 26(a). As shown in Figure 26(b), there is a composite local isolation (or LISS48) between the bottom of the P+ source / drain region of the PMOS and the n-type N-well, and thus another composite local isolation (or LISS48) between the bottom of the N+ source / drain region of the NMOS and the p-type P-well or substrate. In this newly invented CMOS structure shown in Figure 26(a), the advantage of the bottom of the n+ region and the p+ region being completely isolated by an insulator is clearly shown. As shown in Figure 26(b), the possible latch-up path from the bottom of the P+ region of the PMOS to the bottom of the N+ region of the NMOS is completely blocked by the LISS. On the other hand, in conventional CMOS structures, the n+ and p+ regions are not completely isolated by an insulator, such as Figure 27 As shown, possible latching paths exist from the n+ / p junction through the p-well / n-well junction to the n / p+ junction, including lengths a, b, and c. Figure 27 Therefore, from the perspective of component wiring, the reserved edge distance (Xn+Xp) between the NMOS and PMOS in Figure 26(b) may be less than Figure 27 The edge distance (Xn+Xp) is preserved in the range, and (Xn+Xp) may be around 2 to 4λ, for example, 3λ.

[0167] Another combination structure of the new PMOS52 and the new NMOS51 is shown in Figure 28(a), which is a top view. Figure 28(b) shows a cross-section of the combination of the new PMOS52 and the new NMOS51 along the cut line (X-axis) shown in Figure 28(a). As shown in Figure 28(b), this results in a longer path from the n+ / p junction via the p-well (or p-substrate) / n-well junction to the n / p+ junction. Possible latching paths from the LDD-n / p junction through the p-well / n-well junction to the n / LDD-p junction include lengths ①, ② (bottom wall length of one LISS region), ③, ④, ⑤, ⑥, ⑦ (bottom wall length of another LISS region), and length ⑧ marked in Figure 28(b). On the other hand, in Figure 29 In the traditional CMOS structure combining PMOS and NMOS structures shown, the possible latch-up paths from the n+ / p junction through the p-well / n-well junction to the n / p+ junction only include lengths d, e, f, and g (e.g., ...). Figure 29 (As shown). This possible latching path in Figure 28(b) is more... Figure 29The length of the reserved edge (Xn+Xp) between the NMOS and PMOS in Figure 28(b) is therefore, from the perspective of component wiring, the reserved edge distance (Xn+Xp) can be less than [the length of the reserved edge distance]. Figure 29 The margin of preservation is (Xn+Xp). For example, the margin of preservation (Xn+Xp) can be around 2 to 4λ, such as 3λ.

[0168] Furthermore, in conventional SRAMs, the metal lines for high-potential voltage VDD and low-potential voltage VSS (or ground) are distributed above the raw silicon surface of the silicon substrate. This distribution can interfere with other metal lines and byte lines (WL), bit lines (BL and BLBar), or other connection metal lines if there is insufficient space between these lines. This invention discloses a novel SRAM structure in which the metal lines for high-potential voltage VDD and / or low-potential voltage VSS can be distributed below the raw silicon surface of the silicon substrate. Therefore, interference between contact sizes can be eliminated, and even with a reduction in the size of the SRAM cell, wiring of metal lines connecting byte lines (WL), bit lines (BL and BLBar), high-potential voltage VDD, and low-potential voltage VSS can be avoided. Figure 27 As shown, in the drain region of PMOS52, tungsten or other metal material 553 is directly coupled to the N-well of VDD. On the other hand, in the source region of NMOS51, tungsten or other metal material 553 is directly coupled to the P-well or P-type substrate. Therefore, in the new SRAM structure, the source / drain openings originally used for electrically coupling the source / drain regions to metal layer 2 or metal layer 3 for VDD or ground connection can be omitted. A detailed description of the structure and its fabrication process is provided in U.S. Patent Application No. 16 / 991,044, filed August 12, 2020, entitled “TRANSISTOR STRUCTURE AND RELATED INVERTER,” the entire contents of which are incorporated herein by reference.

[0169] In summary, the new 6T SRAM cell has at least the following advantages:

[0170] (1) The linear dimensions of the source, drain, and gate of transistors in SRAM are precisely controlled, and the linear dimensions can be as small as the minimum feature size Lamda(λ). Therefore, when two adjacent transistors are connected together through the drain / source, the length of the transistor will be as small as 3λ, and the distance between the gate edges of two adjacent transistors can be as small as 2λ. Of course, for tolerance purposes, the length of the transistor will be around 3λ to 4λ.

[0171] (2) The first metal interconnect (M1 layer) directly connects the gate, source and / or drain regions through self-aligned miniaturized contacts, without using conventional contact hole opening photomasks and / or Metal-0 conversion layers for M1 connection.

[0172] (3) The gate and / or diffused (source / drain) regions are directly connected to the M2 interconnect in a self-aligned manner, without a transition layer M1. Therefore, the necessary space between one M1 interconnect and another M1 interconnect and some blocking issues in wiring connections will be reduced.

[0173] (4) The n+ and p+ regions of the source / drain regions of NMOS and PMOS transistors are completely isolated by insulators. Such insulators can not only increase resistance to latch-up problems, but also increase the isolation distance to the silicon substrate to separate the contacts in NMOS and PMOS transistors, thereby reducing the surface distance between contacts (e.g., 3λ) and reducing the size of SRAM.

[0174] (5) The metal lines used for high-potential voltage VDD and / or low-potential voltage VSS in the SRAM cell can be distributed below the original silicon surface of the silicon substrate. Therefore, interference between contact sizes can be avoided by reducing the size of the SRAM cell between wirings, and metal lines connecting byte lines (WL), bit lines (BL and BL Bar), high-potential voltage VDD, and low-potential voltage VSS can be avoided. In addition, in the new SRAM structure, the source / drain region openings originally used to electrically connect the source / drain regions to metal layer 2 or metal layer 3 for VDD or ground connection can be omitted.

[0175] Figure 31(a) is Figure 2 A copy of the diagram is shown, illustrating the wiring and connections between the six transistors of the SRAM. Figure 31(b) is a stick diagram of the new 6T SRAM with dimensions according to the advantages of the new 6T SRAM structure. As shown in Figure 31(b), the transistor size can be as small as 3λ (marked by a dotted rectangle), and the distance between the gate edges of two adjacent transistors can be as small as 2λ. Furthermore, the isolation distance into the silicon substrate to separate the contacts in the NMOS and PMOS transistors can be reduced to 3λ (marked by a dashed rectangle). The isolation distance into the silicon substrate to separate the contacts in two PMOS transistors can be reduced to between 1.5 and 2.5λ, for example, as small as 2λ (marked by a dotted rectangle).

[0176] In Figure 31(b), the size of the active region (vertical line) can be as small as λ, as can the gate line (horizontal line). Furthermore, in Figure 31(b), for the transistor in the upper left corner corresponding to the PG transistor in Figure 31(a), to avoid interference between the two contact holes to be formed later, the horizontal distance between the edge of the active region and the boundary of the SRAM cell or bit cell is 1.5λ (marked by two dotted-line rectangles), representing the active region and gate region respectively. The same applies to the transistor in the lower right corner of Figure 31(b), which corresponds to another PG transistor in Figure 31(a). Therefore, for the stick diagram in Figure 31(b), the horizontal length (x-direction) of the SRAM cell or bit cell is 15λ, and the vertical length (y-direction) of the SRAM cell or bit cell is 6λ. Therefore, the total area of ​​the SRAM cell or bit cell in Figure 31(b) is 90λ. 2 .

[0177] Using the stick diagram in Figure 31(b) as a template, at least five SRAM cell structures are proposed in this invention, such as... Figures 32-3 As shown in Figure 7. Figure 32 These are the definitions of the different photomask layers used in Figures 33 to 37, where the abbreviations have the following meanings:

[0178]

[0179]

[0180] As shown in Figure 33(a), which is a copy of Figure 31(b), the area of ​​the SRAM cell in this embodiment is 90λ. 2In Figure 33(b), multiple CT_A layers (for connecting AA (or Poly) to the aperture VIA mask layer of the Metal-1 layer) and CT_B layers (for directly connecting AA (or Poly) to the aperture VIA mask layer of the Metal-2 layer) are formed, as shown by the dashed ellipse. In Figure 33(c), the Metal-1 mask layer (M1) is formed to connect multiple CT_A layers; however, multiple CT_B layers are not connected to the Metal-1 mask layer (M1). In Figure 33(d), the Metal-2 mask layer (M2) is formed to connect at least multiple CT_B layers. Some Metal-2 mask layers (M2) are used as bit lines (BL) and bit lines (BLB), marked by two dashed ellipses. In Figure 33(e), multiple plugs VIA2 are formed. In Figure 33(f), a Metal-3 photomask layer (M3) is formed connecting the multiple plugs VIA2. The Metal-3 photomask layer (M3) serves as a byte line (WL). Figure 33(g) shows the six SRAM cells of the present invention arranged in a two-dimensional array. In this embodiment, there is no VIA1, and the metal lines in the SRAM cells for the high potential voltage VDD and / or low potential voltage VSS are distributed below the original silicon surface of the silicon substrate, such as... Figure 30 As shown in Figure 33(c), the Metal-1 photomask layer (M1) is directly connected to the gate, source, and / or drain regions without the need for conventional contact hole-aperture photomasks and / or Metal-0 conversion layers.

[0181] Figures 34(a) to (h) illustrate another embodiment of the present invention. As shown in Figure 34(a), which is a copy of Figure 31(b), the area of ​​the SRAM cell in this embodiment is still 90λ. 2In Figure 34(b), multiple CT_A (for connecting AA (or Poly) to the opening VIA mask layer of the Metal-1 layer) and CT_B (for directly connecting AA (or Poly) to the opening VIA mask layer of the Metal-2 layer) are formed. Compared to Figure 33(b), two additional CT_A (marked with dashed ellipses) are formed in Figure 34(b) for later electrical connection to Vss. In Figure 34(c), the Metal-1 mask layer (M1) is formed to connect multiple CT_A; however, multiple CT_B are not connected to the Metal-1 mask layer (M1). In Figure 34(d), multiple plug VIA1 (marked with dashed ellipses) are formed for connecting the Metal-1 layer to the Metal-2 layer. In Figure 34(e), the Metal-2 mask layer (M2) is formed to connect at least multiple CT_B and multiple plug VIA1. Some Metal-2 photomask layers (M2) are used as bit lines (BL) and bit lines (BLB). In Figure 34(f), multiple plugs VIA2 are formed, a portion of which (marked by dashed ellipses) will be used for electrical connection to Vss. In Figure 34(g), a Metal-3 photomask layer (M3) is formed to connect the multiple VIA2. One Metal-3 photomask layer (M3) is used as a byte line (WL), and two other Metal-3 photomask layers (marked by dashed ellipses) are used as metal lines connecting Vss. Figure 34(h) shows the six SRAM cells of the present invention arranged in a two-dimensional array. In this embodiment, the metal lines for the high potential voltage VDD in the SRAM cells are distributed below the pristine silicon surface, while the metal lines for the low potential voltage VSS are distributed above the silicon substrate. Furthermore, as shown in Figure 34(c), the Metal-1 photomask layer (M1) is directly connected to the gate, source, and / or drain regions without the need for conventional contact hole-aperture photomasks and / or Metal-0 conversion layers.

[0182] Figures 35(a) to (h) illustrate another embodiment of the present invention. As shown in Figure 35(a), which is a copy of Figure 31(b), the area of ​​the SRAM cell in this embodiment remains 90λ. 2In Figure 35(b), multiple CT_A (for connecting AA (or Poly) to the opening VIA mask layer of the Metal-1 layer) and CT_B (for directly connecting AA (or Poly) to the opening VIA mask layer of the Metal-2 layer) are formed. Compared to Figure 34(b), two more CT_B (marked with dashed ellipses) are formed in Figure 35(b) for later electrical connection to Vdd. In Figure 35(c), the Metal-1 mask layer (M1) is formed to connect multiple CT_A; however, multiple CT_B are not connected to the Metal-1 mask layer (M1). In Figure 35(d), multiple plug VIA1 are formed to connect the Metal-1 layer to the Metal-2 layer. In Figure 35(e), the Metal-2 mask layer (M2) is formed to connect at least multiple CT_B and multiple plug VIA1. Some Metal-2 photomask layers (M2) are used as bit lines (BL) and bit lines (BLB), and one Metal-2 photomask layer (M2) is used as a metal line for Vdd (marked with a dashed ellipse). In Figure 35(f), multiple plugs VIA2 are formed, some of which will be used for electrical connection to Vss. In Figure 35(g), a Metal-3 photomask layer (M3) is formed to connect multiple plugs VIA2. One Metal-3 photomask layer (M3) is used as a byte line (WL), and two other Metal-3 photomask layers are used as metal lines connecting Vss. Figure 35(h) shows the six SRAM cells of the present invention arranged in a two-dimensional array. In this embodiment, the metal lines for the high potential voltage VDD and the low potential voltage VSS are distributed above the silicon substrate. Furthermore, as shown in Figure 35(c), the Metal-1 photomask layer (M1) is directly connected to the gate, source, and / or drain regions without the need for conventional contact hole-aperture photomasks and / or Metal-0 conversion layers.

[0183] Figures 36(a) to (h) illustrate another embodiment of the present invention. As shown in Figure 36(a), slightly different from Figure 31(b) or Figure 35(a), the isolation distance into the silicon substrate to separate the junctions in the NMOS and PMOS transistors is set to 4.5λ (marked by a dashed ellipse) for high-current applications. Furthermore, the horizontal distance between the edge of the active region and the boundary of the SRAM cell or bit cell is actively set to 1λ (marked by a dashed ellipse). Therefore, for the bar diagram in Figure 36(a), the horizontal length (x-direction) of the SRAM cell or bit cell is 17λ, while the vertical length (y-direction) of the SRAM cell or bit cell remains 6λ. Therefore, in this embodiment, the area of ​​the SRAM cell remains 102λ. 2 . Figures 36(b) to 36(h) Other processes and Figures 35(b) to 35(h) Similar. Therefore, omission of the pair Figures 36(b) to 36(h) The description is presented without repetition.

[0184] Figures 37(a) to (h) illustrate another embodiment of the present invention. In this embodiment, horizontally adjacent SRAM bit cells share bit lines / bit lines, and staggered byte lines are used to control the operation of the SRAM cells. A stick diagram of two adjacent SRAM bit cells is shown in Figure 37(a). The horizontal distance between the active region edge and the SRAM bit cell boundary is actively set to 1λ (marked by a dotted-dash ellipse), and the other dimensions of the SRAM bit cells are the same as in Figure 33(b). Therefore, the horizontal length (x-direction) of the SRAM cell or bit cell is 14λ, while the vertical length (y-direction) of the SRAM cell or bit cell remains 6λ. Therefore, the area of ​​the SRAM cell in this embodiment is still 84λ. 2 .

[0185] In Figure 37(b), multiple CT_A (for connecting AA (or Poly) to the opening VIA mask layer of the Metal-1 layer) and CT_B (for directly connecting AA (or Poly) to the opening VIA mask layer of the Metal-2 layer) are formed. Compared to Figure 33(b), only two CT_B (marked by dashed ellipses) are formed in Figure 37(b) for later electrical connection to the interleaved byte lines (WL1 and WL2). In Figure 37(c), the Metal-1 mask layer (M1) is formed to connect multiple CT_A; however, multiple CT_B are not connected to the Metal-1 mask layer (M1). In Figure 37(d), multiple plug VIA1 are formed to connect the Metal-1 layer and the Metal-2 layer. In Figure 37(e), the Metal-2 mask layer (M2) is formed to connect at least multiple CT_B and multiple plug VIA1. Some Metal-2 photomask layers (M2) are used as shared bit lines (BL) and shared bit lines (BLB), as indicated by dashed ellipses. In Figure 37(f), multiple plugs VIA2 are formed, some of which will be used for electrical connections to interleaved byte lines (WL1 / WL2). In Figure 37(g), a Metal-3 photomask layer (M3) is formed to connect the multiple plugs VIA2. The Metal-3 photomask layer (M3) serves as interleaved byte lines (WL1 / WL2). Figure 37(h) shows the 12 SRAM cells of the present invention arranged in a two-dimensional array. In this embodiment, the metal lines for the high potential voltage VDD and the low potential voltage VSS are distributed below the silicon substrate. Furthermore, as shown in Figure 37(c), the Metal-1 photomask layer (M1) directly connects to the gate, source, and / or drain regions without the need for conventional contact-hole photomasks and / or Metal-0 transition layers. Of course, the embodiments in Figures 37(a) to (h) can be modified so that the metal lines for the high potential voltage VDD and / or the low potential voltage VSS are distributed above the silicon substrate.

[0186] Figure 38 Plot the SRAM cell areas (in λ) from different technology nodes of three different foundries A, B, and C. 2 (Data collected from publicly available literature). With the development of techniques for smaller feature sizes, larger SRAM cell sizes (in λ) can be observed. 2 (in units). Through the design described in this invention and its derivatives, the SRAM cell area for different technology nodes can remain flat or insensitive to technology nodes; that is, from the 28nm technology node to the 5nm technology node, the SRAM cell area according to this invention can be maintained at 84λ. 2 ~102λ 2 Within the range.

[0187] Of course, it is not necessary to utilize all the improvements proposed in the new SRAM cell structure of this invention; just one of the proposed techniques is sufficient to reduce the area of ​​the SRAM cell structure compared to a conventional SRAM cell. For example, the reduction in the area of ​​the active region (or only the area connecting the gate / source / drain junction (“CT”) to the second metal layer) according to the invention can reduce the SRAM area to 84λ at the 5nm technology node. 2 ~700λ 2 Within the range, the 7nm technology node is at 84λ 2 ~450λ 2 Within the range, at technology nodes from 10nm to above 7nm, at 84λ 2 ~280λ 2 Within the range, at technology nodes from 20nm to above 10nm, at 84λ 2 ~200λ 2 Within the range, and at technology nodes from 28nm to above 20nm, at 84λ 2 ~150λ 2 Within this range. For example, at the 5nm technology node, the reduction in active region area may result in an SRAM area of ​​160λ. 2 ~240λ 2 Within the range (or larger, if additional tolerances are required), resulting in an SRAM area of ​​107λ at the 16nm technology node. 2 ~161λ 2 Within the range (or more, if additional tolerances are required).

[0188] and Figure 3 The area (λ) of the conventional SRAM shown 2 In comparison, the linear dimension of the present invention can be Figure 3 If the linear dimension of a conventional SRAM is 0.9 times (or smaller, e.g., 0.85, 0.8, or 0.7) that of the present invention, then the area of ​​the present invention can be... Figure 3The area is at least 0.81 times (or less, such as 0.72, 0.64 or 0.5 times) that of conventional SRAM, as shown in the table below.

[0189]

[0190] Therefore, in another embodiment of the present invention, when the minimum feature size (λ) is 5 nm, the area of ​​the SRAM cell of the present invention is no greater than 672λ. 2 When the minimum feature size is 7nm, the area of ​​the SRAM cell is no greater than 440λ. 2 (or 400λ) 2 Or 350λ 2 When the minimum feature size is between 10nm and 7nm or larger, the area of ​​an SRAM cell is no greater than 300λ. 2 (or 268λ) 2 When the minimum feature size (λ) is between 16 nm and greater than 10 nm, the area of ​​the SRAM cell is no greater than 204λ. 2 When the minimum feature size (λ) is between 22 nm and greater than 16 nm, the area of ​​the SRAM cell is no greater than 152λ. 2 When the minimum feature size (λ) is between 28 nm and greater than 22 nm, the area of ​​the SRAM cell is no greater than 139λ. 2 .

[0191] Furthermore, in another embodiment, when the minimum feature size is 5nm, the area of ​​the SRAM cell is 84λ. 2 ~672λ 2 Within this range. When the minimum feature size is 7nm, the area of ​​the SRAM cell is within 84λ. 2 ~440λ 2 Within this range. When the minimum feature size is above 7nm, the area of ​​the SRAM cell is 84λ. 2 ~300λ 2 Within this range. When the minimum feature size is above 10nm (16nm), the area of ​​the SRAM cell is around 84λ. 2 ~204λ 2 Within this range. When the minimum feature size is above 22nm to 16nm, the area of ​​the SRAM cell is around 84λ. 2 ~152λ 2 Within this range. When the minimum feature size is above 28nm to 22nm, the area of ​​the SRAM cell is around 84λ. 2 ~139λ 2 Within the range.

[0192] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An SRAM cell, characterized in that, include: A plurality of transistors, each transistor including a source region, a drain region and a gate structure located between the source region and the drain region, wherein the drain region and the source region of the first transistor of the plurality of transistors respectively include a doped region and a metal region disposed on one side of the doped region and horizontally connected to the doped region; An STI region is disposed next to the drain region and the source region of the first transistor, the STI region having a top surface higher than the gate conductive region of the gate structure of the first transistor; A set of contacts couples to the multiple transistors; A single byte line electrically couples to these multiple transistors; One bit line and one bit line, electrically coupled to the multiple transistors; A VDD connection is used to electrically couple the multiple transistors; and A VSS wire is used to electrically couple multiple transistors.

2. The SRAM cell as described in claim 1, characterized in that, When the minimum feature size λ decreases from 28 nm to 5 nm, the area of ​​the SRAM cell is 84λ. 2 ~102λ 2 between.

3. The SRAM cell as described in claim 2, characterized in that, The length of a transistor is between 3λ and 4λ.

4. The SRAM cell as described in claim 2, characterized in that, The gate region of one of the plurality of transistors is directly connected to the source or drain region of the plurality of transistors through a first metal interconnect without needing to pass through another metal layer below a first metal interconnect.

5. The SRAM cell as described in claim 2, characterized in that, The VDD or VSS wiring is distributed beneath the original silicon surface of a substrate forming the plurality of transistors.

6. The SRAM cell as described in claim 2, characterized in that, The bottom surface of the n+ region of the NMOS transistor in the plurality of transistors is completely isolated by a first insulator, and the bottom surface of the p+ region of the PMOS transistor in the plurality of transistors is completely isolated by a second insulator.

7. The SRAM cell as claimed in claim 6, characterized in that, The edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

8. The SRAM cell as claimed in claim 1, characterized in that, The set of contacts includes a first set of contacts and a second set of contacts. The first set of contacts is connected to a first metal layer, and the second set of contacts is connected to a second metal layer but disconnected from the first metal layer.

9. The SRAM cell as claimed in claim 1, characterized in that, A first contact hole is provided between the STI region and one side of the gate structure of the first transistor for accommodating a first contact in the group of contacts; a second contact hole is provided between the STI region and the other side of the gate structure of the first transistor for accommodating a second contact in the group of contacts; wherein the first contact in the first contact hole is electrically connected to the metal region of the source region of the first transistor, and the second contact in the second contact hole is electrically connected to the metal region of the drain region of the first transistor.

10. An SRAM cell, characterized in that, include: A semiconductor substrate; Multiple transistors are disposed on the semiconductor substrate. Each transistor includes a source region, a drain region, and a gate structure located between the source region and the drain region. The drain region and the source region of the first transistor in the plurality of transistors respectively include a doped region and a metal region disposed on one side of the doped region and horizontally connected to the doped region. The bottom surfaces of the drain region and the source region in the first transistor are completely isolated from the semiconductor substrate by a first insulator and a second insulator, respectively. A set of contacts couples to the multiple transistors; A single byte line electrically couples to these multiple transistors; One bit line and one bit line, electrically coupled to the multiple transistors; A VDD connection is used to electrically couple the multiple transistors; and A VSS wire is used to electrically couple multiple transistors; Specifically, when the minimum feature size λ is 5 nm, the area of ​​the SRAM cell is no greater than 672λ. 2 Alternatively, when the minimum feature size is 7 nm, the area of ​​the SRAM cell is no greater than 440λ. 2 Alternatively, when the minimum feature size is between 7nm and 10nm, the area of ​​the SRAM cell is no greater than 300λ. 2 Alternatively, when the minimum feature size λ is between 10 nm and 16 nm, the area of ​​the SRAM cell is no greater than 204λ. 2 Alternatively, when the minimum feature size λ is between 16nm and 22nm, the area of ​​the SRAM cell is no greater than 152λ. 2 Alternatively, when the minimum feature size λ is between 22nm and 28nm, the area of ​​the SRAM cell is no greater than 139λ. 2 .

11. The SRAM cell as claimed in claim 10, characterized in that, When the minimum feature size is 5nm, the area of ​​this SRAM cell is 84λ. 2 ~672λ 2 Within the range.

12. The SRAM cell as claimed in claim 10, characterized in that, When the minimum feature size is 7nm, the area of ​​this SRAM cell is 84λ. 2 ~440λ 2 Within the range.

13. The SRAM cell as claimed in claim 10, characterized in that, When the minimum feature size is between 10nm and 16nm, the area of ​​this SRAM cell is 84λ. 2 ~204λ 2 Within the range.

14. The SRAM cell as claimed in claim 10, characterized in that, When λ is between 22nm and 28nm, the area of ​​this SRAM cell is 84λ. 2 ~139λ 2 Within the range.

15. The SRAM cell as claimed in claim 10, characterized in that, The transistor further includes an STI region disposed next to the drain region and the source region of the first transistor, a first contact hole disposed between the STI region and one side of the gate structure of the first transistor for accommodating a first contact in the group of contacts, and a second contact hole disposed between the STI region and the other side of the gate structure of the first transistor for accommodating a second contact in the group of contacts; wherein the first contact in the first contact hole is electrically connected to the metal region of the source region of the first transistor, and the second contact in the second contact hole is electrically connected to the metal region of the drain region of the first transistor.

16. An SRAM cell, characterized in that, include: Multiple transistors, including NMOS transistors and PMOS transistors, wherein the NMOS transistor includes: A first gate structure; First passageway area; and A first conductive region is electrically coupled to the first channel region. The first conductive region includes a doped region and a metal region disposed on one side of the doped region and horizontally connected to the doped region of the first conductive region. The PMOS transistor includes: A second gate structure; A second passageway area; and A second conductive region is electrically coupled to the second channel region. The second conductive region includes a doped region and a metal region disposed on one side of the doped region and horizontally connected to the doped region of the second conductive region. One of the STI regions surrounds the NMOS transistor and the PMOS transistor, and the edge of the first conductive region is substantially perpendicular to and opposite to the edge of the second conductive region.

17. The SRAM cell as claimed in claim 16, characterized in that, It also includes a first contact hole located above the first conductive region, the first contact hole including a periphery surrounded by the boundary of the first conductive region.

18. The SRAM cell as claimed in claim 16, characterized in that, The gate region of one of the plurality of transistors is directly connected to the source or drain region of the plurality of transistors through a first metal interconnect without needing to pass through another metal layer below a first metal interconnect.

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