Explicit buffer control

Abstract

A memory storage system includes a non-volatile semiconductor memory device including a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device to specify a subset of n buffers of the plurality of buffers in which a data payload related to the command is to be transferred.

Description

Technical Field

[0001] This disclosure relates to a memory storage system and method that utilizes a specific buffer within a non-volatile semiconductor memory device to control data transfer into and out of a memory array. Background Technology

[0002] Compared to conventional disk drives, storage systems such as solid-state drives (SSDs) typically offer faster performance, are more compact, and are less sensitive to vibration or physical shock. Given these advantages, SSDs are increasingly used as an alternative to or complement to disk drives in computing devices and other consumer products, even though the cost per gigabyte of storage capacity for SSDs is significantly higher than that of disk drives. SSDs utilize physical memory cells, including non-volatile semiconductor storage devices (such as NAND flash memory devices), to store data. A controller within the SSD manages data transfer between the host and the SSD's memory cells. Writing data to and reading data from the SSD's physical memory cells typically involves transferring data between the host and the non-volatile semiconductor storage device, external to the SSD.

[0003] SSDs experience large data flows when receiving multiple read and write requests from the host. These host requests take the form of commands containing logical address information (such as logical block addresses (LBAs) and namespace identifiers (NSIDs)). The SSD translates this logical address information into physical addresses within the non-volatile semiconductor memory (NAND memory page addresses). The SSD then uses these physical NAND addresses to fulfill the requests (e.g., reading data from the NAND memory). However, the large amount of data moving back and forth between the NAND memory often necessitates that the memory controller temporarily store the data while the NAND memory device completes its current activity, especially in write commands involving the transfer of data that has not yet been stored.

[0004] In such cases, the memory controller uses its internal volatile memory to temporarily store the data. If the size of the internal volatile memory is insufficient to hold the amount of data being transferred, external volatile memory is used as appropriate. The use of these SSD resources, effectively used as buffers or cache memory to manage data transfers in and out of the NAND memory device, reduces the controller's ability to perform other tasks with these resources. Data can remain in the buffer until the NAND memory device confirms that the data transfer and / or programming has been successfully completed, resulting in a large amount of buffer space being allocated and occupied for a long time. Furthermore, this type of internal volatile memory cannot scale proportionally with the size of the NAND memory device. Therefore, for example, high data rates and large data transfers require a large amount of volatile memory, increasing the cost of the SSD and placing additional load on the controller and NAND bus. This presents a challenge in efficiently managing read or program / write commands involving large data transfers within the memory storage system. Summary of the Invention

[0005] According to embodiments of this disclosure, a memory storage system is provided, including a non-volatile semiconductor memory device, the non-volatile semiconductor memory device including a memory array and a plurality of buffers. The memory storage system further includes a controller communicating with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device to specify a subset of n buffers of the plurality of buffers in which a data payload associated with the command will be transferred. In some embodiments, when the command includes a data shift command, the controller is configured to transfer the data payload from the controller to the subset of the n buffers. In some embodiments, the controller is further configured to issue a media write command such that the non-volatile memory device stores data contained in the subset of the n buffers in the memory array. In other embodiments, when the command includes a media read command, the controller is configured to transfer the data payload from the memory array to the subset of the n buffers. In some implementations, the controller is further configured to issue a data remove command to transfer the data payload of the subset containing n buffers to the controller.

[0006] According to another embodiment of this disclosure, a method is provided performed by a controller of a memory storage system, the memory storage system including a non-volatile semiconductor memory device having a memory array and a plurality of buffers, and the controller communicating with the plurality of buffers. The method includes issuing a command to the non-volatile semiconductor memory device to specify a subset of n buffers of the plurality of buffers in which a data payload associated with the command will be transferred. In some embodiments, the method includes transferring the data payload from the controller to the subset of n buffers when the command includes a data shift-in command. In another embodiment, the method further includes issuing a media write command to cause the non-volatile memory device to store data contained in the subset of n buffers in the memory array. In some embodiments, the method includes causing the non-volatile memory device to transfer the data payload from the memory array to the subset of n buffers when the command includes a media read command. In another embodiment, the method further includes issuing a data shift-out command to transfer the data payload contained in the subset of n buffers to the controller.

[0007] In other embodiments, the controller is configured to use a unique buffer identifier for at least one buffer in the subset of n buffers when specifying the subset of n buffers among the plurality of buffers. In some embodiments, the controller is configured to issue at least one command at any time to cause the data payload to be transferred between the subset of n buffers and the memory array. In some embodiments, the non-volatile semiconductor memory device further includes a subset of internal buffers and a subset of m buffers, both derived from the plurality of buffers and separate from the n buffers, and the controller is configured to transfer the data payload contained in the subset of m buffers associated with the second command to the internal buffers when the transfer of the data payload associated with the subset of n buffers associated with the first command issued before the second command is nearing completion. In another embodiment, the non-volatile semiconductor memory device further includes a subset of internal buffers and a subset of m buffers, both derived from and separate from the n buffers, and the controller is configured to pause the transfer of the data payload between the subset of n buffers associated with the first command and the memory array before completion, complete the transfer of the data payload between the subset of m buffers associated with the second command and the memory array, and resume the transfer of the data payload associated with the first command.

[0008] In some embodiments, the first command is associated with a first priority value and the second command is associated with a second priority value, which is greater than the first priority value. In another embodiment, the controller is configured to perform any number of transfers of the data payload between the controller and the plurality of buffers and the transfer of the data payload between the subset of the n buffers and the memory array in parallel. In some embodiments, the memory storage system includes memory cells, each storing at least one bit. In other embodiments, the memory storage system includes, for example, single-layer memory cells (SLC), pseudo-single-layer memory cells (pSLC), multi-layer memory cells (MLC), three-layer memory cells (TLC), four-layer memory cells (QLC), and variable-layer memory cells (VLC). In some embodiments, the non-volatile semiconductor memory device is an under-array CMOS (CUA) NAND semiconductor memory. In another embodiment, the controller includes a system-on-a-chip (SoC) controller.

[0009] Furthermore, it should be noted that although this disclosure has used CuA technology to describe NAND memory storage devices having SLC, pSLC, MLC, TLC, QLC or VLC memory arrays, it should be understood that the systems and methods disclosed herein are applicable to any memory technology that utilizes interface buffers for enabling data transfer in and out of the memory array, such as (but not limited to) CuA NAND memory, non-CuA NAND memory, phase-change memory (PCM), magnetoresistive random access memory (MRAM) and ferroelectric random access memory (FeRAM). Attached Figure Description

[0010] The foregoing and other objectives and advantages will become clear from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals refer to like parts, and wherein:

[0011] Figure 1 A schematic diagram illustrating a memory storage system, such as an SSD, configured according to one or more embodiments of the present disclosure;

[0012] Figure 2 Description of one or more embodiments according to this disclosure Figure 1 The interaction between the controller of the memory storage system and the non-volatile semiconductor memory device with memory arrays and multiple buffers;

[0013] Figures 3A to 3E Description of embodiments according to this disclosure Figure 1 The controller of the memory storage system in the memory storage system to Figure 2An exemplary sequence of buffer control commands issued by a non-volatile semiconductor memory device; and

[0014] Figure 4 This is a flowchart of a method for controlling the transfer of data into and out of a non-volatile semiconductor memory device having multiple page buffers, according to one or more embodiments of the present disclosure, using explicit buffer control. Detailed Implementation

[0015] To provide a full understanding of the systems and methods described herein, certain illustrative embodiments will be described. Although the embodiments and features described herein are specifically designed for use in memory storage systems, such as SSDs, in conjunction with memory devices having controllers and page buffers, it should be understood that all components and other features outlined below can be combined with each other in any suitable manner and can be adapted and applied to other types of memory storage system architectures with similar needs for efficiently managing commands involving the transfer of large amounts of data into and out of the memory storage system.

[0016] Three-dimensional (3D) NAND arrays have recently gained attention for their increased data processing capabilities due to the compact footprint resulting from the vertical stacking of NAND planes. Memory devices incorporated into 3D NAND arrays are faster, more efficient, and consume less power compared to conventional NAND memory arrays. The latest generation of 3D NAND memory arrays builds a vertical stack of NAND memory array layers on top of the interface, command, and control logic circuitry of the NAND chips, rather than placing the circuitry on the periphery of the NAND memory array. This requires a larger die area than the area occupied by the NAND memory array alone. In some examples, this interface, command, and control circuitry utilizes complementary metal-oxide-semiconductor (CMOS) technology to result in under-array CMOS (CuA) NAND memory devices. This enhanced memory architecture provides approximately 25% more die space per wafer to the CuA NAND array compared to a 64-layer 3D NAND array. The CMOS logic circuitry also facilitates NAND architecture optimization by adding a large number of NAND page buffers in the CMOS region of the CuA NAND memory device, compared to the limited buffer space provided by peripheral circuitry. Size constraints are imposed to limit the total die size, thus minimizing the amount of peripheral circuitry. These constraints include, for example, the number of buffers or the amount of buffer space available from the memory device. If the buffers are implemented using CuA (Cured-Available) technology, the number of NAND page buffers can be scaled proportionally to the size of the NAND memory. NAND page buffers can be configured for homogeneous use or, as needed, to meet the requirements of the memory storage system. In some implementations where CuA technology is not used, the systems and methods described in this disclosure can still be employed when multiple NAND page buffers are available. The availability of NAND page buffers within a CuA NAND memory device reduces the burden on the volatile memory of the memory controller when processing commands involving large data transfers. However, the management and control of this large number of NAND page buffers presents challenges to the efficient management of data transfers within the memory storage system.

[0017] This disclosure describes systems and methods for addressing the aforementioned challenges and improving the efficiency of SSD programming / write and read commands that cause data payloads to be transferred back and forth within a memory device (e.g., a NAND memory device containing a CuA NAND memory device). This disclosure describes a controller embodiment for controlling data transfer within a NAND memory device, wherein the controller issues a command to the memory device that explicitly identifies a subset of n NAND page buffers within the NAND memory device in which the data payload associated with the command will be transferred. When the command includes a data shift-in command, the controller is configured to transfer the data payload to the subset of the n NAND page buffers. Once the data shift-in operation is complete, the controller may be further configured to issue a media write or programming command that causes the non-volatile memory device to store data contained in the subset of the n NAND page buffers in the NAND memory array. When the command includes a media read command, the controller is configured to cause the non-volatile memory device to transfer the data payload from the NAND memory array to the subset of the n NAND page buffers. Once the media read operation is complete, the controller can be further configured to issue a data shift command to transfer the data payload contained in a subset of the n NAND page buffers to the controller. In this way, the controller effectively controls data transfer to and from the NAND memory array by separating the data shift operations between the controller and the page buffers from the media operations between the page buffers and the memory array.

[0018] By utilizing the NAND page buffers of the NAND memory device in this way, the burden imposed by the controller on its internal volatile memory (or the use of additional external volatile memory) is reduced when processing commands involving large data payloads. This is because the CuA NAND memory device has an increased number of buffers that store data payloads for multiple commands, so that even if a media write / programming command is still pending and the buffer used by the command is still in use, other buffers where subsequent shift-in / shift-out commands can place data remain available. Furthermore, if a media command fails, the command can be resent, and the buffer still containing the shifted-in data can be reused, while other commands are still allowed to continue using other buffers. The need to retain shifted-in data in the host buffer and resend the shift-in data command is eliminated. This allows the SSD to buffer increased data volumes within the CuA NAND memory device itself, thereby improving NAND bus and die utilization. Additionally, since the NAND page buffers are contained within the interface, command, and control circuitry located below the memory array, the number of NAND page buffers is proportional to the number of NAND dies. Furthermore, the separation of data shifting operations from media operations simplifies the implementation of the controller-based scheme of this disclosure.

[0019] As previously mentioned, NAND page buffers are homogeneous buffers that can be used for various processes such as data shift-in write commands, data shift-out read commands, media programming / write commands, and media read commands. In some implementations where heterogeneous buffers are used, the controller may need to comply with individual buffer limitations and special requirements, but in all other respects, the systems and methods described in this disclosure can still be used. The flexibility provided by NAND page buffers thus simplifies their management, as there are few individual characteristics and limitations to consider. The SSD controller and associated firmware have a queue of several read / write requests and can therefore manage and optimize the use of multiple NAND page buffers and CuA memory arrays with greater accuracy. This is achieved, for example, by assigning commands to specific NAND page buffers via NAND page buffer identifiers and NAND page buffer status tables. This allows the controller to control which NAND page buffers are used and allows for flexible management of larger sets of buffers, especially as the size of CuA NAND devices increases proportionally.

[0020] Figure 1 This is a block diagram of a computing system 100 including at least one host 110 communicating with a solid-state device (SSD) 120, according to embodiments of the present disclosure. The host 110 includes a processor or core, a controller, memory, and other components generally known in the art, and for simplicity... Figure 1 The computing system includes other components not shown in the diagram. SSD 120 provides non-volatile storage functionality for use by host 110. SSD 120 may contain an integrated circuit including a controller. This integrated circuit may also be referred to as a system-on-a-chip (SoC) controller 130. SoC is advantageous in SSDs because it provides a single integrated circuit containing all the necessary circuitry and components for the electronic systems required for SSD operation. SoC therefore eliminates the need for a modular, discrete component architecture connected by multiple buses and buffers.

[0021] The SoC controller 130 is communicatively coupled to a non-volatile semiconductor-based memory device 140, which serves as the storage medium (although a single device is shown for simplicity, an entire array of devices, such as NAND-based flash memory devices, may exist communicatively coupled to the controller 130). The storage medium may include multiple NAND devices, such as (for example) 32, 64, 128, or 256 individual NAND devices, and each NAND device may run individual commands on a plane of an individual die (not shown) within the device. As an example, an array of memory devices 140 comprising x NAND devices, each with y dies, may serve up to (x×y) commands from the SoC controller 130 at any given time, where x and y are integers greater than zero. According to embodiments of this disclosure, the non-volatile semiconductor-based memory device 140 may include a three-dimensional (3D) NAND device, such as an under-array complementary metal-oxide-semiconductor (CMOS) (CuA) memory device, as will be described in more detail below. Generally, a CuA memory device includes a memory array 142 on a NAND plane 143 vertically constructed above an interface, command, and control circuitry 144 of the memory device 140. In some embodiments, the interface, command, and control circuitry 144 may include multiple homogeneous NAND page buffers 145 that can be used for various purposes associated with the NAND array 142.

[0022] It should be noted that this disclosure applies to memory cells with any structure, such as (for example) single-level memory cells (SLC), pseudo-single-level memory cells (pSLC), multi-level memory cells (MLC), three-level memory cells (TLC), four-level memory cells (QLC), or variable-level memory cells (VLC). Furthermore, although this disclosure uses CuA technology to describe NAND memory storage devices having SLC, pSLC, MLC, TLC, QLC, or VLC memory arrays, it should be understood that the systems and methods disclosed herein are applicable to any memory technology employing interface buffers for enabling data transfer in and out of the memory array, such as (but not limited to) CuA NAND memory, non-CuA NAND memory, phase-change memory (PCM), magnetoresistive random access memory (MRAM), and ferroelectric random access memory (FeRAM).

[0023] SSD 120 also includes volatile memory, such as dynamic random access memory (“DRAM”) 150, external to SoC controller 130. DRAM 150 includes several buffers (not shown) typically used to buffer data during read and write operations between host 110 and storage device 140 after receiving commands from host 110. It should be noted that, unlike NAND page buffer 145 in storage device 140, DRAM 150 memory can be flexibly allocated and deallocated for any buffering or temporary storage purposes required by controller 130.

[0024] Volatile memory is used in conjunction with a controller because it is fast and responsive. However, the contents stored in volatile memory are lost when power is off. Volatile memory is also expensive and thus increases the overall cost of an SSD. In some implementations, all or part of the external memory DRAM 150 may reside within the SoC controller 130. When located within the SoC controller 130, at least a portion of the external memory may be implemented using fast memory technologies, such as static random access memory (SRAM). In some implementations, a portion of the DRAM located within the SoC 130 may be implemented as a cache. In some implementations, all or part of the external memory may be implemented using fast non-volatile memory technologies, including (but not limited to) magnetic random access memory (MRAM), resistive random access memory (ReRAM), or phase-change memory (PCM).

[0025] The SoC controller 130 includes a host interface 122 capable of communicating with the host 110 to receive commands such as (for example) read and write requests. The SoC controller 130 also includes a NAND interface 124 for communicating with a storage device 140 via a NAND bus, the NAND bus being coupled to an interface, command, and control CuA circuitry 144 including a page buffer 145 comprising a NAND array 142. Furthermore, the SoC controller 130 includes a (DRAM) memory interface 126 for communicating with memory 150 external to the SoC. For example, the host interface 122 on the SoC 130 may include... Serial Advanced Technology Attached (SATA) connectors or NVMe connectors that operate together with the PCIe (Peripheral Component Interface High Speed, hereinafter referred to as PCIe) bus. TM Connector (NVMe) TMIt is an abbreviation for "NVM High Speed," where "NVM" stands for Non-Volatile Memory (hereinafter referred to as NVMe). For example, NAND interface 124 may include an Open NAND Flash Interface (ONFI), a Switchable NAND Interface, or a manufacturer's proprietary interface. Memory interface 126 may include, for example, interfaces according to (but not limited to) the following: Double Data Rate (DDR) memory bus standards, such as DDR3, DDR4, or DDR5; Low Power Double Data Rate (LPDDR) memory bus standards, such as LPDDR3, LPDDR4, or LPDDR5; Hybrid Memory Cube (HMC) memory bus standards.

[0026] The SoC controller 130 may include various internal sub-controllers, such as an NVMe controller 132 coupled to the host interface 122, a memory controller 136 coupled to the memory interface 126, and a NAND controller 138 coupled to the NAND interface 124. The NVMe controller 132 may be configured according to NVM Express, released on June 10, 2019. TM The basic specification (version 1.4) (hereinafter referred to as "NVMe 1.4") operates. The NVMe controller 132 and NAND controller 138 are also coupled to the memory controller 136 via a data bus. Firmware 134, which can store or program various operating parameters of the SSD 120, can be used to control the operation of the NVMe controller 132, NAND controller 138, and memory controller 136 and the data transfer between them. Firmware 134 may include programmable application-specific integrated circuit (ASIC) logic, programmable firmware running on one or more processors, or a combination of both. Firmware 134 may include a flash translation layer that enables the SoC controller 130 to perform various activities that facilitate the processing of read and write commands received from the host 110. One such activity may involve orchestrating the data flow of commands between the NVMe controller 132 and the NAND controller 138. About Figure 1 Firmware configuration circuitry 134 configures and controls the data operations and transfers between controllers 132, 136, and 138. NVMe controller 132, memory controller 136, and NAND controller 138 are interconnected via a common bus and controlled by firmware configuration circuitry 134. Memory controller 136 is connected to DRAM 150 via memory interface 126. NAND controller 138 is connected to NAND interface 124 to communicate with storage device 140, such as... Figure 1 As shown in the diagram. Any interaction between the SoC 130 and the NAND array 142 occurs via the NAND controller 138, the NAND interface 124, and the NAND page buffer 145.

[0027] Once the NVMe controller 132 receives a command from the host 110, such as a read command or a write command, it maps the logical block address contained in the host command to a physical NAND address using settings in the firmware 134. The firmware 134 may use a lookup table to obtain the required NAND address. These NAND addresses are then used in NAND commands based on host commands received by the firmware or generated internally, which are sent to the NAND controller 138. In the case of CuA NAND memory, the NAND controller 138 determines a specific subset of n buffers from a plurality of NAND page buffers 145 in the interface, command, and control CMOS circuitry 144 available for the memory device 140 for use when processing commands, where n is a positive integer. In some embodiments, each of the NAND page buffers 145 has a unique buffer identifier explicitly specified by the SoC 130 when processing commands. The NAND controller 138 then uses the NAND addresses to perform actions or functions on the memory device 140, as defined by commands generated by the host or internally (e.g., obsolete item collection commands).

[0028] Figure 2 This illustration depicts a setup 200 for illustrating the interaction between the SoC controller 130 and the memory device 140 during command processing, according to embodiments of the present disclosure. When processing commands, the SoC controller 130 issues commands to the memory device 140 causing a data shift operation between the SoC controller 130 and the NAND page buffer 145, and also issues commands to the memory device 140 causing a media operation between the memory array 142 and the NAND page buffer 145. The media operation can be performed concurrently with the data shift operation. In some embodiments, only one media operation is performed at any given time, while any number of data shift operations can occur simultaneously, provided that sufficient page buffers 145 are available in the memory device 140. This is because the time required to complete a media operation is typically longer than the time required to complete a data shift operation. For example, a write or programmable media operation typically takes about 2 milliseconds, while a data shift operation typically takes several microseconds.

[0029] The order in which operations are performed within memory device 140 after receiving a command from SoC controller 130 depends on the nature of the command being processed. For example, in the case of receiving a read command from host 110, NAND controller 138 issues one or more read commands to cause one or more media read operations from one or more NAND physical addresses corresponding to one or more logical addresses specified in the read command. Here, NAND controller 138 specifies that the data payload contained at a specified NAND physical address in NAND array 142 will be transferred to n NAND page buffers 145 therein. While performing media read operations between memory array 142 and n NAND page buffers 145, memory device 140 may also perform data shift operations between SoC controller 130 and NAND page buffers 145 in parallel with other commands received from SoC controller 130. Once one or more media read operations are completed, NAND controller 138 issues a data shift command from the n NAND page buffers containing the data payload associated with one or more read commands from SoC controller 130 to be delivered to SoC controller 130. Similar to media read operations, when a data shift operation is performed between n NAND page buffers 145 and SoC controller 130, memory device 140 can also perform media operations between NAND page buffers 145 and NAND array 142 in parallel with other commands received from SoC controller 130.

[0030] As another example, in the case of a write command, the NAND controller 138 issues a data shift command to transfer a data payload from the SoC controller 130 to the memory device 40. Here, the NAND controller 138 specifies that the data payload from the SoC controller 130 will be transferred to n NAND page buffers 145 therein. While the data shift operation is performed between the n NAND page buffers 145 and the SoC controller 130, the memory device 140 can also perform media operations between the NAND page buffers 145 and the NAND array 142 in parallel, in relation to other commands received from the SoC controller 130. Once the data shift operation is complete, the NAND controller 138 issues a command to cause a media write / programming operation from the n NAND page buffers 145 containing the data payload to the NAND physical address specified in the write command. Similar to a data shift operation, when a media write operation is performed between n NAND page buffers 145 and NAND array 142, memory device 140 can perform data shift operations between SoC controller 130 and NAND page buffers 145 in parallel, which are related to other commands received from SoC controller 130.

[0031] Figures 3A to 3E The description describes the NAND controller 138 issuing commands to devices having, according to various embodiments of this disclosure. Figures 1 to 2 The exemplary buffer control command sequence 300, 310, 320, 330, 340 for the CuA NAND memory device 140 configured to perform various actions is shown in the figure. Figures 3A to 3E Taking a CuA NAND memory device 140 with a three-level memory cell (TLC) structure as an example, however, this disclosure is not limited to the TLC memory cell structure. Specifically, this disclosure is applicable to NAND memory devices (e.g., CuA NAND devices) with multiple NAND page buffers and any memory cell structure, such as (for example) single-level memory cell (SLC), pseudo-single-level memory cell (pSLC), multi-level memory cell (MLC), three-level memory cell (TLC), four-level memory cell (QLC), or variable-level memory cell (VLC). Figures 3A to 3E In each of these, SoC controller commands are grouped into alphabetical groups, where commands within each alphabetical group can be executed together.

[0032] Figure 3A An exemplary command sequence 300 for programming / writing or cache programming / writing operations according to embodiments of the present disclosure is provided. Here, the SoC controller 130 issues a data shift-in write operation in command lines 1 to 3, wherein a data payload is transferred to NAND page buffers 4, 5, and 6. The NAND controller 138 may select a specific NAND page buffer from a page buffer identifier. In some embodiments, the NAND controller 138 may maintain a valid table of NAND page buffers with status indications to determine whether any NAND page buffer is available to receive data from the SoC controller 130 or from a physical location within the NAND memory array 142. It should be noted that... Figures 3A to 3EThe exemplary command sequence in the code pertains to a TLC memory cell architecture, and therefore a write operation must contain a data payload for three NAND pages (top, middle, and bottom) for the TLC cell in command lines 1 through 3, thus involving transfers to three NAND page buffers. Once the data payload for all TLC pages has been transferred to NAND page buffers 4, 5, and 6, the NAND controller 138 issues a media programming / write command in command line 4, whereby the data payload contained in NAND page buffers 4, 5, and 6 is stored in the NAND array 142 at the physical address specified in the write command. In parallel with the media programming / write command in command line 4, the SoC controller 130 may also issue data shift commands in command lines 5 through 7 while the media programming / write command in command line 4 is executing. The data shift commands in command lines 5 through 7 are associated with subsequent write commands in which the payload is transferred to available NAND page buffers (e.g., NAND page buffers 0, 3, and 7). In effect, command lines 5 through 7 are used as cache writes while the current media write procedure in command line 4 is executing.

[0033] As previously mentioned, media programming commands typically take about 2 milliseconds to complete, while data shift commands typically take tens of microseconds. Therefore, even after the data shift commands in commands 5 through 7 have completed, controller 130 may still have to wait for the media write command in command line 4 to complete before continuing subsequent media programming operations according to command line 8. During this waiting period, SoC controller 130 can cache more data payload by performing additional data shift operations between SoC controller 130 and any available NAND page buffers 145.

[0034] In some implementations, the SoC controller 130 can specify multiple NAND page buffers 145 as... Figure 2 The NAND page buffers 0 through 8 shown are separate internal or dedicated buffers, which can be used to store data payloads in NAND page buffers 0, 7, and 3. In this way, NAND page buffers 0, 7, and 3 can be cleared when the media write command in command line 4 is completed for use in other data shift operations. If no internal buffer is available, the SoC controller 130 maintains the data in NAND page buffers 0, 7, and 3 without clearing them until the NAND array 142 is available for media programming / writing.

[0035] When the media write command in command line 4 is completed, the NAND controller 138 issues a media programming / write command in command line 9, wherein the data payload contained in NAND page buffers 0, 3, and 7 is stored in the NAND array 142 at the physical address specified in the write command. As disclosed above, in parallel with the media programming command in command line 9, the SoC controller 130 may also perform other data shift operations between the SoC controller 130 and any available NAND page buffers 145 while the media programming command in command line 9 is being executed.

[0036] Figure 3B An exemplary command sequence 320 for a read or cache read operation according to embodiments of the present disclosure is provided. Here, the SoC controller 130 issues a media read command in command line 1, wherein a data payload stored at a physical address in the NAND array 142 specified in the read command from host 110 is transferred to the NAND page buffer 145. In the media read command, the NAND controller 138 specifies that the data payload will be transferred to the NAND page buffer 1 that the NAND controller 138 has determined to be available. The media read command typically takes about tens of microseconds to complete, and therefore the SoC controller 130 waits in command line 2 for the data payload associated with the media read operation in command line 1 to be fully transferred to the NAND page buffer 1. Although not specified in command sequence 310, during this waiting time, the SoC controller 130 can cache the data payload associated with other commands by performing a data shift operation between the SoC controller 130 and any available NAND page buffer 145.

[0037] Once the media read to NAND page buffer 1 is complete, the SoC controller 130 issues a command for the next media operation, such as a media read to NAND page buffer 3, according to command line 3. Again, the media read is for a data payload stored at a physical address in NAND array 142 corresponding to the logical address specified in the read command from host 110, and the NAND controller 138 specifies that the data payload will be transferred to NAND page buffer 3, which the NAND controller 138 has identified as available. In parallel with the media operation specified in command line 3, the SoC controller 130 also issues a data shift read command from NAND page buffer 1 in command line 4 to transfer the data payload contained therein to a host read command for delivery to host 110 to complete the media read operation in command line 1. In effect, command line 3 is used as a cache read when the read command associated with the data payload contained in NAND page buffer 1 is executed. Then, the SoC controller 130 waits in command line 5 for the data payload associated with the media read operation in command line 3 to be fully transferred to NAND page buffer 3. Once the media read to NAND page buffer 3 is complete, SoC controller 130 issues a data remove read command from NAND page buffer 3 in command line 6 to transfer the data payload contained therein to SoC controller 130 for delivery to host 110 to complete the media read operation in command line 3.

[0038] Figure 3C An exemplary command sequence 330 for mixed programming / writing and reading media operations according to embodiments of the present disclosure is provided. The SoC controller 130 issues a media read command in command line 1, wherein a data payload stored at a physical address in the NAND array 142 corresponding to the logical address specified in the read command from host 110 is transferred to the NAND page buffer 145. In the media read command, the NAND controller 138 specifies that the data payload will be transferred to the NAND page buffer 1, which the NAND controller 138 has determined to be available. The SoC controller 130 also issues a data shift-in write operation in commands 2 and 3, wherein a data payload is transferred to NAND page buffers 2 and 3. The NAND controller 138 may select a specific NAND page buffer from a page buffer identifier. Command lines 2 and 3 may be executed in parallel with command line 1. The SoC controller 130 then waits in command line 4 for the data payload associated with the media read operation in command line 1 to be fully transferred to the NAND page buffer 1.

[0039] Next, SoC controller 130 issues a media read command in command line 5, wherein the data payload stored at the physical address in NAND array 142 specified in the read command is transferred to NAND controller 138, which has identified it as available, in NAND page buffer 5. SoC controller 130 also issues a data shift-out read operation in command line 6, wherein the data payload contained in NAND page buffer 1 from the media read operation caused by command line 1 is transferred to SoC controller 130 for delivery to host 110. SoC controller 130 issues a data shift-in write operation in command line 7, wherein the data payload is transferred to NAND page buffer 4. Command lines 6 and 7 can be executed in parallel with command line 5. Then, SoC controller 130 waits in command line 8 for the data payload associated with the media read operation in command line 5 to be fully transferred to NAND page buffer 1. Once the data payload associated with the media read command in command line 5 is delivered to NAND page buffer 5, SoC controller 130 issues another media read command in command line 9, wherein the data payload stored at the physical address specified in the NAND array 142 in the read command is delivered to NAND page buffer 6, which NAND controller 138 has identified as available. Thereafter, SoC controller 130 waits for the data payload received from NAND array 142 in NAND page buffer 6 to complete (command line 10).

[0040] Since the payload for the write command has been transferred to NAND buffer pages 2, 3, and 4 according to the data shift-in write command in commands 2, 3, and 7 (despite interruptions from other operations), the NAND controller 138 issues a media programming / write command in command line 11, which stores the data payload contained in NAND page buffers 2, 3, and 4 at the physical address specified in the write command in the NAND array 142. In parallel with the media programming / write command, the SoC controller 130 also issues data shift-out read commands in commands 12 and 13 while the media programming / write command in command line 11 is being executed. The data shift-out commands in commands 12 and 13 transfer the data payload contained in NAND page buffers 5 and 6 (both caused by previous media read operations in commands 5 and 9) to the SoC controller 130. Command lines 12 and 13 can be executed in parallel with command line 10. Figure 3C This demonstrates how the CuA NAND memory device 140 handles mixed programming / writing and reading media operations.

[0041] Figure 3DAn exemplary command sequence 330 for a programming pause operation is provided according to embodiments of the present disclosure, wherein the data payload is always available for readback. In command lines 1 through 3, the SoC controller 130 issues a data shift-in write operation, wherein the data payload is transferred to the NAND controller 138, which has determined it to be available, NAND page buffers 2, 3, and 4. Once the data payload of all TLC pages has been transferred to the NAND page buffers 2, 3, and 4, the NAND controller 138 issues a media programming / write command in command line 4, wherein the data payload contained in the NAND page buffers 2, 3, and 4 is stored in the NAND array 142 at the physical address specified in the write command.

[0042] However, when processing media programming / write commands, the SoC controller 130 issues a pause command in command line 5 instead of a media read command. As previously mentioned, only one media operation can be performed on the NAND array 142 at any given time. Furthermore, read commands from the host 110 are generally considered more critical than write commands because the host 110 cannot continue its operation without a requested data payload from the NAND array 142. This is why the less critical media write command in command line 4 is paused to give way to the media read command in command line 5.

[0043] In command line 5, SoC controller 130 issues a media read command, in which a data payload stored at a physical address in NAND array 142 corresponding to the logical address specified in the read command from host 110 is transferred to NAND page buffer 1, which NAND controller 138 has identified as available. Then, SoC controller 130 waits for media read from NAND page buffer 1 to complete according to command line 6. Once the data payload is transferred to NAND page buffer 1, SoC controller 130 resumes a media programming / write command in command line 7, in which the data payload in NAND page buffers 2, 3, and 4 is stored at the physical address specified in the write command. In parallel with the media programming / write command in command line 7, SoC controller 130 issues a data shift-out read command in command line 8 while the media programming / write command in command line 7 is being executed. The data shift-out command in command line 8 transfers the data payload contained in NAND page buffer 1 (caused by the previous media read operation in command line 6) to SoC controller 130. Figure 3D This demonstrates how the CuA NAND memory device 140 can be used to pause operation and prioritize the processing of read commands over write commands.

[0044] In some implementations, the SoC controller 130 can specify multiple NAND page buffers 145 as... Figure 2The NAND page buffers 0 through 8 shown are separate internal or dedicated buffers, which can be used to store data payloads in NAND page buffers 2, 3, and 4, as used in command line 4. In this way, NAND page buffers 2, 3, and 4 can be cleared when the media read command in command line 5 is completed for use in other data shift operations. If no internal buffer is available, the SoC controller 130 maintains the data in NAND page buffers 2, 3, and 4 without clearing them until the NAND array 142 is available to resume media programming / writing in command line 7.

[0045] Figure 3E An exemplary command sequence 340 according to embodiments of the present disclosure is provided for prioritizing read operations between data shifts into program pages without requiring a pause operation. The SoC controller 130 issues a data shift write operation at command line 1, wherein a data payload is transferred to the NAND controller 138, which has identified it as an available NAND page buffer 2. A read operation can commence without waiting for data shifts into all pages of the programming operation. In this example, after the first page data input, the SoC controller 130 issues a media read command at command line 2, wherein a data payload stored at a physical address in the NAND array 142 specified in the read command from host 110 is transferred to the NAND controller 138, which has identified it as an also available NAND page buffer 1.

[0046] The SoC controller 130 also issues a data shift-in write command in command line 3 to transfer the data payload to NAND buffer 3, which can be performed in parallel with the media read operation in command line 2. Next, in command line 4, the SoC controller checks for completion of the media read in command line 2 and then issues a command for data shift-out read from buffer 1 to controller 130. In command line 5, the SoC controller issues a data shift-in write command to transfer the data payload to NAND buffer 4. It should be noted that the data shift-out read operation from NAND buffer 1 in command line 4 is inserted between the data shift-in read operations in commands 3 and 5.

[0047] Once the data payload of all TLC pages is transmitted to NAND page buffers 2, 3, and 4 via command lines 1, 3, and 5, the NAND controller 138 issues a media programming / write command in command line 6, which stores the data payload contained in NAND page buffers 2, 3, and 4 at the physical address specified in the write command in the NAND array 142. Figure 3E The pause operation is eliminated by changing the order of media operations, where media read operations occur before media programming / writing operations.

[0048] Figure 4This illustration shows an exemplary flowchart of a method 400 for controlling the transfer of data into and out of an array-based CMOS (CuA) non-volatile semiconductor memory device 140 using an explicit buffer, according to embodiments of the present disclosure. The method can be implemented by the SoC controller 130 of an SSD 120, as described above regarding... Figure 1 Description. The SoC controller 130 generates NAND commands based on commands received from the host 110 or commands generated internally by the firmware (e.g., obsolete item collection), which are then sent to the NAND controller 138. The method begins at step 410, where the SoC controller 130 issues a command to the non-volatile semiconductor memory device 140 relating to the transfer of a data payload back and forth between the memory device 140 and the memory device 140. In some embodiments, the NAND controller 138 within the SoC controller 130 explicitly identifies n NAND page buffers 145 in the memory device 140 where the data payload relating to the command will be transferred. In some embodiments, the NAND page buffers 145 are identified by a unique buffer identifier known to the NAND controller 138.

[0049] Next, in step 420, the method determines whether the command from the SoC controller 130 includes a programming / write command or a read command. If the command includes a programming / write command (i.e., 'No (N)' in step 420), then the SoC controller 130 transfers the data payload from the SoC controller 130 to a subset of the n NAND page buffers 145 via a shift-in write operation according to step 430. Then, in step 440, the SoC controller 130 issues a media programming / write command such that the NAND memory device 142 stores the data payload contained in the subset of the n NAND page buffers in the memory array 142 at the NAND physical address specified in the original write command. In some embodiments, step 440 may be omitted or performed at a later time, for example, if a higher-priority command, such as a read command, needs to be executed first. If the command includes a read command (i.e., 'Yes (Y)' in step 420), then the SoC controller 130, according to step 450, causes the data payload stored in the NAND array 142 at the NAND physical address specified in the original read command from host 110 to be transferred to a subset of n NAND page buffers 145. Then, in step 460, the SoC controller 130 transfers the data payload from the subset of n NAND page buffers 145 to the SoC controller 130 for delivery to host 110 via a data shift-out read operation. In some embodiments, step 460 may be omitted or performed at a later time.

[0050] In the foregoing, all descriptions of “layer” and “engine” should be understood to mean multiple circuits within a controller that facilitate the described function. Such circuits may include electronic components formed on a semiconductor chip, such as (for example) transistors and resistors. It should be noted that the terms “about” or “approximately” in the foregoing indicate a range of ±20% of the stated value. Additionally, all descriptions of “command,” “action,” or “function” in the foregoing should be understood to be based on algorithms and instructions stored on a non-transitory computer-readable medium, which, when executed by a processor, cause the controller of the integrated circuit of the solid-state drive (SSD) to perform commands, actions, or functions. Furthermore, in the foregoing, the terms “write” and “program” are used interchangeably with respect to commands and both relate to the function of transferring a data payload to a specific physical address in the memory device. Regarding the foregoing disclosure, the memory array comprises memory cells, each storing n bits, where n is any integer. For example, n=1 for a single-level memory cell (SLC), n=2 for a multi-level memory cell (MLC), n=3 for a three-level memory cell (TLC), n=4 for a four-level memory cell (QLC), and n=5 for a variable-level memory cell (VLC).

[0051] Those skilled in the art will appreciate other objects, advantages, and embodiments of the various aspects of the invention, which are within the scope of the description and drawings. For example, but not limited to, structural or functional elements can be rearranged according to the invention. Similarly, the principles of the invention can be applied to other instances, which, even if not explicitly described in detail herein, are still within the scope of the invention.

Claims

1. A memory storage system, comprising: A non-volatile semiconductor memory device, comprising a memory array and multiple buffers; and A controller, which communicates with the plurality of buffers and is configured to issue commands to the non-volatile semiconductor memory device to specify a subset of n buffers from the plurality of buffers in which a data payload associated with the command will be transmitted. The plurality of buffers includes a subset of an internal buffer and a subset of m buffers, the subset of the internal buffer and the subset of m buffers being separate from the subset of n buffers, and the controller being further configured to transfer a data payload associated with a first command between the subset of n buffers and the memory array, and to transfer a data payload associated with a second command issued after the first command, contained in the subset of m buffers, to the internal buffer when the transfer of the data payload associated with the first command is nearly complete.

2. The memory storage system of claim 1, wherein when the command includes a data shift command, the controller is configured to transfer the data payload from the controller to the subset of n buffers.

3. The memory storage system of claim 2, wherein the controller is further configured to issue a media write command such that the non-volatile memory device stores data in the subset contained in the n buffers in the memory array.

4. The memory storage system of claim 1, wherein when the command includes a media read command, the controller is configured such that the non-volatile memory device transfers the data payload from the memory array to the subset of n buffers.

5. The memory storage system of claim 4, wherein the controller is further configured to issue a data shift command to transfer the data payload contained in the subset of n buffers to the controller.

6. The memory storage system of claim 1, wherein the controller is configured to use a unique buffer identifier for at least one buffer in the subset of n buffers when specifying the subset of n buffers among the plurality of buffers.

7. The memory storage system of claim 1, wherein the controller is configured to issue at least one command at any time to cause the data payload to be transferred between the subset of the n buffers and the memory array.

8. The memory storage system of claim 1, wherein the controller is configured to pause, complete, and resume the transmission of the data payload between the subset of n buffers associated with the first command and the memory array before completion, complete the transmission of the data payload between the subset of m buffers associated with the second command and the memory array, and resume the transmission of the data payload associated with the first command.

9. The memory storage system of claim 8, wherein the first command is associated with a first priority value and the second command is associated with a second priority value different from the first priority value, the second priority value being greater than the first priority value.

10. The memory storage system of claim 1, wherein the controller is configured to perform in parallel any number of transfers of the data payload between the controller and the plurality of buffers and the transfer of the data payload between the subset of the n buffers and the memory array.

11. The memory storage system of claim 1, wherein the memory storage system comprises memory cells, each storing at least one bit.

12. The memory storage system according to claim 11, wherein the memory storage system includes a single-layer memory cell (SLC), a pseudo-single-layer memory cell (pSLC), a multi-layer memory cell (MLC), a three-layer memory cell (TLC), a four-layer memory cell (QLC), and a variable-layer memory cell (VLC).

13. The memory storage system of claim 1, wherein the non-volatile semiconductor memory device is an array-based CMOS CUA NAND semiconductor memory.

14. The memory storage system of claim 1, wherein the controller comprises a system-on-a-chip (SoC) controller.

15. A method executed by a controller of a memory storage system, the memory storage system comprising a non-volatile semiconductor memory device having a memory array and a plurality of buffers, and the controller communicating with the plurality of buffers, the method comprising: A command is issued to the non-volatile semiconductor memory device to specify a subset of n buffers among the plurality of buffers in which a data payload associated with the command will be transmitted; The data payload associated with the first command is transferred between the subset of n buffers and the memory array; as well as When the transmission of the data payload associated with the first command is almost complete, the data payload associated with the second command issued after the first command, contained in a subset of m buffers, is transmitted to the internal buffer.

16. The method of claim 15, further comprising: When the command includes a data transfer command, the data payload is transferred from the controller to the subset of n buffers.

17. The method of claim 16, further comprising: A media write command is issued such that the non-volatile memory device stores the data contained in the subset of n buffers in the memory array.

18. The method of claim 15, further comprising: When the command includes a media read command, the non-volatile memory device causes the data payload to be transferred from the memory array to the subset of n buffers.

19. The method of claim 18, further comprising: A data shift command is issued to transfer the data payload contained in the subset of n buffers to the controller.

20. The method of claim 15, further comprising: When specifying a subset of n buffers among the plurality of buffers, a unique buffer identifier is used for at least one buffer in the subset of n buffers.

21. The method of claim 15, further comprising: At any given time, at least one command is issued to cause the data payload to be transferred between the subset of the n buffers and the memory array.

22. The method of claim 15, further comprising: The transfer of the data payload between the subset of the n buffers associated with the first command and the memory array is paused until completion; Complete the transfer of the data payload between the subset of m buffers associated with the second command and the memory array; Resume the transmission of the data payload associated with the first command.

23. The method of claim 22, wherein the first command is associated with a first priority value and the second command is associated with a second priority value that is different from the first priority value, the second priority value being greater than the first priority value.

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