Memory device and storage device including the same

Abstract

A memory device and a memory system including the same are provided herein. The memory device includes an input / output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device to perform an operation to store the data in a memory cell of the memory device based on the command and the address received from the input / output circuit. The input / output circuit includes a queue layer configured to temporarily store the command and the address, and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to an electronic device, and more specifically, to a memory device and a storage device including the memory device. Background Technology

[0002] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Such memory devices are classified as volatile memory devices or non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is off. Volatile memory devices include, for example, static random access memory (SRAM) or dynamic random access memory (DRAM).

[0004] Non-volatile memory devices are memory devices that retain stored data even when power is off. Non-volatile memory devices include, for example, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a memory device including a queue layer capable of processing high-speed input commands and addresses, and a storage device including the memory device.

[0006] One embodiment of this disclosure relates to a memory device. The memory device may include input / output circuitry configured to receive commands, addresses, and data from a memory controller. The memory device may also include control logic configured to control peripheral circuitry of the memory device to perform operations that store data in memory cells of the memory device based on the commands and addresses received from the input / output circuitry. The input / output circuitry may include a queue layer configured to temporarily store commands and addresses, and to output commands and addresses to the control logic based on at least one rising edge and falling edge of a write enable signal received by the memory device from the memory controller.

[0007] One embodiment of this disclosure relates to a storage device. The storage device may include a memory device configured to store data based on commands and addresses. The storage device may also include a memory controller configured to send commands, addresses, and data to the memory device. The memory device may include a queue layer. The queue layer is configured to temporarily store commands and addresses received from the memory controller and output the commands and addresses to the control logic of the memory device based on at least one rising edge and falling edge of a write enable signal received from the memory controller. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a storage device according to one embodiment of the present disclosure.

[0009] Figure 2 This is a diagram illustrating the signals exchanged between a memory device and a memory controller according to one embodiment of the present disclosure.

[0010] Figure 3 This is a block diagram illustrating a memory device according to one embodiment of the present disclosure.

[0011] Figure 4 This is a diagram illustrating a storage block according to one embodiment of the present disclosure.

[0012] Figure 5 This is a diagram illustrating a single data rate (SDR) according to one embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating a dual data rate (DDR) according to one embodiment of the present disclosure.

[0014] Figure 7 This is a diagram illustrating a queue layer according to one embodiment of the present disclosure.

[0015] Figure 8 This is a timing diagram describing the operation of input commands and addresses according to one embodiment of this disclosure.

[0016] Figure 9 This is a diagram illustrating data lines according to one embodiment of the present disclosure.

[0017] Figure 10 This is a diagram illustrating a command / address (CA) input controller according to one embodiment of the present disclosure.

[0018] Figure 11 This is a block diagram illustrating a memory controller according to one embodiment of the present disclosure.

[0019] Figure 12This is a diagram illustrating a memory card system according to one embodiment of the present disclosure.

[0020] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system according to one embodiment of the present disclosure.

[0021] Figure 14 This is a diagram illustrating a user system according to one embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are illustrated to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0023] This disclosure will now be described in detail based on its implementation. However, this disclosure can be implemented in many different forms and should not be construed as limited to the implementations set forth herein, but rather as covering variations, equivalents, or alternatives that fall within the spirit and scope of this disclosure. However, this is not intended to limit this disclosure to a particular mode of practice, and it should be understood that all variations, equivalents, and alternatives that do not depart from the spirit and scope of this disclosure are included herein. Detailed descriptions of functions and structures well known to those skilled in the art will be omitted to avoid obscuring the subject matter of this disclosure. This is intended to omit unnecessary descriptions to make the subject matter of this disclosure clear.

[0024] In the following, the present disclosure will be described in detail with reference to the accompanying drawings and embodiments thereof.

[0025] Figure 1 This is a block diagram illustrating a storage device according to one embodiment of the present disclosure.

[0026] Reference Figure 1 The storage device 1000 may include a memory device 100 and a memory controller 200.

[0027] Storage device 1000 may be a device that stores data under the control of host 2000 (e.g., mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC, or in-vehicle infotainment system).

[0028] Depending on the host interface used for communication with the host 2000, the storage device 1000 can be implemented as any of various types of storage devices. For example, the storage device 1000 can be implemented as a solid-state drive (SSD), a multimedia card such as MMC, embedded MMC (eMMC), size-reduced MMC (RS-MMC), or micro MMC, a secure digital card such as SD, mini-SD, or micro-SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a PCMCIA card storage device, a peripheral component interconnect (PCI) card storage device, a PCI Express (PCI-E) card storage device, a compact flash (CF) card, a smart media card, and a memory stick, among other types of storage devices.

[0029] The storage device 1000 can be implemented in any of various types of package forms. For example, the storage device 1000 can be implemented in any of the following types of package forms: point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0030] The memory device 100 can store data or use the stored data. Specifically, the memory device 100 can operate in response to the control of the memory controller 200. Furthermore, the memory device 100 may include a plurality of memory dies, each memory die including a memory cell array comprising a plurality of memory cells storing data.

[0031] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0032] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and a memory block may include multiple pages. Here, each page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0033] The memory device 100 can be implemented using the following methods: dual data rate synchronous dynamic random access memory (DDR SDRAM), low power dual data rate fourth generation (LPDDR4) SDRAM, graphics dual data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory device, resistive RAM (RRAM), phase change memory (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), or spin-transfer torque RAM (STT-RAM). In this specification, for ease of description, it will be assumed that the memory device 100 includes NAND flash memory.

[0034] Memory device 100 may receive commands and addresses from memory controller 200. Memory device 100 may access a region in the memory cell array selected by the received address. Accessing the selected region may indicate performing an operation corresponding to the received command on the selected region. For example, memory device 100 may perform a write operation (i.e., a programming operation), a read operation, or an erase operation. Here, a programming operation may be an operation in which memory device 100 writes data to the region selected by the address. A read operation may be an operation in which memory device 100 reads data from the region selected by the address. An erase operation may be an operation in which memory device 100 erases data stored in the region selected by the address.

[0035] According to one embodiment of this disclosure, the memory device 100 may include a queue layer 50. Specifically, the memory device 100 may temporarily store commands and addresses received from the memory controller 200 in the queue layer 50. The memory device 100 can process high-speed input commands and addresses by including the queue layer 50. Conventional technologies have evolved to include forms where data is input at high speed and the input data is processed, but the input speed of commands and addresses is fixed at a certain speed (e.g., 400 Mbps). As the difference between the input speed of commands and addresses and the input speed of data increases, the performance improvement of the memory device is limited. This disclosure includes a queue layer 50 capable of processing high-speed input commands and addresses, thus enabling high-speed input of commands and addresses, and enabling input of commands and addresses at double data rate (DDR).

[0036] The memory controller 200 can control the overall operation of the storage device 1000.

[0037] When power is supplied to the storage device 1000, the memory controller 200 may run firmware (FW). The firmware (FW) may include a host interface layer (HIL) that receives requests from or outputs responses to the host 2000, a flash translation layer (FTL) that manages the operation between the interface of the host 2000 and the interface of the storage device 100, and a flash interface layer (FIL) that provides commands to or receives responses from the storage device 100.

[0038] The memory controller 200 can receive data and logical addresses (LA) from the host 2000, and can translate the logical addresses into physical addresses (PAs) that indicate the addresses of memory cells included in the memory device 100 and where data will be stored. The logical address can be a logical block address (LBA), and the physical address can be a physical block address (PBA).

[0039] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to requests received from the host 2000. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, physical block addresses, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and physical block addresses. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and physical block addresses.

[0040] The memory controller 200 can control the memory device 100 to autonomously perform programming, reading, or erasing operations regardless of requests received from the host 2000. For example, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations that will be used to perform background operations (e.g., wear leveling, garbage collection, and read-and-reclaim operations).

[0041] The host 2000 can communicate with the storage device 1000 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Unloaded DIMM (LRDIMM).

[0042] Figure 2This is a diagram illustrating the signals exchanged between a memory device and a memory controller according to one embodiment of the present disclosure.

[0043] Reference Figure 2 The memory device 100 can communicate with the memory controller 200 via the data (DQ) line, chip enable (CE) line, write enable (WE_N) line, read enable (RE_N) line, address latch enable (ALE) line, command latch enable (CLE) line, write protect (WP_N) line, and ready / busy (RB) line.

[0044] Despite Figure 2 The diagram illustrates the connection between a memory device 100 and a memory controller 200. However, according to one embodiment, this can also be applied to the connection between the memory controller 200 and multiple memory devices. For example, data (DQ) lines, chip enable (CE) lines, write enable (WE_N) lines, read enable (RE_N) lines, address latch enable (ALE) lines, command latch enable (CLE) lines, write protect (WP_N) lines, and ready / busy (RB) lines can be included in a channel through which the memory controller 200 and multiple memory devices can be interconnected. Therefore, when the memory controller 200 sends a signal through the lines included in a channel, all memory devices connected to the corresponding channel, or the memory device 100 selected by the memory controller 200 from the memory devices connected to the corresponding channel, can receive the signal.

[0045] The data (DQ) lines can input commands, addresses, and data from the memory controller 200 to the memory device 100, or output data from the memory device 100 to the memory controller 200. The data (DQ) lines can consist of eight lines, enabling the transmission / reception of eight bits of data (8-bit data), where each line can transmit / receive one bit of data. However, in various embodiments, the number of data (DQ) lines is not limited to eight and can be extended to, for example, 16 or 32.

[0046] The chip enable (CE) line can transmit a chip enable (CE) signal indicating that the memory device 100 is operable. The chip enable (CE) signal can be selectively applied to memory devices connected to the same channel. When the chip enable (CE) signal transitions to a low state (e.g., a low voltage state distinct from a high voltage state), it can indicate that all operations in the memory device 100 are available. A high chip enable (CE) signal can indicate that the corresponding memory device 100 is in a standby state.

[0047] Memory device 100 can receive a read enable (RE_N) signal via a read enable (RE_N) line and a write enable (WE_N) signal via a write enable (WE_N) line. The read enable (RE_N) signal can be toggled when data is loaded into memory controller 200, and the write enable (WE_N) signal can be toggled when commands and addresses are loaded into memory device 100. In one embodiment, commands and addresses can be input to the selected memory device 100 when the write enable (WE_N) signal transitions from low to high (i.e., at the rising edge of the write enable (WE_N) signal). In another embodiment, commands and addresses can be input to the selected memory device 100 when the write enable (WE_N) signal transitions from high to low (i.e., at the falling edge of the write enable (WE_N) signal). In one implementation, commands and addresses can be input to the selected memory device 100 when the write enable (WE_N) signal transitions from low to high and from high to low (i.e., at the rising and falling edges of the write enable (WE_N) signal).

[0048] The Command Latch Enable (CLE) line can transmit a Command Latch Enable (CLE) signal for inputting a command. Specifically, the memory device 100 can receive the Command Latch Enable (CLE) signal from the memory controller 200 via the Command Latch Enable (CLE) line. Furthermore, the Command Latch Enable (CLE) signal can be high when the command CMD is input to the memory device 100.

[0049] The Address Latch Enable (ALE) line can transmit an Address Latch Enable (ALE) signal used for inputting an address. Specifically, memory device 100 can receive the Address Latch Enable (ALE) signal from memory controller 200 via the Address Latch Enable (ALE) line. The Address Latch Enable (ALE) signal can be high when address ADDR is input to memory device 100.

[0050] The memory device 100 can receive a write protection (WP_N) signal via a write protection (WP_N) line. The write protection (WP_N) signal can be a signal used to disable programming and erasing operations on the memory cell array.

[0051] When an operation is performed in the memory device 100, the Ready / Busy (RB) signal transmitted via the Ready / Busy (RB) line may be in a low state. When the Ready / Busy (RB) signal is low, the memory device 100 may not exchange other signals with external devices. A high Ready / Busy (RB) signal indicates that the memory device 100 is in a ready state. When the memory device 100 is in a ready state, the memory device 100 may exchange signals with external devices.

[0052] Figure 3 This is a block diagram illustrating a memory device according to one embodiment of the present disclosure.

[0053] Reference Figure 3 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0054] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the row decoder 121 via row lines RL. Here, the row line RL may include at least one source select line, multiple word lines, and at least one drain select line. Each of the memory blocks BLK1 to BLKz can be connected to the page buffer group 123 via bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a single page. Therefore, a single memory block may include multiple pages.

[0055] Each of the memory cells included in the memory cell array 110 can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0056] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected areas of the memory cell array 110 under the control of the control logic 130. In other words, the peripheral circuit 120 can drive the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn, or discharge the applied voltages, under the control of the control logic 130.

[0057] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0058] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. Furthermore, the row line RL may also include a pipe select line.

[0059] The row decoder 121 can operate in response to control of the control logic 130. The row decoder 121 can receive the row address RADD from the control logic 130. Specifically, the row decoder 121 can decode the row address RADD. The row decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded address. Furthermore, the row decoder 121 can select at least one word line WL of the selected memory block based on the decoded address, thereby applying a voltage generated by the voltage generator 122 to the at least one word line WL.

[0060] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and apply a programming pass voltage with a level lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage with a level higher than the verification voltage to the unselected word line. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a level higher than the read voltage to the unselected word line.

[0061] In one implementation, the erase operation of the memory cell array 110 can be performed based on memory blocks. During the erase operation, the row decoder 121 can select a memory block based on the decoded address and can apply a ground voltage to the word line connected to the selected memory block.

[0062] Voltage generator 122 can operate under the control of control logic 130. More specifically, voltage generator 122 can generate multiple voltages using the external power supply voltage provided to memory device 100 under the control of control logic 130. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130. That is, voltage generator 122 can generate various operating voltages Vop for programming operations, read operations, and erase operations in response to the operation signal OPSIG.

[0063] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory cell array 110.

[0064] In one embodiment, voltage generator 122 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages, and multiple voltages can be generated by selectively activating the multiple pump capacitors under the control of control logic 130. Furthermore, the multiple generated voltages can be provided to memory cell array 110 by row decoder 121.

[0065] Page buffer group 123 may include first page buffers PB1 to nth page buffers PBn. First page buffers PB1 to nth page buffers PBn may be connected to memory cell array 110 via first bit line BL1 to nth bit line BLn, respectively. Furthermore, first page buffers PB1 to nth page buffers PBn may operate under the control of control logic 130. Specifically, first page buffers PB1 to nth page buffers PBn may operate in response to page buffer control signal PBSIGNALS. For example, first page buffers PB1 to nth page buffers PBn may sense the voltage or current of bit lines BL1 to BLn during read or verification operations, or may temporarily store data received via first bit line BL1 to nth bit line BLn.

[0066] Specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell in the selected page can be programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained.

[0067] During the programming verification operation, page data can be read from the selected memory cell through the first bit line BL1 to the nth bit line BLn.

[0068] During a read operation, the first page buffer PB1 to the nth page buffer PBn can read data DATA from the memory cell in the selected page through the first bit line BL1 to the nth bit line BLn, and can output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0069] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can float the first bit line BL1 to the nth bit line BLn.

[0070] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0071] The input / output circuit 125 can transmit commands (CMD) and addresses (ADDR) received from the memory controller 200 to the control logic 130, or it can exchange data (DATA) with the column decoder 124. According to one embodiment of this disclosure, the input / output circuit 125 may include a queue layer 50, and the input / output circuit 125 can use the queue layer 50 to transmit high-speed input commands (CMD) and addresses (ADDR) to the control logic 130.

[0072] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current, and then output a pass signal PASS or a failure signal FAIL.

[0073] Control logic 130 can respond to commands CMD and address ADDR by controlling peripheral circuitry 120 through outputting operation signals OPS1G, row address RADD, page buffer control signals PBSIGNALS, and enable bit signal VRYBIT. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0074] Furthermore, control logic 130 can determine whether the verification operation passes or fails in response to a PASS signal or a FAIL signal. Additionally, control logic 130 can control page buffer group 123 to temporarily store verification information, including the PASS signal or FAIL signal, in page buffer group 123. Specifically, control logic 130 can determine the programming state of each memory cell in response to a PASS signal or a FAIL signal. For example, when the memory cell operates as a three-level cell (TLC), control logic 130 can determine whether the programming state of the memory cell is erase state E or any of the first programming states P1 to the seventh programming states P7. According to one embodiment of this disclosure, control logic 130 can set the mode of queue layer 50. Specifically, control logic 130 can control queue layer 50 such that queue layer 50 operates in either single data rate (SDR) mode or dual data rate (DDR) mode.

[0075] Figure 4 This is a diagram illustrating a storage block according to one embodiment of the present disclosure.

[0076] Reference Figure 4 Multiple word lines arranged parallel to each other between the first and second select lines can be connected to the memory block BLKi. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL. Specifically, the memory block BLKi can include multiple string STs connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn can be connected to each string ST individually, and the source line SL can be connected to each string ST collectively. The string STs can be configured equally, so the string ST connected to the first bit line BL1 will be described in detail by way of example.

[0077] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and the string ST may include more memory cells than the memory cells F1 to F16 shown in the figure.

[0078] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL, and the gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16 respectively. Among the memory cells included in different string STs, a group of memory cells connected to the same word line can be referred to as a "physical page (PPG)". Therefore, the memory block BLKi can include the same number of physical pages (PPGs) as the number of word lines WL1 to WL16.

[0079] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0080] A single-level cell (SLC) can store 1 bit of data. A physical page (PPG) of a single-level cell can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PPG).

[0081] Multilevel cells (MLC), three-level cells (TLC), and four-level cells (QLC) can store two or more bits of data. Here, a physical page (PPG) can store data corresponding to two or more logical pages (LPG).

[0082] Figure 5 This is a diagram illustrating a single data rate (SDR) according to one embodiment of the present disclosure.

[0083] Reference Figure 5 The diagram shows the data (DQ) line, write enable (WE#) signal, and data strobe (DQS) signal. A brief illustration is provided. Figure 5 The accompanying drawings illustrate a method for inputting commands CMD, address ADDR, and data DATA, and the implementation of this disclosure is not limited thereto.

[0084] Data (DQ) lines can be used to input commands, addresses, and data, or to output data. Specifically, memory device 100 can use data (DQ) lines to receive commands, addresses, and data from memory controller 200, or to output data to memory controller 200.

[0085] The write enable (WE#) signal can be toggled when commands and addresses are loaded into memory device 100. For example, memory device 100 can load commands and addresses from memory controller 200 in response to the write enable (WE#) signal.

[0086] When data is loaded into memory device 100, the data strobe (DQS) signal can be switched. For example, memory device 100 can load data from memory controller 200 in response to the data strobe (DQS) signal.

[0087] According to one embodiment of this disclosure, the memory device 100 can load commands and addresses at a single data rate (SDR). Here, SDR can be the speed (rate) at which data is input, such as at the rising or falling edge of a switching signal. (See also...) Figure 5 When the write enable (WE#) signal transitions from low to high, the memory device 100 can load a command or address. Additionally, the memory device 100 can load data at a dual data rate (DDR). Here, DDR can refer to a rate at which data is input on the rising and falling edges of a switching signal. (See reference...) Figure 5 The memory device 100 can load data when the data strobe (DQS) signal transitions from low to high and from high to low.

[0088] Figure 6 This is a diagram illustrating a dual data rate (DDR) according to one embodiment of the present disclosure.

[0089] Reference Figure 6 The data (DQ) line, write enable (WE#) signal, and data strobe (DQS) signal are shown. A brief illustration is provided. Figure 6 The accompanying drawings illustrate a method for inputting commands CMD, address ADDR, and data DATA, and the implementation of this disclosure is not limited thereto.

[0090] Data (DQ) lines can be used to input commands, addresses, and data, or to output data. Specifically, memory device 100 can use data (DQ) lines to receive commands, addresses, and data from memory controller 200, or to output data to memory controller 200.

[0091] The write enable (WE#) signal can be toggled when commands and addresses are loaded into memory device 100. For example, memory device 100 can load commands and addresses from memory controller 200 in response to the write enable (WE#) signal.

[0092] When data is loaded into memory device 100, the data strobe (DQS) signal can be switched. For example, memory device 100 can load data from memory controller 200 in response to the data strobe (DQS) signal.

[0093] According to one embodiment of this disclosure, the memory device 100 can load commands and addresses at a dual data rate (DDR). Here, DDR can be a rate at which data is input on the rising and falling edges of a switching signal, etc. (See also...) Figure 6 When the write enable (WE#) signal transitions from low to high and from high to low, the memory device 100 can load a command or address. That is, the memory device 100 can load a command or address on both the rising and falling edges of the write enable (WE#) signal. Furthermore, the memory device 100 can load data at a dual data rate (DDR). Here, DDR can refer to a rate at which data is input on the rising and falling edges of a switching signal, etc. (See reference...) Figure 6 The memory device 100 can load data when the data strobe (DQS) signal transitions from low to high and from high to low.

[0094] Figure 7 This is a diagram illustrating a queue layer according to one embodiment of the present disclosure.

[0095] Reference Figure 7 The queue layer 50 may include a command latch 51, an address latch 52, a data latch 53, a queue layer controller 54, a clock generator 55, and a counter 56.

[0096] Command latch 51 can latch a command latch enable (CLE) signal received from memory controller 200. Specifically, queue layer 50 can receive a command latch enable (CLE) signal from memory controller 200 via a command latch enable (CLE) line, and can latch the received command latch enable (CLE) signal in command latch 51. Here, latching can mean temporarily holding or storing a signal state for a certain period of time. That is, command latch 51 can temporarily store the input command latch enable (CLE) signal. According to one embodiment of this disclosure, command latch 51 can latch a high-speed input command latch enable (CLE) signal, and input / output circuit 125 can input the received command to control logic 130 in response to the command latch enable (CLE) signal and write enable (WE) signal latched in command latch 51.

[0097] Address latch 52 can latch an address latch enable (ALE) signal received from memory controller 200. Specifically, queue layer 50 can receive an address latch enable (ALE) signal from memory controller 200 via an address latch enable (ALE) line, and can latch the received address latch enable (ALE) signal in address latch 52. That is, address latch 52 can temporarily store the input address latch enable (ALE) signal. According to one embodiment of this disclosure, address latch 52 can latch a high-speed input address latch enable (ALE) signal, and input / output circuit 125 can input the received address to control logic 130 in response to the address latch enable (ALE) signal and write enable (WE) signal latched in address latch 52.

[0098] Data latch 53 can temporarily store commands, addresses, and data input from memory controller 200. Specifically, queue layer 50 can receive commands, addresses, and data via data (DQ) lines and latch the received commands, addresses, and data in data latch 53. That is, data latch 53 can temporarily store input commands, addresses, and data. According to one embodiment of this disclosure, data latch 53 can latch high-speed input commands, addresses, and data, and input / output circuit 125 can input commands, addresses, and data to control logic 130 in response to write enable (WE) signal and command latch enable (CLE) signal, or in response to write enable (WE) signal and address latch enable (ALE) signal.

[0099] The queue layer controller 54 can control the overall operation of the queue layer. Specifically, the queue layer controller 54 can perform control over the queue layer 50, causing the command latch 51, address latch 52, and data latch 53 to reset. Furthermore, the queue layer controller 54 can perform control to reset the clock generator 55 and counter 56.

[0100] Furthermore, the queue layer controller 54 can perform control to change the operating mode of the queue layer 50 from SDR mode to DDR mode or vice versa. Specifically, under the control of the control logic 130, the queue layer controller 54 can change the operating mode of the queue layer 50 from SDR mode to DDR mode. Additionally, the queue layer controller 54 can control the data latch 53, thereby sending the command latch enable (CLE) signal and address latch enable (ALE) signal, respectively latched in the command latch 51 and address latch 52, to the control logic 130.

[0101] Clock generator 55 can generate clock signals that are input to command latch 51, address latch 52, and data latch 53. Command latch 51 and address latch 52 can distribute and latch the command latch enable (CLE) signal and address latch enable (ALE) signal in response to the clock signal generated by clock generator 55. That is, clock generator 55 can generate clock signals for internal operation.

[0102] Counter 56 can count the write enable (WE) signals input to input / output circuit 125. Specifically, when a write enable (WE) signal is input from memory controller 200, counter 56 can count the input write enable (WE) signal. Furthermore, when the count value obtained by counter 56, which counts the write enable (WE) signals, corresponds to a set of commands and addresses, queue layer controller 54 can control clock generator 55 to generate a signal indicating that the transmission of a set has been completed (e.g., CLK_1).

[0103] Figure 8 This is a timing diagram describing the operation of input commands and addresses according to one embodiment of this disclosure.

[0104] Reference Figure 8This document describes the timing diagrams for the Command Latch Enable (CLE) signal, Address Latch Enable (ALE) signal, Data (DQ) line, and Write Enable (WE) signal. When the Command Latch Enable (CLE) signal is high, the command cycle is enabled. Furthermore, the queue layer controller 54 can receive the 0th data DQ 0 in response to the Write Enable (WE) signal. Specifically, when the Write Enable (WE) signal transitions from low to high while the Command Latch Enable (CLE) signal is high, the queue layer controller 54 can receive the 0th data DQ 0. Additionally, when the Write Enable (WE) signal transitions from high to low while the Command Latch Enable (CLE) signal is high, the queue layer controller 54 can receive the first data DQ 1. When the Command Latch Enable (CLE) signal is low, the command cycle is disabled. Furthermore, when the Address Latch Enable (ALE) signal is high, the address cycle is enabled. When the address latch enable (ALE) signal is high and the write enable (WE) signal transitions from low to high, the queue layer controller 54 can receive the second data DQ 2. Subsequently, the queue layer controller 54 can receive the third data DQ 3, the fourth data DQ 4, the fifth data DQ 5, the sixth data DQ 6, the seventh data DQ 7, the eighth data DQ 8, and the ninth data DQ 9 on the rising or falling edge of the write enable (WE) signal. Here, the 0th data DQ 0 and the first data DQ 1 can be commands, the second data DQ 2 and the third data DQ 3 can be column addresses, the fourth data DQ 4 to the eighth data DQ 8 can be row addresses, and the ninth data DQ 9 can be a command.

[0105] Figure 9 This is a diagram illustrating data lines according to one embodiment of the present disclosure.

[0106] Reference Figure 9 The diagram shows data lines DQ_0 to DQ_9, the first clock signal CLK_1, the clock reset signal CLK_rst, and the counter's count value.

[0107] In one implementation, each of the data lines DQ_0 to DQ_9 can transmit / receive eight bits of data. Furthermore, each of the data lines DQ_0 to DQ_9 can send commands or addresses to the control logic 130. Specifically, data line DQ_0 and the first data line DQ_1 can send commands to the control logic 130, and data lines DQ_2 to DQ_8 can send addresses to the control logic 130. In particular, data lines DQ_2 and DQ_3 can send column addresses to the control logic 130, and data lines DQ_4 to DQ_8 can send row addresses to the control logic 130. Additionally, the ninth data line DQ_9 can send commands to the control logic 130.

[0108] Figure 10 This is a diagram illustrating a command / address (CA) input controller according to one embodiment of the present disclosure.

[0109] Reference Figure 10 The diagram shows a memory controller 200 including a CA input controller 210 and a memory interface 220, a mode setting controller 135, and a queue layer 50.

[0110] The memory controller 200 can input commands and addresses to the memory device 100 using the memory interface 220. Furthermore, the CA input controller 210 can control the input speed of commands and addresses from the memory controller 200. More specifically, the CA input controller 210 can control the input speed of commands and addresses from the memory interface 220, thereby increasing the input speed. Under the control of the CA input controller 210, the memory interface 220 can increase the input speed of commands and addresses to a speed equal to the input speed of data.

[0111] Furthermore, the CA input controller 210 can control the mode setting controller 135 included in the control logic 130, thereby changing the operating mode of the queue layer 50. The mode setting controller 135 or the queue layer 50 can store operating mode setting information corresponding to SDR or DDR, and the CA input controller 210 can control the mode setting controller 135 to operate based on the operating mode setting information corresponding to SDR or DDR during a reset operation of the memory device 100 or an initialization operation of setting initial parameters. The mode setting controller 135 can change the mode of the queue layer 50 under the control of the CA input controller 210, thereby changing the queue layer 50 operating in SDR mode to DDR mode, or changing the queue layer 50 operating in DDR mode to SDR mode.

[0112] Figure 11This is a block diagram illustrating a memory controller according to one embodiment of the present disclosure.

[0113] Reference Figure 11 The memory controller 1300 may include a processor 1310, RAM 1320, error correction circuit (ECC circuit) 1330, ROM 1360, host interface 1370 and memory interface 1380. Figure 11 The memory controller 1300 shown can be Figure 1 One embodiment of the memory controller 200 shown.

[0114] Processor 1310 can communicate with host 2000 using host interface 1370 and can perform logical operations to control the operation of memory controller 1300. For example, in response to requests received from host 2000 or external devices, processor 1310 can load programming commands, data files, data structures, etc., and can perform various types of operations or generate commands and addresses. For example, processor 1310 can generate various commands required for programming operations, read operations, erase operations, suspend operations, and parameter setting operations.

[0115] Furthermore, the processor 1310 can perform the functions of a flash translation layer (FTL). The processor 1310 can use the FTL to translate logical block addresses (LBAs) provided by the host 2000 into physical block addresses (PBAs). The FTL can receive LBAs and use a mapping table to translate LBAs into PBAs. Examples of address mapping methods performed by the FTL can include various methods depending on the mapping unit. Representative address mapping methods include page mapping, block mapping, and hybrid mapping methods.

[0116] Furthermore, the processor 1310 can generate commands even when no request is received from the host 2000. For example, the processor 1310 can generate commands for background operations (e.g., operations for wear leveling of the memory device 100 and operations for garbage collection of the memory device 100).

[0117] RAM 1320 can be used as a buffer memory, working memory, or cache memory for processor 1310. RAM 1320 can store code and commands executed by processor 1310. RAM 1320 can store data processed by processor 1310. Furthermore, in the implementation of RAM 1320, RAM 1320 can be implemented as either static RAM (SRAM) or dynamic RAM (DRAM).

[0118] Error correction circuit 1330 can detect and correct errors during programming or reading operations. Specifically, error correction circuit 1330 can perform error correction operations based on error correction codes (ECC). Furthermore, error correction circuit 1330 can perform error correction encoding (ECC encoding) based on the data to be written to memory device 100. ECC-encoded data can be transmitted to memory device 100 via memory interface 1380. Additionally, error correction circuit 1330 can perform error correction decoding (ECC decoding) on ​​data received from memory device 100 via memory interface 1380.

[0119] ROM 1360 can be used as a storage unit to store various types of information required for the operation of memory controller 1300. Specifically, ROM 1360 may include a mapping table in which physical-logical address information and logical-physical address information can be stored. Furthermore, ROM 1360 can be controlled by processor 1310.

[0120] The host interface 1370 may include protocols for performing data exchange between the host 2000 and the memory controller 1300. In one embodiment, the memory controller 1300 may communicate with the host 2000 via at least one of the following various interface protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0121] The memory interface 1380 can communicate with the memory device 100 using a communication protocol under the control of the processor 1310. Specifically, the memory interface 1380 can send commands, addresses, and data to or receive commands, addresses, and data from the memory device 100 via channels. For example, the memory interface 1380 may include a NAND interface.

[0122] Figure 12 This is a diagram illustrating a memory card system according to one embodiment of the present disclosure.

[0123] Reference Figure 12 The memory card system 3000 may include a memory controller 3100, a memory device 3200, and a connector 3300.

[0124] The memory controller 3100 can be electrically connected to and access the memory device 3200. For example, the memory controller 3100 can control read operations, write operations, erase operations, and background operations of the memory device 3200. The memory controller 3100 can provide an interface between the memory device 3200 and the host. Furthermore, the memory controller 3100 can run firmware for controlling the memory device 3200.

[0125] For example, the memory controller 3100 may include components such as RAM, processing units, host interfaces, memory interfaces, and error correction circuitry.

[0126] The memory controller 3100 can communicate with external devices via connector 3300. The memory controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 3100 can communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe). In one embodiment, connector 3300 can be defined using at least one of the aforementioned communication protocols.

[0127] In one embodiment, the memory device 3200 may be implemented as any of a variety of non-volatile memory devices, including electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0128] The memory controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 3100 and the memory device 3200 can be integrated into a single semiconductor device, and thus a memory card such as a PC card (i.e., PCMCIA), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), or a universal flash memory (UFS) can be formed.

[0129] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system according to one embodiment of the present disclosure.

[0130] Reference Figure 13 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals SIG with the host 4100 through a signal connector 4001 and can be powered by a power connector 4002. The SSD 4200 may include an SSD controller 4210, multiple flash memory units 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0131] In one implementation, the SSD controller 4210 can perform the above-described reference. Figure 1 The memory controller 200 is described in terms of its functionality. The SSD controller 4210 can control multiple flash memory devices 4221 to 422n in response to a signal SIG received from the host 4100. In one embodiment, the signal SIG can indicate a signal based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG can be a signal defined by at least one of the following various interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe) interface.

[0132] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Power (PWR) can be supplied to auxiliary power supply 4230 from host 4100, and auxiliary power supply 4230 can be charged. Auxiliary power supply 4230 can power SSD 4200 when the power supply from host 4100 is not stable. In one implementation, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located within the motherboard and can also provide auxiliary power to SSD 4200.

[0133] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple flash memories 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of flash memories 4221 to 422n. Buffer memory 4240 may include volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or non-volatile memory (e.g., FRAM, ReRAM, STT-MRAM, and PRAM).

[0134] Figure 14 This is a diagram illustrating a user system according to one embodiment of the present disclosure.

[0135] Reference Figure 14 The user system 5000 may include an application processor 5100, a memory module 5200, a network module 5300, a storage module 5400, and a user interface 5500.

[0136] Application processor 5100 can execute components, operating systems (OS), or user programs included in user system 5000. In one embodiment, application processor 5100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 5000. Application processor 5100 may be provided as a system-on-a-chip (SoC).

[0137] Memory module 5200 can be used as main memory, working memory, buffer memory, or cache memory of user system 5000. Memory module 5200 may include volatile RAM (e.g., DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM) or non-volatile RAM (e.g., PRAM, ReRAM, MRAM, and FRAM). In one embodiment, application processor 5100 and memory module 5200 may be packaged based on a stacked package (POP) and then provided as a single semiconductor package.

[0138] Network module 5300 can communicate with external devices. In one embodiment, network module 5300 can support wireless communication, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, Wireless LAN (WLAN), UWB, Bluetooth, or WiFi. In one embodiment, network module 5300 may be included in application processor 5100.

[0139] Storage module 5400 can store data. For example, storage module 5400 can store data received from application processor 5100. Alternatively, storage module 5400 can send data stored in storage module 5400 to application processor 5100. In one embodiment, storage module 5400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In one embodiment, storage module 5400 can be provided as a removable storage medium (removable drive), such as an external drive or memory card of user system 5000.

[0140] In one embodiment, the storage module 5400 may include a plurality of non-volatile memory devices, each of which may be referenced above. Figures 1 to 10 The described memory device operates in the same manner. The memory module 5400 can be compared with the one described above. Figure 1 The described storage device 1000 operates in the same manner.

[0141] User interface 5500 may include an interface for inputting data or instructions to application processor 5100 or outputting data to external devices. In one embodiment, user interface 5500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 5500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0142] According to this disclosure, a memory device is provided that includes a queue layer capable of processing high-speed input commands and addresses, and a storage device including the memory device.

[0143] Cross-reference to related applications

[0144] This application claims priority to Korean Patent Application No. 10-2021-0033365, filed on March 15, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Input / output circuitry that receives commands, addresses, and data from a memory controller; as well as The control logic communicates with the input / output circuitry and controls the peripheral circuitry of the memory device to perform operations that store the data in memory cells of the memory device based on the commands and addresses received from the input / output circuitry. The input / output circuit includes: A queue layer, the queue layer comprising: A command latch, which communicates with the memory controller via a command latch enable line and latches a command latch enable signal input from the memory controller; An address latch, which communicates with the memory controller via an address latch enable line and latches an address latch enable signal input from the memory controller; and A data latch, which communicates with the memory controller via a data line, and temporarily stores the command, the address, and the data. The control logic communicates with the command latch, the address latch, and the data latch, and The queue layer temporarily stores the command and the address, and outputs the command and the address to the control logic based on at least one of the rising and falling edges of the write enable signal received by the memory device from the memory controller, and the latched command latch enable signal or the address latch enable signal.

2. The memory device according to claim 1, wherein, The queue layer also includes: A queue layer controller controls the queue layer, thereby outputting the command and the address from the queue layer to the control logic; A counter, which counts the number of switches in the write enable signal; and A clock generator that generates an internal clock signal corresponding to the command and the address.

3. The memory device according to claim 2, wherein, The queue layer controller outputs the command or the address to the control logic in response to the command latch enable signal or the address latch enable signal.

4. The memory device according to claim 1, wherein, The queue layer receives the command and the address from the memory controller in dual data rate (DDR) mode.

5. The memory device according to claim 4, wherein, The queue layer outputs the command and the address to the control logic in Single Data Rate (SDR) mode.

6. The memory device according to claim 1, wherein, Under the control of the memory controller, the control logic changes the mode of receiving the command and the address from single data rate (SDR) mode to dual data rate (DDR) mode.

7. The memory device according to claim 6, wherein, The control logic includes: A mode setting controller, which sets operation information corresponding to the SDR mode and the DDR mode.

8. The memory device according to claim 1, wherein, The input speed of the commands and addresses from the memory controller to the input / output circuit is higher than the output speed of the commands and addresses to the control logic.

9. A storage device, the storage device comprising: A memory device that stores data based on commands and addresses; as well as The memory controller sends the command, the address, and the data to the memory device. The memory device includes a queue layer, which includes: A command latch, which communicates with the memory controller via a command latch enable line and latches a command latch enable signal input from the memory controller; An address latch, which communicates with the memory controller via an address latch enable line and latches an address latch enable signal input from the memory controller; and A data latch, which communicates with the memory controller via a data line, and temporarily stores the command, the address, and the data. The queue layer temporarily stores the commands and addresses received from the memory controller, and Based on at least one of the rising and falling edges of the write enable signal received from the memory controller, and the latched command latch enable signal or the address latch enable signal, the command and the address are output to the control logic of the memory device. The control logic communicates with the command latch, the address latch, and the data latch.

10. The storage device according to claim 9, wherein, The queue layer also includes: A queue layer controller controls the queue layer, thereby outputting the command and the address from the queue layer to the control logic; A counter, which counts the number of switches in the write enable signal; and A clock generator that generates an internal clock signal corresponding to the command and the address.

11. The storage device according to claim 10, wherein, The queue layer controller outputs the command or the address to the control logic in response to the command latch enable signal or the address latch enable signal.

12. The storage device according to claim 9, wherein, The queue layer receives the command and the address from the memory controller in dual data rate (DDR) mode.

13. The storage device according to claim 12, wherein, The queue layer outputs the command and the address to the control logic in Single Data Rate (SDR) mode.

14. The storage device according to claim 9, wherein, The memory controller controls the queue layer to change the mode from single data rate (SDR) mode to dual data rate (DDR) mode.

15. The storage device according to claim 14, wherein, The control logic includes: A mode setting controller, which sets operation information corresponding to the SDR mode and the DDR mode.

16. The storage device according to claim 9, wherein, The input speed of commands and addresses from the memory controller to the queue layer is higher than the output speed of commands and addresses from the queue layer to the control logic.

Images